| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 98.31 | 100.00 | 96.55 | 100.00 | 100.00 | 95.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 87.31 | 87.31 | 100.00 | 100.00 | 96.55 | 96.55 | 100.00 | 100.00 | 100.00 | 100.00 | 40.00 | 40.00 | /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.846460747 | ||
| 95.31 | 8.00 | 100.00 | 0.00 | 96.55 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 80.00 | 40.00 | /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.2755099944 | ||
| 96.81 | 1.50 | 100.00 | 0.00 | 96.55 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 87.50 | 7.50 | /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.4064395699 | ||
| 98.31 | 1.50 | 100.00 | 0.00 | 96.55 | 0.00 | 100.00 | 0.00 | 100.00 | 0.00 | 95.00 | 7.50 | /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.2803569296 | ||
| Name |
|---|
| /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.2070894513 |
| /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.2802694190 |
| /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.262973332 |
| /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.1631240852 |
| /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.3527519055 |
| /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.115674533 |
| /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.828483451 |
| /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.1786383165 |
| /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.2529554371 |
| /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.75170404 |
| /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.2086919687 |
| /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.1687057615 |
| /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.3743987496 |
| /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.808868792 |
| /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.2476251701 |
| /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.3454028815 |
| /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.2543852478 |
| /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.2307200682 |
| /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.1758061098 |
| /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.2851355197 |
| /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.615847428 |
| /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.2012544566 |
| /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.2349329607 |
| /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.2658354887 |
| /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.715081199 |
| /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.2852529796 |
| /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.668379810 |
| /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.3584094355 |
| /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.1357773962 |
| /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.1102154163 |
| /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.1921234739 |
| /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.963912187 |
| /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.3403324011 |
| /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.3314456122 |
| /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.2530156099 |
| /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.35724688 |
| /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.1200166607 |
| /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.956417321 |
| /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.2616547510 |
| /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.1353710052 |
| /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.922654893 |
| /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.2259220133 |
| /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.102346954 |
| /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.796763205 |
| /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.2262327104 |
| /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.3677121853 |
| /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.3094991505 |
| /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.734484641 |
| /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.3531626467 |
| /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.1456942446 |
| /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.4159315610 |
| /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.2895890130 |
| /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.781413825 |
| /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.4001252384 |
| /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.1769629125 |
| /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.952003814 |
| /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.2004747027 |
| /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.423077727 |
| /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.3893743313 |
| /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.1019623495 |
| /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.3447691627 |
| /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.1044329042 |
| /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.3027203667 |
| /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.3907988465 |
| /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.1891313013 |
| /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.3103941214 |
| /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.1855589815 |
| /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.14288407 |
| /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.990056893 |
| /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.3751375667 |
| /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.3841484515 |
| /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.3385539176 |
| /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.1907005101 |
| /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.2034408758 |
| /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.2236818173 |
| /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.600621692 |
| /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.1941107386 |
| /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.1890361245 |
| /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.366763824 |
| /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.1590333205 |
| /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.3993291928 |
| /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.2696247741 |
| /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.2817448421 |
| /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.1922904107 |
| /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.2793305981 |
| /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.2579058066 |
| /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.1571265454 |
| /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.147593834 |
| /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.45184167 |
| /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.3430240937 |
| /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.1173108675 |
| /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.842266350 |
| /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.2439460245 |
| /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.914794776 |
| /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.2907131049 |
| /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.292908461 |
| /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.3265342436 |
| /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.2395587400 |
| /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.79157995 |
| /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.3059828345 |
| /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.1754000794 |
| /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.725404116 |
| /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.403484097 |
| /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.3408559158 |
| /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.1599300824 |
| /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.1467696086 |
| /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.2990794724 |
| /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.574798117 |
| /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.4245580484 |
| /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.1459729991 |
| /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.520294393 |
| /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.2545252512 |
| /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.2239933065 |
| /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.2932018780 |
| /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.633612152 |
| /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.204523627 |
| /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.3378547539 |
| /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.1920391382 |
| /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.1457414354 |
| /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.2151100094 |
| /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.611920491 |
| /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.4182405737 |
| /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.1443161226 |
| /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.3307425084 |
| /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.1573337243 |
| /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.3991244939 |
| /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.722725843 |
| /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.1601683242 |
| /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.541272411 |
| /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.1432065643 |
| /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.188314048 |
| /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.611423986 |
| /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.1873262531 |
| /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.1441355608 |
| /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.1070230266 |
| /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.1170964951 |
| /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.2473560138 |
| /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.1352837876 |
| /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.4033694916 |
| /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.3983369402 |
| /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.347456351 |
| /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.1898089476 |
| /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.4096793434 |
| /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.1236183826 |
| /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.2472617380 |
| /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.1906182618 |
| /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.2375326029 |
| /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.3141263789 |
| /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.1397468617 |
| /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.4092403610 |
| /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.899616878 |
| /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.769565400 |
| /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.2659808198 |
| /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.2039188010 |
| /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.2360477940 |
| /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.1300231964 |
| /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.3323579599 |
| /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.2811012936 |
| /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.660806906 |
| /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.2581727631 |
| /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.4011418161 |
| /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.1979245705 |
| /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.2975370559 |
| /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.2235480490 |
| /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.4079845714 |
| /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.2497039835 |
| /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.2667295510 |
| /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.3036397243 |
| /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.2810073400 |
| /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.1134623723 |
| /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.2251236975 |
| /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.397460711 |
| /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.3061898545 |
| /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.4230825939 |
| /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.1270666035 |
| /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.1045752761 |
| /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.922130021 |
| /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.900716485 |
| /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.1803906560 |
| /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.3288249453 |
| /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.51089520 |
| /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.63101036 |
| /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.4165477605 |
| /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.1385099894 |
| /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.2916728035 |
| /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.4020495066 |
| /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.1551197731 |
| /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.4060601620 |
| /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.686618359 |
| /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.2051068172 |
| /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.2880268454 |
| /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.3455104693 |
| /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.153938550 |
| /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.765657828 |
| /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.1294461071 |
| /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.4114906167 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.2880268454 | Apr 21 12:22:41 PM PDT 24 | Apr 21 12:22:50 PM PDT 24 | 1371590000 ps | ||
| T2 | /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.846460747 | Apr 21 12:20:44 PM PDT 24 | Apr 21 12:20:55 PM PDT 24 | 1616690000 ps | ||
| T3 | /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.4060601620 | Apr 21 12:21:44 PM PDT 24 | Apr 21 12:21:52 PM PDT 24 | 1517150000 ps | ||
| T7 | /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.2497039835 | Apr 21 12:22:41 PM PDT 24 | Apr 21 12:22:51 PM PDT 24 | 1565110000 ps | ||
| T8 | /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.1979245705 | Apr 21 12:23:47 PM PDT 24 | Apr 21 12:23:55 PM PDT 24 | 1459830000 ps | ||
| T9 | /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.922130021 | Apr 21 12:23:47 PM PDT 24 | Apr 21 12:23:54 PM PDT 24 | 1473610000 ps | ||
| T10 | /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.1294461071 | Apr 21 12:17:58 PM PDT 24 | Apr 21 12:18:07 PM PDT 24 | 1462610000 ps | ||
| T11 | /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.900716485 | Apr 21 12:23:47 PM PDT 24 | Apr 21 12:23:54 PM PDT 24 | 1258410000 ps | ||
| T12 | /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.4011418161 | Apr 21 12:23:51 PM PDT 24 | Apr 21 12:23:59 PM PDT 24 | 1523110000 ps | ||
| T13 | /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.2039188010 | Apr 21 12:22:54 PM PDT 24 | Apr 21 12:23:02 PM PDT 24 | 1353530000 ps | ||
| T41 | /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.765657828 | Apr 21 12:22:37 PM PDT 24 | Apr 21 12:22:47 PM PDT 24 | 1458010000 ps | ||
| T42 | /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.2659808198 | Apr 21 12:20:09 PM PDT 24 | Apr 21 12:20:19 PM PDT 24 | 1503010000 ps | ||
| T43 | /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.1134623723 | Apr 21 12:23:01 PM PDT 24 | Apr 21 12:23:13 PM PDT 24 | 1500970000 ps | ||
| T44 | /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.660806906 | Apr 21 12:20:23 PM PDT 24 | Apr 21 12:20:33 PM PDT 24 | 1435250000 ps | ||
| T45 | /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.153938550 | Apr 21 12:22:47 PM PDT 24 | Apr 21 12:22:57 PM PDT 24 | 1482290000 ps | ||
| T46 | /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.3455104693 | Apr 21 12:21:20 PM PDT 24 | Apr 21 12:21:28 PM PDT 24 | 1490190000 ps | ||
| T47 | /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.2235480490 | Apr 21 12:23:47 PM PDT 24 | Apr 21 12:23:55 PM PDT 24 | 1468250000 ps | ||
| T48 | /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.2581727631 | Apr 21 12:23:10 PM PDT 24 | Apr 21 12:23:18 PM PDT 24 | 1244070000 ps | ||
| T49 | /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.3036397243 | Apr 21 12:22:37 PM PDT 24 | Apr 21 12:22:44 PM PDT 24 | 1324370000 ps | ||
| T50 | /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.1551197731 | Apr 21 12:20:40 PM PDT 24 | Apr 21 12:20:52 PM PDT 24 | 1508250000 ps | ||
| T51 | /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.2810073400 | Apr 21 12:24:02 PM PDT 24 | Apr 21 12:24:13 PM PDT 24 | 1349450000 ps | ||
| T52 | /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.397460711 | Apr 21 12:22:41 PM PDT 24 | Apr 21 12:22:50 PM PDT 24 | 1368070000 ps | ||
| T53 | /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.51089520 | Apr 21 12:21:20 PM PDT 24 | Apr 21 12:21:28 PM PDT 24 | 1492030000 ps | ||
| T54 | /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.4230825939 | Apr 21 12:21:51 PM PDT 24 | Apr 21 12:22:01 PM PDT 24 | 1628470000 ps | ||
| T55 | /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.1803906560 | Apr 21 12:20:28 PM PDT 24 | Apr 21 12:20:38 PM PDT 24 | 1549890000 ps | ||
| T56 | /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.2916728035 | Apr 21 12:21:17 PM PDT 24 | Apr 21 12:21:28 PM PDT 24 | 1377910000 ps | ||
| T57 | /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.3288249453 | Apr 21 12:23:28 PM PDT 24 | Apr 21 12:23:36 PM PDT 24 | 1439610000 ps | ||
| T58 | /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.1270666035 | Apr 21 12:23:37 PM PDT 24 | Apr 21 12:23:44 PM PDT 24 | 1533530000 ps | ||
| T59 | /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.1385099894 | Apr 21 12:21:17 PM PDT 24 | Apr 21 12:21:29 PM PDT 24 | 1494270000 ps | ||
| T60 | /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.1045752761 | Apr 21 12:22:41 PM PDT 24 | Apr 21 12:22:49 PM PDT 24 | 1305010000 ps | ||
| T61 | /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.2360477940 | Apr 21 12:22:02 PM PDT 24 | Apr 21 12:22:11 PM PDT 24 | 1533630000 ps | ||
| T62 | /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.2251236975 | Apr 21 12:24:02 PM PDT 24 | Apr 21 12:24:14 PM PDT 24 | 1557450000 ps | ||
| T63 | /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.899616878 | Apr 21 12:19:55 PM PDT 24 | Apr 21 12:20:04 PM PDT 24 | 1578390000 ps | ||
| T64 | /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.3061898545 | Apr 21 12:22:29 PM PDT 24 | Apr 21 12:22:37 PM PDT 24 | 1373910000 ps | ||
| T65 | /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.686618359 | Apr 21 12:23:31 PM PDT 24 | Apr 21 12:23:40 PM PDT 24 | 1337910000 ps | ||
| T66 | /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.1300231964 | Apr 21 12:20:09 PM PDT 24 | Apr 21 12:20:16 PM PDT 24 | 1303450000 ps | ||
| T67 | /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.2811012936 | Apr 21 12:23:09 PM PDT 24 | Apr 21 12:23:19 PM PDT 24 | 1643450000 ps | ||
| T68 | /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.2975370559 | Apr 21 12:23:52 PM PDT 24 | Apr 21 12:24:05 PM PDT 24 | 1436050000 ps | ||
| T69 | /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.2051068172 | Apr 21 12:23:01 PM PDT 24 | Apr 21 12:23:10 PM PDT 24 | 1575030000 ps | ||
| T70 | /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.4020495066 | Apr 21 12:24:28 PM PDT 24 | Apr 21 12:24:35 PM PDT 24 | 1636130000 ps | ||
| T71 | /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.2667295510 | Apr 21 12:20:25 PM PDT 24 | Apr 21 12:20:33 PM PDT 24 | 1449310000 ps | ||
| T72 | /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.63101036 | Apr 21 12:20:48 PM PDT 24 | Apr 21 12:20:57 PM PDT 24 | 1438050000 ps | ||
| T73 | /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.4092403610 | Apr 21 12:23:02 PM PDT 24 | Apr 21 12:23:11 PM PDT 24 | 1238590000 ps | ||
| T74 | /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.3141263789 | Apr 21 12:22:46 PM PDT 24 | Apr 21 12:22:58 PM PDT 24 | 1558670000 ps | ||
| T75 | /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.3323579599 | Apr 21 12:22:54 PM PDT 24 | Apr 21 12:23:02 PM PDT 24 | 1568090000 ps | ||
| T76 | /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.4165477605 | Apr 21 12:23:38 PM PDT 24 | Apr 21 12:23:48 PM PDT 24 | 1547830000 ps | ||
| T77 | /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.4114906167 | Apr 21 12:18:45 PM PDT 24 | Apr 21 12:18:53 PM PDT 24 | 1372830000 ps | ||
| T78 | /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.4079845714 | Apr 21 12:20:16 PM PDT 24 | Apr 21 12:20:25 PM PDT 24 | 1553770000 ps | ||
| T79 | /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.769565400 | Apr 21 12:20:01 PM PDT 24 | Apr 21 12:20:11 PM PDT 24 | 1540230000 ps | ||
| T80 | /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.1397468617 | Apr 21 12:22:47 PM PDT 24 | Apr 21 12:22:57 PM PDT 24 | 1537710000 ps | ||
| T14 | /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.1855589815 | Apr 21 12:22:40 PM PDT 24 | Apr 21 12:56:59 PM PDT 24 | 336325210000 ps | ||
| T15 | /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.3893743313 | Apr 21 12:22:49 PM PDT 24 | Apr 21 12:57:53 PM PDT 24 | 336402530000 ps | ||
| T16 | /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.366763824 | Apr 21 12:23:32 PM PDT 24 | Apr 21 12:55:50 PM PDT 24 | 336760370000 ps | ||
| T17 | /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.1571265454 | Apr 21 12:24:04 PM PDT 24 | Apr 21 12:56:21 PM PDT 24 | 337007130000 ps | ||
| T18 | /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.3265342436 | Apr 21 12:23:31 PM PDT 24 | Apr 21 12:59:20 PM PDT 24 | 336419690000 ps | ||
| T19 | /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.2755099944 | Apr 21 12:24:28 PM PDT 24 | Apr 21 12:51:40 PM PDT 24 | 336829730000 ps | ||
| T20 | /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.2817448421 | Apr 21 12:21:44 PM PDT 24 | Apr 21 12:49:56 PM PDT 24 | 336463270000 ps | ||
| T21 | /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.1907005101 | Apr 21 12:20:24 PM PDT 24 | Apr 21 12:52:52 PM PDT 24 | 337077170000 ps | ||
| T22 | /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.3385539176 | Apr 21 12:21:44 PM PDT 24 | Apr 21 12:50:06 PM PDT 24 | 336279110000 ps | ||
| T23 | /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.990056893 | Apr 21 12:22:46 PM PDT 24 | Apr 21 12:47:07 PM PDT 24 | 336407170000 ps | ||
| T81 | /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.600621692 | Apr 21 12:23:51 PM PDT 24 | Apr 21 12:49:23 PM PDT 24 | 336713290000 ps | ||
| T82 | /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.1019623495 | Apr 21 12:22:49 PM PDT 24 | Apr 21 12:56:49 PM PDT 24 | 336741870000 ps | ||
| T83 | /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.2895890130 | Apr 21 12:18:38 PM PDT 24 | Apr 21 12:53:08 PM PDT 24 | 336368570000 ps | ||
| T84 | /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.2696247741 | Apr 21 12:20:53 PM PDT 24 | Apr 21 12:44:50 PM PDT 24 | 336710230000 ps | ||
| T85 | /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.1941107386 | Apr 21 12:23:00 PM PDT 24 | Apr 21 12:57:08 PM PDT 24 | 337035050000 ps | ||
| T86 | /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.1173108675 | Apr 21 12:23:18 PM PDT 24 | Apr 21 12:52:52 PM PDT 24 | 336599630000 ps | ||
| T87 | /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.3447691627 | Apr 21 12:23:31 PM PDT 24 | Apr 21 12:59:46 PM PDT 24 | 336611870000 ps | ||
| T88 | /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.3993291928 | Apr 21 12:23:51 PM PDT 24 | Apr 21 12:50:13 PM PDT 24 | 337068170000 ps | ||
| T89 | /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.952003814 | Apr 21 12:22:34 PM PDT 24 | Apr 21 12:57:33 PM PDT 24 | 336434250000 ps | ||
| T90 | /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.2793305981 | Apr 21 12:23:03 PM PDT 24 | Apr 21 12:57:30 PM PDT 24 | 336387090000 ps | ||
| T91 | /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.3430240937 | Apr 21 12:23:32 PM PDT 24 | Apr 21 12:54:59 PM PDT 24 | 336591450000 ps | ||
| T92 | /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.2395587400 | Apr 21 12:22:33 PM PDT 24 | Apr 21 12:59:03 PM PDT 24 | 336479490000 ps | ||
| T93 | /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.1922904107 | Apr 21 12:18:54 PM PDT 24 | Apr 21 12:54:19 PM PDT 24 | 336731070000 ps | ||
| T94 | /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.14288407 | Apr 21 12:22:40 PM PDT 24 | Apr 21 12:57:00 PM PDT 24 | 336660910000 ps | ||
| T95 | /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.781413825 | Apr 21 12:22:34 PM PDT 24 | Apr 21 12:58:23 PM PDT 24 | 336865150000 ps | ||
| T96 | /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.3027203667 | Apr 21 12:22:48 PM PDT 24 | Apr 21 12:57:46 PM PDT 24 | 336794970000 ps | ||
| T97 | /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.3841484515 | Apr 21 12:23:01 PM PDT 24 | Apr 21 12:57:01 PM PDT 24 | 336484710000 ps | ||
| T98 | /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.4159315610 | Apr 21 12:22:33 PM PDT 24 | Apr 21 12:58:43 PM PDT 24 | 337023710000 ps | ||
| T99 | /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.423077727 | Apr 21 12:22:34 PM PDT 24 | Apr 21 12:57:43 PM PDT 24 | 336310790000 ps | ||
| T100 | /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.1769629125 | Apr 21 12:22:33 PM PDT 24 | Apr 21 12:59:03 PM PDT 24 | 336644330000 ps | ||
| T101 | /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.147593834 | Apr 21 12:24:18 PM PDT 24 | Apr 21 12:57:18 PM PDT 24 | 336449970000 ps | ||
| T102 | /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.4001252384 | Apr 21 12:22:33 PM PDT 24 | Apr 21 12:59:18 PM PDT 24 | 336674070000 ps | ||
| T103 | /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.1044329042 | Apr 21 12:20:15 PM PDT 24 | Apr 21 12:52:59 PM PDT 24 | 337012410000 ps | ||
| T104 | /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.1456942446 | Apr 21 12:24:03 PM PDT 24 | Apr 21 12:51:48 PM PDT 24 | 336754090000 ps | ||
| T105 | /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.2579058066 | Apr 21 12:23:59 PM PDT 24 | Apr 21 12:50:19 PM PDT 24 | 336699910000 ps | ||
| T106 | /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.1890361245 | Apr 21 12:22:37 PM PDT 24 | Apr 21 12:45:47 PM PDT 24 | 336827350000 ps | ||
| T107 | /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.45184167 | Apr 21 12:23:13 PM PDT 24 | Apr 21 12:57:54 PM PDT 24 | 337013630000 ps | ||
| T108 | /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.2907131049 | Apr 21 12:23:32 PM PDT 24 | Apr 21 12:57:54 PM PDT 24 | 336376150000 ps | ||
| T109 | /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.1891313013 | Apr 21 12:22:49 PM PDT 24 | Apr 21 12:57:31 PM PDT 24 | 336439950000 ps | ||
| T110 | /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.292908461 | Apr 21 12:23:31 PM PDT 24 | Apr 21 12:58:45 PM PDT 24 | 336944410000 ps | ||
| T111 | /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.842266350 | Apr 21 12:23:14 PM PDT 24 | Apr 21 12:57:21 PM PDT 24 | 336504510000 ps | ||
| T112 | /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.3907988465 | Apr 21 12:20:23 PM PDT 24 | Apr 21 12:52:46 PM PDT 24 | 336874630000 ps | ||
| T113 | /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.2439460245 | Apr 21 12:23:14 PM PDT 24 | Apr 21 12:57:09 PM PDT 24 | 336621950000 ps | ||
| T114 | /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.2004747027 | Apr 21 12:22:52 PM PDT 24 | Apr 21 12:46:50 PM PDT 24 | 336730630000 ps | ||
| T115 | /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.914794776 | Apr 21 12:23:38 PM PDT 24 | Apr 21 12:47:59 PM PDT 24 | 336449230000 ps | ||
| T116 | /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.3751375667 | Apr 21 12:20:15 PM PDT 24 | Apr 21 12:53:04 PM PDT 24 | 336666450000 ps | ||
| T117 | /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.1590333205 | Apr 21 12:24:04 PM PDT 24 | Apr 21 12:55:27 PM PDT 24 | 336832230000 ps | ||
| T118 | /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.2034408758 | Apr 21 12:22:40 PM PDT 24 | Apr 21 12:56:57 PM PDT 24 | 336554870000 ps | ||
| T119 | /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.3103941214 | Apr 21 12:20:23 PM PDT 24 | Apr 21 12:53:40 PM PDT 24 | 336990630000 ps | ||
| T120 | /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.2236818173 | Apr 21 12:23:52 PM PDT 24 | Apr 21 12:49:45 PM PDT 24 | 336737650000 ps | ||
| T4 | /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.611920491 | Apr 21 12:21:57 PM PDT 24 | Apr 21 12:22:05 PM PDT 24 | 1330190000 ps | ||
| T5 | /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.2803569296 | Apr 21 12:21:15 PM PDT 24 | Apr 21 12:21:24 PM PDT 24 | 1504530000 ps | ||
| T6 | /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.2239933065 | Apr 21 12:21:32 PM PDT 24 | Apr 21 12:21:41 PM PDT 24 | 1539530000 ps | ||
| T24 | /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.347456351 | Apr 21 12:22:35 PM PDT 24 | Apr 21 12:22:47 PM PDT 24 | 1574550000 ps | ||
| T25 | /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.1898089476 | Apr 21 12:22:46 PM PDT 24 | Apr 21 12:22:56 PM PDT 24 | 1289450000 ps | ||
| T26 | /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.204523627 | Apr 21 12:22:39 PM PDT 24 | Apr 21 12:22:48 PM PDT 24 | 1493450000 ps | ||
| T27 | /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.1873262531 | Apr 21 12:22:34 PM PDT 24 | Apr 21 12:22:45 PM PDT 24 | 1484450000 ps | ||
| T28 | /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.4182405737 | Apr 21 12:20:32 PM PDT 24 | Apr 21 12:20:40 PM PDT 24 | 1461290000 ps | ||
| T29 | /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.725404116 | Apr 21 12:20:22 PM PDT 24 | Apr 21 12:20:32 PM PDT 24 | 1243570000 ps | ||
| T30 | /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.4245580484 | Apr 21 12:19:38 PM PDT 24 | Apr 21 12:19:48 PM PDT 24 | 1572370000 ps | ||
| T121 | /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.3991244939 | Apr 21 12:22:54 PM PDT 24 | Apr 21 12:23:02 PM PDT 24 | 1381430000 ps | ||
| T122 | /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.79157995 | Apr 21 12:23:31 PM PDT 24 | Apr 21 12:23:41 PM PDT 24 | 1465150000 ps | ||
| T123 | /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.2375326029 | Apr 21 12:23:51 PM PDT 24 | Apr 21 12:24:00 PM PDT 24 | 1411470000 ps | ||
| T124 | /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.722725843 | Apr 21 12:19:49 PM PDT 24 | Apr 21 12:19:58 PM PDT 24 | 1568750000 ps | ||
| T125 | /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.3307425084 | Apr 21 12:20:27 PM PDT 24 | Apr 21 12:20:37 PM PDT 24 | 1491610000 ps | ||
| T126 | /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.611423986 | Apr 21 12:23:51 PM PDT 24 | Apr 21 12:24:00 PM PDT 24 | 1555530000 ps | ||
| T127 | /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.2545252512 | Apr 21 12:22:37 PM PDT 24 | Apr 21 12:22:47 PM PDT 24 | 1425910000 ps | ||
| T128 | /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.633612152 | Apr 21 12:19:30 PM PDT 24 | Apr 21 12:19:37 PM PDT 24 | 1445210000 ps | ||
| T129 | /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.3983369402 | Apr 21 12:23:38 PM PDT 24 | Apr 21 12:23:46 PM PDT 24 | 1504970000 ps | ||
| T130 | /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.2472617380 | Apr 21 12:22:41 PM PDT 24 | Apr 21 12:22:51 PM PDT 24 | 1455290000 ps | ||
| T131 | /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.2151100094 | Apr 21 12:20:28 PM PDT 24 | Apr 21 12:20:38 PM PDT 24 | 1418670000 ps | ||
| T132 | /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.541272411 | Apr 21 12:22:57 PM PDT 24 | Apr 21 12:23:06 PM PDT 24 | 1419790000 ps | ||
| T133 | /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.1754000794 | Apr 21 12:20:22 PM PDT 24 | Apr 21 12:20:34 PM PDT 24 | 1622750000 ps | ||
| T134 | /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.1920391382 | Apr 21 12:22:38 PM PDT 24 | Apr 21 12:22:48 PM PDT 24 | 1583170000 ps | ||
| T135 | /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.1906182618 | Apr 21 12:18:50 PM PDT 24 | Apr 21 12:18:59 PM PDT 24 | 1358490000 ps | ||
| T136 | /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.2990794724 | Apr 21 12:20:23 PM PDT 24 | Apr 21 12:20:33 PM PDT 24 | 1352170000 ps | ||
| T137 | /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.188314048 | Apr 21 12:22:48 PM PDT 24 | Apr 21 12:23:00 PM PDT 24 | 1566150000 ps | ||
| T138 | /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.1352837876 | Apr 21 12:21:17 PM PDT 24 | Apr 21 12:21:27 PM PDT 24 | 1301550000 ps | ||
| T139 | /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.574798117 | Apr 21 12:20:15 PM PDT 24 | Apr 21 12:20:25 PM PDT 24 | 1482090000 ps | ||
| T140 | /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.1601683242 | Apr 21 12:22:58 PM PDT 24 | Apr 21 12:23:07 PM PDT 24 | 1475870000 ps | ||
| T141 | /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.4033694916 | Apr 21 12:22:40 PM PDT 24 | Apr 21 12:22:50 PM PDT 24 | 1407710000 ps | ||
| T142 | /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.1070230266 | Apr 21 12:19:54 PM PDT 24 | Apr 21 12:20:02 PM PDT 24 | 1419490000 ps | ||
| T143 | /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.3059828345 | Apr 21 12:21:32 PM PDT 24 | Apr 21 12:21:39 PM PDT 24 | 1333950000 ps | ||
| T144 | /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.1573337243 | Apr 21 12:19:46 PM PDT 24 | Apr 21 12:19:56 PM PDT 24 | 1241230000 ps | ||
| T145 | /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.2932018780 | Apr 21 12:22:38 PM PDT 24 | Apr 21 12:22:47 PM PDT 24 | 1467790000 ps | ||
| T146 | /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.1457414354 | Apr 21 12:21:03 PM PDT 24 | Apr 21 12:21:12 PM PDT 24 | 1460470000 ps | ||
| T147 | /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.1170964951 | Apr 21 12:22:48 PM PDT 24 | Apr 21 12:22:57 PM PDT 24 | 1451470000 ps | ||
| T148 | /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.1236183826 | Apr 21 12:23:51 PM PDT 24 | Apr 21 12:24:00 PM PDT 24 | 1318490000 ps | ||
| T149 | /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.4096793434 | Apr 21 12:20:30 PM PDT 24 | Apr 21 12:20:42 PM PDT 24 | 1488310000 ps | ||
| T150 | /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.1599300824 | Apr 21 12:17:55 PM PDT 24 | Apr 21 12:18:03 PM PDT 24 | 1531530000 ps | ||
| T151 | /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.1467696086 | Apr 21 12:20:43 PM PDT 24 | Apr 21 12:20:52 PM PDT 24 | 1483290000 ps | ||
| T152 | /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.403484097 | Apr 21 12:20:23 PM PDT 24 | Apr 21 12:20:33 PM PDT 24 | 1270590000 ps | ||
| T153 | /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.1459729991 | Apr 21 12:23:31 PM PDT 24 | Apr 21 12:23:41 PM PDT 24 | 1452970000 ps | ||
| T154 | /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.1441355608 | Apr 21 12:19:57 PM PDT 24 | Apr 21 12:20:06 PM PDT 24 | 1341630000 ps | ||
| T155 | /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.1443161226 | Apr 21 12:22:35 PM PDT 24 | Apr 21 12:22:44 PM PDT 24 | 1408870000 ps | ||
| T156 | /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.3408559158 | Apr 21 12:22:40 PM PDT 24 | Apr 21 12:22:51 PM PDT 24 | 1417770000 ps | ||
| T157 | /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.520294393 | Apr 21 12:23:02 PM PDT 24 | Apr 21 12:23:10 PM PDT 24 | 1194090000 ps | ||
| T158 | /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.3378547539 | Apr 21 12:23:09 PM PDT 24 | Apr 21 12:23:19 PM PDT 24 | 1552530000 ps | ||
| T159 | /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.2473560138 | Apr 21 12:22:48 PM PDT 24 | Apr 21 12:22:58 PM PDT 24 | 1539750000 ps | ||
| T160 | /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.1432065643 | Apr 21 12:19:47 PM PDT 24 | Apr 21 12:19:55 PM PDT 24 | 1509250000 ps | ||
| T31 | /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.3584094355 | Apr 21 12:38:36 PM PDT 24 | Apr 21 01:10:19 PM PDT 24 | 336929190000 ps | ||
| T32 | /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.1687057615 | Apr 21 12:38:34 PM PDT 24 | Apr 21 01:14:31 PM PDT 24 | 336888470000 ps | ||
| T33 | /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.3094991505 | Apr 21 12:38:49 PM PDT 24 | Apr 21 01:15:04 PM PDT 24 | 336966470000 ps | ||
| T34 | /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.3743987496 | Apr 21 12:38:46 PM PDT 24 | Apr 21 01:11:29 PM PDT 24 | 336870530000 ps | ||
| T35 | /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.4064395699 | Apr 21 12:38:56 PM PDT 24 | Apr 21 01:15:35 PM PDT 24 | 336305150000 ps | ||
| T36 | /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.2307200682 | Apr 21 12:38:52 PM PDT 24 | Apr 21 01:15:48 PM PDT 24 | 336807350000 ps | ||
| T37 | /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.956417321 | Apr 21 12:38:44 PM PDT 24 | Apr 21 01:06:04 PM PDT 24 | 336853550000 ps | ||
| T38 | /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.1786383165 | Apr 21 12:38:48 PM PDT 24 | Apr 21 01:13:50 PM PDT 24 | 336721550000 ps | ||
| T39 | /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.2530156099 | Apr 21 12:38:50 PM PDT 24 | Apr 21 01:09:32 PM PDT 24 | 336804450000 ps | ||
| T40 | /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.3527519055 | Apr 21 12:38:49 PM PDT 24 | Apr 21 01:07:15 PM PDT 24 | 336617970000 ps | ||
| T161 | /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.2476251701 | Apr 21 12:38:52 PM PDT 24 | Apr 21 01:15:49 PM PDT 24 | 336996830000 ps | ||
| T162 | /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.1353710052 | Apr 21 12:39:02 PM PDT 24 | Apr 21 01:13:54 PM PDT 24 | 336690750000 ps | ||
| T163 | /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.2086919687 | Apr 21 12:38:46 PM PDT 24 | Apr 21 01:15:18 PM PDT 24 | 336435330000 ps | ||
| T164 | /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.1102154163 | Apr 21 12:38:41 PM PDT 24 | Apr 21 01:16:15 PM PDT 24 | 336439230000 ps | ||
| T165 | /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.2852529796 | Apr 21 12:38:41 PM PDT 24 | Apr 21 01:12:00 PM PDT 24 | 336584170000 ps | ||
| T166 | /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.808868792 | Apr 21 12:38:59 PM PDT 24 | Apr 21 01:21:36 PM PDT 24 | 336790210000 ps | ||
| T167 | /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.35724688 | Apr 21 12:38:44 PM PDT 24 | Apr 21 01:15:09 PM PDT 24 | 336342330000 ps | ||
| T168 | /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.1921234739 | Apr 21 12:38:30 PM PDT 24 | Apr 21 01:08:51 PM PDT 24 | 336619990000 ps | ||
| T169 | /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.2543852478 | Apr 21 12:38:48 PM PDT 24 | Apr 21 01:09:05 PM PDT 24 | 336911790000 ps | ||
| T170 | /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.3531626467 | Apr 21 12:38:48 PM PDT 24 | Apr 21 01:15:07 PM PDT 24 | 337019350000 ps | ||
| T171 | /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.1631240852 | Apr 21 12:38:59 PM PDT 24 | Apr 21 01:13:53 PM PDT 24 | 336621630000 ps | ||
| T172 | /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.3403324011 | Apr 21 12:38:56 PM PDT 24 | Apr 21 01:04:02 PM PDT 24 | 336894470000 ps | ||
| T173 | /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.3454028815 | Apr 21 12:38:50 PM PDT 24 | Apr 21 01:15:59 PM PDT 24 | 336990370000 ps | ||
| T174 | /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.262973332 | Apr 21 12:38:32 PM PDT 24 | Apr 21 01:16:14 PM PDT 24 | 336961710000 ps | ||
| T175 | /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.2616547510 | Apr 21 12:38:51 PM PDT 24 | Apr 21 01:06:43 PM PDT 24 | 336712670000 ps | ||
| T176 | /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.2259220133 | Apr 21 12:39:05 PM PDT 24 | Apr 21 01:09:02 PM PDT 24 | 337123910000 ps | ||
| T177 | /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.668379810 | Apr 21 12:38:56 PM PDT 24 | Apr 21 01:07:53 PM PDT 24 | 336986450000 ps | ||
| T178 | /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.828483451 | Apr 21 12:38:46 PM PDT 24 | Apr 21 01:13:38 PM PDT 24 | 336403590000 ps | ||
| T179 | /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.922654893 | Apr 21 12:38:54 PM PDT 24 | Apr 21 01:16:21 PM PDT 24 | 336927150000 ps | ||
| T180 | /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.2012544566 | Apr 21 12:38:55 PM PDT 24 | Apr 21 01:09:53 PM PDT 24 | 336661770000 ps | ||
| T181 | /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.615847428 | Apr 21 12:38:57 PM PDT 24 | Apr 21 01:08:27 PM PDT 24 | 336978950000 ps | ||
| T182 | /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.1357773962 | Apr 21 12:38:47 PM PDT 24 | Apr 21 01:07:58 PM PDT 24 | 337150350000 ps | ||
| T183 | /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.2529554371 | Apr 21 12:38:50 PM PDT 24 | Apr 21 01:08:48 PM PDT 24 | 337081710000 ps | ||
| T184 | /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.715081199 | Apr 21 12:38:59 PM PDT 24 | Apr 21 01:12:05 PM PDT 24 | 336921650000 ps | ||
| T185 | /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.734484641 | Apr 21 12:38:59 PM PDT 24 | Apr 21 01:21:29 PM PDT 24 | 336858670000 ps | ||
| T186 | /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.2802694190 | Apr 21 12:38:39 PM PDT 24 | Apr 21 01:20:37 PM PDT 24 | 336466430000 ps | ||
| T187 | /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.963912187 | Apr 21 12:38:46 PM PDT 24 | Apr 21 01:09:31 PM PDT 24 | 336523490000 ps | ||
| T188 | /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.115674533 | Apr 21 12:39:12 PM PDT 24 | Apr 21 01:13:33 PM PDT 24 | 336537590000 ps | ||
| T189 | /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.2851355197 | Apr 21 12:38:52 PM PDT 24 | Apr 21 01:05:12 PM PDT 24 | 336415270000 ps | ||
| T190 | /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.3677121853 | Apr 21 12:38:53 PM PDT 24 | Apr 21 01:15:15 PM PDT 24 | 336686150000 ps | ||
| T191 | /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.102346954 | Apr 21 12:38:44 PM PDT 24 | Apr 21 01:15:24 PM PDT 24 | 336378330000 ps | ||
| T192 | /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.1758061098 | Apr 21 12:38:56 PM PDT 24 | Apr 21 01:15:41 PM PDT 24 | 336484170000 ps | ||
| T193 | /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.2658354887 | Apr 21 12:38:38 PM PDT 24 | Apr 21 01:11:56 PM PDT 24 | 337062250000 ps | ||
| T194 | /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.796763205 | Apr 21 12:39:02 PM PDT 24 | Apr 21 01:04:01 PM PDT 24 | 336741690000 ps | ||
| T195 | /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.3314456122 | Apr 21 12:38:45 PM PDT 24 | Apr 21 01:11:21 PM PDT 24 | 336770290000 ps | ||
| T196 | /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.2262327104 | Apr 21 12:38:46 PM PDT 24 | Apr 21 01:15:30 PM PDT 24 | 336853750000 ps | ||
| T197 | /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.1200166607 | Apr 21 12:38:52 PM PDT 24 | Apr 21 01:08:22 PM PDT 24 | 336321990000 ps | ||
| T198 | /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.2349329607 | Apr 21 12:38:44 PM PDT 24 | Apr 21 01:15:10 PM PDT 24 | 336618430000 ps | ||
| T199 | /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.2070894513 | Apr 21 12:38:41 PM PDT 24 | Apr 21 01:21:57 PM PDT 24 | 336598090000 ps | ||
| T200 | /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.75170404 | Apr 21 12:38:44 PM PDT 24 | Apr 21 01:22:01 PM PDT 24 | 336563770000 ps |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.846460747 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 1616690000 ps |
| CPU time | 4.87 seconds |
| Started | Apr 21 12:20:44 PM PDT 24 |
| Finished | Apr 21 12:20:55 PM PDT 24 |
| Peak memory | 166612 kb |
| Host | smart-8a5f0a81-07ab-4a14-b849-4858ed965b4e |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=846460747 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_smoke.846460747 |
| Directory | /workspace/12.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.2755099944 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 336829730000 ps |
| CPU time | 651.52 seconds |
| Started | Apr 21 12:24:28 PM PDT 24 |
| Finished | Apr 21 12:51:40 PM PDT 24 |
| Peak memory | 160464 kb |
| Host | smart-3978fbb5-b3bf-4ece-81c1-3d39732aedc3 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2755099944 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_test.2755099944 |
| Directory | /workspace/0.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.4064395699 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 336305150000 ps |
| CPU time | 883.32 seconds |
| Started | Apr 21 12:38:56 PM PDT 24 |
| Finished | Apr 21 01:15:35 PM PDT 24 |
| Peak memory | 160744 kb |
| Host | smart-885ed689-e0cd-4aed-be5e-ec0afc91d992 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4064395699 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_test.4064395699 |
| Directory | /workspace/11.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.2803569296 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 1504530000 ps |
| CPU time | 4.01 seconds |
| Started | Apr 21 12:21:15 PM PDT 24 |
| Finished | Apr 21 12:21:24 PM PDT 24 |
| Peak memory | 164800 kb |
| Host | smart-2a15616a-16d5-444f-bf1f-3644775839fb |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2803569296 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_smoke.2803569296 |
| Directory | /workspace/10.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.2070894513 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 336598090000 ps |
| CPU time | 1025.87 seconds |
| Started | Apr 21 12:38:41 PM PDT 24 |
| Finished | Apr 21 01:21:57 PM PDT 24 |
| Peak memory | 160776 kb |
| Host | smart-34e43591-780d-4f16-b3da-a93d67928591 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2070894513 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_test.2070894513 |
| Directory | /workspace/0.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.2802694190 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 336466430000 ps |
| CPU time | 995.56 seconds |
| Started | Apr 21 12:38:39 PM PDT 24 |
| Finished | Apr 21 01:20:37 PM PDT 24 |
| Peak memory | 160776 kb |
| Host | smart-9397f4f4-42ce-45a5-b294-58fab575daa1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2802694190 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_test.2802694190 |
| Directory | /workspace/1.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.262973332 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 336961710000 ps |
| CPU time | 935.75 seconds |
| Started | Apr 21 12:38:32 PM PDT 24 |
| Finished | Apr 21 01:16:14 PM PDT 24 |
| Peak memory | 160688 kb |
| Host | smart-4ce390a6-6787-4b76-b9b3-7410ffded5df |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=262973332 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_test.262973332 |
| Directory | /workspace/10.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.1631240852 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 336621630000 ps |
| CPU time | 838.05 seconds |
| Started | Apr 21 12:38:59 PM PDT 24 |
| Finished | Apr 21 01:13:53 PM PDT 24 |
| Peak memory | 160796 kb |
| Host | smart-6faca1bd-ac1a-4251-91a7-1838d0de1d01 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1631240852 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_test.1631240852 |
| Directory | /workspace/12.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.3527519055 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 336617970000 ps |
| CPU time | 693.67 seconds |
| Started | Apr 21 12:38:49 PM PDT 24 |
| Finished | Apr 21 01:07:15 PM PDT 24 |
| Peak memory | 160708 kb |
| Host | smart-4d01b0f1-18b8-492a-b020-f6b56c319dde |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3527519055 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_test.3527519055 |
| Directory | /workspace/13.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.115674533 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 336537590000 ps |
| CPU time | 823.88 seconds |
| Started | Apr 21 12:39:12 PM PDT 24 |
| Finished | Apr 21 01:13:33 PM PDT 24 |
| Peak memory | 160780 kb |
| Host | smart-52ed1943-06f2-45c0-b93e-0c968192c6a3 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=115674533 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_test.115674533 |
| Directory | /workspace/14.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.828483451 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 336403590000 ps |
| CPU time | 824.25 seconds |
| Started | Apr 21 12:38:46 PM PDT 24 |
| Finished | Apr 21 01:13:38 PM PDT 24 |
| Peak memory | 160780 kb |
| Host | smart-9a146999-570a-4464-831f-e8a301fc06e4 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=828483451 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_test.828483451 |
| Directory | /workspace/15.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.1786383165 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 336721550000 ps |
| CPU time | 828.93 seconds |
| Started | Apr 21 12:38:48 PM PDT 24 |
| Finished | Apr 21 01:13:50 PM PDT 24 |
| Peak memory | 160796 kb |
| Host | smart-d2d679ab-27cc-4179-a765-c79bddf4899f |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1786383165 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_test.1786383165 |
| Directory | /workspace/16.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.2529554371 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 337081710000 ps |
| CPU time | 726.19 seconds |
| Started | Apr 21 12:38:50 PM PDT 24 |
| Finished | Apr 21 01:08:48 PM PDT 24 |
| Peak memory | 160716 kb |
| Host | smart-8b149c09-8227-4f14-8796-88dadb75b5c0 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2529554371 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_test.2529554371 |
| Directory | /workspace/17.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.75170404 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 336563770000 ps |
| CPU time | 1028.64 seconds |
| Started | Apr 21 12:38:44 PM PDT 24 |
| Finished | Apr 21 01:22:01 PM PDT 24 |
| Peak memory | 160776 kb |
| Host | smart-f5560086-edb3-475e-8acc-13955bb7a058 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=75170404 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_test.75170404 |
| Directory | /workspace/18.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.2086919687 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 336435330000 ps |
| CPU time | 886.79 seconds |
| Started | Apr 21 12:38:46 PM PDT 24 |
| Finished | Apr 21 01:15:18 PM PDT 24 |
| Peak memory | 160684 kb |
| Host | smart-9687dd66-a949-4c7f-89fe-ca581fcbf094 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2086919687 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_test.2086919687 |
| Directory | /workspace/19.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.1687057615 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 336888470000 ps |
| CPU time | 876.41 seconds |
| Started | Apr 21 12:38:34 PM PDT 24 |
| Finished | Apr 21 01:14:31 PM PDT 24 |
| Peak memory | 160704 kb |
| Host | smart-a5255e93-a469-4c7d-a942-51cdccb61274 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1687057615 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_test.1687057615 |
| Directory | /workspace/2.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.3743987496 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 336870530000 ps |
| CPU time | 815.38 seconds |
| Started | Apr 21 12:38:46 PM PDT 24 |
| Finished | Apr 21 01:11:29 PM PDT 24 |
| Peak memory | 160704 kb |
| Host | smart-d2bc2fc1-9a14-4809-b41d-3809ad9d7e8d |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3743987496 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_test.3743987496 |
| Directory | /workspace/20.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.808868792 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 336790210000 ps |
| CPU time | 1013.37 seconds |
| Started | Apr 21 12:38:59 PM PDT 24 |
| Finished | Apr 21 01:21:36 PM PDT 24 |
| Peak memory | 160244 kb |
| Host | smart-90e6c140-7167-4db1-b8a2-d7aa1438824c |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=808868792 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_test.808868792 |
| Directory | /workspace/21.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.2476251701 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 336996830000 ps |
| CPU time | 902.45 seconds |
| Started | Apr 21 12:38:52 PM PDT 24 |
| Finished | Apr 21 01:15:49 PM PDT 24 |
| Peak memory | 160712 kb |
| Host | smart-ecfe6d50-c710-4396-8808-10fe3b419504 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2476251701 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_test.2476251701 |
| Directory | /workspace/22.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.3454028815 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 336990370000 ps |
| CPU time | 900.33 seconds |
| Started | Apr 21 12:38:50 PM PDT 24 |
| Finished | Apr 21 01:15:59 PM PDT 24 |
| Peak memory | 160704 kb |
| Host | smart-343f88b3-a689-476a-adda-01f946ab56c1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3454028815 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_test.3454028815 |
| Directory | /workspace/23.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.2543852478 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 336911790000 ps |
| CPU time | 743.08 seconds |
| Started | Apr 21 12:38:48 PM PDT 24 |
| Finished | Apr 21 01:09:05 PM PDT 24 |
| Peak memory | 160784 kb |
| Host | smart-fabe2752-4d06-4491-bbd9-699064f5bd51 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2543852478 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_test.2543852478 |
| Directory | /workspace/24.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.2307200682 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 336807350000 ps |
| CPU time | 901.6 seconds |
| Started | Apr 21 12:38:52 PM PDT 24 |
| Finished | Apr 21 01:15:48 PM PDT 24 |
| Peak memory | 160712 kb |
| Host | smart-cc7f38e1-803e-473f-9d49-6e4c3f27bde7 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2307200682 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_test.2307200682 |
| Directory | /workspace/25.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.1758061098 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 336484170000 ps |
| CPU time | 904.75 seconds |
| Started | Apr 21 12:38:56 PM PDT 24 |
| Finished | Apr 21 01:15:41 PM PDT 24 |
| Peak memory | 160692 kb |
| Host | smart-0e8501ef-ce7e-4714-9d1f-64f8044db77c |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1758061098 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_test.1758061098 |
| Directory | /workspace/26.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.2851355197 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 336415270000 ps |
| CPU time | 634.32 seconds |
| Started | Apr 21 12:38:52 PM PDT 24 |
| Finished | Apr 21 01:05:12 PM PDT 24 |
| Peak memory | 160712 kb |
| Host | smart-3967ff18-8fb9-4b54-9de9-bd6efacbd29a |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2851355197 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_test.2851355197 |
| Directory | /workspace/27.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.615847428 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 336978950000 ps |
| CPU time | 725.57 seconds |
| Started | Apr 21 12:38:57 PM PDT 24 |
| Finished | Apr 21 01:08:27 PM PDT 24 |
| Peak memory | 160884 kb |
| Host | smart-0fb53264-7d6d-4524-b79e-0b95d02de4ea |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=615847428 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_test.615847428 |
| Directory | /workspace/28.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.2012544566 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 336661770000 ps |
| CPU time | 760.56 seconds |
| Started | Apr 21 12:38:55 PM PDT 24 |
| Finished | Apr 21 01:09:53 PM PDT 24 |
| Peak memory | 160780 kb |
| Host | smart-016d79ad-a134-429b-994b-4f2b386144dc |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2012544566 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_test.2012544566 |
| Directory | /workspace/29.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.2349329607 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 336618430000 ps |
| CPU time | 885.97 seconds |
| Started | Apr 21 12:38:44 PM PDT 24 |
| Finished | Apr 21 01:15:10 PM PDT 24 |
| Peak memory | 160696 kb |
| Host | smart-f7a2d234-2af4-4c1d-b247-148453242f62 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2349329607 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_test.2349329607 |
| Directory | /workspace/3.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.2658354887 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 337062250000 ps |
| CPU time | 809.84 seconds |
| Started | Apr 21 12:38:38 PM PDT 24 |
| Finished | Apr 21 01:11:56 PM PDT 24 |
| Peak memory | 160692 kb |
| Host | smart-53a99c15-cd60-4f05-be04-a98dde691142 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2658354887 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_test.2658354887 |
| Directory | /workspace/30.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.715081199 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 336921650000 ps |
| CPU time | 802.93 seconds |
| Started | Apr 21 12:38:59 PM PDT 24 |
| Finished | Apr 21 01:12:05 PM PDT 24 |
| Peak memory | 160684 kb |
| Host | smart-4e8277e9-3152-48e6-adb6-ed833b99a835 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=715081199 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_test.715081199 |
| Directory | /workspace/31.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.2852529796 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 336584170000 ps |
| CPU time | 807.66 seconds |
| Started | Apr 21 12:38:41 PM PDT 24 |
| Finished | Apr 21 01:12:00 PM PDT 24 |
| Peak memory | 160692 kb |
| Host | smart-c1b67bd8-8b80-43e8-9358-0261d64e69c4 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2852529796 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_test.2852529796 |
| Directory | /workspace/32.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.668379810 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 336986450000 ps |
| CPU time | 704.99 seconds |
| Started | Apr 21 12:38:56 PM PDT 24 |
| Finished | Apr 21 01:07:53 PM PDT 24 |
| Peak memory | 160700 kb |
| Host | smart-0c4c99b9-0e3a-4f95-a472-ac687a214423 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=668379810 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_test.668379810 |
| Directory | /workspace/33.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.3584094355 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 336929190000 ps |
| CPU time | 775.65 seconds |
| Started | Apr 21 12:38:36 PM PDT 24 |
| Finished | Apr 21 01:10:19 PM PDT 24 |
| Peak memory | 160792 kb |
| Host | smart-e6ac8906-e6aa-4304-89c3-b6a9fef61456 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3584094355 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_test.3584094355 |
| Directory | /workspace/34.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.1357773962 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 337150350000 ps |
| CPU time | 710.37 seconds |
| Started | Apr 21 12:38:47 PM PDT 24 |
| Finished | Apr 21 01:07:58 PM PDT 24 |
| Peak memory | 160776 kb |
| Host | smart-33028b04-00c9-4740-ade2-b48882c89856 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1357773962 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_test.1357773962 |
| Directory | /workspace/35.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.1102154163 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 336439230000 ps |
| CPU time | 934.3 seconds |
| Started | Apr 21 12:38:41 PM PDT 24 |
| Finished | Apr 21 01:16:15 PM PDT 24 |
| Peak memory | 160696 kb |
| Host | smart-333916cf-a294-494d-a3a4-99b20e0a192e |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1102154163 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_test.1102154163 |
| Directory | /workspace/36.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.1921234739 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 336619990000 ps |
| CPU time | 737.61 seconds |
| Started | Apr 21 12:38:30 PM PDT 24 |
| Finished | Apr 21 01:08:51 PM PDT 24 |
| Peak memory | 160788 kb |
| Host | smart-ec452bda-3a29-4ba6-8cc9-49ab89874d7b |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1921234739 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_test.1921234739 |
| Directory | /workspace/37.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.963912187 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 336523490000 ps |
| CPU time | 748.31 seconds |
| Started | Apr 21 12:38:46 PM PDT 24 |
| Finished | Apr 21 01:09:31 PM PDT 24 |
| Peak memory | 160740 kb |
| Host | smart-958a0e31-03cc-4f16-8f32-353b1cadeb45 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=963912187 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_test.963912187 |
| Directory | /workspace/38.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.3403324011 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 336894470000 ps |
| CPU time | 588.96 seconds |
| Started | Apr 21 12:38:56 PM PDT 24 |
| Finished | Apr 21 01:04:02 PM PDT 24 |
| Peak memory | 160632 kb |
| Host | smart-761132c7-f4d8-40be-b01b-ce3b4408f51f |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3403324011 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_test.3403324011 |
| Directory | /workspace/39.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.3314456122 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 336770290000 ps |
| CPU time | 808.99 seconds |
| Started | Apr 21 12:38:45 PM PDT 24 |
| Finished | Apr 21 01:11:21 PM PDT 24 |
| Peak memory | 160696 kb |
| Host | smart-db0ac289-b1aa-4b8a-ae33-e01e248d4515 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3314456122 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_test.3314456122 |
| Directory | /workspace/4.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.2530156099 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 336804450000 ps |
| CPU time | 746.62 seconds |
| Started | Apr 21 12:38:50 PM PDT 24 |
| Finished | Apr 21 01:09:32 PM PDT 24 |
| Peak memory | 160784 kb |
| Host | smart-554d2a5f-8e92-43b0-8fd9-d71740ae97ac |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2530156099 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_test.2530156099 |
| Directory | /workspace/40.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.35724688 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 336342330000 ps |
| CPU time | 883.93 seconds |
| Started | Apr 21 12:38:44 PM PDT 24 |
| Finished | Apr 21 01:15:09 PM PDT 24 |
| Peak memory | 160696 kb |
| Host | smart-ad0cb679-1239-4840-a639-49b0e4ece1ab |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=35724688 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_test.35724688 |
| Directory | /workspace/41.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.1200166607 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 336321990000 ps |
| CPU time | 720.92 seconds |
| Started | Apr 21 12:38:52 PM PDT 24 |
| Finished | Apr 21 01:08:22 PM PDT 24 |
| Peak memory | 160716 kb |
| Host | smart-ef4d199b-3569-4d47-abf1-efb1f63e97e6 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1200166607 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_test.1200166607 |
| Directory | /workspace/42.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.956417321 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 336853550000 ps |
| CPU time | 658.43 seconds |
| Started | Apr 21 12:38:44 PM PDT 24 |
| Finished | Apr 21 01:06:04 PM PDT 24 |
| Peak memory | 160780 kb |
| Host | smart-a4d95866-b35f-42c2-805b-390142044402 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=956417321 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_test.956417321 |
| Directory | /workspace/43.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.2616547510 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 336712670000 ps |
| CPU time | 681.2 seconds |
| Started | Apr 21 12:38:51 PM PDT 24 |
| Finished | Apr 21 01:06:43 PM PDT 24 |
| Peak memory | 160804 kb |
| Host | smart-5c175a1c-dda8-44f3-908c-442d120c8353 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2616547510 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_test.2616547510 |
| Directory | /workspace/44.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.1353710052 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 336690750000 ps |
| CPU time | 844.6 seconds |
| Started | Apr 21 12:39:02 PM PDT 24 |
| Finished | Apr 21 01:13:54 PM PDT 24 |
| Peak memory | 160744 kb |
| Host | smart-7c844f8a-83e7-403c-aa05-1417e65386b1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1353710052 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_test.1353710052 |
| Directory | /workspace/45.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.922654893 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 336927150000 ps |
| CPU time | 929.45 seconds |
| Started | Apr 21 12:38:54 PM PDT 24 |
| Finished | Apr 21 01:16:21 PM PDT 24 |
| Peak memory | 160676 kb |
| Host | smart-693e0ca5-a5ad-44b9-8cdc-7a66c117ca3d |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=922654893 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_test.922654893 |
| Directory | /workspace/46.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.2259220133 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 337123910000 ps |
| CPU time | 719.77 seconds |
| Started | Apr 21 12:39:05 PM PDT 24 |
| Finished | Apr 21 01:09:02 PM PDT 24 |
| Peak memory | 160800 kb |
| Host | smart-51ad85c9-fc1b-4751-b72a-733e12ee4bd3 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2259220133 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_test.2259220133 |
| Directory | /workspace/47.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.102346954 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 336378330000 ps |
| CPU time | 903.38 seconds |
| Started | Apr 21 12:38:44 PM PDT 24 |
| Finished | Apr 21 01:15:24 PM PDT 24 |
| Peak memory | 160708 kb |
| Host | smart-68f98a5f-fada-4aec-a05f-8dabfdde010c |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=102346954 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_test.102346954 |
| Directory | /workspace/48.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.796763205 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 336741690000 ps |
| CPU time | 599.49 seconds |
| Started | Apr 21 12:39:02 PM PDT 24 |
| Finished | Apr 21 01:04:01 PM PDT 24 |
| Peak memory | 160792 kb |
| Host | smart-0ce75bd9-6a28-4f9d-9111-21d2149d5d7c |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=796763205 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_test.796763205 |
| Directory | /workspace/49.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.2262327104 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 336853750000 ps |
| CPU time | 894.76 seconds |
| Started | Apr 21 12:38:46 PM PDT 24 |
| Finished | Apr 21 01:15:30 PM PDT 24 |
| Peak memory | 160688 kb |
| Host | smart-8f1d7050-e56a-4aa2-937e-909f42517ed0 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2262327104 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_test.2262327104 |
| Directory | /workspace/5.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.3677121853 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 336686150000 ps |
| CPU time | 886.07 seconds |
| Started | Apr 21 12:38:53 PM PDT 24 |
| Finished | Apr 21 01:15:15 PM PDT 24 |
| Peak memory | 160716 kb |
| Host | smart-52d967e8-df4a-441d-b05a-f4803268f0b5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3677121853 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_test.3677121853 |
| Directory | /workspace/6.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.3094991505 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 336966470000 ps |
| CPU time | 887.06 seconds |
| Started | Apr 21 12:38:49 PM PDT 24 |
| Finished | Apr 21 01:15:04 PM PDT 24 |
| Peak memory | 160684 kb |
| Host | smart-620f9dee-3233-4c3d-8ceb-75ef4530fe51 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3094991505 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_test.3094991505 |
| Directory | /workspace/7.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.734484641 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 336858670000 ps |
| CPU time | 1014.81 seconds |
| Started | Apr 21 12:38:59 PM PDT 24 |
| Finished | Apr 21 01:21:29 PM PDT 24 |
| Peak memory | 160240 kb |
| Host | smart-5931afd6-c689-4394-9de3-6cf9ed95249c |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=734484641 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_test.734484641 |
| Directory | /workspace/8.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.3531626467 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 337019350000 ps |
| CPU time | 894.59 seconds |
| Started | Apr 21 12:38:48 PM PDT 24 |
| Finished | Apr 21 01:15:07 PM PDT 24 |
| Peak memory | 160684 kb |
| Host | smart-8875346b-58ab-4fbf-9905-2aa2a7bd3dd3 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3531626467 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_test.3531626467 |
| Directory | /workspace/9.prim_lfsr_fib_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.1456942446 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 336754090000 ps |
| CPU time | 658.25 seconds |
| Started | Apr 21 12:24:03 PM PDT 24 |
| Finished | Apr 21 12:51:48 PM PDT 24 |
| Peak memory | 160124 kb |
| Host | smart-bd42943b-8873-43e2-91d1-a38167558b3d |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1456942446 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_test.1456942446 |
| Directory | /workspace/1.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.4159315610 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 337023710000 ps |
| CPU time | 870.58 seconds |
| Started | Apr 21 12:22:33 PM PDT 24 |
| Finished | Apr 21 12:58:43 PM PDT 24 |
| Peak memory | 158620 kb |
| Host | smart-f470d174-188b-4a12-91e5-ecc71eeefa49 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4159315610 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_test.4159315610 |
| Directory | /workspace/10.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.2895890130 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 336368570000 ps |
| CPU time | 849.51 seconds |
| Started | Apr 21 12:18:38 PM PDT 24 |
| Finished | Apr 21 12:53:08 PM PDT 24 |
| Peak memory | 160660 kb |
| Host | smart-89055b23-ef3f-4321-bd67-defab9ac0f3a |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2895890130 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_test.2895890130 |
| Directory | /workspace/11.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.781413825 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 336865150000 ps |
| CPU time | 868.96 seconds |
| Started | Apr 21 12:22:34 PM PDT 24 |
| Finished | Apr 21 12:58:23 PM PDT 24 |
| Peak memory | 160088 kb |
| Host | smart-3f328a24-5df1-46fa-9adc-bb5149c0dadf |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=781413825 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_test.781413825 |
| Directory | /workspace/12.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.4001252384 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 336674070000 ps |
| CPU time | 890.71 seconds |
| Started | Apr 21 12:22:33 PM PDT 24 |
| Finished | Apr 21 12:59:18 PM PDT 24 |
| Peak memory | 158408 kb |
| Host | smart-d6d5d828-0707-4ca4-9aef-fa638640a77e |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4001252384 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_test.4001252384 |
| Directory | /workspace/13.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.1769629125 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 336644330000 ps |
| CPU time | 878.38 seconds |
| Started | Apr 21 12:22:33 PM PDT 24 |
| Finished | Apr 21 12:59:03 PM PDT 24 |
| Peak memory | 158492 kb |
| Host | smart-231b4f67-7269-43f3-8fa0-30fd3a0a23e5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1769629125 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_test.1769629125 |
| Directory | /workspace/14.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.952003814 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 336434250000 ps |
| CPU time | 842.46 seconds |
| Started | Apr 21 12:22:34 PM PDT 24 |
| Finished | Apr 21 12:57:33 PM PDT 24 |
| Peak memory | 160336 kb |
| Host | smart-d8d39828-5292-46c2-9339-c0b3ba7e0722 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=952003814 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_test.952003814 |
| Directory | /workspace/15.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.2004747027 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 336730630000 ps |
| CPU time | 575.69 seconds |
| Started | Apr 21 12:22:52 PM PDT 24 |
| Finished | Apr 21 12:46:50 PM PDT 24 |
| Peak memory | 160444 kb |
| Host | smart-1956a36a-765f-4708-813c-b836978c18f0 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2004747027 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_test.2004747027 |
| Directory | /workspace/16.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.423077727 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 336310790000 ps |
| CPU time | 850.93 seconds |
| Started | Apr 21 12:22:34 PM PDT 24 |
| Finished | Apr 21 12:57:43 PM PDT 24 |
| Peak memory | 160328 kb |
| Host | smart-36e559ad-f7f0-487e-8ae0-9a3421af3cc2 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=423077727 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_test.423077727 |
| Directory | /workspace/17.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.3893743313 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 336402530000 ps |
| CPU time | 840.16 seconds |
| Started | Apr 21 12:22:49 PM PDT 24 |
| Finished | Apr 21 12:57:53 PM PDT 24 |
| Peak memory | 160192 kb |
| Host | smart-8db3f09f-bd4f-479e-85e6-cd539c37966b |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3893743313 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_test.3893743313 |
| Directory | /workspace/18.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.1019623495 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 336741870000 ps |
| CPU time | 791.43 seconds |
| Started | Apr 21 12:22:49 PM PDT 24 |
| Finished | Apr 21 12:56:49 PM PDT 24 |
| Peak memory | 160192 kb |
| Host | smart-4cdbb12a-ea2b-4a10-b629-37853a7d473b |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1019623495 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_test.1019623495 |
| Directory | /workspace/19.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.3447691627 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 336611870000 ps |
| CPU time | 877.33 seconds |
| Started | Apr 21 12:23:31 PM PDT 24 |
| Finished | Apr 21 12:59:46 PM PDT 24 |
| Peak memory | 159020 kb |
| Host | smart-bc1f72e4-0e3d-4a00-8471-f7171c41a459 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3447691627 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_test.3447691627 |
| Directory | /workspace/2.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.1044329042 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 337012410000 ps |
| CPU time | 783.39 seconds |
| Started | Apr 21 12:20:15 PM PDT 24 |
| Finished | Apr 21 12:52:59 PM PDT 24 |
| Peak memory | 159320 kb |
| Host | smart-e16a1e2e-2434-41eb-bc29-fb896ad25165 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1044329042 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_test.1044329042 |
| Directory | /workspace/20.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.3027203667 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 336794970000 ps |
| CPU time | 836.47 seconds |
| Started | Apr 21 12:22:48 PM PDT 24 |
| Finished | Apr 21 12:57:46 PM PDT 24 |
| Peak memory | 160192 kb |
| Host | smart-822655d0-8f65-4da8-8981-5b7ffe65ee40 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3027203667 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_test.3027203667 |
| Directory | /workspace/21.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.3907988465 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 336874630000 ps |
| CPU time | 771.01 seconds |
| Started | Apr 21 12:20:23 PM PDT 24 |
| Finished | Apr 21 12:52:46 PM PDT 24 |
| Peak memory | 160240 kb |
| Host | smart-3fa8ec57-feda-410e-8cd9-0c7a78222ee2 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3907988465 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_test.3907988465 |
| Directory | /workspace/22.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.1891313013 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 336439950000 ps |
| CPU time | 826.77 seconds |
| Started | Apr 21 12:22:49 PM PDT 24 |
| Finished | Apr 21 12:57:31 PM PDT 24 |
| Peak memory | 160192 kb |
| Host | smart-03c1c6c5-1c68-4730-ae20-831269ca3f26 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1891313013 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_test.1891313013 |
| Directory | /workspace/23.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.3103941214 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 336990630000 ps |
| CPU time | 802.69 seconds |
| Started | Apr 21 12:20:23 PM PDT 24 |
| Finished | Apr 21 12:53:40 PM PDT 24 |
| Peak memory | 160240 kb |
| Host | smart-a2bf51c6-f523-40ba-a76c-9abc474907d7 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3103941214 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_test.3103941214 |
| Directory | /workspace/24.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.1855589815 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 336325210000 ps |
| CPU time | 811.25 seconds |
| Started | Apr 21 12:22:40 PM PDT 24 |
| Finished | Apr 21 12:56:59 PM PDT 24 |
| Peak memory | 159520 kb |
| Host | smart-0920725f-f605-49c0-aea3-1375240c5776 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1855589815 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_test.1855589815 |
| Directory | /workspace/25.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.14288407 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 336660910000 ps |
| CPU time | 810.13 seconds |
| Started | Apr 21 12:22:40 PM PDT 24 |
| Finished | Apr 21 12:57:00 PM PDT 24 |
| Peak memory | 158868 kb |
| Host | smart-817df41c-f2e0-408d-88d6-65bb50cf8d96 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=14288407 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_test.14288407 |
| Directory | /workspace/26.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.990056893 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 336407170000 ps |
| CPU time | 584.4 seconds |
| Started | Apr 21 12:22:46 PM PDT 24 |
| Finished | Apr 21 12:47:07 PM PDT 24 |
| Peak memory | 159588 kb |
| Host | smart-e7810166-38be-4da8-b4eb-c87cf322709b |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=990056893 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_test.990056893 |
| Directory | /workspace/27.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.3751375667 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 336666450000 ps |
| CPU time | 787.72 seconds |
| Started | Apr 21 12:20:15 PM PDT 24 |
| Finished | Apr 21 12:53:04 PM PDT 24 |
| Peak memory | 159304 kb |
| Host | smart-e3e68513-8400-4689-9c7d-f3b1d9cfb524 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3751375667 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_test.3751375667 |
| Directory | /workspace/28.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.3841484515 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 336484710000 ps |
| CPU time | 834.88 seconds |
| Started | Apr 21 12:23:01 PM PDT 24 |
| Finished | Apr 21 12:57:01 PM PDT 24 |
| Peak memory | 159616 kb |
| Host | smart-2f181955-1cea-45e9-b83d-c01834c48789 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3841484515 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_test.3841484515 |
| Directory | /workspace/29.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.3385539176 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 336279110000 ps |
| CPU time | 690.26 seconds |
| Started | Apr 21 12:21:44 PM PDT 24 |
| Finished | Apr 21 12:50:06 PM PDT 24 |
| Peak memory | 160628 kb |
| Host | smart-24fb0874-b7c4-4f96-98aa-7fead04da6e2 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3385539176 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_test.3385539176 |
| Directory | /workspace/3.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.1907005101 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 337077170000 ps |
| CPU time | 773.51 seconds |
| Started | Apr 21 12:20:24 PM PDT 24 |
| Finished | Apr 21 12:52:52 PM PDT 24 |
| Peak memory | 160240 kb |
| Host | smart-ee59a36b-09ad-4aab-8c49-bc42aa72add5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1907005101 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_test.1907005101 |
| Directory | /workspace/30.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.2034408758 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 336554870000 ps |
| CPU time | 806.01 seconds |
| Started | Apr 21 12:22:40 PM PDT 24 |
| Finished | Apr 21 12:56:57 PM PDT 24 |
| Peak memory | 158776 kb |
| Host | smart-4aaa807e-a3b6-4ef8-bc3f-40d199df7862 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2034408758 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_test.2034408758 |
| Directory | /workspace/31.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.2236818173 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 336737650000 ps |
| CPU time | 620.73 seconds |
| Started | Apr 21 12:23:52 PM PDT 24 |
| Finished | Apr 21 12:49:45 PM PDT 24 |
| Peak memory | 160608 kb |
| Host | smart-ed167d75-2e44-4b75-99a4-46c81b52e7c4 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2236818173 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_test.2236818173 |
| Directory | /workspace/32.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.600621692 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 336713290000 ps |
| CPU time | 614.96 seconds |
| Started | Apr 21 12:23:51 PM PDT 24 |
| Finished | Apr 21 12:49:23 PM PDT 24 |
| Peak memory | 160256 kb |
| Host | smart-f6dea174-406f-4f0e-a63d-a257a54fbd1e |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=600621692 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_test.600621692 |
| Directory | /workspace/33.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.1941107386 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 337035050000 ps |
| CPU time | 839.64 seconds |
| Started | Apr 21 12:23:00 PM PDT 24 |
| Finished | Apr 21 12:57:08 PM PDT 24 |
| Peak memory | 159188 kb |
| Host | smart-aeb8925d-1a52-4b4d-ba88-e91e123e5f94 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1941107386 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_test.1941107386 |
| Directory | /workspace/34.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.1890361245 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 336827350000 ps |
| CPU time | 551.69 seconds |
| Started | Apr 21 12:22:37 PM PDT 24 |
| Finished | Apr 21 12:45:47 PM PDT 24 |
| Peak memory | 159284 kb |
| Host | smart-a7b6547f-8902-4bc9-9a65-ea125417f512 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1890361245 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_test.1890361245 |
| Directory | /workspace/35.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.366763824 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 336760370000 ps |
| CPU time | 783.89 seconds |
| Started | Apr 21 12:23:32 PM PDT 24 |
| Finished | Apr 21 12:55:50 PM PDT 24 |
| Peak memory | 160240 kb |
| Host | smart-a48de7c6-bf09-46b5-8053-99dcfd1349cb |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=366763824 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_test.366763824 |
| Directory | /workspace/36.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.1590333205 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 336832230000 ps |
| CPU time | 758.22 seconds |
| Started | Apr 21 12:24:04 PM PDT 24 |
| Finished | Apr 21 12:55:27 PM PDT 24 |
| Peak memory | 160488 kb |
| Host | smart-a63dabdf-0531-4aeb-aa92-f4772467dfc0 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1590333205 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_test.1590333205 |
| Directory | /workspace/37.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.3993291928 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 337068170000 ps |
| CPU time | 634.72 seconds |
| Started | Apr 21 12:23:51 PM PDT 24 |
| Finished | Apr 21 12:50:13 PM PDT 24 |
| Peak memory | 159476 kb |
| Host | smart-0409f782-17c9-4fa0-ae5f-8e76e41fc8f6 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3993291928 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_test.3993291928 |
| Directory | /workspace/38.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.2696247741 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 336710230000 ps |
| CPU time | 570.48 seconds |
| Started | Apr 21 12:20:53 PM PDT 24 |
| Finished | Apr 21 12:44:50 PM PDT 24 |
| Peak memory | 159648 kb |
| Host | smart-176fd7ad-e187-430d-a3a2-9023d4521a0a |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2696247741 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_test.2696247741 |
| Directory | /workspace/39.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.2817448421 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 336463270000 ps |
| CPU time | 686.25 seconds |
| Started | Apr 21 12:21:44 PM PDT 24 |
| Finished | Apr 21 12:49:56 PM PDT 24 |
| Peak memory | 160628 kb |
| Host | smart-92f28f44-2c8c-4537-96cf-d476d3e236f5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2817448421 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_test.2817448421 |
| Directory | /workspace/4.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.1922904107 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 336731070000 ps |
| CPU time | 870.39 seconds |
| Started | Apr 21 12:18:54 PM PDT 24 |
| Finished | Apr 21 12:54:19 PM PDT 24 |
| Peak memory | 160660 kb |
| Host | smart-07caba30-de48-4509-b12d-87bc12d74d75 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1922904107 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_test.1922904107 |
| Directory | /workspace/40.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.2793305981 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 336387090000 ps |
| CPU time | 838.86 seconds |
| Started | Apr 21 12:23:03 PM PDT 24 |
| Finished | Apr 21 12:57:30 PM PDT 24 |
| Peak memory | 159760 kb |
| Host | smart-c0442d6c-da27-4efe-a2f4-773d7d561755 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2793305981 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_test.2793305981 |
| Directory | /workspace/41.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.2579058066 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 336699910000 ps |
| CPU time | 630.04 seconds |
| Started | Apr 21 12:23:59 PM PDT 24 |
| Finished | Apr 21 12:50:19 PM PDT 24 |
| Peak memory | 160660 kb |
| Host | smart-58b24ebc-403b-41a0-a433-d962c5d007da |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2579058066 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_test.2579058066 |
| Directory | /workspace/42.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.1571265454 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 337007130000 ps |
| CPU time | 783.88 seconds |
| Started | Apr 21 12:24:04 PM PDT 24 |
| Finished | Apr 21 12:56:21 PM PDT 24 |
| Peak memory | 160340 kb |
| Host | smart-6168dd85-bbc1-4e13-a326-13f318fc38ed |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1571265454 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_test.1571265454 |
| Directory | /workspace/43.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.147593834 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 336449970000 ps |
| CPU time | 798.5 seconds |
| Started | Apr 21 12:24:18 PM PDT 24 |
| Finished | Apr 21 12:57:18 PM PDT 24 |
| Peak memory | 160648 kb |
| Host | smart-6fd96d4d-684c-4463-a60b-99de3b69f0a4 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=147593834 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_test.147593834 |
| Directory | /workspace/44.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.45184167 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 337013630000 ps |
| CPU time | 835.7 seconds |
| Started | Apr 21 12:23:13 PM PDT 24 |
| Finished | Apr 21 12:57:54 PM PDT 24 |
| Peak memory | 160240 kb |
| Host | smart-966a14a9-00eb-4870-ba42-e0f3577c1302 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=45184167 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_test.45184167 |
| Directory | /workspace/45.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.3430240937 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 336591450000 ps |
| CPU time | 759.85 seconds |
| Started | Apr 21 12:23:32 PM PDT 24 |
| Finished | Apr 21 12:54:59 PM PDT 24 |
| Peak memory | 160480 kb |
| Host | smart-388a0753-6d54-4b7f-b144-54762d662881 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3430240937 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_test.3430240937 |
| Directory | /workspace/46.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.1173108675 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 336599630000 ps |
| CPU time | 723.64 seconds |
| Started | Apr 21 12:23:18 PM PDT 24 |
| Finished | Apr 21 12:52:52 PM PDT 24 |
| Peak memory | 159752 kb |
| Host | smart-275f6f90-696a-4bf4-a518-eb6e05130bb4 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1173108675 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_test.1173108675 |
| Directory | /workspace/47.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.842266350 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 336504510000 ps |
| CPU time | 821.15 seconds |
| Started | Apr 21 12:23:14 PM PDT 24 |
| Finished | Apr 21 12:57:21 PM PDT 24 |
| Peak memory | 160240 kb |
| Host | smart-7031694a-6e25-4fe6-b856-865067c49485 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=842266350 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_test.842266350 |
| Directory | /workspace/48.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.2439460245 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 336621950000 ps |
| CPU time | 818.34 seconds |
| Started | Apr 21 12:23:14 PM PDT 24 |
| Finished | Apr 21 12:57:09 PM PDT 24 |
| Peak memory | 160256 kb |
| Host | smart-006bbc56-3990-429d-97fb-26a3a1fce23a |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2439460245 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_test.2439460245 |
| Directory | /workspace/49.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.914794776 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 336449230000 ps |
| CPU time | 582.32 seconds |
| Started | Apr 21 12:23:38 PM PDT 24 |
| Finished | Apr 21 12:47:59 PM PDT 24 |
| Peak memory | 159384 kb |
| Host | smart-cdd72660-13f3-4ffc-a4de-f236046979de |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=914794776 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_test.914794776 |
| Directory | /workspace/5.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.2907131049 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 336376150000 ps |
| CPU time | 817.8 seconds |
| Started | Apr 21 12:23:32 PM PDT 24 |
| Finished | Apr 21 12:57:54 PM PDT 24 |
| Peak memory | 160216 kb |
| Host | smart-e897a1ea-5eb8-4071-92cf-a8d761ee2653 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2907131049 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_test.2907131049 |
| Directory | /workspace/6.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.292908461 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 336944410000 ps |
| CPU time | 844.08 seconds |
| Started | Apr 21 12:23:31 PM PDT 24 |
| Finished | Apr 21 12:58:45 PM PDT 24 |
| Peak memory | 160124 kb |
| Host | smart-013b8d3b-b5f1-49fd-b103-0e8a997e9270 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=292908461 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_test.292908461 |
| Directory | /workspace/7.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.3265342436 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 336419690000 ps |
| CPU time | 864.17 seconds |
| Started | Apr 21 12:23:31 PM PDT 24 |
| Finished | Apr 21 12:59:20 PM PDT 24 |
| Peak memory | 159040 kb |
| Host | smart-eb0a18f7-0068-4feb-b984-b03f118cff85 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3265342436 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_test.3265342436 |
| Directory | /workspace/8.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.2395587400 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 336479490000 ps |
| CPU time | 879.17 seconds |
| Started | Apr 21 12:22:33 PM PDT 24 |
| Finished | Apr 21 12:59:03 PM PDT 24 |
| Peak memory | 158396 kb |
| Host | smart-fd7252f9-7710-452a-ad47-7f4a29774659 |
| User | root |
| Command | /workspace/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2395587400 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_test.2395587400 |
| Directory | /workspace/9.prim_lfsr_gal_test/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.79157995 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 1465150000 ps |
| CPU time | 4.26 seconds |
| Started | Apr 21 12:23:31 PM PDT 24 |
| Finished | Apr 21 12:23:41 PM PDT 24 |
| Peak memory | 164224 kb |
| Host | smart-f953804b-22e1-4ccf-9ab2-645d08dacbf0 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=79157995 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_smoke.79157995 |
| Directory | /workspace/0.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.3059828345 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 1333950000 ps |
| CPU time | 3.3 seconds |
| Started | Apr 21 12:21:32 PM PDT 24 |
| Finished | Apr 21 12:21:39 PM PDT 24 |
| Peak memory | 164524 kb |
| Host | smart-6861098a-5ba6-48b5-a441-9a73e7ec7075 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3059828345 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_smoke.3059828345 |
| Directory | /workspace/1.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.1754000794 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 1622750000 ps |
| CPU time | 4.84 seconds |
| Started | Apr 21 12:20:22 PM PDT 24 |
| Finished | Apr 21 12:20:34 PM PDT 24 |
| Peak memory | 165872 kb |
| Host | smart-5874c9f2-310f-4104-be74-449353cd881e |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1754000794 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_smoke.1754000794 |
| Directory | /workspace/11.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.725404116 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 1243570000 ps |
| CPU time | 4.21 seconds |
| Started | Apr 21 12:20:22 PM PDT 24 |
| Finished | Apr 21 12:20:32 PM PDT 24 |
| Peak memory | 164224 kb |
| Host | smart-cca09f38-15e5-4120-8963-3f0e149eb5cb |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=725404116 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_smoke.725404116 |
| Directory | /workspace/12.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.403484097 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 1270590000 ps |
| CPU time | 4.1 seconds |
| Started | Apr 21 12:20:23 PM PDT 24 |
| Finished | Apr 21 12:20:33 PM PDT 24 |
| Peak memory | 164224 kb |
| Host | smart-9de217fb-01ea-469c-9614-bf2751c1f229 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=403484097 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_smoke.403484097 |
| Directory | /workspace/13.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.3408559158 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 1417770000 ps |
| CPU time | 4.18 seconds |
| Started | Apr 21 12:22:40 PM PDT 24 |
| Finished | Apr 21 12:22:51 PM PDT 24 |
| Peak memory | 162828 kb |
| Host | smart-d9d4541a-8fe8-4b32-8404-0e541b2036d9 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3408559158 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_smoke.3408559158 |
| Directory | /workspace/14.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.1599300824 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 1531530000 ps |
| CPU time | 3.64 seconds |
| Started | Apr 21 12:17:55 PM PDT 24 |
| Finished | Apr 21 12:18:03 PM PDT 24 |
| Peak memory | 164752 kb |
| Host | smart-f2f864f3-428e-4df0-a6dd-658fc05b3423 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1599300824 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_smoke.1599300824 |
| Directory | /workspace/15.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.1467696086 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 1483290000 ps |
| CPU time | 4.03 seconds |
| Started | Apr 21 12:20:43 PM PDT 24 |
| Finished | Apr 21 12:20:52 PM PDT 24 |
| Peak memory | 164800 kb |
| Host | smart-2df6d0d6-9236-4077-84a9-a8f8f3acb9c4 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1467696086 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_smoke.1467696086 |
| Directory | /workspace/16.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.2990794724 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 1352170000 ps |
| CPU time | 4.31 seconds |
| Started | Apr 21 12:20:23 PM PDT 24 |
| Finished | Apr 21 12:20:33 PM PDT 24 |
| Peak memory | 165872 kb |
| Host | smart-1d3ff4ff-dc91-45c9-ad05-1b79f4a3065f |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2990794724 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_smoke.2990794724 |
| Directory | /workspace/17.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.574798117 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 1482090000 ps |
| CPU time | 4.42 seconds |
| Started | Apr 21 12:20:15 PM PDT 24 |
| Finished | Apr 21 12:20:25 PM PDT 24 |
| Peak memory | 163656 kb |
| Host | smart-58efe768-c2f7-49bc-855b-42d4c86790ca |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=574798117 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_smoke.574798117 |
| Directory | /workspace/18.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.4245580484 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 1572370000 ps |
| CPU time | 4.25 seconds |
| Started | Apr 21 12:19:38 PM PDT 24 |
| Finished | Apr 21 12:19:48 PM PDT 24 |
| Peak memory | 164800 kb |
| Host | smart-c4f83c71-5d80-4e43-a511-4fe76852781c |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4245580484 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_smoke.4245580484 |
| Directory | /workspace/19.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.1459729991 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 1452970000 ps |
| CPU time | 4.2 seconds |
| Started | Apr 21 12:23:31 PM PDT 24 |
| Finished | Apr 21 12:23:41 PM PDT 24 |
| Peak memory | 163284 kb |
| Host | smart-7bfd0044-57be-460c-95dd-0815641637a0 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1459729991 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_smoke.1459729991 |
| Directory | /workspace/2.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.520294393 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 1194090000 ps |
| CPU time | 3.45 seconds |
| Started | Apr 21 12:23:02 PM PDT 24 |
| Finished | Apr 21 12:23:10 PM PDT 24 |
| Peak memory | 164772 kb |
| Host | smart-ac82e4db-817f-4278-afcf-df24109669f8 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=520294393 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_smoke.520294393 |
| Directory | /workspace/20.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.2545252512 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 1425910000 ps |
| CPU time | 3.98 seconds |
| Started | Apr 21 12:22:37 PM PDT 24 |
| Finished | Apr 21 12:22:47 PM PDT 24 |
| Peak memory | 162848 kb |
| Host | smart-40619bad-80f4-4b91-bf90-5132a674e90e |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2545252512 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_smoke.2545252512 |
| Directory | /workspace/21.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.2239933065 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 1539530000 ps |
| CPU time | 4.01 seconds |
| Started | Apr 21 12:21:32 PM PDT 24 |
| Finished | Apr 21 12:21:41 PM PDT 24 |
| Peak memory | 164796 kb |
| Host | smart-7ca7dd05-0e93-484c-a023-2c7ad7e4f41b |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2239933065 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_smoke.2239933065 |
| Directory | /workspace/22.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.2932018780 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 1467790000 ps |
| CPU time | 3.92 seconds |
| Started | Apr 21 12:22:38 PM PDT 24 |
| Finished | Apr 21 12:22:47 PM PDT 24 |
| Peak memory | 164280 kb |
| Host | smart-e12f7091-4ee7-4867-afdd-6dce3ea52a0c |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2932018780 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_smoke.2932018780 |
| Directory | /workspace/23.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.633612152 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 1445210000 ps |
| CPU time | 3.2 seconds |
| Started | Apr 21 12:19:30 PM PDT 24 |
| Finished | Apr 21 12:19:37 PM PDT 24 |
| Peak memory | 164524 kb |
| Host | smart-d4b05043-3060-49c9-b4c8-83f1db71f201 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=633612152 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_smoke.633612152 |
| Directory | /workspace/24.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.204523627 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 1493450000 ps |
| CPU time | 3.93 seconds |
| Started | Apr 21 12:22:39 PM PDT 24 |
| Finished | Apr 21 12:22:48 PM PDT 24 |
| Peak memory | 164532 kb |
| Host | smart-db40b05d-b4be-45d0-ba4a-55a83cd9f4d5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=204523627 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_smoke.204523627 |
| Directory | /workspace/25.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.3378547539 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 1552530000 ps |
| CPU time | 4.37 seconds |
| Started | Apr 21 12:23:09 PM PDT 24 |
| Finished | Apr 21 12:23:19 PM PDT 24 |
| Peak memory | 164744 kb |
| Host | smart-04442749-1148-4fd8-8ac2-7e73c9ea6102 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3378547539 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_smoke.3378547539 |
| Directory | /workspace/26.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.1920391382 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 1583170000 ps |
| CPU time | 4.31 seconds |
| Started | Apr 21 12:22:38 PM PDT 24 |
| Finished | Apr 21 12:22:48 PM PDT 24 |
| Peak memory | 164332 kb |
| Host | smart-8a26a3a2-7981-4493-b4c6-c4e59d268ac4 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1920391382 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_smoke.1920391382 |
| Directory | /workspace/27.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.1457414354 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 1460470000 ps |
| CPU time | 4.01 seconds |
| Started | Apr 21 12:21:03 PM PDT 24 |
| Finished | Apr 21 12:21:12 PM PDT 24 |
| Peak memory | 164952 kb |
| Host | smart-7175f5a9-51b1-4154-a739-397ba452085f |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1457414354 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_smoke.1457414354 |
| Directory | /workspace/28.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.2151100094 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 1418670000 ps |
| CPU time | 4.39 seconds |
| Started | Apr 21 12:20:28 PM PDT 24 |
| Finished | Apr 21 12:20:38 PM PDT 24 |
| Peak memory | 164740 kb |
| Host | smart-6dc1f770-32a9-42f8-b274-69232735966e |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2151100094 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_smoke.2151100094 |
| Directory | /workspace/29.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.611920491 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 1330190000 ps |
| CPU time | 3.42 seconds |
| Started | Apr 21 12:21:57 PM PDT 24 |
| Finished | Apr 21 12:22:05 PM PDT 24 |
| Peak memory | 164776 kb |
| Host | smart-94a42166-2d69-4862-a7fe-b5e3912b9a5d |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=611920491 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_smoke.611920491 |
| Directory | /workspace/3.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.4182405737 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 1461290000 ps |
| CPU time | 3.73 seconds |
| Started | Apr 21 12:20:32 PM PDT 24 |
| Finished | Apr 21 12:20:40 PM PDT 24 |
| Peak memory | 165044 kb |
| Host | smart-f0926e79-6f4d-4e8f-bd0c-3ccb98e01d13 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4182405737 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_smoke.4182405737 |
| Directory | /workspace/30.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.1443161226 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 1408870000 ps |
| CPU time | 3.29 seconds |
| Started | Apr 21 12:22:35 PM PDT 24 |
| Finished | Apr 21 12:22:44 PM PDT 24 |
| Peak memory | 163656 kb |
| Host | smart-def212f0-c0b8-4a21-9d67-dca2dbbf9ef3 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1443161226 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_smoke.1443161226 |
| Directory | /workspace/31.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.3307425084 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 1491610000 ps |
| CPU time | 4.6 seconds |
| Started | Apr 21 12:20:27 PM PDT 24 |
| Finished | Apr 21 12:20:37 PM PDT 24 |
| Peak memory | 164740 kb |
| Host | smart-9ccbbab3-dae2-430f-bf3f-ed47076c6a12 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3307425084 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_smoke.3307425084 |
| Directory | /workspace/32.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.1573337243 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 1241230000 ps |
| CPU time | 4.18 seconds |
| Started | Apr 21 12:19:46 PM PDT 24 |
| Finished | Apr 21 12:19:56 PM PDT 24 |
| Peak memory | 164816 kb |
| Host | smart-420f0003-f57c-4042-8a81-8ecfca5e5f4f |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1573337243 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_smoke.1573337243 |
| Directory | /workspace/33.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.3991244939 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 1381430000 ps |
| CPU time | 3.36 seconds |
| Started | Apr 21 12:22:54 PM PDT 24 |
| Finished | Apr 21 12:23:02 PM PDT 24 |
| Peak memory | 163500 kb |
| Host | smart-17dfe24f-2f61-4aa8-b98e-11242c9d41ea |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3991244939 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_smoke.3991244939 |
| Directory | /workspace/34.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.722725843 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 1568750000 ps |
| CPU time | 3.96 seconds |
| Started | Apr 21 12:19:49 PM PDT 24 |
| Finished | Apr 21 12:19:58 PM PDT 24 |
| Peak memory | 164796 kb |
| Host | smart-4feb9151-4ac2-4e4b-9c20-a6dce2dfe333 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=722725843 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_smoke.722725843 |
| Directory | /workspace/35.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.1601683242 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 1475870000 ps |
| CPU time | 4.14 seconds |
| Started | Apr 21 12:22:58 PM PDT 24 |
| Finished | Apr 21 12:23:07 PM PDT 24 |
| Peak memory | 164448 kb |
| Host | smart-37174d73-5393-48de-8f1d-f53903e281d5 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1601683242 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_smoke.1601683242 |
| Directory | /workspace/36.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.541272411 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 1419790000 ps |
| CPU time | 4.07 seconds |
| Started | Apr 21 12:22:57 PM PDT 24 |
| Finished | Apr 21 12:23:06 PM PDT 24 |
| Peak memory | 163552 kb |
| Host | smart-993de359-8005-4511-ab53-c683d9c8fe2e |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=541272411 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_smoke.541272411 |
| Directory | /workspace/37.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.1432065643 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 1509250000 ps |
| CPU time | 3.61 seconds |
| Started | Apr 21 12:19:47 PM PDT 24 |
| Finished | Apr 21 12:19:55 PM PDT 24 |
| Peak memory | 165044 kb |
| Host | smart-aabc9834-2124-495a-9119-48690bf82698 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1432065643 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_smoke.1432065643 |
| Directory | /workspace/38.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.188314048 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 1566150000 ps |
| CPU time | 4.97 seconds |
| Started | Apr 21 12:22:48 PM PDT 24 |
| Finished | Apr 21 12:23:00 PM PDT 24 |
| Peak memory | 164220 kb |
| Host | smart-3595fd68-752f-4461-9daf-9b05f3a1fd1c |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=188314048 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_smoke.188314048 |
| Directory | /workspace/39.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.611423986 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 1555530000 ps |
| CPU time | 3.89 seconds |
| Started | Apr 21 12:23:51 PM PDT 24 |
| Finished | Apr 21 12:24:00 PM PDT 24 |
| Peak memory | 165988 kb |
| Host | smart-564c63a9-ea15-464b-b57c-6292e360d4f7 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=611423986 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_smoke.611423986 |
| Directory | /workspace/4.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.1873262531 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 1484450000 ps |
| CPU time | 4.64 seconds |
| Started | Apr 21 12:22:34 PM PDT 24 |
| Finished | Apr 21 12:22:45 PM PDT 24 |
| Peak memory | 164124 kb |
| Host | smart-d3e7b626-f639-4a32-8f01-2fc625502f8c |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1873262531 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_smoke.1873262531 |
| Directory | /workspace/40.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.1441355608 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 1341630000 ps |
| CPU time | 3.89 seconds |
| Started | Apr 21 12:19:57 PM PDT 24 |
| Finished | Apr 21 12:20:06 PM PDT 24 |
| Peak memory | 164740 kb |
| Host | smart-eb6cd1e7-4804-4a6d-b182-4074fc2be2eb |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1441355608 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_smoke.1441355608 |
| Directory | /workspace/41.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.1070230266 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 1419490000 ps |
| CPU time | 3.5 seconds |
| Started | Apr 21 12:19:54 PM PDT 24 |
| Finished | Apr 21 12:20:02 PM PDT 24 |
| Peak memory | 164800 kb |
| Host | smart-e442c8ba-1aa5-4f40-ae46-95c4ba2cc375 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1070230266 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_smoke.1070230266 |
| Directory | /workspace/42.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.1170964951 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 1451470000 ps |
| CPU time | 3.87 seconds |
| Started | Apr 21 12:22:48 PM PDT 24 |
| Finished | Apr 21 12:22:57 PM PDT 24 |
| Peak memory | 164296 kb |
| Host | smart-7124f1a0-5c4d-4865-a92e-f7b41c4bd5ff |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1170964951 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_smoke.1170964951 |
| Directory | /workspace/43.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.2473560138 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 1539750000 ps |
| CPU time | 3.97 seconds |
| Started | Apr 21 12:22:48 PM PDT 24 |
| Finished | Apr 21 12:22:58 PM PDT 24 |
| Peak memory | 164188 kb |
| Host | smart-3271247f-028c-4e5a-99f6-75fcd5937119 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2473560138 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_smoke.2473560138 |
| Directory | /workspace/44.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.1352837876 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 1301550000 ps |
| CPU time | 4.33 seconds |
| Started | Apr 21 12:21:17 PM PDT 24 |
| Finished | Apr 21 12:21:27 PM PDT 24 |
| Peak memory | 162860 kb |
| Host | smart-cdfaebf9-41d7-45bc-a4e1-0280494debac |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1352837876 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_smoke.1352837876 |
| Directory | /workspace/45.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.4033694916 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 1407710000 ps |
| CPU time | 4.05 seconds |
| Started | Apr 21 12:22:40 PM PDT 24 |
| Finished | Apr 21 12:22:50 PM PDT 24 |
| Peak memory | 163572 kb |
| Host | smart-8b499496-9f2c-4ce5-8407-a9ec3081ffd4 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4033694916 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_smoke.4033694916 |
| Directory | /workspace/46.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.3983369402 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 1504970000 ps |
| CPU time | 3.03 seconds |
| Started | Apr 21 12:23:38 PM PDT 24 |
| Finished | Apr 21 12:23:46 PM PDT 24 |
| Peak memory | 164344 kb |
| Host | smart-ecdf9ee5-5cfe-481d-a342-f4c2760f00bd |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3983369402 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_smoke.3983369402 |
| Directory | /workspace/47.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.347456351 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 1574550000 ps |
| CPU time | 4.84 seconds |
| Started | Apr 21 12:22:35 PM PDT 24 |
| Finished | Apr 21 12:22:47 PM PDT 24 |
| Peak memory | 164428 kb |
| Host | smart-7ac9cee6-21cc-40c1-b1fe-89702bb59513 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=347456351 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_smoke.347456351 |
| Directory | /workspace/48.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.1898089476 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 1289450000 ps |
| CPU time | 3.71 seconds |
| Started | Apr 21 12:22:46 PM PDT 24 |
| Finished | Apr 21 12:22:56 PM PDT 24 |
| Peak memory | 162920 kb |
| Host | smart-00ec120d-080e-4b71-a3ad-e1757a5b0c2c |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1898089476 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_smoke.1898089476 |
| Directory | /workspace/49.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.4096793434 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 1488310000 ps |
| CPU time | 5.17 seconds |
| Started | Apr 21 12:20:30 PM PDT 24 |
| Finished | Apr 21 12:20:42 PM PDT 24 |
| Peak memory | 164816 kb |
| Host | smart-c5caca54-bb4e-41ac-b1cd-4d6113dc3d2d |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4096793434 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_smoke.4096793434 |
| Directory | /workspace/5.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.1236183826 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 1318490000 ps |
| CPU time | 4.02 seconds |
| Started | Apr 21 12:23:51 PM PDT 24 |
| Finished | Apr 21 12:24:00 PM PDT 24 |
| Peak memory | 163000 kb |
| Host | smart-17788b37-25bc-4e7a-83d0-2f69bfde0423 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1236183826 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_smoke.1236183826 |
| Directory | /workspace/6.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.2472617380 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 1455290000 ps |
| CPU time | 4.31 seconds |
| Started | Apr 21 12:22:41 PM PDT 24 |
| Finished | Apr 21 12:22:51 PM PDT 24 |
| Peak memory | 164132 kb |
| Host | smart-e946bcf4-8382-4bc6-acd3-a25d985c2948 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2472617380 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_smoke.2472617380 |
| Directory | /workspace/7.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.1906182618 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 1358490000 ps |
| CPU time | 3.96 seconds |
| Started | Apr 21 12:18:50 PM PDT 24 |
| Finished | Apr 21 12:18:59 PM PDT 24 |
| Peak memory | 165012 kb |
| Host | smart-2de90d31-a6aa-49fd-9387-a27d64fc44cd |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1906182618 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_smoke.1906182618 |
| Directory | /workspace/8.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.2375326029 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 1411470000 ps |
| CPU time | 3.86 seconds |
| Started | Apr 21 12:23:51 PM PDT 24 |
| Finished | Apr 21 12:24:00 PM PDT 24 |
| Peak memory | 162892 kb |
| Host | smart-1f1611e9-e420-4e54-b4d3-ef7f2050ad75 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2375326029 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_smoke.2375326029 |
| Directory | /workspace/9.prim_lfsr_fib_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.3141263789 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 1558670000 ps |
| CPU time | 4.49 seconds |
| Started | Apr 21 12:22:46 PM PDT 24 |
| Finished | Apr 21 12:22:58 PM PDT 24 |
| Peak memory | 162996 kb |
| Host | smart-6578f33b-28be-4118-9042-7c89b47e9464 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3141263789 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_smoke.3141263789 |
| Directory | /workspace/0.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.1397468617 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 1537710000 ps |
| CPU time | 4.01 seconds |
| Started | Apr 21 12:22:47 PM PDT 24 |
| Finished | Apr 21 12:22:57 PM PDT 24 |
| Peak memory | 164348 kb |
| Host | smart-b6e4a619-8bbe-4de3-a81d-d5470f447a01 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1397468617 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_smoke.1397468617 |
| Directory | /workspace/1.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.4092403610 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 1238590000 ps |
| CPU time | 3.74 seconds |
| Started | Apr 21 12:23:02 PM PDT 24 |
| Finished | Apr 21 12:23:11 PM PDT 24 |
| Peak memory | 164712 kb |
| Host | smart-6e8299b5-fed1-434f-9bc0-67125b837f34 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4092403610 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_smoke.4092403610 |
| Directory | /workspace/10.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.899616878 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 1578390000 ps |
| CPU time | 3.61 seconds |
| Started | Apr 21 12:19:55 PM PDT 24 |
| Finished | Apr 21 12:20:04 PM PDT 24 |
| Peak memory | 164796 kb |
| Host | smart-fed9c31e-1610-4c05-98cb-b3ebb604818f |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=899616878 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_smoke.899616878 |
| Directory | /workspace/11.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.769565400 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 1540230000 ps |
| CPU time | 4.25 seconds |
| Started | Apr 21 12:20:01 PM PDT 24 |
| Finished | Apr 21 12:20:11 PM PDT 24 |
| Peak memory | 164796 kb |
| Host | smart-27689868-405c-4fac-b1c4-647c525f598c |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=769565400 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_smoke.769565400 |
| Directory | /workspace/13.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.2659808198 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 1503010000 ps |
| CPU time | 4.49 seconds |
| Started | Apr 21 12:20:09 PM PDT 24 |
| Finished | Apr 21 12:20:19 PM PDT 24 |
| Peak memory | 164800 kb |
| Host | smart-60fd3050-906a-4cb5-9746-feaabfb02700 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2659808198 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_smoke.2659808198 |
| Directory | /workspace/14.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.2039188010 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 1353530000 ps |
| CPU time | 3.34 seconds |
| Started | Apr 21 12:22:54 PM PDT 24 |
| Finished | Apr 21 12:23:02 PM PDT 24 |
| Peak memory | 163428 kb |
| Host | smart-97dc250d-1497-4743-b00c-e6c08f9b4e9c |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2039188010 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_smoke.2039188010 |
| Directory | /workspace/15.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.2360477940 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 1533630000 ps |
| CPU time | 3.67 seconds |
| Started | Apr 21 12:22:02 PM PDT 24 |
| Finished | Apr 21 12:22:11 PM PDT 24 |
| Peak memory | 164772 kb |
| Host | smart-188a6af4-ef0e-468f-a2dd-5e594b648070 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2360477940 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_smoke.2360477940 |
| Directory | /workspace/16.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.1300231964 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 1303450000 ps |
| CPU time | 3.25 seconds |
| Started | Apr 21 12:20:09 PM PDT 24 |
| Finished | Apr 21 12:20:16 PM PDT 24 |
| Peak memory | 164740 kb |
| Host | smart-f80d761c-b728-4c01-898a-b81104838b51 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1300231964 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_smoke.1300231964 |
| Directory | /workspace/17.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.3323579599 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 1568090000 ps |
| CPU time | 3.53 seconds |
| Started | Apr 21 12:22:54 PM PDT 24 |
| Finished | Apr 21 12:23:02 PM PDT 24 |
| Peak memory | 163244 kb |
| Host | smart-bdca64ee-0f72-4201-b829-2b75fbdbed1c |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3323579599 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_smoke.3323579599 |
| Directory | /workspace/18.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.2811012936 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 1643450000 ps |
| CPU time | 4.39 seconds |
| Started | Apr 21 12:23:09 PM PDT 24 |
| Finished | Apr 21 12:23:19 PM PDT 24 |
| Peak memory | 164744 kb |
| Host | smart-57906773-c001-49cc-9c42-683866dd758f |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2811012936 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_smoke.2811012936 |
| Directory | /workspace/19.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.660806906 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 1435250000 ps |
| CPU time | 4.35 seconds |
| Started | Apr 21 12:20:23 PM PDT 24 |
| Finished | Apr 21 12:20:33 PM PDT 24 |
| Peak memory | 164224 kb |
| Host | smart-1af3891d-46d1-4634-bf24-cad824c806b8 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=660806906 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_smoke.660806906 |
| Directory | /workspace/2.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.2581727631 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 1244070000 ps |
| CPU time | 3.77 seconds |
| Started | Apr 21 12:23:10 PM PDT 24 |
| Finished | Apr 21 12:23:18 PM PDT 24 |
| Peak memory | 164720 kb |
| Host | smart-706781df-fcb4-43f8-bc82-dff157065439 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2581727631 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_smoke.2581727631 |
| Directory | /workspace/20.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.4011418161 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 1523110000 ps |
| CPU time | 3.45 seconds |
| Started | Apr 21 12:23:51 PM PDT 24 |
| Finished | Apr 21 12:23:59 PM PDT 24 |
| Peak memory | 163972 kb |
| Host | smart-9789b761-69c0-490f-a55d-3578500c14ac |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4011418161 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_smoke.4011418161 |
| Directory | /workspace/21.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.1979245705 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 1459830000 ps |
| CPU time | 3.15 seconds |
| Started | Apr 21 12:23:47 PM PDT 24 |
| Finished | Apr 21 12:23:55 PM PDT 24 |
| Peak memory | 162616 kb |
| Host | smart-bf99bef8-17db-4915-bb48-b87854c601cf |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1979245705 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_smoke.1979245705 |
| Directory | /workspace/22.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.2975370559 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 1436050000 ps |
| CPU time | 3.61 seconds |
| Started | Apr 21 12:23:52 PM PDT 24 |
| Finished | Apr 21 12:24:05 PM PDT 24 |
| Peak memory | 164224 kb |
| Host | smart-5a3c2739-7896-4358-a805-2788342b32e3 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2975370559 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_smoke.2975370559 |
| Directory | /workspace/23.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.2235480490 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 1468250000 ps |
| CPU time | 3.28 seconds |
| Started | Apr 21 12:23:47 PM PDT 24 |
| Finished | Apr 21 12:23:55 PM PDT 24 |
| Peak memory | 162676 kb |
| Host | smart-ff1f1c87-3c8b-4cf3-b8f0-318c58e36d19 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2235480490 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_smoke.2235480490 |
| Directory | /workspace/24.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.4079845714 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 1553770000 ps |
| CPU time | 4.35 seconds |
| Started | Apr 21 12:20:16 PM PDT 24 |
| Finished | Apr 21 12:20:25 PM PDT 24 |
| Peak memory | 164756 kb |
| Host | smart-a246d34c-bd40-46c3-a70d-ecc103f3535c |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4079845714 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_smoke.4079845714 |
| Directory | /workspace/25.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.2497039835 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 1565110000 ps |
| CPU time | 3.9 seconds |
| Started | Apr 21 12:22:41 PM PDT 24 |
| Finished | Apr 21 12:22:51 PM PDT 24 |
| Peak memory | 164656 kb |
| Host | smart-9bf13967-91b6-4440-a48b-28655ec8eac1 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2497039835 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_smoke.2497039835 |
| Directory | /workspace/26.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.2667295510 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 1449310000 ps |
| CPU time | 3.49 seconds |
| Started | Apr 21 12:20:25 PM PDT 24 |
| Finished | Apr 21 12:20:33 PM PDT 24 |
| Peak memory | 164524 kb |
| Host | smart-56a612f7-75a2-4b56-891a-9f859ee71cfb |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2667295510 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_smoke.2667295510 |
| Directory | /workspace/27.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.3036397243 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 1324370000 ps |
| CPU time | 2.65 seconds |
| Started | Apr 21 12:22:37 PM PDT 24 |
| Finished | Apr 21 12:22:44 PM PDT 24 |
| Peak memory | 164492 kb |
| Host | smart-0bbb5836-8ddd-4ab9-8b42-5cd71e88a6a9 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3036397243 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_smoke.3036397243 |
| Directory | /workspace/28.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.2810073400 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 1349450000 ps |
| CPU time | 4.54 seconds |
| Started | Apr 21 12:24:02 PM PDT 24 |
| Finished | Apr 21 12:24:13 PM PDT 24 |
| Peak memory | 163848 kb |
| Host | smart-ce92be3c-b391-4c85-b258-8bb5ae9c02d4 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2810073400 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_smoke.2810073400 |
| Directory | /workspace/29.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.1134623723 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 1500970000 ps |
| CPU time | 5.1 seconds |
| Started | Apr 21 12:23:01 PM PDT 24 |
| Finished | Apr 21 12:23:13 PM PDT 24 |
| Peak memory | 163308 kb |
| Host | smart-67803242-ad7a-4574-b6b2-3e3cb4dd5363 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1134623723 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_smoke.1134623723 |
| Directory | /workspace/3.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.2251236975 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 1557450000 ps |
| CPU time | 4.85 seconds |
| Started | Apr 21 12:24:02 PM PDT 24 |
| Finished | Apr 21 12:24:14 PM PDT 24 |
| Peak memory | 163240 kb |
| Host | smart-396fa1c8-6a9d-4b14-8cfe-213182af463b |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2251236975 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_smoke.2251236975 |
| Directory | /workspace/30.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.397460711 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 1368070000 ps |
| CPU time | 3.52 seconds |
| Started | Apr 21 12:22:41 PM PDT 24 |
| Finished | Apr 21 12:22:50 PM PDT 24 |
| Peak memory | 164548 kb |
| Host | smart-9b9c5602-3e49-44b4-8deb-3b4fe1a8da40 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=397460711 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_smoke.397460711 |
| Directory | /workspace/31.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.3061898545 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 1373910000 ps |
| CPU time | 3.29 seconds |
| Started | Apr 21 12:22:29 PM PDT 24 |
| Finished | Apr 21 12:22:37 PM PDT 24 |
| Peak memory | 164344 kb |
| Host | smart-90b8e5c1-9a5b-443f-aee2-555ee8b878ea |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3061898545 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_smoke.3061898545 |
| Directory | /workspace/32.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.4230825939 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 1628470000 ps |
| CPU time | 4.5 seconds |
| Started | Apr 21 12:21:51 PM PDT 24 |
| Finished | Apr 21 12:22:01 PM PDT 24 |
| Peak memory | 164748 kb |
| Host | smart-85725e79-a7f0-4f4e-841c-ecd4e9295a83 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4230825939 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_smoke.4230825939 |
| Directory | /workspace/33.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.1270666035 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 1533530000 ps |
| CPU time | 3.16 seconds |
| Started | Apr 21 12:23:37 PM PDT 24 |
| Finished | Apr 21 12:23:44 PM PDT 24 |
| Peak memory | 164444 kb |
| Host | smart-2aa0529a-84fc-4e0c-958d-6044aa4cf829 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1270666035 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_smoke.1270666035 |
| Directory | /workspace/34.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.1045752761 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 1305010000 ps |
| CPU time | 3.51 seconds |
| Started | Apr 21 12:22:41 PM PDT 24 |
| Finished | Apr 21 12:22:49 PM PDT 24 |
| Peak memory | 164492 kb |
| Host | smart-8ff86c7a-1ece-49af-bd0f-7cfa920d6e2a |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1045752761 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_smoke.1045752761 |
| Directory | /workspace/35.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.922130021 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 1473610000 ps |
| CPU time | 3.06 seconds |
| Started | Apr 21 12:23:47 PM PDT 24 |
| Finished | Apr 21 12:23:54 PM PDT 24 |
| Peak memory | 163652 kb |
| Host | smart-d0f575f0-1e82-460c-94bc-4c1b918f073f |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=922130021 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_smoke.922130021 |
| Directory | /workspace/36.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.900716485 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 1258410000 ps |
| CPU time | 2.9 seconds |
| Started | Apr 21 12:23:47 PM PDT 24 |
| Finished | Apr 21 12:23:54 PM PDT 24 |
| Peak memory | 162816 kb |
| Host | smart-e6db928c-32dc-4f47-b0ec-0bb7e6e5d644 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=900716485 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_smoke.900716485 |
| Directory | /workspace/37.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.1803906560 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 1549890000 ps |
| CPU time | 4.37 seconds |
| Started | Apr 21 12:20:28 PM PDT 24 |
| Finished | Apr 21 12:20:38 PM PDT 24 |
| Peak memory | 164784 kb |
| Host | smart-20519c54-4fcd-43fa-9f25-aee73bc1c81e |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1803906560 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_smoke.1803906560 |
| Directory | /workspace/38.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.3288249453 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 1439610000 ps |
| CPU time | 3 seconds |
| Started | Apr 21 12:23:28 PM PDT 24 |
| Finished | Apr 21 12:23:36 PM PDT 24 |
| Peak memory | 164384 kb |
| Host | smart-a7e1bb5d-7848-4115-8d98-c924109d2603 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3288249453 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_smoke.3288249453 |
| Directory | /workspace/39.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.51089520 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 1492030000 ps |
| CPU time | 3.32 seconds |
| Started | Apr 21 12:21:20 PM PDT 24 |
| Finished | Apr 21 12:21:28 PM PDT 24 |
| Peak memory | 164732 kb |
| Host | smart-2197a04e-eca3-4624-9dd8-bf877c834bad |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=51089520 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_smoke.51089520 |
| Directory | /workspace/4.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.63101036 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 1438050000 ps |
| CPU time | 3.92 seconds |
| Started | Apr 21 12:20:48 PM PDT 24 |
| Finished | Apr 21 12:20:57 PM PDT 24 |
| Peak memory | 164716 kb |
| Host | smart-de652632-a293-422a-878a-696087f646fb |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=63101036 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_smoke.63101036 |
| Directory | /workspace/40.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.4165477605 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 1547830000 ps |
| CPU time | 4.07 seconds |
| Started | Apr 21 12:23:38 PM PDT 24 |
| Finished | Apr 21 12:23:48 PM PDT 24 |
| Peak memory | 163360 kb |
| Host | smart-4b628ea5-43e9-4b35-81df-1f948108399a |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4165477605 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_smoke.4165477605 |
| Directory | /workspace/41.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.1385099894 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 1494270000 ps |
| CPU time | 5.31 seconds |
| Started | Apr 21 12:21:17 PM PDT 24 |
| Finished | Apr 21 12:21:29 PM PDT 24 |
| Peak memory | 162616 kb |
| Host | smart-35626110-07b7-4ca3-b1e9-8d63793a1124 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1385099894 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_smoke.1385099894 |
| Directory | /workspace/42.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.2916728035 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 1377910000 ps |
| CPU time | 4.86 seconds |
| Started | Apr 21 12:21:17 PM PDT 24 |
| Finished | Apr 21 12:21:28 PM PDT 24 |
| Peak memory | 162708 kb |
| Host | smart-30a2dfb3-f680-44d2-87f5-0be712d1ac73 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2916728035 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_smoke.2916728035 |
| Directory | /workspace/43.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.4020495066 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 1636130000 ps |
| CPU time | 3.1 seconds |
| Started | Apr 21 12:24:28 PM PDT 24 |
| Finished | Apr 21 12:24:35 PM PDT 24 |
| Peak memory | 164340 kb |
| Host | smart-19b36782-1c21-4410-bc2a-19798da85891 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4020495066 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_smoke.4020495066 |
| Directory | /workspace/44.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.1551197731 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 1508250000 ps |
| CPU time | 5.17 seconds |
| Started | Apr 21 12:20:40 PM PDT 24 |
| Finished | Apr 21 12:20:52 PM PDT 24 |
| Peak memory | 164816 kb |
| Host | smart-85308964-b64f-4fa2-920e-5964ee52a011 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1551197731 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_smoke.1551197731 |
| Directory | /workspace/45.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.4060601620 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 1517150000 ps |
| CPU time | 3.43 seconds |
| Started | Apr 21 12:21:44 PM PDT 24 |
| Finished | Apr 21 12:21:52 PM PDT 24 |
| Peak memory | 164772 kb |
| Host | smart-d816f281-dfdf-4d07-8d75-c5cfa48ad929 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4060601620 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_smoke.4060601620 |
| Directory | /workspace/46.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.686618359 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 1337910000 ps |
| CPU time | 4.05 seconds |
| Started | Apr 21 12:23:31 PM PDT 24 |
| Finished | Apr 21 12:23:40 PM PDT 24 |
| Peak memory | 163856 kb |
| Host | smart-62f38cb1-372a-4278-a718-825d15dda24e |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=686618359 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_smoke.686618359 |
| Directory | /workspace/47.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.2051068172 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 1575030000 ps |
| CPU time | 3.94 seconds |
| Started | Apr 21 12:23:01 PM PDT 24 |
| Finished | Apr 21 12:23:10 PM PDT 24 |
| Peak memory | 164788 kb |
| Host | smart-ba504d2f-6272-4e31-a079-b1959336cfcf |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2051068172 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_smoke.2051068172 |
| Directory | /workspace/48.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.2880268454 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 1371590000 ps |
| CPU time | 3.41 seconds |
| Started | Apr 21 12:22:41 PM PDT 24 |
| Finished | Apr 21 12:22:50 PM PDT 24 |
| Peak memory | 164504 kb |
| Host | smart-c8a1676b-0531-4eda-ae90-09c52e5dbeb6 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2880268454 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_smoke.2880268454 |
| Directory | /workspace/49.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.3455104693 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 1490190000 ps |
| CPU time | 3.2 seconds |
| Started | Apr 21 12:21:20 PM PDT 24 |
| Finished | Apr 21 12:21:28 PM PDT 24 |
| Peak memory | 164792 kb |
| Host | smart-eb944856-1bc7-4b16-b1da-91c5ddde7ffa |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3455104693 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_smoke.3455104693 |
| Directory | /workspace/5.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.153938550 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 1482290000 ps |
| CPU time | 3.98 seconds |
| Started | Apr 21 12:22:47 PM PDT 24 |
| Finished | Apr 21 12:22:57 PM PDT 24 |
| Peak memory | 165896 kb |
| Host | smart-b95ccb75-2097-4de3-ada2-d99ff2ecc57a |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=153938550 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_smoke.153938550 |
| Directory | /workspace/6.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.765657828 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 1458010000 ps |
| CPU time | 3.77 seconds |
| Started | Apr 21 12:22:37 PM PDT 24 |
| Finished | Apr 21 12:22:47 PM PDT 24 |
| Peak memory | 162888 kb |
| Host | smart-6319b16e-a129-43e6-89b3-36d1a6eb3db9 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=765657828 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_smoke.765657828 |
| Directory | /workspace/7.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.1294461071 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 1462610000 ps |
| CPU time | 3.72 seconds |
| Started | Apr 21 12:17:58 PM PDT 24 |
| Finished | Apr 21 12:18:07 PM PDT 24 |
| Peak memory | 164812 kb |
| Host | smart-01f67cfa-3d04-45c3-af3f-bcdf1917a34f |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1294461071 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_smoke.1294461071 |
| Directory | /workspace/8.prim_lfsr_gal_smoke/latest |
| Test location | /workspace/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.4114906167 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 1372830000 ps |
| CPU time | 3.86 seconds |
| Started | Apr 21 12:18:45 PM PDT 24 |
| Finished | Apr 21 12:18:53 PM PDT 24 |
| Peak memory | 164852 kb |
| Host | smart-b01c47c1-fb9a-43bf-be44-1381cfb3fc29 |
| User | root |
| Command | /workspace/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4114906167 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_smoke.4114906167 |
| Directory | /workspace/9.prim_lfsr_gal_smoke/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |