Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.31 100.00 96.55 100.00 100.00 95.00


Total tests in report: 200
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
87.31 87.31 100.00 100.00 96.55 96.55 100.00 100.00 100.00 100.00 40.00 40.00 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.1322076757
96.81 9.50 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 87.50 47.50 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.3555659664
98.31 1.50 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 95.00 7.50 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.2192862722

Tests that do not contribute to grading

Name   
/workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.353553759
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/workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.2736080581
/workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.543669062
/workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.1666493412
/workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.1885169135
/workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.546585993
/workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.311624099
/workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.494768602
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/workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.1242650668
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/workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.2641953336
/workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.1360136168
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/workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.386594924
/workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.1525585190
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/workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.1672416606
/workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.1187082549
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/workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.3100067212
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/workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.995922169
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/workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.1263896978



Total test records in report: 200
tests.html | tests1.html | tests2.html | tests3.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.1322076757 Feb 08 05:39:22 AM UTC 25 Feb 08 05:39:32 AM UTC 25 1101850000 ps
T2 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.3159788404 Feb 08 05:39:22 AM UTC 25 Feb 08 05:39:34 AM UTC 25 1481210000 ps
T3 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.4044790587 Feb 08 05:39:22 AM UTC 25 Feb 08 05:39:34 AM UTC 25 1430190000 ps
T7 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.2798935133 Feb 08 05:39:22 AM UTC 25 Feb 08 05:39:34 AM UTC 25 1308190000 ps
T8 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.1360136168 Feb 08 05:39:22 AM UTC 25 Feb 08 05:39:34 AM UTC 25 1523370000 ps
T9 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.1263896978 Feb 08 05:39:22 AM UTC 25 Feb 08 05:39:34 AM UTC 25 1333170000 ps
T10 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.3076194044 Feb 08 05:39:22 AM UTC 25 Feb 08 05:39:35 AM UTC 25 1479350000 ps
T11 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.1234933759 Feb 08 05:39:22 AM UTC 25 Feb 08 05:39:35 AM UTC 25 1422030000 ps
T12 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.3571122083 Feb 08 05:39:23 AM UTC 25 Feb 08 05:39:35 AM UTC 25 1301770000 ps
T13 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.693520421 Feb 08 05:39:22 AM UTC 25 Feb 08 05:39:35 AM UTC 25 1581870000 ps
T31 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.386594924 Feb 08 05:39:22 AM UTC 25 Feb 08 05:39:35 AM UTC 25 1604450000 ps
T32 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.1977037553 Feb 08 05:39:23 AM UTC 25 Feb 08 05:39:35 AM UTC 25 1319910000 ps
T33 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.2965094859 Feb 08 05:39:23 AM UTC 25 Feb 08 05:39:35 AM UTC 25 1325230000 ps
T34 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.1897769143 Feb 08 05:39:22 AM UTC 25 Feb 08 05:39:35 AM UTC 25 1522970000 ps
T35 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.1683022974 Feb 08 05:39:22 AM UTC 25 Feb 08 05:39:35 AM UTC 25 1511610000 ps
T36 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.1525585190 Feb 08 05:39:22 AM UTC 25 Feb 08 05:39:35 AM UTC 25 1593850000 ps
T37 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.898348076 Feb 08 05:39:23 AM UTC 25 Feb 08 05:39:35 AM UTC 25 1395130000 ps
T38 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.1938169142 Feb 08 05:39:22 AM UTC 25 Feb 08 05:39:35 AM UTC 25 1560910000 ps
T39 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.3533695570 Feb 08 05:39:22 AM UTC 25 Feb 08 05:39:36 AM UTC 25 1537030000 ps
T40 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.2641953336 Feb 08 05:39:22 AM UTC 25 Feb 08 05:39:36 AM UTC 25 1574790000 ps
T41 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.1449332789 Feb 08 05:39:25 AM UTC 25 Feb 08 05:39:37 AM UTC 25 1469630000 ps
T42 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.2821238753 Feb 08 05:39:27 AM UTC 25 Feb 08 05:39:38 AM UTC 25 1449550000 ps
T43 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.3463797414 Feb 08 05:39:28 AM UTC 25 Feb 08 05:39:38 AM UTC 25 1360690000 ps
T44 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.2641394404 Feb 08 05:39:28 AM UTC 25 Feb 08 05:39:38 AM UTC 25 1337410000 ps
T45 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.2788073249 Feb 08 05:39:28 AM UTC 25 Feb 08 05:39:38 AM UTC 25 1389850000 ps
T46 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.2793897159 Feb 08 05:39:28 AM UTC 25 Feb 08 05:39:39 AM UTC 25 1365430000 ps
T47 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.2167419856 Feb 08 05:39:28 AM UTC 25 Feb 08 05:39:39 AM UTC 25 1361190000 ps
T48 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.1266343227 Feb 08 05:39:28 AM UTC 25 Feb 08 05:39:39 AM UTC 25 1331850000 ps
T49 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.3717268836 Feb 08 05:39:28 AM UTC 25 Feb 08 05:39:39 AM UTC 25 1424990000 ps
T50 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.1672416606 Feb 08 05:39:27 AM UTC 25 Feb 08 05:39:39 AM UTC 25 1615270000 ps
T51 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.1187082549 Feb 08 05:39:28 AM UTC 25 Feb 08 05:39:39 AM UTC 25 1484410000 ps
T52 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.437232962 Feb 08 05:39:28 AM UTC 25 Feb 08 05:39:39 AM UTC 25 1520570000 ps
T53 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.995922169 Feb 08 05:39:28 AM UTC 25 Feb 08 05:39:39 AM UTC 25 1422070000 ps
T54 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.2766198438 Feb 08 05:39:28 AM UTC 25 Feb 08 05:39:39 AM UTC 25 1521450000 ps
T55 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.3394339049 Feb 08 05:39:28 AM UTC 25 Feb 08 05:39:39 AM UTC 25 1436130000 ps
T56 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.3484141236 Feb 08 05:39:28 AM UTC 25 Feb 08 05:39:39 AM UTC 25 1482110000 ps
T57 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.3100067212 Feb 08 05:39:28 AM UTC 25 Feb 08 05:39:40 AM UTC 25 1590010000 ps
T58 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.35294613 Feb 08 05:39:28 AM UTC 25 Feb 08 05:39:40 AM UTC 25 1509030000 ps
T59 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.1053826209 Feb 08 05:39:28 AM UTC 25 Feb 08 05:39:40 AM UTC 25 1510950000 ps
T60 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.1907384036 Feb 08 05:39:28 AM UTC 25 Feb 08 05:39:40 AM UTC 25 1589270000 ps
T61 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.2350819856 Feb 08 05:39:28 AM UTC 25 Feb 08 05:39:40 AM UTC 25 1578690000 ps
T62 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.3897297676 Feb 08 05:39:29 AM UTC 25 Feb 08 05:39:41 AM UTC 25 1545450000 ps
T63 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.631103096 Feb 08 05:39:33 AM UTC 25 Feb 08 05:39:44 AM UTC 25 1356110000 ps
T64 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.14081870 Feb 08 05:39:33 AM UTC 25 Feb 08 05:39:45 AM UTC 25 1504090000 ps
T65 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.1795186056 Feb 08 05:39:35 AM UTC 25 Feb 08 05:39:45 AM UTC 25 1359950000 ps
T66 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.3379354940 Feb 08 05:39:35 AM UTC 25 Feb 08 05:39:45 AM UTC 25 1453750000 ps
T67 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.739011214 Feb 08 05:39:35 AM UTC 25 Feb 08 05:39:45 AM UTC 25 1506030000 ps
T68 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.3752308026 Feb 08 05:39:35 AM UTC 25 Feb 08 05:39:46 AM UTC 25 1576270000 ps
T69 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.1851799312 Feb 08 05:39:35 AM UTC 25 Feb 08 05:39:46 AM UTC 25 1622830000 ps
T70 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.3206180478 Feb 08 05:39:36 AM UTC 25 Feb 08 05:39:47 AM UTC 25 1510230000 ps
T4 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.1744524576 Feb 08 07:34:11 AM UTC 25 Feb 08 08:06:06 AM UTC 25 336530830000 ps
T5 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.1072735754 Feb 08 07:34:11 AM UTC 25 Feb 08 08:06:07 AM UTC 25 336341570000 ps
T6 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.3555659664 Feb 08 07:34:10 AM UTC 25 Feb 08 08:06:07 AM UTC 25 336847630000 ps
T14 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.3120108507 Feb 08 07:34:11 AM UTC 25 Feb 08 08:06:09 AM UTC 25 336605810000 ps
T15 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.2591371447 Feb 08 07:34:11 AM UTC 25 Feb 08 08:06:10 AM UTC 25 336881110000 ps
T16 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.873937729 Feb 08 07:34:11 AM UTC 25 Feb 08 08:06:11 AM UTC 25 336392130000 ps
T17 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.494768602 Feb 08 07:34:11 AM UTC 25 Feb 08 08:06:11 AM UTC 25 337065110000 ps
T18 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.543669062 Feb 08 07:34:15 AM UTC 25 Feb 08 08:06:11 AM UTC 25 336297970000 ps
T19 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.3596381051 Feb 08 07:34:14 AM UTC 25 Feb 08 08:06:12 AM UTC 25 336654070000 ps
T20 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.1666493412 Feb 08 07:34:15 AM UTC 25 Feb 08 08:06:13 AM UTC 25 336389890000 ps
T71 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.2743303080 Feb 08 07:34:15 AM UTC 25 Feb 08 08:06:14 AM UTC 25 336621690000 ps
T72 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.3082787403 Feb 08 07:34:14 AM UTC 25 Feb 08 08:06:15 AM UTC 25 336814950000 ps
T73 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.311624099 Feb 08 07:34:15 AM UTC 25 Feb 08 08:06:16 AM UTC 25 337185430000 ps
T74 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.1665636083 Feb 08 07:34:11 AM UTC 25 Feb 08 08:06:16 AM UTC 25 337025890000 ps
T75 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.2924075689 Feb 08 07:34:13 AM UTC 25 Feb 08 08:06:16 AM UTC 25 336947430000 ps
T76 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.1946532404 Feb 08 07:34:15 AM UTC 25 Feb 08 08:06:17 AM UTC 25 336350970000 ps
T77 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.3088574647 Feb 08 07:34:19 AM UTC 25 Feb 08 08:06:18 AM UTC 25 336509150000 ps
T78 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.353553759 Feb 08 07:34:10 AM UTC 25 Feb 08 08:06:18 AM UTC 25 336789250000 ps
T79 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.24101717 Feb 08 07:34:13 AM UTC 25 Feb 08 08:06:18 AM UTC 25 336515930000 ps
T80 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.546585993 Feb 08 07:34:15 AM UTC 25 Feb 08 08:06:19 AM UTC 25 337005650000 ps
T81 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.2736080581 Feb 08 07:34:15 AM UTC 25 Feb 08 08:06:19 AM UTC 25 336711650000 ps
T82 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.1885169135 Feb 08 07:34:15 AM UTC 25 Feb 08 08:06:21 AM UTC 25 336814010000 ps
T83 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.3235469311 Feb 08 07:34:19 AM UTC 25 Feb 08 08:06:21 AM UTC 25 336471950000 ps
T84 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.4066061805 Feb 08 07:34:14 AM UTC 25 Feb 08 08:06:23 AM UTC 25 336651950000 ps
T85 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.1753685725 Feb 08 07:34:20 AM UTC 25 Feb 08 08:06:23 AM UTC 25 336575070000 ps
T86 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.4080518263 Feb 08 07:34:23 AM UTC 25 Feb 08 08:06:28 AM UTC 25 336530070000 ps
T87 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.1631763383 Feb 08 07:34:25 AM UTC 25 Feb 08 08:06:28 AM UTC 25 336375310000 ps
T88 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.3179354499 Feb 08 07:34:22 AM UTC 25 Feb 08 08:06:28 AM UTC 25 336816530000 ps
T89 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.3011124213 Feb 08 07:34:25 AM UTC 25 Feb 08 08:06:31 AM UTC 25 336797650000 ps
T90 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.1377771916 Feb 08 07:34:27 AM UTC 25 Feb 08 08:06:32 AM UTC 25 336570710000 ps
T91 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.3940752837 Feb 08 07:34:25 AM UTC 25 Feb 08 08:06:33 AM UTC 25 336638230000 ps
T92 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.3966489380 Feb 08 07:34:25 AM UTC 25 Feb 08 08:06:33 AM UTC 25 336525690000 ps
T93 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.1595323949 Feb 08 07:34:27 AM UTC 25 Feb 08 08:06:34 AM UTC 25 336838550000 ps
T94 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.1830564287 Feb 08 07:34:25 AM UTC 25 Feb 08 08:06:34 AM UTC 25 336662230000 ps
T95 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.1648577502 Feb 08 07:34:24 AM UTC 25 Feb 08 08:06:34 AM UTC 25 336868310000 ps
T96 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.1944949579 Feb 08 07:34:27 AM UTC 25 Feb 08 08:06:34 AM UTC 25 336764430000 ps
T97 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.1040162077 Feb 08 07:34:25 AM UTC 25 Feb 08 08:06:37 AM UTC 25 336581690000 ps
T98 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.560854613 Feb 08 07:34:26 AM UTC 25 Feb 08 08:06:37 AM UTC 25 337101870000 ps
T99 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.2729208721 Feb 08 07:34:27 AM UTC 25 Feb 08 08:06:37 AM UTC 25 336428990000 ps
T100 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.2417975219 Feb 08 07:34:26 AM UTC 25 Feb 08 08:06:37 AM UTC 25 336497370000 ps
T101 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.1563686153 Feb 08 07:34:27 AM UTC 25 Feb 08 08:06:37 AM UTC 25 336929650000 ps
T102 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.3467598842 Feb 08 07:34:23 AM UTC 25 Feb 08 08:06:38 AM UTC 25 336714150000 ps
T103 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.3970141050 Feb 08 07:34:27 AM UTC 25 Feb 08 08:06:38 AM UTC 25 336770270000 ps
T104 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.1982179668 Feb 08 07:34:27 AM UTC 25 Feb 08 08:06:38 AM UTC 25 336923390000 ps
T105 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.262467979 Feb 08 07:34:27 AM UTC 25 Feb 08 08:06:38 AM UTC 25 336863250000 ps
T106 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.1188865473 Feb 08 07:34:27 AM UTC 25 Feb 08 08:06:39 AM UTC 25 336706910000 ps
T107 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.2070804639 Feb 08 07:34:25 AM UTC 25 Feb 08 08:06:39 AM UTC 25 336857950000 ps
T108 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.713676936 Feb 08 07:34:27 AM UTC 25 Feb 08 08:06:39 AM UTC 25 336855670000 ps
T109 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.490316163 Feb 08 07:34:27 AM UTC 25 Feb 08 08:06:40 AM UTC 25 336600150000 ps
T110 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.3986562546 Feb 08 07:34:25 AM UTC 25 Feb 08 08:06:41 AM UTC 25 336967250000 ps
T111 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.67457915 Feb 08 05:39:36 AM UTC 25 Feb 08 05:39:46 AM UTC 25 1339910000 ps
T112 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.851492987 Feb 08 05:39:36 AM UTC 25 Feb 08 05:39:46 AM UTC 25 1378170000 ps
T113 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.1336648041 Feb 08 05:39:36 AM UTC 25 Feb 08 05:39:46 AM UTC 25 1425950000 ps
T114 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.3622761515 Feb 08 05:39:36 AM UTC 25 Feb 08 05:39:47 AM UTC 25 1482690000 ps
T115 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.869138364 Feb 08 05:39:36 AM UTC 25 Feb 08 05:39:47 AM UTC 25 1397030000 ps
T116 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.2628878337 Feb 08 05:39:36 AM UTC 25 Feb 08 05:39:47 AM UTC 25 1448710000 ps
T117 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.3720699633 Feb 08 05:39:36 AM UTC 25 Feb 08 05:39:47 AM UTC 25 1421710000 ps
T118 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.191153856 Feb 08 05:39:36 AM UTC 25 Feb 08 05:39:47 AM UTC 25 1420130000 ps
T119 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.2833077757 Feb 08 05:39:36 AM UTC 25 Feb 08 05:39:47 AM UTC 25 1501350000 ps
T120 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.4150333268 Feb 08 05:39:36 AM UTC 25 Feb 08 05:39:47 AM UTC 25 1583150000 ps
T121 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.1242650668 Feb 08 05:39:36 AM UTC 25 Feb 08 05:39:48 AM UTC 25 1564130000 ps
T122 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.1723485774 Feb 08 05:39:37 AM UTC 25 Feb 08 05:39:49 AM UTC 25 1517450000 ps
T123 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.4048246701 Feb 08 05:39:38 AM UTC 25 Feb 08 05:39:49 AM UTC 25 1356710000 ps
T124 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.2312852529 Feb 08 05:39:37 AM UTC 25 Feb 08 05:39:49 AM UTC 25 1502810000 ps
T125 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.3919330302 Feb 08 05:39:37 AM UTC 25 Feb 08 05:39:49 AM UTC 25 1513810000 ps
T126 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.1907790992 Feb 08 05:39:40 AM UTC 25 Feb 08 05:39:49 AM UTC 25 1239610000 ps
T127 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.3145811544 Feb 08 05:39:38 AM UTC 25 Feb 08 05:39:49 AM UTC 25 1392830000 ps
T128 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.1814498308 Feb 08 05:39:40 AM UTC 25 Feb 08 05:39:50 AM UTC 25 1345690000 ps
T129 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.107643364 Feb 08 05:39:40 AM UTC 25 Feb 08 05:39:50 AM UTC 25 1335250000 ps
T130 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.2864019583 Feb 08 05:39:39 AM UTC 25 Feb 08 05:39:50 AM UTC 25 1455130000 ps
T131 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.3469380674 Feb 08 05:39:41 AM UTC 25 Feb 08 05:39:50 AM UTC 25 1208250000 ps
T132 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.791875468 Feb 08 05:39:41 AM UTC 25 Feb 08 05:39:50 AM UTC 25 1249950000 ps
T133 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.4112276166 Feb 08 05:39:40 AM UTC 25 Feb 08 05:39:50 AM UTC 25 1462030000 ps
T134 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.1299087969 Feb 08 05:39:39 AM UTC 25 Feb 08 05:39:51 AM UTC 25 1559950000 ps
T135 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.762211733 Feb 08 05:39:39 AM UTC 25 Feb 08 05:39:51 AM UTC 25 1567550000 ps
T136 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.1856940087 Feb 08 05:39:39 AM UTC 25 Feb 08 05:39:51 AM UTC 25 1561090000 ps
T137 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.4280689786 Feb 08 05:39:40 AM UTC 25 Feb 08 05:39:51 AM UTC 25 1571550000 ps
T138 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.209322890 Feb 08 05:39:41 AM UTC 25 Feb 08 05:39:51 AM UTC 25 1391970000 ps
T139 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.3095168562 Feb 08 05:39:41 AM UTC 25 Feb 08 05:39:51 AM UTC 25 1365990000 ps
T140 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.2609748697 Feb 08 05:39:41 AM UTC 25 Feb 08 05:39:52 AM UTC 25 1528710000 ps
T141 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.3323733252 Feb 08 05:39:41 AM UTC 25 Feb 08 05:39:52 AM UTC 25 1551830000 ps
T142 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.53098703 Feb 08 05:39:41 AM UTC 25 Feb 08 05:39:52 AM UTC 25 1508050000 ps
T143 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.1404591606 Feb 08 05:39:41 AM UTC 25 Feb 08 05:39:52 AM UTC 25 1543410000 ps
T144 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.3513214266 Feb 08 05:39:41 AM UTC 25 Feb 08 05:39:52 AM UTC 25 1605230000 ps
T145 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.3952279191 Feb 08 05:39:41 AM UTC 25 Feb 08 05:39:52 AM UTC 25 1575410000 ps
T146 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.3281467861 Feb 08 05:39:42 AM UTC 25 Feb 08 05:39:53 AM UTC 25 1580770000 ps
T147 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.4143742570 Feb 08 05:39:45 AM UTC 25 Feb 08 05:39:56 AM UTC 25 1505530000 ps
T148 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.3837848891 Feb 08 05:39:46 AM UTC 25 Feb 08 05:39:56 AM UTC 25 1366250000 ps
T149 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.183144573 Feb 08 05:39:46 AM UTC 25 Feb 08 05:39:56 AM UTC 25 1419230000 ps
T150 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.3385623015 Feb 08 05:39:46 AM UTC 25 Feb 08 05:39:57 AM UTC 25 1498590000 ps
T151 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.534447354 Feb 08 05:39:46 AM UTC 25 Feb 08 05:39:57 AM UTC 25 1537110000 ps
T152 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.426270319 Feb 08 05:39:46 AM UTC 25 Feb 08 05:39:57 AM UTC 25 1504870000 ps
T153 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.3385239750 Feb 08 05:39:48 AM UTC 25 Feb 08 05:39:58 AM UTC 25 1289270000 ps
T154 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.4153920361 Feb 08 05:39:47 AM UTC 25 Feb 08 05:39:58 AM UTC 25 1415030000 ps
T155 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.3858967179 Feb 08 05:39:47 AM UTC 25 Feb 08 05:39:58 AM UTC 25 1455990000 ps
T156 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.2027495282 Feb 08 05:39:48 AM UTC 25 Feb 08 05:39:58 AM UTC 25 1495930000 ps
T157 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.3685189257 Feb 08 05:39:47 AM UTC 25 Feb 08 05:39:58 AM UTC 25 1469490000 ps
T158 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.1457473115 Feb 08 05:39:48 AM UTC 25 Feb 08 05:39:58 AM UTC 25 1502350000 ps
T159 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.3528474733 Feb 08 05:39:48 AM UTC 25 Feb 08 05:39:58 AM UTC 25 1497010000 ps
T160 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.16754233 Feb 08 05:39:47 AM UTC 25 Feb 08 05:39:59 AM UTC 25 1573670000 ps
T21 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.814006143 Feb 08 08:11:13 AM UTC 25 Feb 08 08:41:30 AM UTC 25 336609950000 ps
T22 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.2341836732 Feb 08 08:11:13 AM UTC 25 Feb 08 08:41:32 AM UTC 25 336388530000 ps
T23 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.1245052923 Feb 08 08:11:14 AM UTC 25 Feb 08 08:41:33 AM UTC 25 336611010000 ps
T24 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.3827605625 Feb 08 08:11:13 AM UTC 25 Feb 08 08:41:33 AM UTC 25 337000350000 ps
T25 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.2192862722 Feb 08 08:11:13 AM UTC 25 Feb 08 08:41:33 AM UTC 25 336720330000 ps
T26 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.2784284915 Feb 08 08:11:13 AM UTC 25 Feb 08 08:41:33 AM UTC 25 336815770000 ps
T27 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.3333659134 Feb 08 08:11:16 AM UTC 25 Feb 08 08:41:33 AM UTC 25 336571190000 ps
T28 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.3866695786 Feb 08 08:11:13 AM UTC 25 Feb 08 08:41:34 AM UTC 25 336780290000 ps
T29 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.1743675013 Feb 08 08:11:13 AM UTC 25 Feb 08 08:41:34 AM UTC 25 336369370000 ps
T30 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.1812419389 Feb 08 08:11:14 AM UTC 25 Feb 08 08:41:35 AM UTC 25 336517110000 ps
T161 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.3923537662 Feb 08 08:11:13 AM UTC 25 Feb 08 08:41:35 AM UTC 25 336849190000 ps
T162 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.208752173 Feb 08 08:11:13 AM UTC 25 Feb 08 08:41:35 AM UTC 25 337124830000 ps
T163 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.705725986 Feb 08 08:11:14 AM UTC 25 Feb 08 08:41:36 AM UTC 25 336452350000 ps
T164 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.1575865145 Feb 08 08:11:13 AM UTC 25 Feb 08 08:41:36 AM UTC 25 336768210000 ps
T165 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.1169503093 Feb 08 08:11:14 AM UTC 25 Feb 08 08:41:36 AM UTC 25 336905690000 ps
T166 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.3398478177 Feb 08 08:11:13 AM UTC 25 Feb 08 08:41:36 AM UTC 25 336578710000 ps
T167 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.502269422 Feb 08 08:11:13 AM UTC 25 Feb 08 08:41:37 AM UTC 25 337072070000 ps
T168 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.2060786298 Feb 08 08:11:13 AM UTC 25 Feb 08 08:41:37 AM UTC 25 336619470000 ps
T169 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.2328131812 Feb 08 08:11:16 AM UTC 25 Feb 08 08:41:37 AM UTC 25 336364950000 ps
T170 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.1793324262 Feb 08 08:11:13 AM UTC 25 Feb 08 08:41:37 AM UTC 25 336430730000 ps
T171 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.3180035389 Feb 08 08:11:14 AM UTC 25 Feb 08 08:41:38 AM UTC 25 336503850000 ps
T172 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.3975084647 Feb 08 08:11:13 AM UTC 25 Feb 08 08:41:38 AM UTC 25 336696290000 ps
T173 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.3146465928 Feb 08 08:11:13 AM UTC 25 Feb 08 08:41:38 AM UTC 25 336821610000 ps
T174 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.317907164 Feb 08 08:11:13 AM UTC 25 Feb 08 08:41:38 AM UTC 25 336569050000 ps
T175 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.2177127599 Feb 08 08:11:14 AM UTC 25 Feb 08 08:41:39 AM UTC 25 336425030000 ps
T176 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.663080114 Feb 08 08:11:14 AM UTC 25 Feb 08 08:41:39 AM UTC 25 336969570000 ps
T177 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.2310172659 Feb 08 08:11:13 AM UTC 25 Feb 08 08:41:39 AM UTC 25 336865230000 ps
T178 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.4280375468 Feb 08 08:11:13 AM UTC 25 Feb 08 08:41:39 AM UTC 25 336724310000 ps
T179 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.1002538394 Feb 08 08:11:13 AM UTC 25 Feb 08 08:41:40 AM UTC 25 336459370000 ps
T180 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.4151270472 Feb 08 08:11:13 AM UTC 25 Feb 08 08:41:40 AM UTC 25 336993830000 ps
T181 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.2335789682 Feb 08 08:11:13 AM UTC 25 Feb 08 08:41:40 AM UTC 25 336633210000 ps
T182 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.3956721267 Feb 08 08:11:13 AM UTC 25 Feb 08 08:41:40 AM UTC 25 336668450000 ps
T183 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.2963606104 Feb 08 08:11:13 AM UTC 25 Feb 08 08:41:40 AM UTC 25 336494850000 ps
T184 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.3475847470 Feb 08 08:11:21 AM UTC 25 Feb 08 08:41:41 AM UTC 25 336885310000 ps
T185 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.2696669303 Feb 08 08:11:15 AM UTC 25 Feb 08 08:41:41 AM UTC 25 336645190000 ps
T186 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.4071717029 Feb 08 08:11:13 AM UTC 25 Feb 08 08:41:41 AM UTC 25 336628170000 ps
T187 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.4142873018 Feb 08 08:11:16 AM UTC 25 Feb 08 08:41:42 AM UTC 25 336453990000 ps
T188 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.216975155 Feb 08 08:11:21 AM UTC 25 Feb 08 08:41:43 AM UTC 25 336495410000 ps
T189 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.4142762516 Feb 08 08:11:14 AM UTC 25 Feb 08 08:41:43 AM UTC 25 336843530000 ps
T190 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.2518033714 Feb 08 08:11:13 AM UTC 25 Feb 08 08:41:43 AM UTC 25 336530010000 ps
T191 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.3124849605 Feb 08 08:11:13 AM UTC 25 Feb 08 08:41:44 AM UTC 25 336382330000 ps
T192 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.1840920119 Feb 08 08:11:21 AM UTC 25 Feb 08 08:41:45 AM UTC 25 336819510000 ps
T193 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.3186147383 Feb 08 08:11:13 AM UTC 25 Feb 08 08:41:45 AM UTC 25 336879090000 ps
T194 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.3518514514 Feb 08 08:11:14 AM UTC 25 Feb 08 08:41:45 AM UTC 25 336576390000 ps
T195 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.2373708014 Feb 08 08:11:13 AM UTC 25 Feb 08 08:41:45 AM UTC 25 336812550000 ps
T196 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.999268801 Feb 08 08:11:16 AM UTC 25 Feb 08 08:41:46 AM UTC 25 336629850000 ps
T197 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.3625466664 Feb 08 08:11:21 AM UTC 25 Feb 08 08:41:47 AM UTC 25 336636770000 ps
T198 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.2831216338 Feb 08 08:11:16 AM UTC 25 Feb 08 08:41:48 AM UTC 25 337023030000 ps
T199 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.844751103 Feb 08 08:11:21 AM UTC 25 Feb 08 08:41:54 AM UTC 25 336432170000 ps
T200 /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.3562770593 Feb 08 08:11:28 AM UTC 25 Feb 08 08:41:59 AM UTC 25 336432730000 ps

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.1322076757
Short name T1
Test name
Test status
Simulation time 1101850000 ps
CPU time 1.41 seconds
Started Feb 08 05:39:22 AM UTC 25
Finished Feb 08 05:39:32 AM UTC 25
Peak memory 177796 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1322076757 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/n
ull -cm_name 0.prim_lfsr_gal_smoke.1322076757
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/0.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.3555659664
Short name T6
Test name
Test status
Simulation time 336847630000 ps
CPU time 241.02 seconds
Started Feb 08 07:34:10 AM UTC 25
Finished Feb 08 08:06:07 AM UTC 25
Peak memory 175120 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3555659664 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev
/null -cm_name 1.prim_lfsr_fib_test.3555659664
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/1.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.2192862722
Short name T25
Test name
Test status
Simulation time 336720330000 ps
CPU time 231.32 seconds
Started Feb 08 08:11:13 AM UTC 25
Finished Feb 08 08:41:33 AM UTC 25
Peak memory 176652 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2192862722 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev
/null -cm_name 1.prim_lfsr_gal_test.2192862722
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/1.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.353553759
Short name T78
Test name
Test status
Simulation time 336789250000 ps
CPU time 237.94 seconds
Started Feb 08 07:34:10 AM UTC 25
Finished Feb 08 08:06:18 AM UTC 25
Peak memory 175124 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=353553759 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/
null -cm_name 0.prim_lfsr_fib_test.353553759
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/0.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.2924075689
Short name T75
Test name
Test status
Simulation time 336947430000 ps
CPU time 240.94 seconds
Started Feb 08 07:34:13 AM UTC 25
Finished Feb 08 08:06:16 AM UTC 25
Peak memory 175120 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2924075689 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev
/null -cm_name 10.prim_lfsr_fib_test.2924075689
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/10.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.3082787403
Short name T72
Test name
Test status
Simulation time 336814950000 ps
CPU time 239.52 seconds
Started Feb 08 07:34:14 AM UTC 25
Finished Feb 08 08:06:15 AM UTC 25
Peak memory 176652 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3082787403 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev
/null -cm_name 11.prim_lfsr_fib_test.3082787403
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/11.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.4066061805
Short name T84
Test name
Test status
Simulation time 336651950000 ps
CPU time 239.25 seconds
Started Feb 08 07:34:14 AM UTC 25
Finished Feb 08 08:06:23 AM UTC 25
Peak memory 175120 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4066061805 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev
/null -cm_name 12.prim_lfsr_fib_test.4066061805
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/12.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.3596381051
Short name T19
Test name
Test status
Simulation time 336654070000 ps
CPU time 242.54 seconds
Started Feb 08 07:34:14 AM UTC 25
Finished Feb 08 08:06:12 AM UTC 25
Peak memory 176652 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3596381051 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev
/null -cm_name 13.prim_lfsr_fib_test.3596381051
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/13.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.2736080581
Short name T81
Test name
Test status
Simulation time 336711650000 ps
CPU time 242.02 seconds
Started Feb 08 07:34:15 AM UTC 25
Finished Feb 08 08:06:19 AM UTC 25
Peak memory 176652 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2736080581 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev
/null -cm_name 14.prim_lfsr_fib_test.2736080581
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/14.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.543669062
Short name T18
Test name
Test status
Simulation time 336297970000 ps
CPU time 242.1 seconds
Started Feb 08 07:34:15 AM UTC 25
Finished Feb 08 08:06:11 AM UTC 25
Peak memory 175124 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=543669062 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/
null -cm_name 15.prim_lfsr_fib_test.543669062
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/15.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.1666493412
Short name T20
Test name
Test status
Simulation time 336389890000 ps
CPU time 238.54 seconds
Started Feb 08 07:34:15 AM UTC 25
Finished Feb 08 08:06:13 AM UTC 25
Peak memory 175120 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1666493412 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev
/null -cm_name 16.prim_lfsr_fib_test.1666493412
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/16.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.1885169135
Short name T82
Test name
Test status
Simulation time 336814010000 ps
CPU time 241.48 seconds
Started Feb 08 07:34:15 AM UTC 25
Finished Feb 08 08:06:21 AM UTC 25
Peak memory 176652 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1885169135 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev
/null -cm_name 17.prim_lfsr_fib_test.1885169135
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/17.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.546585993
Short name T80
Test name
Test status
Simulation time 337005650000 ps
CPU time 239.18 seconds
Started Feb 08 07:34:15 AM UTC 25
Finished Feb 08 08:06:19 AM UTC 25
Peak memory 175124 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=546585993 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/
null -cm_name 18.prim_lfsr_fib_test.546585993
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/18.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.311624099
Short name T73
Test name
Test status
Simulation time 337185430000 ps
CPU time 241.48 seconds
Started Feb 08 07:34:15 AM UTC 25
Finished Feb 08 08:06:16 AM UTC 25
Peak memory 176656 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=311624099 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/
null -cm_name 19.prim_lfsr_fib_test.311624099
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/19.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.494768602
Short name T17
Test name
Test status
Simulation time 337065110000 ps
CPU time 240.88 seconds
Started Feb 08 07:34:11 AM UTC 25
Finished Feb 08 08:06:11 AM UTC 25
Peak memory 176656 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=494768602 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/
null -cm_name 2.prim_lfsr_fib_test.494768602
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/2.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.2743303080
Short name T71
Test name
Test status
Simulation time 336621690000 ps
CPU time 239.15 seconds
Started Feb 08 07:34:15 AM UTC 25
Finished Feb 08 08:06:14 AM UTC 25
Peak memory 176652 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2743303080 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev
/null -cm_name 20.prim_lfsr_fib_test.2743303080
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/20.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.1946532404
Short name T76
Test name
Test status
Simulation time 336350970000 ps
CPU time 240.2 seconds
Started Feb 08 07:34:15 AM UTC 25
Finished Feb 08 08:06:17 AM UTC 25
Peak memory 176652 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1946532404 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev
/null -cm_name 21.prim_lfsr_fib_test.1946532404
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/21.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.3235469311
Short name T83
Test name
Test status
Simulation time 336471950000 ps
CPU time 239.31 seconds
Started Feb 08 07:34:19 AM UTC 25
Finished Feb 08 08:06:21 AM UTC 25
Peak memory 175052 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3235469311 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev
/null -cm_name 22.prim_lfsr_fib_test.3235469311
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/22.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.3088574647
Short name T77
Test name
Test status
Simulation time 336509150000 ps
CPU time 241.64 seconds
Started Feb 08 07:34:19 AM UTC 25
Finished Feb 08 08:06:18 AM UTC 25
Peak memory 176612 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3088574647 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev
/null -cm_name 23.prim_lfsr_fib_test.3088574647
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/23.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.1753685725
Short name T85
Test name
Test status
Simulation time 336575070000 ps
CPU time 242.3 seconds
Started Feb 08 07:34:20 AM UTC 25
Finished Feb 08 08:06:23 AM UTC 25
Peak memory 176652 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1753685725 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev
/null -cm_name 24.prim_lfsr_fib_test.1753685725
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/24.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.3179354499
Short name T88
Test name
Test status
Simulation time 336816530000 ps
CPU time 243.93 seconds
Started Feb 08 07:34:22 AM UTC 25
Finished Feb 08 08:06:28 AM UTC 25
Peak memory 175120 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3179354499 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev
/null -cm_name 25.prim_lfsr_fib_test.3179354499
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/25.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.4080518263
Short name T86
Test name
Test status
Simulation time 336530070000 ps
CPU time 242.77 seconds
Started Feb 08 07:34:23 AM UTC 25
Finished Feb 08 08:06:28 AM UTC 25
Peak memory 175120 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4080518263 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev
/null -cm_name 26.prim_lfsr_fib_test.4080518263
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/26.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.3467598842
Short name T102
Test name
Test status
Simulation time 336714150000 ps
CPU time 240.11 seconds
Started Feb 08 07:34:23 AM UTC 25
Finished Feb 08 08:06:38 AM UTC 25
Peak memory 175120 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3467598842 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev
/null -cm_name 27.prim_lfsr_fib_test.3467598842
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/27.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.1648577502
Short name T95
Test name
Test status
Simulation time 336868310000 ps
CPU time 241.08 seconds
Started Feb 08 07:34:24 AM UTC 25
Finished Feb 08 08:06:34 AM UTC 25
Peak memory 176652 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1648577502 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev
/null -cm_name 28.prim_lfsr_fib_test.1648577502
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/28.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.3011124213
Short name T89
Test name
Test status
Simulation time 336797650000 ps
CPU time 242.49 seconds
Started Feb 08 07:34:25 AM UTC 25
Finished Feb 08 08:06:31 AM UTC 25
Peak memory 176620 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3011124213 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev
/null -cm_name 29.prim_lfsr_fib_test.3011124213
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/29.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.1744524576
Short name T4
Test name
Test status
Simulation time 336530830000 ps
CPU time 240.02 seconds
Started Feb 08 07:34:11 AM UTC 25
Finished Feb 08 08:06:06 AM UTC 25
Peak memory 176496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1744524576 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev
/null -cm_name 3.prim_lfsr_fib_test.1744524576
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/3.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.3986562546
Short name T110
Test name
Test status
Simulation time 336967250000 ps
CPU time 241.56 seconds
Started Feb 08 07:34:25 AM UTC 25
Finished Feb 08 08:06:41 AM UTC 25
Peak memory 176652 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3986562546 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev
/null -cm_name 30.prim_lfsr_fib_test.3986562546
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/30.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.1830564287
Short name T94
Test name
Test status
Simulation time 336662230000 ps
CPU time 239.69 seconds
Started Feb 08 07:34:25 AM UTC 25
Finished Feb 08 08:06:34 AM UTC 25
Peak memory 176648 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1830564287 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev
/null -cm_name 31.prim_lfsr_fib_test.1830564287
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/31.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.1631763383
Short name T87
Test name
Test status
Simulation time 336375310000 ps
CPU time 243.52 seconds
Started Feb 08 07:34:25 AM UTC 25
Finished Feb 08 08:06:28 AM UTC 25
Peak memory 176652 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1631763383 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev
/null -cm_name 32.prim_lfsr_fib_test.1631763383
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/32.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.3966489380
Short name T92
Test name
Test status
Simulation time 336525690000 ps
CPU time 239.72 seconds
Started Feb 08 07:34:25 AM UTC 25
Finished Feb 08 08:06:33 AM UTC 25
Peak memory 176560 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3966489380 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev
/null -cm_name 33.prim_lfsr_fib_test.3966489380
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/33.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.1040162077
Short name T97
Test name
Test status
Simulation time 336581690000 ps
CPU time 241.12 seconds
Started Feb 08 07:34:25 AM UTC 25
Finished Feb 08 08:06:37 AM UTC 25
Peak memory 176572 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1040162077 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev
/null -cm_name 34.prim_lfsr_fib_test.1040162077
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/34.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.3940752837
Short name T91
Test name
Test status
Simulation time 336638230000 ps
CPU time 241.6 seconds
Started Feb 08 07:34:25 AM UTC 25
Finished Feb 08 08:06:33 AM UTC 25
Peak memory 175104 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3940752837 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev
/null -cm_name 35.prim_lfsr_fib_test.3940752837
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/35.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.2070804639
Short name T107
Test name
Test status
Simulation time 336857950000 ps
CPU time 241.82 seconds
Started Feb 08 07:34:25 AM UTC 25
Finished Feb 08 08:06:39 AM UTC 25
Peak memory 176632 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2070804639 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev
/null -cm_name 36.prim_lfsr_fib_test.2070804639
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/36.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.560854613
Short name T98
Test name
Test status
Simulation time 337101870000 ps
CPU time 241.58 seconds
Started Feb 08 07:34:26 AM UTC 25
Finished Feb 08 08:06:37 AM UTC 25
Peak memory 176652 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=560854613 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/
null -cm_name 37.prim_lfsr_fib_test.560854613
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/37.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.2417975219
Short name T100
Test name
Test status
Simulation time 336497370000 ps
CPU time 243.49 seconds
Started Feb 08 07:34:26 AM UTC 25
Finished Feb 08 08:06:37 AM UTC 25
Peak memory 176652 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2417975219 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev
/null -cm_name 38.prim_lfsr_fib_test.2417975219
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/38.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.2729208721
Short name T99
Test name
Test status
Simulation time 336428990000 ps
CPU time 242.98 seconds
Started Feb 08 07:34:27 AM UTC 25
Finished Feb 08 08:06:37 AM UTC 25
Peak memory 175120 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2729208721 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev
/null -cm_name 39.prim_lfsr_fib_test.2729208721
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/39.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.1072735754
Short name T5
Test name
Test status
Simulation time 336341570000 ps
CPU time 240.38 seconds
Started Feb 08 07:34:11 AM UTC 25
Finished Feb 08 08:06:07 AM UTC 25
Peak memory 176476 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1072735754 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev
/null -cm_name 4.prim_lfsr_fib_test.1072735754
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/4.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.1188865473
Short name T106
Test name
Test status
Simulation time 336706910000 ps
CPU time 240.63 seconds
Started Feb 08 07:34:27 AM UTC 25
Finished Feb 08 08:06:39 AM UTC 25
Peak memory 176652 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1188865473 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev
/null -cm_name 40.prim_lfsr_fib_test.1188865473
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/40.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.3970141050
Short name T103
Test name
Test status
Simulation time 336770270000 ps
CPU time 242.19 seconds
Started Feb 08 07:34:27 AM UTC 25
Finished Feb 08 08:06:38 AM UTC 25
Peak memory 176652 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3970141050 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev
/null -cm_name 41.prim_lfsr_fib_test.3970141050
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/41.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.490316163
Short name T109
Test name
Test status
Simulation time 336600150000 ps
CPU time 239.34 seconds
Started Feb 08 07:34:27 AM UTC 25
Finished Feb 08 08:06:40 AM UTC 25
Peak memory 175124 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=490316163 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/
null -cm_name 42.prim_lfsr_fib_test.490316163
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/42.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.1377771916
Short name T90
Test name
Test status
Simulation time 336570710000 ps
CPU time 242.3 seconds
Started Feb 08 07:34:27 AM UTC 25
Finished Feb 08 08:06:32 AM UTC 25
Peak memory 176652 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1377771916 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev
/null -cm_name 43.prim_lfsr_fib_test.1377771916
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/43.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.713676936
Short name T108
Test name
Test status
Simulation time 336855670000 ps
CPU time 240.99 seconds
Started Feb 08 07:34:27 AM UTC 25
Finished Feb 08 08:06:39 AM UTC 25
Peak memory 176656 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=713676936 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/
null -cm_name 44.prim_lfsr_fib_test.713676936
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/44.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.1944949579
Short name T96
Test name
Test status
Simulation time 336764430000 ps
CPU time 243.19 seconds
Started Feb 08 07:34:27 AM UTC 25
Finished Feb 08 08:06:34 AM UTC 25
Peak memory 175120 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1944949579 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev
/null -cm_name 45.prim_lfsr_fib_test.1944949579
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/45.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.1595323949
Short name T93
Test name
Test status
Simulation time 336838550000 ps
CPU time 242.74 seconds
Started Feb 08 07:34:27 AM UTC 25
Finished Feb 08 08:06:34 AM UTC 25
Peak memory 176652 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1595323949 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev
/null -cm_name 46.prim_lfsr_fib_test.1595323949
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/46.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.262467979
Short name T105
Test name
Test status
Simulation time 336863250000 ps
CPU time 239.57 seconds
Started Feb 08 07:34:27 AM UTC 25
Finished Feb 08 08:06:38 AM UTC 25
Peak memory 176656 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=262467979 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/
null -cm_name 47.prim_lfsr_fib_test.262467979
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/47.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.1563686153
Short name T101
Test name
Test status
Simulation time 336929650000 ps
CPU time 241.5 seconds
Started Feb 08 07:34:27 AM UTC 25
Finished Feb 08 08:06:37 AM UTC 25
Peak memory 176652 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1563686153 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev
/null -cm_name 48.prim_lfsr_fib_test.1563686153
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/48.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.1982179668
Short name T104
Test name
Test status
Simulation time 336923390000 ps
CPU time 239.44 seconds
Started Feb 08 07:34:27 AM UTC 25
Finished Feb 08 08:06:38 AM UTC 25
Peak memory 175120 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1982179668 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev
/null -cm_name 49.prim_lfsr_fib_test.1982179668
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/49.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.2591371447
Short name T15
Test name
Test status
Simulation time 336881110000 ps
CPU time 239.51 seconds
Started Feb 08 07:34:11 AM UTC 25
Finished Feb 08 08:06:10 AM UTC 25
Peak memory 175124 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2591371447 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev
/null -cm_name 5.prim_lfsr_fib_test.2591371447
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/5.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.873937729
Short name T16
Test name
Test status
Simulation time 336392130000 ps
CPU time 239.08 seconds
Started Feb 08 07:34:11 AM UTC 25
Finished Feb 08 08:06:11 AM UTC 25
Peak memory 175124 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=873937729 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/
null -cm_name 6.prim_lfsr_fib_test.873937729
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/6.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.3120108507
Short name T14
Test name
Test status
Simulation time 336605810000 ps
CPU time 241.32 seconds
Started Feb 08 07:34:11 AM UTC 25
Finished Feb 08 08:06:09 AM UTC 25
Peak memory 176652 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3120108507 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev
/null -cm_name 7.prim_lfsr_fib_test.3120108507
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/7.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.1665636083
Short name T74
Test name
Test status
Simulation time 337025890000 ps
CPU time 239.67 seconds
Started Feb 08 07:34:11 AM UTC 25
Finished Feb 08 08:06:16 AM UTC 25
Peak memory 176656 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1665636083 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev
/null -cm_name 8.prim_lfsr_fib_test.1665636083
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/8.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.24101717
Short name T79
Test name
Test status
Simulation time 336515930000 ps
CPU time 240.97 seconds
Started Feb 08 07:34:13 AM UTC 25
Finished Feb 08 08:06:18 AM UTC 25
Peak memory 176660 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=24101717 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib.vdb -cm_log /dev/n
ull -cm_name 9.prim_lfsr_fib_test.24101717
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/9.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.502269422
Short name T167
Test name
Test status
Simulation time 337072070000 ps
CPU time 231.62 seconds
Started Feb 08 08:11:13 AM UTC 25
Finished Feb 08 08:41:37 AM UTC 25
Peak memory 176420 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=502269422 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/
null -cm_name 0.prim_lfsr_gal_test.502269422
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/0.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.317907164
Short name T174
Test name
Test status
Simulation time 336569050000 ps
CPU time 231.12 seconds
Started Feb 08 08:11:13 AM UTC 25
Finished Feb 08 08:41:38 AM UTC 25
Peak memory 175120 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=317907164 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/
null -cm_name 10.prim_lfsr_gal_test.317907164
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/10.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.1743675013
Short name T29
Test name
Test status
Simulation time 336369370000 ps
CPU time 231.07 seconds
Started Feb 08 08:11:13 AM UTC 25
Finished Feb 08 08:41:34 AM UTC 25
Peak memory 176652 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1743675013 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev
/null -cm_name 11.prim_lfsr_gal_test.1743675013
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/11.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.814006143
Short name T21
Test name
Test status
Simulation time 336609950000 ps
CPU time 230.97 seconds
Started Feb 08 08:11:13 AM UTC 25
Finished Feb 08 08:41:30 AM UTC 25
Peak memory 176720 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=814006143 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/
null -cm_name 12.prim_lfsr_gal_test.814006143
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/12.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.3866695786
Short name T28
Test name
Test status
Simulation time 336780290000 ps
CPU time 230.9 seconds
Started Feb 08 08:11:13 AM UTC 25
Finished Feb 08 08:41:34 AM UTC 25
Peak memory 176652 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3866695786 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev
/null -cm_name 13.prim_lfsr_gal_test.3866695786
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/13.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.3398478177
Short name T166
Test name
Test status
Simulation time 336578710000 ps
CPU time 230.84 seconds
Started Feb 08 08:11:13 AM UTC 25
Finished Feb 08 08:41:36 AM UTC 25
Peak memory 175120 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3398478177 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev
/null -cm_name 14.prim_lfsr_gal_test.3398478177
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/14.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.2310172659
Short name T177
Test name
Test status
Simulation time 336865230000 ps
CPU time 232.32 seconds
Started Feb 08 08:11:13 AM UTC 25
Finished Feb 08 08:41:39 AM UTC 25
Peak memory 175120 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2310172659 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev
/null -cm_name 15.prim_lfsr_gal_test.2310172659
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/15.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.3827605625
Short name T24
Test name
Test status
Simulation time 337000350000 ps
CPU time 230.88 seconds
Started Feb 08 08:11:13 AM UTC 25
Finished Feb 08 08:41:33 AM UTC 25
Peak memory 175120 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3827605625 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev
/null -cm_name 16.prim_lfsr_gal_test.3827605625
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/16.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.3186147383
Short name T193
Test name
Test status
Simulation time 336879090000 ps
CPU time 231.15 seconds
Started Feb 08 08:11:13 AM UTC 25
Finished Feb 08 08:41:45 AM UTC 25
Peak memory 175120 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3186147383 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev
/null -cm_name 17.prim_lfsr_gal_test.3186147383
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/17.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.1793324262
Short name T170
Test name
Test status
Simulation time 336430730000 ps
CPU time 231.49 seconds
Started Feb 08 08:11:13 AM UTC 25
Finished Feb 08 08:41:37 AM UTC 25
Peak memory 176652 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1793324262 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev
/null -cm_name 18.prim_lfsr_gal_test.1793324262
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/18.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.2784284915
Short name T26
Test name
Test status
Simulation time 336815770000 ps
CPU time 231.64 seconds
Started Feb 08 08:11:13 AM UTC 25
Finished Feb 08 08:41:33 AM UTC 25
Peak memory 176652 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2784284915 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev
/null -cm_name 19.prim_lfsr_gal_test.2784284915
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/19.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.4071717029
Short name T186
Test name
Test status
Simulation time 336628170000 ps
CPU time 232.34 seconds
Started Feb 08 08:11:13 AM UTC 25
Finished Feb 08 08:41:41 AM UTC 25
Peak memory 175120 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4071717029 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev
/null -cm_name 2.prim_lfsr_gal_test.4071717029
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/2.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.2335789682
Short name T181
Test name
Test status
Simulation time 336633210000 ps
CPU time 231.21 seconds
Started Feb 08 08:11:13 AM UTC 25
Finished Feb 08 08:41:40 AM UTC 25
Peak memory 175120 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2335789682 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev
/null -cm_name 20.prim_lfsr_gal_test.2335789682
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/20.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.208752173
Short name T162
Test name
Test status
Simulation time 337124830000 ps
CPU time 231.46 seconds
Started Feb 08 08:11:13 AM UTC 25
Finished Feb 08 08:41:35 AM UTC 25
Peak memory 175056 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=208752173 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/
null -cm_name 21.prim_lfsr_gal_test.208752173
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/21.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.2341836732
Short name T22
Test name
Test status
Simulation time 336388530000 ps
CPU time 230.46 seconds
Started Feb 08 08:11:13 AM UTC 25
Finished Feb 08 08:41:32 AM UTC 25
Peak memory 176652 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2341836732 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev
/null -cm_name 22.prim_lfsr_gal_test.2341836732
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/22.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.1575865145
Short name T164
Test name
Test status
Simulation time 336768210000 ps
CPU time 232.63 seconds
Started Feb 08 08:11:13 AM UTC 25
Finished Feb 08 08:41:36 AM UTC 25
Peak memory 176652 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1575865145 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev
/null -cm_name 23.prim_lfsr_gal_test.1575865145
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/23.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.3975084647
Short name T172
Test name
Test status
Simulation time 336696290000 ps
CPU time 231.35 seconds
Started Feb 08 08:11:13 AM UTC 25
Finished Feb 08 08:41:38 AM UTC 25
Peak memory 175120 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3975084647 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev
/null -cm_name 24.prim_lfsr_gal_test.3975084647
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/24.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.4151270472
Short name T180
Test name
Test status
Simulation time 336993830000 ps
CPU time 231.82 seconds
Started Feb 08 08:11:13 AM UTC 25
Finished Feb 08 08:41:40 AM UTC 25
Peak memory 176652 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4151270472 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev
/null -cm_name 25.prim_lfsr_gal_test.4151270472
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/25.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.1002538394
Short name T179
Test name
Test status
Simulation time 336459370000 ps
CPU time 231.63 seconds
Started Feb 08 08:11:13 AM UTC 25
Finished Feb 08 08:41:40 AM UTC 25
Peak memory 175120 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1002538394 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev
/null -cm_name 26.prim_lfsr_gal_test.1002538394
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/26.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.2373708014
Short name T195
Test name
Test status
Simulation time 336812550000 ps
CPU time 231.11 seconds
Started Feb 08 08:11:13 AM UTC 25
Finished Feb 08 08:41:45 AM UTC 25
Peak memory 176652 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2373708014 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev
/null -cm_name 27.prim_lfsr_gal_test.2373708014
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/27.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.2963606104
Short name T183
Test name
Test status
Simulation time 336494850000 ps
CPU time 230.98 seconds
Started Feb 08 08:11:13 AM UTC 25
Finished Feb 08 08:41:40 AM UTC 25
Peak memory 176652 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2963606104 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev
/null -cm_name 28.prim_lfsr_gal_test.2963606104
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/28.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.3518514514
Short name T194
Test name
Test status
Simulation time 336576390000 ps
CPU time 230.7 seconds
Started Feb 08 08:11:14 AM UTC 25
Finished Feb 08 08:41:45 AM UTC 25
Peak memory 176652 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3518514514 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev
/null -cm_name 29.prim_lfsr_gal_test.3518514514
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/29.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.3124849605
Short name T191
Test name
Test status
Simulation time 336382330000 ps
CPU time 231.43 seconds
Started Feb 08 08:11:13 AM UTC 25
Finished Feb 08 08:41:44 AM UTC 25
Peak memory 175124 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3124849605 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev
/null -cm_name 3.prim_lfsr_gal_test.3124849605
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/3.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.1169503093
Short name T165
Test name
Test status
Simulation time 336905690000 ps
CPU time 231.15 seconds
Started Feb 08 08:11:14 AM UTC 25
Finished Feb 08 08:41:36 AM UTC 25
Peak memory 175020 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1169503093 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev
/null -cm_name 30.prim_lfsr_gal_test.1169503093
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/30.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.663080114
Short name T176
Test name
Test status
Simulation time 336969570000 ps
CPU time 232.23 seconds
Started Feb 08 08:11:14 AM UTC 25
Finished Feb 08 08:41:39 AM UTC 25
Peak memory 176656 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=663080114 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/
null -cm_name 31.prim_lfsr_gal_test.663080114
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/31.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.1245052923
Short name T23
Test name
Test status
Simulation time 336611010000 ps
CPU time 230.25 seconds
Started Feb 08 08:11:14 AM UTC 25
Finished Feb 08 08:41:33 AM UTC 25
Peak memory 176624 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1245052923 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev
/null -cm_name 32.prim_lfsr_gal_test.1245052923
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/32.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.2177127599
Short name T175
Test name
Test status
Simulation time 336425030000 ps
CPU time 230.55 seconds
Started Feb 08 08:11:14 AM UTC 25
Finished Feb 08 08:41:39 AM UTC 25
Peak memory 174436 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2177127599 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev
/null -cm_name 33.prim_lfsr_gal_test.2177127599
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/33.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.3180035389
Short name T171
Test name
Test status
Simulation time 336503850000 ps
CPU time 231 seconds
Started Feb 08 08:11:14 AM UTC 25
Finished Feb 08 08:41:38 AM UTC 25
Peak memory 176652 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3180035389 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev
/null -cm_name 34.prim_lfsr_gal_test.3180035389
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/34.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.4142762516
Short name T189
Test name
Test status
Simulation time 336843530000 ps
CPU time 231.69 seconds
Started Feb 08 08:11:14 AM UTC 25
Finished Feb 08 08:41:43 AM UTC 25
Peak memory 175120 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4142762516 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev
/null -cm_name 35.prim_lfsr_gal_test.4142762516
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/35.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.705725986
Short name T163
Test name
Test status
Simulation time 336452350000 ps
CPU time 232.09 seconds
Started Feb 08 08:11:14 AM UTC 25
Finished Feb 08 08:41:36 AM UTC 25
Peak memory 176656 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=705725986 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/
null -cm_name 36.prim_lfsr_gal_test.705725986
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/36.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.1812419389
Short name T30
Test name
Test status
Simulation time 336517110000 ps
CPU time 230.16 seconds
Started Feb 08 08:11:14 AM UTC 25
Finished Feb 08 08:41:35 AM UTC 25
Peak memory 174424 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1812419389 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev
/null -cm_name 37.prim_lfsr_gal_test.1812419389
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/37.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.2696669303
Short name T185
Test name
Test status
Simulation time 336645190000 ps
CPU time 231.11 seconds
Started Feb 08 08:11:15 AM UTC 25
Finished Feb 08 08:41:41 AM UTC 25
Peak memory 175120 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2696669303 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev
/null -cm_name 38.prim_lfsr_gal_test.2696669303
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/38.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.4142873018
Short name T187
Test name
Test status
Simulation time 336453990000 ps
CPU time 230.52 seconds
Started Feb 08 08:11:16 AM UTC 25
Finished Feb 08 08:41:42 AM UTC 25
Peak memory 176652 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4142873018 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev
/null -cm_name 39.prim_lfsr_gal_test.4142873018
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/39.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.3956721267
Short name T182
Test name
Test status
Simulation time 336668450000 ps
CPU time 231.24 seconds
Started Feb 08 08:11:13 AM UTC 25
Finished Feb 08 08:41:40 AM UTC 25
Peak memory 176652 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3956721267 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev
/null -cm_name 4.prim_lfsr_gal_test.3956721267
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/4.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.2831216338
Short name T198
Test name
Test status
Simulation time 337023030000 ps
CPU time 231.3 seconds
Started Feb 08 08:11:16 AM UTC 25
Finished Feb 08 08:41:48 AM UTC 25
Peak memory 176652 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2831216338 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev
/null -cm_name 40.prim_lfsr_gal_test.2831216338
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/40.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.2328131812
Short name T169
Test name
Test status
Simulation time 336364950000 ps
CPU time 231.46 seconds
Started Feb 08 08:11:16 AM UTC 25
Finished Feb 08 08:41:37 AM UTC 25
Peak memory 175120 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2328131812 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev
/null -cm_name 41.prim_lfsr_gal_test.2328131812
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/41.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.3333659134
Short name T27
Test name
Test status
Simulation time 336571190000 ps
CPU time 230.92 seconds
Started Feb 08 08:11:16 AM UTC 25
Finished Feb 08 08:41:33 AM UTC 25
Peak memory 176652 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3333659134 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev
/null -cm_name 42.prim_lfsr_gal_test.3333659134
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/42.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.999268801
Short name T196
Test name
Test status
Simulation time 336629850000 ps
CPU time 232.62 seconds
Started Feb 08 08:11:16 AM UTC 25
Finished Feb 08 08:41:46 AM UTC 25
Peak memory 176656 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=999268801 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/
null -cm_name 43.prim_lfsr_gal_test.999268801
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/43.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.1840920119
Short name T192
Test name
Test status
Simulation time 336819510000 ps
CPU time 232.63 seconds
Started Feb 08 08:11:21 AM UTC 25
Finished Feb 08 08:41:45 AM UTC 25
Peak memory 176652 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1840920119 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev
/null -cm_name 44.prim_lfsr_gal_test.1840920119
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/44.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.3625466664
Short name T197
Test name
Test status
Simulation time 336636770000 ps
CPU time 231.71 seconds
Started Feb 08 08:11:21 AM UTC 25
Finished Feb 08 08:41:47 AM UTC 25
Peak memory 175120 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3625466664 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev
/null -cm_name 45.prim_lfsr_gal_test.3625466664
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/45.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.3475847470
Short name T184
Test name
Test status
Simulation time 336885310000 ps
CPU time 230.58 seconds
Started Feb 08 08:11:21 AM UTC 25
Finished Feb 08 08:41:41 AM UTC 25
Peak memory 176652 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3475847470 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev
/null -cm_name 46.prim_lfsr_gal_test.3475847470
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/46.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.216975155
Short name T188
Test name
Test status
Simulation time 336495410000 ps
CPU time 231.42 seconds
Started Feb 08 08:11:21 AM UTC 25
Finished Feb 08 08:41:43 AM UTC 25
Peak memory 176644 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=216975155 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/
null -cm_name 47.prim_lfsr_gal_test.216975155
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/47.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.844751103
Short name T199
Test name
Test status
Simulation time 336432170000 ps
CPU time 233.04 seconds
Started Feb 08 08:11:21 AM UTC 25
Finished Feb 08 08:41:54 AM UTC 25
Peak memory 175124 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=844751103 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev/
null -cm_name 48.prim_lfsr_gal_test.844751103
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/48.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.3562770593
Short name T200
Test name
Test status
Simulation time 336432730000 ps
CPU time 232.59 seconds
Started Feb 08 08:11:28 AM UTC 25
Finished Feb 08 08:41:59 AM UTC 25
Peak memory 174916 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3562770593 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev
/null -cm_name 49.prim_lfsr_gal_test.3562770593
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/49.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.2060786298
Short name T168
Test name
Test status
Simulation time 336619470000 ps
CPU time 231.36 seconds
Started Feb 08 08:11:13 AM UTC 25
Finished Feb 08 08:41:37 AM UTC 25
Peak memory 176656 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2060786298 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev
/null -cm_name 5.prim_lfsr_gal_test.2060786298
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/5.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.4280375468
Short name T178
Test name
Test status
Simulation time 336724310000 ps
CPU time 231.11 seconds
Started Feb 08 08:11:13 AM UTC 25
Finished Feb 08 08:41:39 AM UTC 25
Peak memory 176656 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4280375468 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev
/null -cm_name 6.prim_lfsr_gal_test.4280375468
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/6.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.2518033714
Short name T190
Test name
Test status
Simulation time 336530010000 ps
CPU time 230.84 seconds
Started Feb 08 08:11:13 AM UTC 25
Finished Feb 08 08:41:43 AM UTC 25
Peak memory 176416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2518033714 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev
/null -cm_name 7.prim_lfsr_gal_test.2518033714
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/7.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.3146465928
Short name T173
Test name
Test status
Simulation time 336821610000 ps
CPU time 231.67 seconds
Started Feb 08 08:11:13 AM UTC 25
Finished Feb 08 08:41:38 AM UTC 25
Peak memory 175120 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3146465928 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev
/null -cm_name 8.prim_lfsr_gal_test.3146465928
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/8.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.3923537662
Short name T161
Test name
Test status
Simulation time 336849190000 ps
CPU time 231.77 seconds
Started Feb 08 08:11:13 AM UTC 25
Finished Feb 08 08:41:35 AM UTC 25
Peak memory 176652 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3923537662 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal.vdb -cm_log /dev
/null -cm_name 9.prim_lfsr_gal_test.3923537662
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/9.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.4150333268
Short name T120
Test name
Test status
Simulation time 1583150000 ps
CPU time 1.93 seconds
Started Feb 08 05:39:36 AM UTC 25
Finished Feb 08 05:39:47 AM UTC 25
Peak memory 177732 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4150333268 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/n
ull -cm_name 0.prim_lfsr_fib_smoke.4150333268
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/0.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.1336648041
Short name T113
Test name
Test status
Simulation time 1425950000 ps
CPU time 1.74 seconds
Started Feb 08 05:39:36 AM UTC 25
Finished Feb 08 05:39:46 AM UTC 25
Peak memory 177732 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1336648041 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/n
ull -cm_name 1.prim_lfsr_fib_smoke.1336648041
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/1.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.869138364
Short name T115
Test name
Test status
Simulation time 1397030000 ps
CPU time 1.75 seconds
Started Feb 08 05:39:36 AM UTC 25
Finished Feb 08 05:39:47 AM UTC 25
Peak memory 177724 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=869138364 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/nu
ll -cm_name 10.prim_lfsr_fib_smoke.869138364
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/10.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.1723485774
Short name T122
Test name
Test status
Simulation time 1517450000 ps
CPU time 1.9 seconds
Started Feb 08 05:39:37 AM UTC 25
Finished Feb 08 05:39:49 AM UTC 25
Peak memory 177732 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1723485774 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/n
ull -cm_name 11.prim_lfsr_fib_smoke.1723485774
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/11.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.2312852529
Short name T124
Test name
Test status
Simulation time 1502810000 ps
CPU time 1.91 seconds
Started Feb 08 05:39:37 AM UTC 25
Finished Feb 08 05:39:49 AM UTC 25
Peak memory 177732 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2312852529 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/n
ull -cm_name 12.prim_lfsr_fib_smoke.2312852529
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/12.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.3919330302
Short name T125
Test name
Test status
Simulation time 1513810000 ps
CPU time 1.94 seconds
Started Feb 08 05:39:37 AM UTC 25
Finished Feb 08 05:39:49 AM UTC 25
Peak memory 177732 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3919330302 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/n
ull -cm_name 13.prim_lfsr_fib_smoke.3919330302
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/13.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.4048246701
Short name T123
Test name
Test status
Simulation time 1356710000 ps
CPU time 1.87 seconds
Started Feb 08 05:39:38 AM UTC 25
Finished Feb 08 05:39:49 AM UTC 25
Peak memory 177732 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4048246701 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/n
ull -cm_name 14.prim_lfsr_fib_smoke.4048246701
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/14.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.3145811544
Short name T127
Test name
Test status
Simulation time 1392830000 ps
CPU time 1.78 seconds
Started Feb 08 05:39:38 AM UTC 25
Finished Feb 08 05:39:49 AM UTC 25
Peak memory 177732 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3145811544 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/n
ull -cm_name 15.prim_lfsr_fib_smoke.3145811544
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/15.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.762211733
Short name T135
Test name
Test status
Simulation time 1567550000 ps
CPU time 1.82 seconds
Started Feb 08 05:39:39 AM UTC 25
Finished Feb 08 05:39:51 AM UTC 25
Peak memory 177724 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=762211733 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/nu
ll -cm_name 16.prim_lfsr_fib_smoke.762211733
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/16.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.1856940087
Short name T136
Test name
Test status
Simulation time 1561090000 ps
CPU time 1.98 seconds
Started Feb 08 05:39:39 AM UTC 25
Finished Feb 08 05:39:51 AM UTC 25
Peak memory 177732 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1856940087 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/n
ull -cm_name 17.prim_lfsr_fib_smoke.1856940087
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/17.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.2864019583
Short name T130
Test name
Test status
Simulation time 1455130000 ps
CPU time 1.82 seconds
Started Feb 08 05:39:39 AM UTC 25
Finished Feb 08 05:39:50 AM UTC 25
Peak memory 177732 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2864019583 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/n
ull -cm_name 18.prim_lfsr_fib_smoke.2864019583
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/18.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.1299087969
Short name T134
Test name
Test status
Simulation time 1559950000 ps
CPU time 2.02 seconds
Started Feb 08 05:39:39 AM UTC 25
Finished Feb 08 05:39:51 AM UTC 25
Peak memory 177720 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1299087969 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/n
ull -cm_name 19.prim_lfsr_fib_smoke.1299087969
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/19.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.67457915
Short name T111
Test name
Test status
Simulation time 1339910000 ps
CPU time 1.8 seconds
Started Feb 08 05:39:36 AM UTC 25
Finished Feb 08 05:39:46 AM UTC 25
Peak memory 177828 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=67457915 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/nul
l -cm_name 2.prim_lfsr_fib_smoke.67457915
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/2.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.1907790992
Short name T126
Test name
Test status
Simulation time 1239610000 ps
CPU time 1.74 seconds
Started Feb 08 05:39:40 AM UTC 25
Finished Feb 08 05:39:49 AM UTC 25
Peak memory 177732 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1907790992 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/n
ull -cm_name 20.prim_lfsr_fib_smoke.1907790992
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/20.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.107643364
Short name T129
Test name
Test status
Simulation time 1335250000 ps
CPU time 1.82 seconds
Started Feb 08 05:39:40 AM UTC 25
Finished Feb 08 05:39:50 AM UTC 25
Peak memory 177724 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=107643364 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/nu
ll -cm_name 21.prim_lfsr_fib_smoke.107643364
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/21.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.1814498308
Short name T128
Test name
Test status
Simulation time 1345690000 ps
CPU time 1.64 seconds
Started Feb 08 05:39:40 AM UTC 25
Finished Feb 08 05:39:50 AM UTC 25
Peak memory 177732 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1814498308 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/n
ull -cm_name 22.prim_lfsr_fib_smoke.1814498308
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/22.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.4280689786
Short name T137
Test name
Test status
Simulation time 1571550000 ps
CPU time 2.01 seconds
Started Feb 08 05:39:40 AM UTC 25
Finished Feb 08 05:39:51 AM UTC 25
Peak memory 177720 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4280689786 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/n
ull -cm_name 23.prim_lfsr_fib_smoke.4280689786
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/23.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.4112276166
Short name T133
Test name
Test status
Simulation time 1462030000 ps
CPU time 1.67 seconds
Started Feb 08 05:39:40 AM UTC 25
Finished Feb 08 05:39:50 AM UTC 25
Peak memory 177732 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4112276166 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/n
ull -cm_name 24.prim_lfsr_fib_smoke.4112276166
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/24.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.791875468
Short name T132
Test name
Test status
Simulation time 1249950000 ps
CPU time 1.7 seconds
Started Feb 08 05:39:41 AM UTC 25
Finished Feb 08 05:39:50 AM UTC 25
Peak memory 177724 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=791875468 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/nu
ll -cm_name 25.prim_lfsr_fib_smoke.791875468
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/25.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.2609748697
Short name T140
Test name
Test status
Simulation time 1528710000 ps
CPU time 2.02 seconds
Started Feb 08 05:39:41 AM UTC 25
Finished Feb 08 05:39:52 AM UTC 25
Peak memory 177732 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2609748697 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/n
ull -cm_name 26.prim_lfsr_fib_smoke.2609748697
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/26.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.3469380674
Short name T131
Test name
Test status
Simulation time 1208250000 ps
CPU time 1.66 seconds
Started Feb 08 05:39:41 AM UTC 25
Finished Feb 08 05:39:50 AM UTC 25
Peak memory 177700 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3469380674 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/n
ull -cm_name 27.prim_lfsr_fib_smoke.3469380674
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/27.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.3323733252
Short name T141
Test name
Test status
Simulation time 1551830000 ps
CPU time 1.93 seconds
Started Feb 08 05:39:41 AM UTC 25
Finished Feb 08 05:39:52 AM UTC 25
Peak memory 177732 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3323733252 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/n
ull -cm_name 28.prim_lfsr_fib_smoke.3323733252
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/28.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.3952279191
Short name T145
Test name
Test status
Simulation time 1575410000 ps
CPU time 2.07 seconds
Started Feb 08 05:39:41 AM UTC 25
Finished Feb 08 05:39:52 AM UTC 25
Peak memory 177732 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3952279191 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/n
ull -cm_name 29.prim_lfsr_fib_smoke.3952279191
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/29.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.851492987
Short name T112
Test name
Test status
Simulation time 1378170000 ps
CPU time 1.67 seconds
Started Feb 08 05:39:36 AM UTC 25
Finished Feb 08 05:39:46 AM UTC 25
Peak memory 177640 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=851492987 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/nu
ll -cm_name 3.prim_lfsr_fib_smoke.851492987
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/3.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.3513214266
Short name T144
Test name
Test status
Simulation time 1605230000 ps
CPU time 1.96 seconds
Started Feb 08 05:39:41 AM UTC 25
Finished Feb 08 05:39:52 AM UTC 25
Peak memory 177732 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3513214266 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/n
ull -cm_name 30.prim_lfsr_fib_smoke.3513214266
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/30.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.53098703
Short name T142
Test name
Test status
Simulation time 1508050000 ps
CPU time 1.85 seconds
Started Feb 08 05:39:41 AM UTC 25
Finished Feb 08 05:39:52 AM UTC 25
Peak memory 177692 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=53098703 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/nul
l -cm_name 31.prim_lfsr_fib_smoke.53098703
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/31.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.1404591606
Short name T143
Test name
Test status
Simulation time 1543410000 ps
CPU time 1.92 seconds
Started Feb 08 05:39:41 AM UTC 25
Finished Feb 08 05:39:52 AM UTC 25
Peak memory 177732 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1404591606 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/n
ull -cm_name 32.prim_lfsr_fib_smoke.1404591606
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/32.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.3095168562
Short name T139
Test name
Test status
Simulation time 1365990000 ps
CPU time 1.68 seconds
Started Feb 08 05:39:41 AM UTC 25
Finished Feb 08 05:39:51 AM UTC 25
Peak memory 177660 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3095168562 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/n
ull -cm_name 33.prim_lfsr_fib_smoke.3095168562
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/33.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.209322890
Short name T138
Test name
Test status
Simulation time 1391970000 ps
CPU time 1.82 seconds
Started Feb 08 05:39:41 AM UTC 25
Finished Feb 08 05:39:51 AM UTC 25
Peak memory 177724 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=209322890 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/nu
ll -cm_name 34.prim_lfsr_fib_smoke.209322890
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/34.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.3281467861
Short name T146
Test name
Test status
Simulation time 1580770000 ps
CPU time 1.95 seconds
Started Feb 08 05:39:42 AM UTC 25
Finished Feb 08 05:39:53 AM UTC 25
Peak memory 177732 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3281467861 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/n
ull -cm_name 35.prim_lfsr_fib_smoke.3281467861
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/35.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.4143742570
Short name T147
Test name
Test status
Simulation time 1505530000 ps
CPU time 2.02 seconds
Started Feb 08 05:39:45 AM UTC 25
Finished Feb 08 05:39:56 AM UTC 25
Peak memory 177732 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4143742570 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/n
ull -cm_name 36.prim_lfsr_fib_smoke.4143742570
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/36.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.534447354
Short name T151
Test name
Test status
Simulation time 1537110000 ps
CPU time 1.93 seconds
Started Feb 08 05:39:46 AM UTC 25
Finished Feb 08 05:39:57 AM UTC 25
Peak memory 177720 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=534447354 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/nu
ll -cm_name 37.prim_lfsr_fib_smoke.534447354
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/37.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.183144573
Short name T149
Test name
Test status
Simulation time 1419230000 ps
CPU time 1.79 seconds
Started Feb 08 05:39:46 AM UTC 25
Finished Feb 08 05:39:56 AM UTC 25
Peak memory 177724 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=183144573 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/nu
ll -cm_name 38.prim_lfsr_fib_smoke.183144573
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/38.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.3837848891
Short name T148
Test name
Test status
Simulation time 1366250000 ps
CPU time 1.82 seconds
Started Feb 08 05:39:46 AM UTC 25
Finished Feb 08 05:39:56 AM UTC 25
Peak memory 177732 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3837848891 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/n
ull -cm_name 39.prim_lfsr_fib_smoke.3837848891
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/39.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.3622761515
Short name T114
Test name
Test status
Simulation time 1482690000 ps
CPU time 1.79 seconds
Started Feb 08 05:39:36 AM UTC 25
Finished Feb 08 05:39:47 AM UTC 25
Peak memory 177732 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3622761515 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/n
ull -cm_name 4.prim_lfsr_fib_smoke.3622761515
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/4.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.3385623015
Short name T150
Test name
Test status
Simulation time 1498590000 ps
CPU time 1.94 seconds
Started Feb 08 05:39:46 AM UTC 25
Finished Feb 08 05:39:57 AM UTC 25
Peak memory 177732 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3385623015 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/n
ull -cm_name 40.prim_lfsr_fib_smoke.3385623015
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/40.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.426270319
Short name T152
Test name
Test status
Simulation time 1504870000 ps
CPU time 1.93 seconds
Started Feb 08 05:39:46 AM UTC 25
Finished Feb 08 05:39:57 AM UTC 25
Peak memory 177724 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=426270319 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/nu
ll -cm_name 41.prim_lfsr_fib_smoke.426270319
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/41.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.4153920361
Short name T154
Test name
Test status
Simulation time 1415030000 ps
CPU time 1.92 seconds
Started Feb 08 05:39:47 AM UTC 25
Finished Feb 08 05:39:58 AM UTC 25
Peak memory 177732 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4153920361 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/n
ull -cm_name 42.prim_lfsr_fib_smoke.4153920361
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/42.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.16754233
Short name T160
Test name
Test status
Simulation time 1573670000 ps
CPU time 2.22 seconds
Started Feb 08 05:39:47 AM UTC 25
Finished Feb 08 05:39:59 AM UTC 25
Peak memory 177768 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16754233 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/nul
l -cm_name 43.prim_lfsr_fib_smoke.16754233
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/43.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.3858967179
Short name T155
Test name
Test status
Simulation time 1455990000 ps
CPU time 1.89 seconds
Started Feb 08 05:39:47 AM UTC 25
Finished Feb 08 05:39:58 AM UTC 25
Peak memory 177732 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3858967179 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/n
ull -cm_name 44.prim_lfsr_fib_smoke.3858967179
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/44.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.3685189257
Short name T157
Test name
Test status
Simulation time 1469490000 ps
CPU time 1.91 seconds
Started Feb 08 05:39:47 AM UTC 25
Finished Feb 08 05:39:58 AM UTC 25
Peak memory 177732 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3685189257 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/n
ull -cm_name 45.prim_lfsr_fib_smoke.3685189257
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/45.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.2027495282
Short name T156
Test name
Test status
Simulation time 1495930000 ps
CPU time 1.98 seconds
Started Feb 08 05:39:48 AM UTC 25
Finished Feb 08 05:39:58 AM UTC 25
Peak memory 177580 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2027495282 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/n
ull -cm_name 46.prim_lfsr_fib_smoke.2027495282
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/46.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.3528474733
Short name T159
Test name
Test status
Simulation time 1497010000 ps
CPU time 2.03 seconds
Started Feb 08 05:39:48 AM UTC 25
Finished Feb 08 05:39:58 AM UTC 25
Peak memory 177732 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3528474733 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/n
ull -cm_name 47.prim_lfsr_fib_smoke.3528474733
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/47.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.1457473115
Short name T158
Test name
Test status
Simulation time 1502350000 ps
CPU time 2.01 seconds
Started Feb 08 05:39:48 AM UTC 25
Finished Feb 08 05:39:58 AM UTC 25
Peak memory 177628 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1457473115 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/n
ull -cm_name 48.prim_lfsr_fib_smoke.1457473115
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/48.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.3385239750
Short name T153
Test name
Test status
Simulation time 1289270000 ps
CPU time 1.81 seconds
Started Feb 08 05:39:48 AM UTC 25
Finished Feb 08 05:39:58 AM UTC 25
Peak memory 177732 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3385239750 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/n
ull -cm_name 49.prim_lfsr_fib_smoke.3385239750
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/49.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.2628878337
Short name T116
Test name
Test status
Simulation time 1448710000 ps
CPU time 1.79 seconds
Started Feb 08 05:39:36 AM UTC 25
Finished Feb 08 05:39:47 AM UTC 25
Peak memory 177732 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2628878337 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/n
ull -cm_name 5.prim_lfsr_fib_smoke.2628878337
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/5.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.2833077757
Short name T119
Test name
Test status
Simulation time 1501350000 ps
CPU time 1.89 seconds
Started Feb 08 05:39:36 AM UTC 25
Finished Feb 08 05:39:47 AM UTC 25
Peak memory 177732 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2833077757 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/n
ull -cm_name 6.prim_lfsr_fib_smoke.2833077757
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/6.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.3720699633
Short name T117
Test name
Test status
Simulation time 1421710000 ps
CPU time 1.91 seconds
Started Feb 08 05:39:36 AM UTC 25
Finished Feb 08 05:39:47 AM UTC 25
Peak memory 177736 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3720699633 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/n
ull -cm_name 7.prim_lfsr_fib_smoke.3720699633
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/7.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.191153856
Short name T118
Test name
Test status
Simulation time 1420130000 ps
CPU time 1.88 seconds
Started Feb 08 05:39:36 AM UTC 25
Finished Feb 08 05:39:47 AM UTC 25
Peak memory 177736 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=191153856 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/nu
ll -cm_name 8.prim_lfsr_fib_smoke.191153856
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/8.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.1242650668
Short name T121
Test name
Test status
Simulation time 1564130000 ps
CPU time 1.85 seconds
Started Feb 08 05:39:36 AM UTC 25
Finished Feb 08 05:39:48 AM UTC 25
Peak memory 177732 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1242650668 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib.vdb -cm_log /dev/n
ull -cm_name 9.prim_lfsr_fib_smoke.1242650668
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/9.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.1938169142
Short name T38
Test name
Test status
Simulation time 1560910000 ps
CPU time 2 seconds
Started Feb 08 05:39:22 AM UTC 25
Finished Feb 08 05:39:35 AM UTC 25
Peak memory 177732 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1938169142 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/n
ull -cm_name 1.prim_lfsr_gal_smoke.1938169142
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/1.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.3533695570
Short name T39
Test name
Test status
Simulation time 1537030000 ps
CPU time 1.73 seconds
Started Feb 08 05:39:22 AM UTC 25
Finished Feb 08 05:39:36 AM UTC 25
Peak memory 177704 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3533695570 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/n
ull -cm_name 10.prim_lfsr_gal_smoke.3533695570
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/10.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.2641953336
Short name T40
Test name
Test status
Simulation time 1574790000 ps
CPU time 1.92 seconds
Started Feb 08 05:39:22 AM UTC 25
Finished Feb 08 05:39:36 AM UTC 25
Peak memory 177708 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2641953336 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/n
ull -cm_name 11.prim_lfsr_gal_smoke.2641953336
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/11.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.1360136168
Short name T8
Test name
Test status
Simulation time 1523370000 ps
CPU time 1.64 seconds
Started Feb 08 05:39:22 AM UTC 25
Finished Feb 08 05:39:34 AM UTC 25
Peak memory 177732 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1360136168 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/n
ull -cm_name 12.prim_lfsr_gal_smoke.1360136168
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/12.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.1897769143
Short name T34
Test name
Test status
Simulation time 1522970000 ps
CPU time 1.68 seconds
Started Feb 08 05:39:22 AM UTC 25
Finished Feb 08 05:39:35 AM UTC 25
Peak memory 177732 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1897769143 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/n
ull -cm_name 13.prim_lfsr_gal_smoke.1897769143
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/13.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.386594924
Short name T31
Test name
Test status
Simulation time 1604450000 ps
CPU time 1.74 seconds
Started Feb 08 05:39:22 AM UTC 25
Finished Feb 08 05:39:35 AM UTC 25
Peak memory 177724 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=386594924 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/nu
ll -cm_name 14.prim_lfsr_gal_smoke.386594924
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/14.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.1525585190
Short name T36
Test name
Test status
Simulation time 1593850000 ps
CPU time 1.73 seconds
Started Feb 08 05:39:22 AM UTC 25
Finished Feb 08 05:39:35 AM UTC 25
Peak memory 177732 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1525585190 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/n
ull -cm_name 15.prim_lfsr_gal_smoke.1525585190
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/15.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.2965094859
Short name T33
Test name
Test status
Simulation time 1325230000 ps
CPU time 1.65 seconds
Started Feb 08 05:39:23 AM UTC 25
Finished Feb 08 05:39:35 AM UTC 25
Peak memory 177552 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2965094859 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/n
ull -cm_name 16.prim_lfsr_gal_smoke.2965094859
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/16.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.1977037553
Short name T32
Test name
Test status
Simulation time 1319910000 ps
CPU time 1.66 seconds
Started Feb 08 05:39:23 AM UTC 25
Finished Feb 08 05:39:35 AM UTC 25
Peak memory 177640 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1977037553 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/n
ull -cm_name 17.prim_lfsr_gal_smoke.1977037553
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/17.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.898348076
Short name T37
Test name
Test status
Simulation time 1395130000 ps
CPU time 1.59 seconds
Started Feb 08 05:39:23 AM UTC 25
Finished Feb 08 05:39:35 AM UTC 25
Peak memory 177732 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=898348076 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/nu
ll -cm_name 18.prim_lfsr_gal_smoke.898348076
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/18.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.3571122083
Short name T12
Test name
Test status
Simulation time 1301770000 ps
CPU time 1.57 seconds
Started Feb 08 05:39:23 AM UTC 25
Finished Feb 08 05:39:35 AM UTC 25
Peak memory 177732 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3571122083 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/n
ull -cm_name 19.prim_lfsr_gal_smoke.3571122083
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/19.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.1234933759
Short name T11
Test name
Test status
Simulation time 1422030000 ps
CPU time 1.78 seconds
Started Feb 08 05:39:22 AM UTC 25
Finished Feb 08 05:39:35 AM UTC 25
Peak memory 177668 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1234933759 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/n
ull -cm_name 2.prim_lfsr_gal_smoke.1234933759
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/2.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.1449332789
Short name T41
Test name
Test status
Simulation time 1469630000 ps
CPU time 1.85 seconds
Started Feb 08 05:39:25 AM UTC 25
Finished Feb 08 05:39:37 AM UTC 25
Peak memory 177732 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1449332789 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/n
ull -cm_name 20.prim_lfsr_gal_smoke.1449332789
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/20.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.2821238753
Short name T42
Test name
Test status
Simulation time 1449550000 ps
CPU time 1.86 seconds
Started Feb 08 05:39:27 AM UTC 25
Finished Feb 08 05:39:38 AM UTC 25
Peak memory 177732 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2821238753 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/n
ull -cm_name 21.prim_lfsr_gal_smoke.2821238753
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/21.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.1672416606
Short name T50
Test name
Test status
Simulation time 1615270000 ps
CPU time 1.83 seconds
Started Feb 08 05:39:27 AM UTC 25
Finished Feb 08 05:39:39 AM UTC 25
Peak memory 177732 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1672416606 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/n
ull -cm_name 22.prim_lfsr_gal_smoke.1672416606
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/22.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.1187082549
Short name T51
Test name
Test status
Simulation time 1484410000 ps
CPU time 1.91 seconds
Started Feb 08 05:39:28 AM UTC 25
Finished Feb 08 05:39:39 AM UTC 25
Peak memory 177732 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1187082549 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/n
ull -cm_name 23.prim_lfsr_gal_smoke.1187082549
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/23.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.3463797414
Short name T43
Test name
Test status
Simulation time 1360690000 ps
CPU time 1.77 seconds
Started Feb 08 05:39:28 AM UTC 25
Finished Feb 08 05:39:38 AM UTC 25
Peak memory 177732 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3463797414 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/n
ull -cm_name 24.prim_lfsr_gal_smoke.3463797414
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/24.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.2766198438
Short name T54
Test name
Test status
Simulation time 1521450000 ps
CPU time 1.95 seconds
Started Feb 08 05:39:28 AM UTC 25
Finished Feb 08 05:39:39 AM UTC 25
Peak memory 177732 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2766198438 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/n
ull -cm_name 25.prim_lfsr_gal_smoke.2766198438
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/25.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.3100067212
Short name T57
Test name
Test status
Simulation time 1590010000 ps
CPU time 1.9 seconds
Started Feb 08 05:39:28 AM UTC 25
Finished Feb 08 05:39:40 AM UTC 25
Peak memory 177732 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3100067212 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/n
ull -cm_name 26.prim_lfsr_gal_smoke.3100067212
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/26.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.3717268836
Short name T49
Test name
Test status
Simulation time 1424990000 ps
CPU time 1.94 seconds
Started Feb 08 05:39:28 AM UTC 25
Finished Feb 08 05:39:39 AM UTC 25
Peak memory 177732 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3717268836 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/n
ull -cm_name 27.prim_lfsr_gal_smoke.3717268836
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/27.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.2788073249
Short name T45
Test name
Test status
Simulation time 1389850000 ps
CPU time 1.88 seconds
Started Feb 08 05:39:28 AM UTC 25
Finished Feb 08 05:39:38 AM UTC 25
Peak memory 177728 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2788073249 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/n
ull -cm_name 28.prim_lfsr_gal_smoke.2788073249
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/28.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.1907384036
Short name T60
Test name
Test status
Simulation time 1589270000 ps
CPU time 1.94 seconds
Started Feb 08 05:39:28 AM UTC 25
Finished Feb 08 05:39:40 AM UTC 25
Peak memory 177732 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1907384036 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/n
ull -cm_name 29.prim_lfsr_gal_smoke.1907384036
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/29.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.693520421
Short name T13
Test name
Test status
Simulation time 1581870000 ps
CPU time 1.65 seconds
Started Feb 08 05:39:22 AM UTC 25
Finished Feb 08 05:39:35 AM UTC 25
Peak memory 177736 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=693520421 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/nu
ll -cm_name 3.prim_lfsr_gal_smoke.693520421
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/3.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.2641394404
Short name T44
Test name
Test status
Simulation time 1337410000 ps
CPU time 1.75 seconds
Started Feb 08 05:39:28 AM UTC 25
Finished Feb 08 05:39:38 AM UTC 25
Peak memory 177732 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2641394404 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/n
ull -cm_name 30.prim_lfsr_gal_smoke.2641394404
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/30.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.437232962
Short name T52
Test name
Test status
Simulation time 1520570000 ps
CPU time 1.84 seconds
Started Feb 08 05:39:28 AM UTC 25
Finished Feb 08 05:39:39 AM UTC 25
Peak memory 177724 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=437232962 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/nu
ll -cm_name 31.prim_lfsr_gal_smoke.437232962
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/31.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.2350819856
Short name T61
Test name
Test status
Simulation time 1578690000 ps
CPU time 2 seconds
Started Feb 08 05:39:28 AM UTC 25
Finished Feb 08 05:39:40 AM UTC 25
Peak memory 177732 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2350819856 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/n
ull -cm_name 32.prim_lfsr_gal_smoke.2350819856
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/32.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.2793897159
Short name T46
Test name
Test status
Simulation time 1365430000 ps
CPU time 1.76 seconds
Started Feb 08 05:39:28 AM UTC 25
Finished Feb 08 05:39:39 AM UTC 25
Peak memory 177732 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2793897159 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/n
ull -cm_name 33.prim_lfsr_gal_smoke.2793897159
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/33.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.2167419856
Short name T47
Test name
Test status
Simulation time 1361190000 ps
CPU time 1.77 seconds
Started Feb 08 05:39:28 AM UTC 25
Finished Feb 08 05:39:39 AM UTC 25
Peak memory 177732 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2167419856 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/n
ull -cm_name 34.prim_lfsr_gal_smoke.2167419856
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/34.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.35294613
Short name T58
Test name
Test status
Simulation time 1509030000 ps
CPU time 1.9 seconds
Started Feb 08 05:39:28 AM UTC 25
Finished Feb 08 05:39:40 AM UTC 25
Peak memory 177628 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=35294613 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/nul
l -cm_name 35.prim_lfsr_gal_smoke.35294613
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/35.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.3394339049
Short name T55
Test name
Test status
Simulation time 1436130000 ps
CPU time 1.92 seconds
Started Feb 08 05:39:28 AM UTC 25
Finished Feb 08 05:39:39 AM UTC 25
Peak memory 177688 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3394339049 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/n
ull -cm_name 36.prim_lfsr_gal_smoke.3394339049
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/36.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.3484141236
Short name T56
Test name
Test status
Simulation time 1482110000 ps
CPU time 1.8 seconds
Started Feb 08 05:39:28 AM UTC 25
Finished Feb 08 05:39:39 AM UTC 25
Peak memory 177732 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3484141236 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/n
ull -cm_name 37.prim_lfsr_gal_smoke.3484141236
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/37.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.1053826209
Short name T59
Test name
Test status
Simulation time 1510950000 ps
CPU time 1.84 seconds
Started Feb 08 05:39:28 AM UTC 25
Finished Feb 08 05:39:40 AM UTC 25
Peak memory 177700 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1053826209 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/n
ull -cm_name 38.prim_lfsr_gal_smoke.1053826209
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/38.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.1266343227
Short name T48
Test name
Test status
Simulation time 1331850000 ps
CPU time 1.92 seconds
Started Feb 08 05:39:28 AM UTC 25
Finished Feb 08 05:39:39 AM UTC 25
Peak memory 177732 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1266343227 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/n
ull -cm_name 39.prim_lfsr_gal_smoke.1266343227
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/39.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.3076194044
Short name T10
Test name
Test status
Simulation time 1479350000 ps
CPU time 1.69 seconds
Started Feb 08 05:39:22 AM UTC 25
Finished Feb 08 05:39:35 AM UTC 25
Peak memory 177732 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3076194044 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/n
ull -cm_name 4.prim_lfsr_gal_smoke.3076194044
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/4.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.995922169
Short name T53
Test name
Test status
Simulation time 1422070000 ps
CPU time 1.81 seconds
Started Feb 08 05:39:28 AM UTC 25
Finished Feb 08 05:39:39 AM UTC 25
Peak memory 177724 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=995922169 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/nu
ll -cm_name 40.prim_lfsr_gal_smoke.995922169
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/40.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.3897297676
Short name T62
Test name
Test status
Simulation time 1545450000 ps
CPU time 1.93 seconds
Started Feb 08 05:39:29 AM UTC 25
Finished Feb 08 05:39:41 AM UTC 25
Peak memory 177732 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3897297676 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/n
ull -cm_name 41.prim_lfsr_gal_smoke.3897297676
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/41.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.631103096
Short name T63
Test name
Test status
Simulation time 1356110000 ps
CPU time 1.82 seconds
Started Feb 08 05:39:33 AM UTC 25
Finished Feb 08 05:39:44 AM UTC 25
Peak memory 177700 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=631103096 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/nu
ll -cm_name 42.prim_lfsr_gal_smoke.631103096
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/42.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.14081870
Short name T64
Test name
Test status
Simulation time 1504090000 ps
CPU time 1.98 seconds
Started Feb 08 05:39:33 AM UTC 25
Finished Feb 08 05:39:45 AM UTC 25
Peak memory 177756 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=14081870 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/nul
l -cm_name 43.prim_lfsr_gal_smoke.14081870
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/43.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.739011214
Short name T67
Test name
Test status
Simulation time 1506030000 ps
CPU time 1.85 seconds
Started Feb 08 05:39:35 AM UTC 25
Finished Feb 08 05:39:45 AM UTC 25
Peak memory 177724 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=739011214 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/nu
ll -cm_name 44.prim_lfsr_gal_smoke.739011214
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/44.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.3379354940
Short name T66
Test name
Test status
Simulation time 1453750000 ps
CPU time 1.88 seconds
Started Feb 08 05:39:35 AM UTC 25
Finished Feb 08 05:39:45 AM UTC 25
Peak memory 177732 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3379354940 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/n
ull -cm_name 45.prim_lfsr_gal_smoke.3379354940
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/45.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.3752308026
Short name T68
Test name
Test status
Simulation time 1576270000 ps
CPU time 1.89 seconds
Started Feb 08 05:39:35 AM UTC 25
Finished Feb 08 05:39:46 AM UTC 25
Peak memory 177732 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3752308026 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/n
ull -cm_name 46.prim_lfsr_gal_smoke.3752308026
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/46.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.1851799312
Short name T69
Test name
Test status
Simulation time 1622830000 ps
CPU time 1.95 seconds
Started Feb 08 05:39:35 AM UTC 25
Finished Feb 08 05:39:46 AM UTC 25
Peak memory 177728 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1851799312 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/n
ull -cm_name 47.prim_lfsr_gal_smoke.1851799312
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/47.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.1795186056
Short name T65
Test name
Test status
Simulation time 1359950000 ps
CPU time 1.89 seconds
Started Feb 08 05:39:35 AM UTC 25
Finished Feb 08 05:39:45 AM UTC 25
Peak memory 177732 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1795186056 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/n
ull -cm_name 48.prim_lfsr_gal_smoke.1795186056
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/48.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.3206180478
Short name T70
Test name
Test status
Simulation time 1510230000 ps
CPU time 1.88 seconds
Started Feb 08 05:39:36 AM UTC 25
Finished Feb 08 05:39:47 AM UTC 25
Peak memory 177732 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3206180478 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/n
ull -cm_name 49.prim_lfsr_gal_smoke.3206180478
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/49.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.2798935133
Short name T7
Test name
Test status
Simulation time 1308190000 ps
CPU time 1.59 seconds
Started Feb 08 05:39:22 AM UTC 25
Finished Feb 08 05:39:34 AM UTC 25
Peak memory 177712 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2798935133 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/n
ull -cm_name 5.prim_lfsr_gal_smoke.2798935133
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/5.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.1683022974
Short name T35
Test name
Test status
Simulation time 1511610000 ps
CPU time 1.8 seconds
Started Feb 08 05:39:22 AM UTC 25
Finished Feb 08 05:39:35 AM UTC 25
Peak memory 177732 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1683022974 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/n
ull -cm_name 6.prim_lfsr_gal_smoke.1683022974
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/6.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.4044790587
Short name T3
Test name
Test status
Simulation time 1430190000 ps
CPU time 1.7 seconds
Started Feb 08 05:39:22 AM UTC 25
Finished Feb 08 05:39:34 AM UTC 25
Peak memory 177732 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4044790587 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/n
ull -cm_name 7.prim_lfsr_gal_smoke.4044790587
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/7.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.3159788404
Short name T2
Test name
Test status
Simulation time 1481210000 ps
CPU time 1.55 seconds
Started Feb 08 05:39:22 AM UTC 25
Finished Feb 08 05:39:34 AM UTC 25
Peak memory 177688 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3159788404 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/n
ull -cm_name 8.prim_lfsr_gal_smoke.3159788404
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/8.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.1263896978
Short name T9
Test name
Test status
Simulation time 1333170000 ps
CPU time 1.55 seconds
Started Feb 08 05:39:22 AM UTC 25
Finished Feb 08 05:39:34 AM UTC 25
Peak memory 177732 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1263896978 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal.vdb -cm_log /dev/n
ull -cm_name 9.prim_lfsr_gal_smoke.1263896978
Directory /workspaces/repo/scratch/os_regression/prim_lfsr-sim-vcs/9.prim_lfsr_gal_smoke/latest