Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.31 100.00 96.55 100.00 100.00 95.00


Total tests in report: 200
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
87.31 87.31 100.00 100.00 96.55 96.55 100.00 100.00 100.00 100.00 40.00 40.00 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.268297415
95.31 8.00 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 80.00 40.00 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.4226153622
96.81 1.50 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 87.50 7.50 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.2156182190
98.31 1.50 100.00 0.00 96.55 0.00 100.00 0.00 100.00 0.00 95.00 7.50 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.290442687

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.2785468238
/workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.1907055475
/workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.1034590518
/workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.3942375716
/workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.2328855339
/workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.2774986128
/workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.2165190948
/workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.2595896361
/workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.124414276
/workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.1951046571
/workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.2486168683
/workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.2977760165
/workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.884530539
/workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.3247344900
/workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.1996037091
/workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.215579857
/workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.1077668160
/workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.2029164509
/workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.2059129471
/workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.2467767389
/workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.2255307047
/workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.3940176208
/workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.3534980528
/workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.1589771503
/workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.3497510105
/workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.606651036
/workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.4167900197
/workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.4226817424
/workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.779215569
/workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.2626562307
/workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.2784261029
/workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.1699457417
/workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.4073668133
/workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.339151417
/workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.888040457
/workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.1037747884
/workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.1288340985
/workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.3362144550
/workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.1567579845
/workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.2092251426
/workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.2751816340
/workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.276131533
/workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.3932460883
/workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.870611839
/workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.2460898650
/workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.609382012
/workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.2872225494
/workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.1529768388
/workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.1001866752
/workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.2421669502
/workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.1803381168
/workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.2870120109
/workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.3715992753
/workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.1904273778
/workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.2074401117
/workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.3235907450
/workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.694321738
/workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.4000682557
/workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.2540920670
/workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.215015667
/workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.799223318
/workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.1820175651
/workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.1173005968
/workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.2758501594
/workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.4008775256
/workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.3193461296
/workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.3435999803
/workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.426282012
/workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.4260381010
/workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.3736017095
/workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.2353539686
/workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.3401877886
/workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.279216646
/workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.591365725
/workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.2747477321
/workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.2748073802
/workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.2881246029
/workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.825692050
/workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.2548202508
/workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.1501853236
/workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.2479635297
/workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.4177263239
/workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.764037647
/workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.1074098437
/workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.2716683982
/workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.368717099
/workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.1742303862
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/workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.2223759740
/workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.88555695
/workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.2040610106
/workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.1158307234
/workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.29009156
/workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.206481761
/workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.1889275855
/workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.3520769943
/workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.1097022322
/workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.1650463293
/workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.2062439586
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Total test records in report: 200
tests.html | tests1.html | tests2.html | tests3.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.9228132 Oct 15 09:48:18 AM UTC 24 Oct 15 09:48:29 AM UTC 24 1171730000 ps
T2 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.265413297 Oct 15 09:48:17 AM UTC 24 Oct 15 09:48:29 AM UTC 24 1268370000 ps
T3 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.935376137 Oct 15 09:48:17 AM UTC 24 Oct 15 09:48:29 AM UTC 24 1293490000 ps
T7 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.904211642 Oct 15 09:48:17 AM UTC 24 Oct 15 09:48:29 AM UTC 24 1350390000 ps
T8 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.268297415 Oct 15 09:48:17 AM UTC 24 Oct 15 09:48:29 AM UTC 24 1325390000 ps
T9 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.632709679 Oct 15 09:48:17 AM UTC 24 Oct 15 09:48:29 AM UTC 24 1318150000 ps
T10 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.1652894155 Oct 15 09:48:17 AM UTC 24 Oct 15 09:48:29 AM UTC 24 1327550000 ps
T11 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.3996021680 Oct 15 09:48:17 AM UTC 24 Oct 15 09:48:30 AM UTC 24 1353810000 ps
T12 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.3268988708 Oct 15 09:48:17 AM UTC 24 Oct 15 09:48:30 AM UTC 24 1323090000 ps
T13 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.1016565072 Oct 15 09:48:18 AM UTC 24 Oct 15 09:48:30 AM UTC 24 1334470000 ps
T41 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.2680666258 Oct 15 09:48:17 AM UTC 24 Oct 15 09:48:30 AM UTC 24 1456410000 ps
T42 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.3103589569 Oct 15 09:48:17 AM UTC 24 Oct 15 09:48:30 AM UTC 24 1488090000 ps
T43 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.1752158774 Oct 15 09:48:17 AM UTC 24 Oct 15 09:48:30 AM UTC 24 1428310000 ps
T44 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.265882668 Oct 15 09:48:17 AM UTC 24 Oct 15 09:48:30 AM UTC 24 1407030000 ps
T45 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.3200872253 Oct 15 09:48:18 AM UTC 24 Oct 15 09:48:30 AM UTC 24 1408130000 ps
T46 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.1674279373 Oct 15 09:48:17 AM UTC 24 Oct 15 09:48:30 AM UTC 24 1452430000 ps
T47 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.2164436422 Oct 15 09:48:17 AM UTC 24 Oct 15 09:48:30 AM UTC 24 1460590000 ps
T48 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.825556102 Oct 15 09:48:18 AM UTC 24 Oct 15 09:48:31 AM UTC 24 1458790000 ps
T49 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.3187082928 Oct 15 09:48:18 AM UTC 24 Oct 15 09:48:31 AM UTC 24 1440170000 ps
T50 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.769350748 Oct 15 09:48:17 AM UTC 24 Oct 15 09:48:31 AM UTC 24 1577950000 ps
T51 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.461852847 Oct 15 09:48:17 AM UTC 24 Oct 15 09:48:31 AM UTC 24 1536610000 ps
T52 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.2818867720 Oct 15 09:48:17 AM UTC 24 Oct 15 09:48:31 AM UTC 24 1567350000 ps
T53 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.2904784285 Oct 15 09:48:17 AM UTC 24 Oct 15 09:48:31 AM UTC 24 1557610000 ps
T54 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.2722945881 Oct 15 09:48:20 AM UTC 24 Oct 15 09:48:31 AM UTC 24 1257150000 ps
T55 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.2837893542 Oct 15 09:48:18 AM UTC 24 Oct 15 09:48:31 AM UTC 24 1541290000 ps
T56 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.3415969220 Oct 15 09:48:18 AM UTC 24 Oct 15 09:48:31 AM UTC 24 1565770000 ps
T57 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.2783986334 Oct 15 09:48:17 AM UTC 24 Oct 15 09:48:32 AM UTC 24 1613910000 ps
T58 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.1781503602 Oct 15 09:48:20 AM UTC 24 Oct 15 09:48:32 AM UTC 24 1300490000 ps
T59 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.1418210133 Oct 15 09:48:20 AM UTC 24 Oct 15 09:48:32 AM UTC 24 1430310000 ps
T60 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.3076610606 Oct 15 09:48:20 AM UTC 24 Oct 15 09:48:32 AM UTC 24 1449950000 ps
T61 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.3755030158 Oct 15 09:48:20 AM UTC 24 Oct 15 09:48:33 AM UTC 24 1512470000 ps
T62 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.3196413061 Oct 15 09:48:22 AM UTC 24 Oct 15 09:48:33 AM UTC 24 1309710000 ps
T63 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.3998506987 Oct 15 09:48:22 AM UTC 24 Oct 15 09:48:34 AM UTC 24 1434070000 ps
T64 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.1453123139 Oct 15 09:48:22 AM UTC 24 Oct 15 09:48:35 AM UTC 24 1466770000 ps
T65 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.3926894695 Oct 15 09:48:27 AM UTC 24 Oct 15 09:48:37 AM UTC 24 1256090000 ps
T66 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.1439588815 Oct 15 09:48:27 AM UTC 24 Oct 15 09:48:37 AM UTC 24 1252970000 ps
T67 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.771799632 Oct 15 09:48:27 AM UTC 24 Oct 15 09:48:37 AM UTC 24 1250970000 ps
T68 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.3327309982 Oct 15 09:48:27 AM UTC 24 Oct 15 09:48:37 AM UTC 24 1228130000 ps
T69 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.1402852482 Oct 15 09:48:27 AM UTC 24 Oct 15 09:48:37 AM UTC 24 1369770000 ps
T70 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.155802523 Oct 15 09:48:27 AM UTC 24 Oct 15 09:48:37 AM UTC 24 1280590000 ps
T71 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.1645593396 Oct 15 09:48:27 AM UTC 24 Oct 15 09:48:37 AM UTC 24 1389910000 ps
T72 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.1017368306 Oct 15 09:48:27 AM UTC 24 Oct 15 09:48:38 AM UTC 24 1461630000 ps
T73 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.1030405888 Oct 15 09:48:27 AM UTC 24 Oct 15 09:48:38 AM UTC 24 1444150000 ps
T74 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.3419004261 Oct 15 09:48:27 AM UTC 24 Oct 15 09:48:38 AM UTC 24 1428690000 ps
T75 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.2708093597 Oct 15 09:48:27 AM UTC 24 Oct 15 09:48:38 AM UTC 24 1447510000 ps
T76 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.2897609950 Oct 15 09:48:27 AM UTC 24 Oct 15 09:48:38 AM UTC 24 1526270000 ps
T77 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.93605104 Oct 15 09:48:27 AM UTC 24 Oct 15 09:48:38 AM UTC 24 1512990000 ps
T78 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.4142159001 Oct 15 09:48:27 AM UTC 24 Oct 15 09:48:39 AM UTC 24 1526450000 ps
T79 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.3217960459 Oct 15 09:48:27 AM UTC 24 Oct 15 09:48:39 AM UTC 24 1570110000 ps
T80 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.3229883183 Oct 15 09:48:27 AM UTC 24 Oct 15 09:48:39 AM UTC 24 1583670000 ps
T14 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.3520769943 Oct 15 09:52:53 AM UTC 24 Oct 15 10:27:11 AM UTC 24 336702030000 ps
T15 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.1889275855 Oct 15 09:52:53 AM UTC 24 Oct 15 10:27:15 AM UTC 24 336572270000 ps
T16 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.4226153622 Oct 15 09:52:50 AM UTC 24 Oct 15 10:27:16 AM UTC 24 336889830000 ps
T17 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.799223318 Oct 15 09:52:51 AM UTC 24 Oct 15 10:27:17 AM UTC 24 336940510000 ps
T18 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.1097022322 Oct 15 09:52:53 AM UTC 24 Oct 15 10:27:17 AM UTC 24 336380170000 ps
T19 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.2421669502 Oct 15 09:52:50 AM UTC 24 Oct 15 10:27:18 AM UTC 24 336348230000 ps
T20 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.2870120109 Oct 15 09:52:56 AM UTC 24 Oct 15 10:27:19 AM UTC 24 336633650000 ps
T21 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.1650463293 Oct 15 09:52:53 AM UTC 24 Oct 15 10:27:20 AM UTC 24 336971870000 ps
T22 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.764037647 Oct 15 09:52:52 AM UTC 24 Oct 15 10:27:21 AM UTC 24 337040070000 ps
T23 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.3401877886 Oct 15 09:52:51 AM UTC 24 Oct 15 10:27:21 AM UTC 24 336981190000 ps
T81 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.1904273778 Oct 15 09:52:58 AM UTC 24 Oct 15 10:27:21 AM UTC 24 336621710000 ps
T82 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.694321738 Oct 15 09:52:59 AM UTC 24 Oct 15 10:27:22 AM UTC 24 336450390000 ps
T83 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.1803381168 Oct 15 09:52:54 AM UTC 24 Oct 15 10:27:23 AM UTC 24 336393990000 ps
T84 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.206481761 Oct 15 09:52:53 AM UTC 24 Oct 15 10:27:24 AM UTC 24 336456230000 ps
T85 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.2881246029 Oct 15 09:53:04 AM UTC 24 Oct 15 10:27:24 AM UTC 24 336664710000 ps
T86 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.3715992753 Oct 15 09:52:58 AM UTC 24 Oct 15 10:27:24 AM UTC 24 336727190000 ps
T87 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.4000682557 Oct 15 09:53:00 AM UTC 24 Oct 15 10:27:25 AM UTC 24 336462530000 ps
T88 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.3235907450 Oct 15 09:52:59 AM UTC 24 Oct 15 10:27:26 AM UTC 24 336851750000 ps
T89 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.2353539686 Oct 15 09:53:02 AM UTC 24 Oct 15 10:27:26 AM UTC 24 336533550000 ps
T90 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.3193461296 Oct 15 09:53:02 AM UTC 24 Oct 15 10:27:28 AM UTC 24 336715430000 ps
T91 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.1820175651 Oct 15 09:53:02 AM UTC 24 Oct 15 10:27:28 AM UTC 24 336883430000 ps
T92 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.215015667 Oct 15 09:53:02 AM UTC 24 Oct 15 10:27:28 AM UTC 24 336880330000 ps
T93 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.825692050 Oct 15 09:53:05 AM UTC 24 Oct 15 10:27:28 AM UTC 24 336500570000 ps
T94 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.1173005968 Oct 15 09:53:02 AM UTC 24 Oct 15 10:27:29 AM UTC 24 336578330000 ps
T95 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.279216646 Oct 15 09:53:02 AM UTC 24 Oct 15 10:27:29 AM UTC 24 336759450000 ps
T96 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.426282012 Oct 15 09:53:02 AM UTC 24 Oct 15 10:27:30 AM UTC 24 336859130000 ps
T97 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.2758501594 Oct 15 09:53:02 AM UTC 24 Oct 15 10:27:30 AM UTC 24 337099530000 ps
T98 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.2074401117 Oct 15 09:52:58 AM UTC 24 Oct 15 10:27:30 AM UTC 24 336424270000 ps
T99 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.1074098437 Oct 15 09:53:07 AM UTC 24 Oct 15 10:27:30 AM UTC 24 336827670000 ps
T100 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.3736017095 Oct 15 09:53:02 AM UTC 24 Oct 15 10:27:30 AM UTC 24 336733870000 ps
T101 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.2748073802 Oct 15 09:53:04 AM UTC 24 Oct 15 10:27:31 AM UTC 24 336442930000 ps
T102 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.3435999803 Oct 15 09:53:02 AM UTC 24 Oct 15 10:27:31 AM UTC 24 336479450000 ps
T103 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.4008775256 Oct 15 09:53:02 AM UTC 24 Oct 15 10:27:31 AM UTC 24 337062490000 ps
T104 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.2223759740 Oct 15 09:53:09 AM UTC 24 Oct 15 10:27:31 AM UTC 24 336427290000 ps
T105 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.1501853236 Oct 15 09:53:05 AM UTC 24 Oct 15 10:27:32 AM UTC 24 336709010000 ps
T106 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.2040610106 Oct 15 09:53:10 AM UTC 24 Oct 15 10:27:34 AM UTC 24 336983350000 ps
T107 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.4177263239 Oct 15 09:53:07 AM UTC 24 Oct 15 10:27:34 AM UTC 24 336891510000 ps
T108 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.591365725 Oct 15 09:53:04 AM UTC 24 Oct 15 10:27:36 AM UTC 24 337015690000 ps
T109 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.1158307234 Oct 15 09:53:10 AM UTC 24 Oct 15 10:27:36 AM UTC 24 336858870000 ps
T110 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.2548202508 Oct 15 09:53:05 AM UTC 24 Oct 15 10:27:37 AM UTC 24 336610410000 ps
T111 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.2540920670 Oct 15 09:53:00 AM UTC 24 Oct 15 10:27:37 AM UTC 24 337041890000 ps
T112 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.4260381010 Oct 15 09:53:02 AM UTC 24 Oct 15 10:27:39 AM UTC 24 336510770000 ps
T113 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.2747477321 Oct 15 09:53:04 AM UTC 24 Oct 15 10:27:39 AM UTC 24 336736310000 ps
T114 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.368717099 Oct 15 09:53:09 AM UTC 24 Oct 15 10:27:40 AM UTC 24 336643810000 ps
T115 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.88555695 Oct 15 09:53:09 AM UTC 24 Oct 15 10:27:40 AM UTC 24 336950150000 ps
T116 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.2716683982 Oct 15 09:53:07 AM UTC 24 Oct 15 10:27:40 AM UTC 24 336868090000 ps
T117 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.2479635297 Oct 15 09:53:07 AM UTC 24 Oct 15 10:27:41 AM UTC 24 336623790000 ps
T118 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.1742303862 Oct 15 09:53:09 AM UTC 24 Oct 15 10:27:43 AM UTC 24 336908050000 ps
T119 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.3148589877 Oct 15 09:53:09 AM UTC 24 Oct 15 10:27:43 AM UTC 24 336906970000 ps
T120 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.29009156 Oct 15 09:53:14 AM UTC 24 Oct 15 10:27:44 AM UTC 24 336779830000 ps
T4 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.683937629 Oct 15 09:48:33 AM UTC 24 Oct 15 09:48:42 AM UTC 24 1106210000 ps
T5 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.655838017 Oct 15 09:48:33 AM UTC 24 Oct 15 09:48:42 AM UTC 24 1290250000 ps
T6 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.2783678557 Oct 15 09:48:33 AM UTC 24 Oct 15 09:48:42 AM UTC 24 1311530000 ps
T24 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.4053206861 Oct 15 09:48:33 AM UTC 24 Oct 15 09:48:43 AM UTC 24 1337290000 ps
T25 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.4219565927 Oct 15 09:48:33 AM UTC 24 Oct 15 09:48:43 AM UTC 24 1364530000 ps
T26 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.2323029305 Oct 15 09:48:33 AM UTC 24 Oct 15 09:48:43 AM UTC 24 1352330000 ps
T27 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.290442687 Oct 15 09:48:32 AM UTC 24 Oct 15 09:48:43 AM UTC 24 1437050000 ps
T28 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.3278746822 Oct 15 09:48:33 AM UTC 24 Oct 15 09:48:43 AM UTC 24 1298810000 ps
T29 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.2464476434 Oct 15 09:48:33 AM UTC 24 Oct 15 09:48:43 AM UTC 24 1428830000 ps
T30 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.2062439586 Oct 15 09:48:32 AM UTC 24 Oct 15 09:48:43 AM UTC 24 1479810000 ps
T121 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.1261241058 Oct 15 09:48:33 AM UTC 24 Oct 15 09:48:43 AM UTC 24 1389270000 ps
T122 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.3476773411 Oct 15 09:48:33 AM UTC 24 Oct 15 09:48:43 AM UTC 24 1425570000 ps
T123 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.203105368 Oct 15 09:48:32 AM UTC 24 Oct 15 09:48:43 AM UTC 24 1478770000 ps
T124 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.3446213637 Oct 15 09:48:33 AM UTC 24 Oct 15 09:48:43 AM UTC 24 1460190000 ps
T125 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.3629624425 Oct 15 09:48:33 AM UTC 24 Oct 15 09:48:43 AM UTC 24 1440150000 ps
T126 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.4024633283 Oct 15 09:48:32 AM UTC 24 Oct 15 09:48:43 AM UTC 24 1537970000 ps
T127 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.2255581286 Oct 15 09:48:33 AM UTC 24 Oct 15 09:48:44 AM UTC 24 1448030000 ps
T128 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.2473906403 Oct 15 09:48:33 AM UTC 24 Oct 15 09:48:44 AM UTC 24 1513090000 ps
T129 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.959224163 Oct 15 09:48:33 AM UTC 24 Oct 15 09:48:44 AM UTC 24 1520070000 ps
T130 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.3631250390 Oct 15 09:48:34 AM UTC 24 Oct 15 09:48:44 AM UTC 24 1278050000 ps
T131 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.93618885 Oct 15 09:48:33 AM UTC 24 Oct 15 09:48:44 AM UTC 24 1519850000 ps
T132 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.4213465908 Oct 15 09:48:33 AM UTC 24 Oct 15 09:48:44 AM UTC 24 1498790000 ps
T133 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.149185671 Oct 15 09:48:32 AM UTC 24 Oct 15 09:48:44 AM UTC 24 1591870000 ps
T134 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.1460473439 Oct 15 09:48:33 AM UTC 24 Oct 15 09:48:44 AM UTC 24 1469190000 ps
T135 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.2274549363 Oct 15 09:48:33 AM UTC 24 Oct 15 09:48:44 AM UTC 24 1583010000 ps
T136 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.3407837472 Oct 15 09:48:33 AM UTC 24 Oct 15 09:48:44 AM UTC 24 1471530000 ps
T137 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.2461003298 Oct 15 09:48:33 AM UTC 24 Oct 15 09:48:44 AM UTC 24 1570950000 ps
T138 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.1409293546 Oct 15 09:48:33 AM UTC 24 Oct 15 09:48:44 AM UTC 24 1444210000 ps
T139 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.447653111 Oct 15 09:48:33 AM UTC 24 Oct 15 09:48:44 AM UTC 24 1566530000 ps
T140 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.2780259199 Oct 15 09:48:33 AM UTC 24 Oct 15 09:48:44 AM UTC 24 1493330000 ps
T141 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.1802642528 Oct 15 09:48:33 AM UTC 24 Oct 15 09:48:44 AM UTC 24 1607530000 ps
T142 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.381309445 Oct 15 09:48:35 AM UTC 24 Oct 15 09:48:44 AM UTC 24 1370990000 ps
T143 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.1309049713 Oct 15 09:48:34 AM UTC 24 Oct 15 09:48:45 AM UTC 24 1498510000 ps
T144 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.3652028264 Oct 15 09:48:36 AM UTC 24 Oct 15 09:48:45 AM UTC 24 1345710000 ps
T145 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.3941222067 Oct 15 09:48:35 AM UTC 24 Oct 15 09:48:45 AM UTC 24 1555710000 ps
T146 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.909884426 Oct 15 09:48:35 AM UTC 24 Oct 15 09:48:46 AM UTC 24 1589610000 ps
T147 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.2992296527 Oct 15 09:48:39 AM UTC 24 Oct 15 09:48:47 AM UTC 24 1142170000 ps
T148 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.1493618391 Oct 15 09:48:37 AM UTC 24 Oct 15 09:48:47 AM UTC 24 1383110000 ps
T149 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.3695926254 Oct 15 09:48:37 AM UTC 24 Oct 15 09:48:47 AM UTC 24 1382830000 ps
T150 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.3519262525 Oct 15 09:48:39 AM UTC 24 Oct 15 09:48:47 AM UTC 24 1254170000 ps
T151 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.4035206661 Oct 15 09:48:37 AM UTC 24 Oct 15 09:48:48 AM UTC 24 1521030000 ps
T152 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.2779369492 Oct 15 09:48:37 AM UTC 24 Oct 15 09:48:48 AM UTC 24 1532710000 ps
T153 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.1812274991 Oct 15 09:48:39 AM UTC 24 Oct 15 09:48:48 AM UTC 24 1367630000 ps
T154 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.545679672 Oct 15 09:48:37 AM UTC 24 Oct 15 09:48:48 AM UTC 24 1600430000 ps
T155 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.3043499650 Oct 15 09:48:39 AM UTC 24 Oct 15 09:48:48 AM UTC 24 1407210000 ps
T156 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.1966663773 Oct 15 09:48:39 AM UTC 24 Oct 15 09:48:49 AM UTC 24 1499670000 ps
T157 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.3958842178 Oct 15 09:48:39 AM UTC 24 Oct 15 09:48:49 AM UTC 24 1485830000 ps
T158 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.857128024 Oct 15 09:48:39 AM UTC 24 Oct 15 09:48:49 AM UTC 24 1480750000 ps
T159 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.3188105255 Oct 15 09:48:39 AM UTC 24 Oct 15 09:48:49 AM UTC 24 1602770000 ps
T160 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.1454009425 Oct 15 09:48:40 AM UTC 24 Oct 15 09:48:50 AM UTC 24 1492990000 ps
T31 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.2156182190 Oct 15 09:53:14 AM UTC 24 Oct 15 10:27:38 AM UTC 24 336363110000 ps
T32 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.2977760165 Oct 15 09:53:15 AM UTC 24 Oct 15 10:27:41 AM UTC 24 337095890000 ps
T33 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.2785468238 Oct 15 09:53:14 AM UTC 24 Oct 15 10:27:45 AM UTC 24 336789570000 ps
T34 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.3534980528 Oct 15 09:53:34 AM UTC 24 Oct 15 10:28:08 AM UTC 24 336866930000 ps
T35 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.2460898650 Oct 15 09:54:23 AM UTC 24 Oct 15 10:28:38 AM UTC 24 336372330000 ps
T36 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.339151417 Oct 15 09:54:22 AM UTC 24 Oct 15 10:28:45 AM UTC 24 336932810000 ps
T37 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.609382012 Oct 15 09:54:45 AM UTC 24 Oct 15 10:28:59 AM UTC 24 336356210000 ps
T38 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.2872225494 Oct 15 10:02:29 AM UTC 24 Oct 15 10:37:37 AM UTC 24 336947150000 ps
T39 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.1529768388 Oct 15 10:08:17 AM UTC 24 Oct 15 10:43:51 AM UTC 24 336795490000 ps
T40 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.1001866752 Oct 15 10:11:49 AM UTC 24 Oct 15 10:47:49 AM UTC 24 336942670000 ps
T161 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.1907055475 Oct 15 10:20:52 AM UTC 24 Oct 15 10:57:43 AM UTC 24 336527730000 ps
T162 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.1034590518 Oct 15 10:27:12 AM UTC 24 Oct 15 11:04:45 AM UTC 24 336346090000 ps
T163 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.3942375716 Oct 15 10:27:12 AM UTC 24 Oct 15 11:04:49 AM UTC 24 336665930000 ps
T164 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.2595896361 Oct 15 10:27:19 AM UTC 24 Oct 15 11:04:49 AM UTC 24 336368190000 ps
T165 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.2328855339 Oct 15 10:27:16 AM UTC 24 Oct 15 11:04:50 AM UTC 24 336854250000 ps
T166 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.2165190948 Oct 15 10:27:18 AM UTC 24 Oct 15 11:04:52 AM UTC 24 337026870000 ps
T167 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.1951046571 Oct 15 10:27:20 AM UTC 24 Oct 15 11:04:53 AM UTC 24 336476650000 ps
T168 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.124414276 Oct 15 10:27:19 AM UTC 24 Oct 15 11:04:53 AM UTC 24 336599510000 ps
T169 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.884530539 Oct 15 10:27:22 AM UTC 24 Oct 15 11:04:54 AM UTC 24 336370270000 ps
T170 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.2774986128 Oct 15 10:27:17 AM UTC 24 Oct 15 11:04:54 AM UTC 24 336540350000 ps
T171 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.2029164509 Oct 15 10:27:24 AM UTC 24 Oct 15 11:04:57 AM UTC 24 336487810000 ps
T172 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.2059129471 Oct 15 10:27:24 AM UTC 24 Oct 15 11:04:59 AM UTC 24 336731090000 ps
T173 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.1996037091 Oct 15 10:27:22 AM UTC 24 Oct 15 11:05:00 AM UTC 24 336642450000 ps
T174 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.3940176208 Oct 15 10:27:26 AM UTC 24 Oct 15 11:05:01 AM UTC 24 336810150000 ps
T175 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.2467767389 Oct 15 10:27:25 AM UTC 24 Oct 15 11:05:01 AM UTC 24 336846950000 ps
T176 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.1077668160 Oct 15 10:27:24 AM UTC 24 Oct 15 11:05:02 AM UTC 24 336891810000 ps
T177 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.1589771503 Oct 15 10:27:27 AM UTC 24 Oct 15 11:05:03 AM UTC 24 336897730000 ps
T178 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.215579857 Oct 15 10:27:23 AM UTC 24 Oct 15 11:05:03 AM UTC 24 336488310000 ps
T179 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.2486168683 Oct 15 10:27:21 AM UTC 24 Oct 15 11:05:05 AM UTC 24 336754190000 ps
T180 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.2784261029 Oct 15 10:27:31 AM UTC 24 Oct 15 11:05:06 AM UTC 24 336488590000 ps
T181 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.4226817424 Oct 15 10:27:30 AM UTC 24 Oct 15 11:05:06 AM UTC 24 336849830000 ps
T182 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.3497510105 Oct 15 10:27:28 AM UTC 24 Oct 15 11:05:08 AM UTC 24 336574330000 ps
T183 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.3247344900 Oct 15 10:27:22 AM UTC 24 Oct 15 11:05:08 AM UTC 24 336960130000 ps
T184 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.1567579845 Oct 15 10:27:32 AM UTC 24 Oct 15 11:05:08 AM UTC 24 336514910000 ps
T185 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.779215569 Oct 15 10:27:30 AM UTC 24 Oct 15 11:05:09 AM UTC 24 337019370000 ps
T186 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.2092251426 Oct 15 10:27:32 AM UTC 24 Oct 15 11:05:10 AM UTC 24 336375650000 ps
T187 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.2626562307 Oct 15 10:27:30 AM UTC 24 Oct 15 11:05:10 AM UTC 24 337068810000 ps
T188 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.276131533 Oct 15 10:27:34 AM UTC 24 Oct 15 11:05:11 AM UTC 24 336484450000 ps
T189 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.4167900197 Oct 15 10:27:30 AM UTC 24 Oct 15 11:05:12 AM UTC 24 336856430000 ps
T190 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.2255307047 Oct 15 10:27:26 AM UTC 24 Oct 15 11:05:14 AM UTC 24 336875730000 ps
T191 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.606651036 Oct 15 10:27:30 AM UTC 24 Oct 15 11:05:14 AM UTC 24 336369250000 ps
T192 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.4073668133 Oct 15 10:27:31 AM UTC 24 Oct 15 11:05:14 AM UTC 24 336907310000 ps
T193 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.1288340985 Oct 15 10:27:32 AM UTC 24 Oct 15 11:05:15 AM UTC 24 336579990000 ps
T194 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.888040457 Oct 15 10:27:31 AM UTC 24 Oct 15 11:05:16 AM UTC 24 336682990000 ps
T195 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.1699457417 Oct 15 10:27:31 AM UTC 24 Oct 15 11:05:16 AM UTC 24 336452110000 ps
T196 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.3362144550 Oct 15 10:27:32 AM UTC 24 Oct 15 11:05:19 AM UTC 24 336488050000 ps
T197 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.2751816340 Oct 15 10:27:33 AM UTC 24 Oct 15 11:05:19 AM UTC 24 336414190000 ps
T198 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.870611839 Oct 15 10:27:36 AM UTC 24 Oct 15 11:05:19 AM UTC 24 336496550000 ps
T199 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.1037747884 Oct 15 10:27:31 AM UTC 24 Oct 15 11:05:21 AM UTC 24 337021350000 ps
T200 /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.3932460883 Oct 15 10:27:35 AM UTC 24 Oct 15 11:05:25 AM UTC 24 336781990000 ps

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/13.prim_lfsr_gal_smoke.268297415
Short name T8
Test name
Test status
Simulation time 1325390000 ps
CPU time 1.67 seconds
Started Oct 15 09:48:17 AM UTC 24
Finished Oct 15 09:48:29 AM UTC 24
Peak memory 177728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=268297415 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_g
al.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_smoke.268297415
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/13.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/0.prim_lfsr_gal_test.4226153622
Short name T16
Test name
Test status
Simulation time 336889830000 ps
CPU time 238.18 seconds
Started Oct 15 09:52:50 AM UTC 24
Finished Oct 15 10:27:16 AM UTC 24
Peak memory 174984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4226153622 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_test.4226153622
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/0.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/0.prim_lfsr_fib_test.2156182190
Short name T31
Test name
Test status
Simulation time 336363110000 ps
CPU time 243.23 seconds
Started Oct 15 09:53:14 AM UTC 24
Finished Oct 15 10:27:38 AM UTC 24
Peak memory 175052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2156182190 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_test.2156182190
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/0.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/0.prim_lfsr_fib_smoke.290442687
Short name T27
Test name
Test status
Simulation time 1437050000 ps
CPU time 1.92 seconds
Started Oct 15 09:48:32 AM UTC 24
Finished Oct 15 09:48:43 AM UTC 24
Peak memory 177796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=290442687 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_f
ib.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_fib_smoke.290442687
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/0.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/1.prim_lfsr_fib_test.2785468238
Short name T33
Test name
Test status
Simulation time 336789570000 ps
CPU time 243.05 seconds
Started Oct 15 09:53:14 AM UTC 24
Finished Oct 15 10:27:45 AM UTC 24
Peak memory 174984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2785468238 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_test.2785468238
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/1.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/10.prim_lfsr_fib_test.1907055475
Short name T161
Test name
Test status
Simulation time 336527730000 ps
CPU time 249.21 seconds
Started Oct 15 10:20:52 AM UTC 24
Finished Oct 15 10:57:43 AM UTC 24
Peak memory 174996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1907055475 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_test.1907055475
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/10.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/11.prim_lfsr_fib_test.1034590518
Short name T162
Test name
Test status
Simulation time 336346090000 ps
CPU time 254.73 seconds
Started Oct 15 10:27:12 AM UTC 24
Finished Oct 15 11:04:45 AM UTC 24
Peak memory 174996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1034590518 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_test.1034590518
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/11.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/12.prim_lfsr_fib_test.3942375716
Short name T163
Test name
Test status
Simulation time 336665930000 ps
CPU time 254.83 seconds
Started Oct 15 10:27:12 AM UTC 24
Finished Oct 15 11:04:49 AM UTC 24
Peak memory 174996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3942375716 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_test.3942375716
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/12.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/13.prim_lfsr_fib_test.2328855339
Short name T165
Test name
Test status
Simulation time 336854250000 ps
CPU time 255.89 seconds
Started Oct 15 10:27:16 AM UTC 24
Finished Oct 15 11:04:50 AM UTC 24
Peak memory 176536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2328855339 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_test.2328855339
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/13.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/14.prim_lfsr_fib_test.2774986128
Short name T170
Test name
Test status
Simulation time 336540350000 ps
CPU time 253.53 seconds
Started Oct 15 10:27:17 AM UTC 24
Finished Oct 15 11:04:54 AM UTC 24
Peak memory 176536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2774986128 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_test.2774986128
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/14.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/15.prim_lfsr_fib_test.2165190948
Short name T166
Test name
Test status
Simulation time 337026870000 ps
CPU time 255.46 seconds
Started Oct 15 10:27:18 AM UTC 24
Finished Oct 15 11:04:52 AM UTC 24
Peak memory 174992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2165190948 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_test.2165190948
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/15.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/16.prim_lfsr_fib_test.2595896361
Short name T164
Test name
Test status
Simulation time 336368190000 ps
CPU time 255.48 seconds
Started Oct 15 10:27:19 AM UTC 24
Finished Oct 15 11:04:49 AM UTC 24
Peak memory 174772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2595896361 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_test.2595896361
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/16.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/17.prim_lfsr_fib_test.124414276
Short name T168
Test name
Test status
Simulation time 336599510000 ps
CPU time 256.47 seconds
Started Oct 15 10:27:19 AM UTC 24
Finished Oct 15 11:04:53 AM UTC 24
Peak memory 174752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=124414276 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_test.124414276
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/17.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/18.prim_lfsr_fib_test.1951046571
Short name T167
Test name
Test status
Simulation time 336476650000 ps
CPU time 256.58 seconds
Started Oct 15 10:27:20 AM UTC 24
Finished Oct 15 11:04:53 AM UTC 24
Peak memory 176536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1951046571 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_test.1951046571
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/18.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/19.prim_lfsr_fib_test.2486168683
Short name T179
Test name
Test status
Simulation time 336754190000 ps
CPU time 253.17 seconds
Started Oct 15 10:27:21 AM UTC 24
Finished Oct 15 11:05:05 AM UTC 24
Peak memory 176536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2486168683 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_test.2486168683
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/19.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/2.prim_lfsr_fib_test.2977760165
Short name T32
Test name
Test status
Simulation time 337095890000 ps
CPU time 243.81 seconds
Started Oct 15 09:53:15 AM UTC 24
Finished Oct 15 10:27:41 AM UTC 24
Peak memory 174984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2977760165 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_test.2977760165
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/2.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/20.prim_lfsr_fib_test.884530539
Short name T169
Test name
Test status
Simulation time 336370270000 ps
CPU time 256.02 seconds
Started Oct 15 10:27:22 AM UTC 24
Finished Oct 15 11:04:54 AM UTC 24
Peak memory 174996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=884530539 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_test.884530539
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/20.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/21.prim_lfsr_fib_test.3247344900
Short name T183
Test name
Test status
Simulation time 336960130000 ps
CPU time 254.37 seconds
Started Oct 15 10:27:22 AM UTC 24
Finished Oct 15 11:05:08 AM UTC 24
Peak memory 176536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3247344900 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_test.3247344900
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/21.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/22.prim_lfsr_fib_test.1996037091
Short name T173
Test name
Test status
Simulation time 336642450000 ps
CPU time 255.96 seconds
Started Oct 15 10:27:22 AM UTC 24
Finished Oct 15 11:05:00 AM UTC 24
Peak memory 174996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1996037091 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_test.1996037091
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/22.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/23.prim_lfsr_fib_test.215579857
Short name T178
Test name
Test status
Simulation time 336488310000 ps
CPU time 255.03 seconds
Started Oct 15 10:27:23 AM UTC 24
Finished Oct 15 11:05:03 AM UTC 24
Peak memory 174996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=215579857 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_test.215579857
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/23.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/24.prim_lfsr_fib_test.1077668160
Short name T176
Test name
Test status
Simulation time 336891810000 ps
CPU time 255.15 seconds
Started Oct 15 10:27:24 AM UTC 24
Finished Oct 15 11:05:02 AM UTC 24
Peak memory 176360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1077668160 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_test.1077668160
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/24.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/25.prim_lfsr_fib_test.2029164509
Short name T171
Test name
Test status
Simulation time 336487810000 ps
CPU time 256.82 seconds
Started Oct 15 10:27:24 AM UTC 24
Finished Oct 15 11:04:57 AM UTC 24
Peak memory 174736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2029164509 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_test.2029164509
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/25.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/26.prim_lfsr_fib_test.2059129471
Short name T172
Test name
Test status
Simulation time 336731090000 ps
CPU time 256.4 seconds
Started Oct 15 10:27:24 AM UTC 24
Finished Oct 15 11:04:59 AM UTC 24
Peak memory 176536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2059129471 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_test.2059129471
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/26.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/27.prim_lfsr_fib_test.2467767389
Short name T175
Test name
Test status
Simulation time 336846950000 ps
CPU time 256.97 seconds
Started Oct 15 10:27:25 AM UTC 24
Finished Oct 15 11:05:01 AM UTC 24
Peak memory 176536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2467767389 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_test.2467767389
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/27.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/28.prim_lfsr_fib_test.2255307047
Short name T190
Test name
Test status
Simulation time 336875730000 ps
CPU time 254.38 seconds
Started Oct 15 10:27:26 AM UTC 24
Finished Oct 15 11:05:14 AM UTC 24
Peak memory 174996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2255307047 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_test.2255307047
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/28.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/29.prim_lfsr_fib_test.3940176208
Short name T174
Test name
Test status
Simulation time 336810150000 ps
CPU time 254.65 seconds
Started Oct 15 10:27:26 AM UTC 24
Finished Oct 15 11:05:01 AM UTC 24
Peak memory 176536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3940176208 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_test.3940176208
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/29.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/3.prim_lfsr_fib_test.3534980528
Short name T34
Test name
Test status
Simulation time 336866930000 ps
CPU time 240.69 seconds
Started Oct 15 09:53:34 AM UTC 24
Finished Oct 15 10:28:08 AM UTC 24
Peak memory 174988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3534980528 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_test.3534980528
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/3.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/30.prim_lfsr_fib_test.1589771503
Short name T177
Test name
Test status
Simulation time 336897730000 ps
CPU time 255.88 seconds
Started Oct 15 10:27:27 AM UTC 24
Finished Oct 15 11:05:03 AM UTC 24
Peak memory 174996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1589771503 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_test.1589771503
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/30.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/31.prim_lfsr_fib_test.3497510105
Short name T182
Test name
Test status
Simulation time 336574330000 ps
CPU time 257.82 seconds
Started Oct 15 10:27:28 AM UTC 24
Finished Oct 15 11:05:08 AM UTC 24
Peak memory 174996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3497510105 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_test.3497510105
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/31.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/32.prim_lfsr_fib_test.606651036
Short name T191
Test name
Test status
Simulation time 336369250000 ps
CPU time 253.61 seconds
Started Oct 15 10:27:30 AM UTC 24
Finished Oct 15 11:05:14 AM UTC 24
Peak memory 176536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=606651036 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_fib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_test.606651036
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/32.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/33.prim_lfsr_fib_test.4167900197
Short name T189
Test name
Test status
Simulation time 336856430000 ps
CPU time 253.26 seconds
Started Oct 15 10:27:30 AM UTC 24
Finished Oct 15 11:05:12 AM UTC 24
Peak memory 176456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4167900197 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_test.4167900197
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/33.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/34.prim_lfsr_fib_test.4226817424
Short name T181
Test name
Test status
Simulation time 336849830000 ps
CPU time 255.19 seconds
Started Oct 15 10:27:30 AM UTC 24
Finished Oct 15 11:05:06 AM UTC 24
Peak memory 174996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4226817424 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_test.4226817424
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/34.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/35.prim_lfsr_fib_test.779215569
Short name T185
Test name
Test status
Simulation time 337019370000 ps
CPU time 257.55 seconds
Started Oct 15 10:27:30 AM UTC 24
Finished Oct 15 11:05:09 AM UTC 24
Peak memory 176536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=779215569 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_test.779215569
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/35.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/36.prim_lfsr_fib_test.2626562307
Short name T187
Test name
Test status
Simulation time 337068810000 ps
CPU time 257.39 seconds
Started Oct 15 10:27:30 AM UTC 24
Finished Oct 15 11:05:10 AM UTC 24
Peak memory 176536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2626562307 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_test.2626562307
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/36.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/37.prim_lfsr_fib_test.2784261029
Short name T180
Test name
Test status
Simulation time 336488590000 ps
CPU time 257.31 seconds
Started Oct 15 10:27:31 AM UTC 24
Finished Oct 15 11:05:06 AM UTC 24
Peak memory 176536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2784261029 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_test.2784261029
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/37.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/38.prim_lfsr_fib_test.1699457417
Short name T195
Test name
Test status
Simulation time 336452110000 ps
CPU time 254.98 seconds
Started Oct 15 10:27:31 AM UTC 24
Finished Oct 15 11:05:16 AM UTC 24
Peak memory 176532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1699457417 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_test.1699457417
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/38.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/39.prim_lfsr_fib_test.4073668133
Short name T192
Test name
Test status
Simulation time 336907310000 ps
CPU time 253.2 seconds
Started Oct 15 10:27:31 AM UTC 24
Finished Oct 15 11:05:14 AM UTC 24
Peak memory 176536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4073668133 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_test.4073668133
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/39.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/4.prim_lfsr_fib_test.339151417
Short name T36
Test name
Test status
Simulation time 336932810000 ps
CPU time 241.07 seconds
Started Oct 15 09:54:22 AM UTC 24
Finished Oct 15 10:28:45 AM UTC 24
Peak memory 174992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=339151417 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_fib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_test.339151417
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/4.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/40.prim_lfsr_fib_test.888040457
Short name T194
Test name
Test status
Simulation time 336682990000 ps
CPU time 254.51 seconds
Started Oct 15 10:27:31 AM UTC 24
Finished Oct 15 11:05:16 AM UTC 24
Peak memory 174996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=888040457 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_test.888040457
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/40.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/41.prim_lfsr_fib_test.1037747884
Short name T199
Test name
Test status
Simulation time 337021350000 ps
CPU time 254.71 seconds
Started Oct 15 10:27:31 AM UTC 24
Finished Oct 15 11:05:21 AM UTC 24
Peak memory 176532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1037747884 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_test.1037747884
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/41.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/42.prim_lfsr_fib_test.1288340985
Short name T193
Test name
Test status
Simulation time 336579990000 ps
CPU time 256.04 seconds
Started Oct 15 10:27:32 AM UTC 24
Finished Oct 15 11:05:15 AM UTC 24
Peak memory 176536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1288340985 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_test.1288340985
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/42.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/43.prim_lfsr_fib_test.3362144550
Short name T196
Test name
Test status
Simulation time 336488050000 ps
CPU time 254.31 seconds
Started Oct 15 10:27:32 AM UTC 24
Finished Oct 15 11:05:19 AM UTC 24
Peak memory 176536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3362144550 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_test.3362144550
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/43.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/44.prim_lfsr_fib_test.1567579845
Short name T184
Test name
Test status
Simulation time 336514910000 ps
CPU time 257.08 seconds
Started Oct 15 10:27:32 AM UTC 24
Finished Oct 15 11:05:08 AM UTC 24
Peak memory 174996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1567579845 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_test.1567579845
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/44.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/45.prim_lfsr_fib_test.2092251426
Short name T186
Test name
Test status
Simulation time 336375650000 ps
CPU time 257.6 seconds
Started Oct 15 10:27:32 AM UTC 24
Finished Oct 15 11:05:10 AM UTC 24
Peak memory 174996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2092251426 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_test.2092251426
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/45.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/46.prim_lfsr_fib_test.2751816340
Short name T197
Test name
Test status
Simulation time 336414190000 ps
CPU time 253.73 seconds
Started Oct 15 10:27:33 AM UTC 24
Finished Oct 15 11:05:19 AM UTC 24
Peak memory 176532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2751816340 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_test.2751816340
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/46.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/47.prim_lfsr_fib_test.276131533
Short name T188
Test name
Test status
Simulation time 336484450000 ps
CPU time 256.98 seconds
Started Oct 15 10:27:34 AM UTC 24
Finished Oct 15 11:05:11 AM UTC 24
Peak memory 174988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=276131533 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_test.276131533
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/47.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/48.prim_lfsr_fib_test.3932460883
Short name T200
Test name
Test status
Simulation time 336781990000 ps
CPU time 255.11 seconds
Started Oct 15 10:27:35 AM UTC 24
Finished Oct 15 11:05:25 AM UTC 24
Peak memory 176536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3932460883 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_test.3932460883
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/48.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/49.prim_lfsr_fib_test.870611839
Short name T198
Test name
Test status
Simulation time 336496550000 ps
CPU time 256.77 seconds
Started Oct 15 10:27:36 AM UTC 24
Finished Oct 15 11:05:19 AM UTC 24
Peak memory 176564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=870611839 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_test.870611839
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/49.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/5.prim_lfsr_fib_test.2460898650
Short name T35
Test name
Test status
Simulation time 336372330000 ps
CPU time 240.24 seconds
Started Oct 15 09:54:23 AM UTC 24
Finished Oct 15 10:28:38 AM UTC 24
Peak memory 176536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2460898650 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_test.2460898650
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/5.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/6.prim_lfsr_fib_test.609382012
Short name T37
Test name
Test status
Simulation time 336356210000 ps
CPU time 241.63 seconds
Started Oct 15 09:54:45 AM UTC 24
Finished Oct 15 10:28:59 AM UTC 24
Peak memory 174988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=609382012 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_test.609382012
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/6.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/7.prim_lfsr_fib_test.2872225494
Short name T38
Test name
Test status
Simulation time 336947150000 ps
CPU time 242.97 seconds
Started Oct 15 10:02:29 AM UTC 24
Finished Oct 15 10:37:37 AM UTC 24
Peak memory 174988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2872225494 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_test.2872225494
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/7.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/8.prim_lfsr_fib_test.1529768388
Short name T39
Test name
Test status
Simulation time 336795490000 ps
CPU time 243.89 seconds
Started Oct 15 10:08:17 AM UTC 24
Finished Oct 15 10:43:51 AM UTC 24
Peak memory 174988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1529768388 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_test.1529768388
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/8.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_fib/9.prim_lfsr_fib_test.1001866752
Short name T40
Test name
Test status
Simulation time 336942670000 ps
CPU time 244.5 seconds
Started Oct 15 10:11:49 AM UTC 24
Finished Oct 15 10:47:49 AM UTC 24
Peak memory 176528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_24_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1001866752 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_test.1001866752
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/9.prim_lfsr_fib_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/1.prim_lfsr_gal_test.2421669502
Short name T19
Test name
Test status
Simulation time 336348230000 ps
CPU time 237.85 seconds
Started Oct 15 09:52:50 AM UTC 24
Finished Oct 15 10:27:18 AM UTC 24
Peak memory 174984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2421669502 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_test.2421669502
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/1.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/10.prim_lfsr_gal_test.1803381168
Short name T83
Test name
Test status
Simulation time 336393990000 ps
CPU time 238.4 seconds
Started Oct 15 09:52:54 AM UTC 24
Finished Oct 15 10:27:23 AM UTC 24
Peak memory 174992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1803381168 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_test.1803381168
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/10.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/11.prim_lfsr_gal_test.2870120109
Short name T20
Test name
Test status
Simulation time 336633650000 ps
CPU time 237.97 seconds
Started Oct 15 09:52:56 AM UTC 24
Finished Oct 15 10:27:19 AM UTC 24
Peak memory 174992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2870120109 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_test.2870120109
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/11.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/12.prim_lfsr_gal_test.3715992753
Short name T86
Test name
Test status
Simulation time 336727190000 ps
CPU time 238.49 seconds
Started Oct 15 09:52:58 AM UTC 24
Finished Oct 15 10:27:24 AM UTC 24
Peak memory 174992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3715992753 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_test.3715992753
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/12.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/13.prim_lfsr_gal_test.1904273778
Short name T81
Test name
Test status
Simulation time 336621710000 ps
CPU time 238.96 seconds
Started Oct 15 09:52:58 AM UTC 24
Finished Oct 15 10:27:21 AM UTC 24
Peak memory 174988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1904273778 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_gal_test.1904273778
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/13.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/14.prim_lfsr_gal_test.2074401117
Short name T98
Test name
Test status
Simulation time 336424270000 ps
CPU time 239.01 seconds
Started Oct 15 09:52:58 AM UTC 24
Finished Oct 15 10:27:30 AM UTC 24
Peak memory 174992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2074401117 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_test.2074401117
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/14.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/15.prim_lfsr_gal_test.3235907450
Short name T88
Test name
Test status
Simulation time 336851750000 ps
CPU time 241.63 seconds
Started Oct 15 09:52:59 AM UTC 24
Finished Oct 15 10:27:26 AM UTC 24
Peak memory 174740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3235907450 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_test.3235907450
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/15.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/16.prim_lfsr_gal_test.694321738
Short name T82
Test name
Test status
Simulation time 336450390000 ps
CPU time 240.54 seconds
Started Oct 15 09:52:59 AM UTC 24
Finished Oct 15 10:27:22 AM UTC 24
Peak memory 174992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=694321738 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_test.694321738
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/16.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/17.prim_lfsr_gal_test.4000682557
Short name T87
Test name
Test status
Simulation time 336462530000 ps
CPU time 240.66 seconds
Started Oct 15 09:53:00 AM UTC 24
Finished Oct 15 10:27:25 AM UTC 24
Peak memory 174992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4000682557 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_test.4000682557
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/17.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/18.prim_lfsr_gal_test.2540920670
Short name T111
Test name
Test status
Simulation time 337041890000 ps
CPU time 238.83 seconds
Started Oct 15 09:53:00 AM UTC 24
Finished Oct 15 10:27:37 AM UTC 24
Peak memory 174996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2540920670 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_test.2540920670
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/18.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/19.prim_lfsr_gal_test.215015667
Short name T92
Test name
Test status
Simulation time 336880330000 ps
CPU time 241.56 seconds
Started Oct 15 09:53:02 AM UTC 24
Finished Oct 15 10:27:28 AM UTC 24
Peak memory 174992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=215015667 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_test.215015667
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/19.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/2.prim_lfsr_gal_test.799223318
Short name T17
Test name
Test status
Simulation time 336940510000 ps
CPU time 237.94 seconds
Started Oct 15 09:52:51 AM UTC 24
Finished Oct 15 10:27:17 AM UTC 24
Peak memory 174988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=799223318 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_gal.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_test.799223318
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/2.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/20.prim_lfsr_gal_test.1820175651
Short name T91
Test name
Test status
Simulation time 336883430000 ps
CPU time 240.83 seconds
Started Oct 15 09:53:02 AM UTC 24
Finished Oct 15 10:27:28 AM UTC 24
Peak memory 174992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1820175651 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_test.1820175651
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/20.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/21.prim_lfsr_gal_test.1173005968
Short name T94
Test name
Test status
Simulation time 336578330000 ps
CPU time 239.11 seconds
Started Oct 15 09:53:02 AM UTC 24
Finished Oct 15 10:27:29 AM UTC 24
Peak memory 174992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1173005968 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_test.1173005968
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/21.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/22.prim_lfsr_gal_test.2758501594
Short name T97
Test name
Test status
Simulation time 337099530000 ps
CPU time 240.85 seconds
Started Oct 15 09:53:02 AM UTC 24
Finished Oct 15 10:27:30 AM UTC 24
Peak memory 174936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2758501594 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_test.2758501594
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/22.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/23.prim_lfsr_gal_test.4008775256
Short name T103
Test name
Test status
Simulation time 337062490000 ps
CPU time 239.78 seconds
Started Oct 15 09:53:02 AM UTC 24
Finished Oct 15 10:27:31 AM UTC 24
Peak memory 174960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4008775256 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_test.4008775256
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/23.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/24.prim_lfsr_gal_test.3193461296
Short name T90
Test name
Test status
Simulation time 336715430000 ps
CPU time 238.77 seconds
Started Oct 15 09:53:02 AM UTC 24
Finished Oct 15 10:27:28 AM UTC 24
Peak memory 174988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3193461296 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_test.3193461296
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/24.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/25.prim_lfsr_gal_test.3435999803
Short name T102
Test name
Test status
Simulation time 336479450000 ps
CPU time 238.53 seconds
Started Oct 15 09:53:02 AM UTC 24
Finished Oct 15 10:27:31 AM UTC 24
Peak memory 174992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3435999803 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_test.3435999803
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/25.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/26.prim_lfsr_gal_test.426282012
Short name T96
Test name
Test status
Simulation time 336859130000 ps
CPU time 239.55 seconds
Started Oct 15 09:53:02 AM UTC 24
Finished Oct 15 10:27:30 AM UTC 24
Peak memory 174992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=426282012 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_test.426282012
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/26.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/27.prim_lfsr_gal_test.4260381010
Short name T112
Test name
Test status
Simulation time 336510770000 ps
CPU time 238.86 seconds
Started Oct 15 09:53:02 AM UTC 24
Finished Oct 15 10:27:39 AM UTC 24
Peak memory 174992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4260381010 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_test.4260381010
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/27.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/28.prim_lfsr_gal_test.3736017095
Short name T100
Test name
Test status
Simulation time 336733870000 ps
CPU time 238.11 seconds
Started Oct 15 09:53:02 AM UTC 24
Finished Oct 15 10:27:30 AM UTC 24
Peak memory 174992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3736017095 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_test.3736017095
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/28.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/29.prim_lfsr_gal_test.2353539686
Short name T89
Test name
Test status
Simulation time 336533550000 ps
CPU time 240.84 seconds
Started Oct 15 09:53:02 AM UTC 24
Finished Oct 15 10:27:26 AM UTC 24
Peak memory 174992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2353539686 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_test.2353539686
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/29.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/3.prim_lfsr_gal_test.3401877886
Short name T23
Test name
Test status
Simulation time 336981190000 ps
CPU time 239.78 seconds
Started Oct 15 09:52:51 AM UTC 24
Finished Oct 15 10:27:21 AM UTC 24
Peak memory 174988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3401877886 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_test.3401877886
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/3.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/30.prim_lfsr_gal_test.279216646
Short name T95
Test name
Test status
Simulation time 336759450000 ps
CPU time 239.98 seconds
Started Oct 15 09:53:02 AM UTC 24
Finished Oct 15 10:27:29 AM UTC 24
Peak memory 174992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=279216646 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_test.279216646
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/30.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/31.prim_lfsr_gal_test.591365725
Short name T108
Test name
Test status
Simulation time 337015690000 ps
CPU time 239.41 seconds
Started Oct 15 09:53:04 AM UTC 24
Finished Oct 15 10:27:36 AM UTC 24
Peak memory 174984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=591365725 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_test.591365725
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/31.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/32.prim_lfsr_gal_test.2747477321
Short name T113
Test name
Test status
Simulation time 336736310000 ps
CPU time 239.91 seconds
Started Oct 15 09:53:04 AM UTC 24
Finished Oct 15 10:27:39 AM UTC 24
Peak memory 174992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2747477321 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_test.2747477321
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/32.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/33.prim_lfsr_gal_test.2748073802
Short name T101
Test name
Test status
Simulation time 336442930000 ps
CPU time 240.87 seconds
Started Oct 15 09:53:04 AM UTC 24
Finished Oct 15 10:27:31 AM UTC 24
Peak memory 174992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2748073802 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_test.2748073802
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/33.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/34.prim_lfsr_gal_test.2881246029
Short name T85
Test name
Test status
Simulation time 336664710000 ps
CPU time 240.26 seconds
Started Oct 15 09:53:04 AM UTC 24
Finished Oct 15 10:27:24 AM UTC 24
Peak memory 174992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2881246029 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_test.2881246029
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/34.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/35.prim_lfsr_gal_test.825692050
Short name T93
Test name
Test status
Simulation time 336500570000 ps
CPU time 239.73 seconds
Started Oct 15 09:53:05 AM UTC 24
Finished Oct 15 10:27:28 AM UTC 24
Peak memory 174984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=825692050 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_test.825692050
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/35.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/36.prim_lfsr_gal_test.2548202508
Short name T110
Test name
Test status
Simulation time 336610410000 ps
CPU time 238.91 seconds
Started Oct 15 09:53:05 AM UTC 24
Finished Oct 15 10:27:37 AM UTC 24
Peak memory 175044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2548202508 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_test.2548202508
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/36.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/37.prim_lfsr_gal_test.1501853236
Short name T105
Test name
Test status
Simulation time 336709010000 ps
CPU time 240.93 seconds
Started Oct 15 09:53:05 AM UTC 24
Finished Oct 15 10:27:32 AM UTC 24
Peak memory 174992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1501853236 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_test.1501853236
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/37.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/38.prim_lfsr_gal_test.2479635297
Short name T117
Test name
Test status
Simulation time 336623790000 ps
CPU time 241.4 seconds
Started Oct 15 09:53:07 AM UTC 24
Finished Oct 15 10:27:41 AM UTC 24
Peak memory 174992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2479635297 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_test.2479635297
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/38.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/39.prim_lfsr_gal_test.4177263239
Short name T107
Test name
Test status
Simulation time 336891510000 ps
CPU time 240.89 seconds
Started Oct 15 09:53:07 AM UTC 24
Finished Oct 15 10:27:34 AM UTC 24
Peak memory 174992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4177263239 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_test.4177263239
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/39.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/4.prim_lfsr_gal_test.764037647
Short name T22
Test name
Test status
Simulation time 337040070000 ps
CPU time 240.62 seconds
Started Oct 15 09:52:52 AM UTC 24
Finished Oct 15 10:27:21 AM UTC 24
Peak memory 174988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=764037647 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_gal.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_test.764037647
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/4.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/40.prim_lfsr_gal_test.1074098437
Short name T99
Test name
Test status
Simulation time 336827670000 ps
CPU time 240.68 seconds
Started Oct 15 09:53:07 AM UTC 24
Finished Oct 15 10:27:30 AM UTC 24
Peak memory 174992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1074098437 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_test.1074098437
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/40.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/41.prim_lfsr_gal_test.2716683982
Short name T116
Test name
Test status
Simulation time 336868090000 ps
CPU time 240.74 seconds
Started Oct 15 09:53:07 AM UTC 24
Finished Oct 15 10:27:40 AM UTC 24
Peak memory 175044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2716683982 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_test.2716683982
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/41.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/42.prim_lfsr_gal_test.368717099
Short name T114
Test name
Test status
Simulation time 336643810000 ps
CPU time 237.51 seconds
Started Oct 15 09:53:09 AM UTC 24
Finished Oct 15 10:27:40 AM UTC 24
Peak memory 175044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=368717099 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_test.368717099
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/42.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/43.prim_lfsr_gal_test.1742303862
Short name T118
Test name
Test status
Simulation time 336908050000 ps
CPU time 240.02 seconds
Started Oct 15 09:53:09 AM UTC 24
Finished Oct 15 10:27:43 AM UTC 24
Peak memory 174996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1742303862 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_test.1742303862
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/43.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/44.prim_lfsr_gal_test.3148589877
Short name T119
Test name
Test status
Simulation time 336906970000 ps
CPU time 241.66 seconds
Started Oct 15 09:53:09 AM UTC 24
Finished Oct 15 10:27:43 AM UTC 24
Peak memory 174996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3148589877 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_test.3148589877
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/44.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/45.prim_lfsr_gal_test.2223759740
Short name T104
Test name
Test status
Simulation time 336427290000 ps
CPU time 241.24 seconds
Started Oct 15 09:53:09 AM UTC 24
Finished Oct 15 10:27:31 AM UTC 24
Peak memory 174992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2223759740 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_test.2223759740
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/45.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/46.prim_lfsr_gal_test.88555695
Short name T115
Test name
Test status
Simulation time 336950150000 ps
CPU time 239.39 seconds
Started Oct 15 09:53:09 AM UTC 24
Finished Oct 15 10:27:40 AM UTC 24
Peak memory 174980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=88555695 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_
gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_test.88555695
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/46.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/47.prim_lfsr_gal_test.2040610106
Short name T106
Test name
Test status
Simulation time 336983350000 ps
CPU time 241.62 seconds
Started Oct 15 09:53:10 AM UTC 24
Finished Oct 15 10:27:34 AM UTC 24
Peak memory 174992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2040610106 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_test.2040610106
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/47.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/48.prim_lfsr_gal_test.1158307234
Short name T109
Test name
Test status
Simulation time 336858870000 ps
CPU time 239.17 seconds
Started Oct 15 09:53:10 AM UTC 24
Finished Oct 15 10:27:36 AM UTC 24
Peak memory 174992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1158307234 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_test.1158307234
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/48.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/49.prim_lfsr_gal_test.29009156
Short name T120
Test name
Test status
Simulation time 336779830000 ps
CPU time 240.49 seconds
Started Oct 15 09:53:14 AM UTC 24
Finished Oct 15 10:27:44 AM UTC 24
Peak memory 174976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=29009156 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_
gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_test.29009156
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/49.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/5.prim_lfsr_gal_test.206481761
Short name T84
Test name
Test status
Simulation time 336456230000 ps
CPU time 236.73 seconds
Started Oct 15 09:52:53 AM UTC 24
Finished Oct 15 10:27:24 AM UTC 24
Peak memory 174988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=206481761 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24
_gal.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_test.206481761
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/5.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/6.prim_lfsr_gal_test.1889275855
Short name T15
Test name
Test status
Simulation time 336572270000 ps
CPU time 239.58 seconds
Started Oct 15 09:52:53 AM UTC 24
Finished Oct 15 10:27:15 AM UTC 24
Peak memory 174984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1889275855 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_test.1889275855
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/6.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/7.prim_lfsr_gal_test.3520769943
Short name T14
Test name
Test status
Simulation time 336702030000 ps
CPU time 239.18 seconds
Started Oct 15 09:52:53 AM UTC 24
Finished Oct 15 10:27:11 AM UTC 24
Peak memory 175052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3520769943 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_test.3520769943
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/7.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/8.prim_lfsr_gal_test.1097022322
Short name T18
Test name
Test status
Simulation time 336380170000 ps
CPU time 237.22 seconds
Started Oct 15 09:52:53 AM UTC 24
Finished Oct 15 10:27:17 AM UTC 24
Peak memory 174984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1097022322 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_test.1097022322
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/8.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_24_gal/9.prim_lfsr_gal_test.1650463293
Short name T21
Test name
Test status
Simulation time 336971870000 ps
CPU time 237.73 seconds
Started Oct 15 09:52:53 AM UTC 24
Finished Oct 15 10:27:20 AM UTC 24
Peak memory 174984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_24_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1650463293 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_2
4_gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_test.1650463293
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/9.prim_lfsr_gal_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/1.prim_lfsr_fib_smoke.2062439586
Short name T30
Test name
Test status
Simulation time 1479810000 ps
CPU time 1.99 seconds
Started Oct 15 09:48:32 AM UTC 24
Finished Oct 15 09:48:43 AM UTC 24
Peak memory 177764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2062439586 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_fib_smoke.2062439586
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/1.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/10.prim_lfsr_fib_smoke.655838017
Short name T5
Test name
Test status
Simulation time 1290250000 ps
CPU time 1.74 seconds
Started Oct 15 09:48:33 AM UTC 24
Finished Oct 15 09:48:42 AM UTC 24
Peak memory 177760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=655838017 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_f
ib.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_fib_smoke.655838017
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/10.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/11.prim_lfsr_fib_smoke.93618885
Short name T131
Test name
Test status
Simulation time 1519850000 ps
CPU time 1.79 seconds
Started Oct 15 09:48:33 AM UTC 24
Finished Oct 15 09:48:44 AM UTC 24
Peak memory 177764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=93618885 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fi
b.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_fib_smoke.93618885
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/11.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/12.prim_lfsr_fib_smoke.3446213637
Short name T124
Test name
Test status
Simulation time 1460190000 ps
CPU time 1.9 seconds
Started Oct 15 09:48:33 AM UTC 24
Finished Oct 15 09:48:43 AM UTC 24
Peak memory 177796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3446213637 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_fib_smoke.3446213637
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/12.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/13.prim_lfsr_fib_smoke.4053206861
Short name T24
Test name
Test status
Simulation time 1337290000 ps
CPU time 1.76 seconds
Started Oct 15 09:48:33 AM UTC 24
Finished Oct 15 09:48:43 AM UTC 24
Peak memory 177768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4053206861 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 13.prim_lfsr_fib_smoke.4053206861
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/13.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/14.prim_lfsr_fib_smoke.2473906403
Short name T128
Test name
Test status
Simulation time 1513090000 ps
CPU time 1.85 seconds
Started Oct 15 09:48:33 AM UTC 24
Finished Oct 15 09:48:44 AM UTC 24
Peak memory 177796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2473906403 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_fib_smoke.2473906403
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/14.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/15.prim_lfsr_fib_smoke.1802642528
Short name T141
Test name
Test status
Simulation time 1607530000 ps
CPU time 1.99 seconds
Started Oct 15 09:48:33 AM UTC 24
Finished Oct 15 09:48:44 AM UTC 24
Peak memory 177796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1802642528 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_fib_smoke.1802642528
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/15.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/16.prim_lfsr_fib_smoke.4219565927
Short name T25
Test name
Test status
Simulation time 1364530000 ps
CPU time 1.84 seconds
Started Oct 15 09:48:33 AM UTC 24
Finished Oct 15 09:48:43 AM UTC 24
Peak memory 177796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4219565927 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_fib_smoke.4219565927
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/16.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/17.prim_lfsr_fib_smoke.3476773411
Short name T122
Test name
Test status
Simulation time 1425570000 ps
CPU time 1.82 seconds
Started Oct 15 09:48:33 AM UTC 24
Finished Oct 15 09:48:43 AM UTC 24
Peak memory 177796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3476773411 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_fib_smoke.3476773411
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/17.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/18.prim_lfsr_fib_smoke.447653111
Short name T139
Test name
Test status
Simulation time 1566530000 ps
CPU time 1.9 seconds
Started Oct 15 09:48:33 AM UTC 24
Finished Oct 15 09:48:44 AM UTC 24
Peak memory 177760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=447653111 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_f
ib.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_fib_smoke.447653111
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/18.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/19.prim_lfsr_fib_smoke.4213465908
Short name T132
Test name
Test status
Simulation time 1498790000 ps
CPU time 1.9 seconds
Started Oct 15 09:48:33 AM UTC 24
Finished Oct 15 09:48:44 AM UTC 24
Peak memory 177796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4213465908 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_fib_smoke.4213465908
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/19.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/2.prim_lfsr_fib_smoke.4024633283
Short name T126
Test name
Test status
Simulation time 1537970000 ps
CPU time 1.83 seconds
Started Oct 15 09:48:32 AM UTC 24
Finished Oct 15 09:48:43 AM UTC 24
Peak memory 177764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4024633283 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_fib_smoke.4024633283
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/2.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/20.prim_lfsr_fib_smoke.3629624425
Short name T125
Test name
Test status
Simulation time 1440150000 ps
CPU time 1.89 seconds
Started Oct 15 09:48:33 AM UTC 24
Finished Oct 15 09:48:43 AM UTC 24
Peak memory 177796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3629624425 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_fib_smoke.3629624425
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/20.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/21.prim_lfsr_fib_smoke.2255581286
Short name T127
Test name
Test status
Simulation time 1448030000 ps
CPU time 1.77 seconds
Started Oct 15 09:48:33 AM UTC 24
Finished Oct 15 09:48:44 AM UTC 24
Peak memory 177796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2255581286 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_fib_smoke.2255581286
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/21.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/22.prim_lfsr_fib_smoke.2323029305
Short name T26
Test name
Test status
Simulation time 1352330000 ps
CPU time 1.79 seconds
Started Oct 15 09:48:33 AM UTC 24
Finished Oct 15 09:48:43 AM UTC 24
Peak memory 177796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2323029305 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_fib_smoke.2323029305
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/22.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/23.prim_lfsr_fib_smoke.1261241058
Short name T121
Test name
Test status
Simulation time 1389270000 ps
CPU time 1.9 seconds
Started Oct 15 09:48:33 AM UTC 24
Finished Oct 15 09:48:43 AM UTC 24
Peak memory 177656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1261241058 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_fib_smoke.1261241058
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/23.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/24.prim_lfsr_fib_smoke.1460473439
Short name T134
Test name
Test status
Simulation time 1469190000 ps
CPU time 1.83 seconds
Started Oct 15 09:48:33 AM UTC 24
Finished Oct 15 09:48:44 AM UTC 24
Peak memory 177796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1460473439 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_fib_smoke.1460473439
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/24.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/25.prim_lfsr_fib_smoke.2780259199
Short name T140
Test name
Test status
Simulation time 1493330000 ps
CPU time 1.91 seconds
Started Oct 15 09:48:33 AM UTC 24
Finished Oct 15 09:48:44 AM UTC 24
Peak memory 177796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2780259199 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_fib_smoke.2780259199
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/25.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/26.prim_lfsr_fib_smoke.3407837472
Short name T136
Test name
Test status
Simulation time 1471530000 ps
CPU time 1.81 seconds
Started Oct 15 09:48:33 AM UTC 24
Finished Oct 15 09:48:44 AM UTC 24
Peak memory 177796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3407837472 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_fib_smoke.3407837472
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/26.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/27.prim_lfsr_fib_smoke.683937629
Short name T4
Test name
Test status
Simulation time 1106210000 ps
CPU time 1.58 seconds
Started Oct 15 09:48:33 AM UTC 24
Finished Oct 15 09:48:42 AM UTC 24
Peak memory 177828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=683937629 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_f
ib.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_fib_smoke.683937629
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/27.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/28.prim_lfsr_fib_smoke.3278746822
Short name T28
Test name
Test status
Simulation time 1298810000 ps
CPU time 1.66 seconds
Started Oct 15 09:48:33 AM UTC 24
Finished Oct 15 09:48:43 AM UTC 24
Peak memory 177632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3278746822 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_fib_smoke.3278746822
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/28.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/29.prim_lfsr_fib_smoke.1409293546
Short name T138
Test name
Test status
Simulation time 1444210000 ps
CPU time 1.93 seconds
Started Oct 15 09:48:33 AM UTC 24
Finished Oct 15 09:48:44 AM UTC 24
Peak memory 177796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1409293546 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_fib_smoke.1409293546
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/29.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/3.prim_lfsr_fib_smoke.149185671
Short name T133
Test name
Test status
Simulation time 1591870000 ps
CPU time 1.84 seconds
Started Oct 15 09:48:32 AM UTC 24
Finished Oct 15 09:48:44 AM UTC 24
Peak memory 177796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=149185671 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_f
ib.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_fib_smoke.149185671
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/3.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/30.prim_lfsr_fib_smoke.1309049713
Short name T143
Test name
Test status
Simulation time 1498510000 ps
CPU time 1.86 seconds
Started Oct 15 09:48:34 AM UTC 24
Finished Oct 15 09:48:45 AM UTC 24
Peak memory 177792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1309049713 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_fib_smoke.1309049713
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/30.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/31.prim_lfsr_fib_smoke.3631250390
Short name T130
Test name
Test status
Simulation time 1278050000 ps
CPU time 1.59 seconds
Started Oct 15 09:48:34 AM UTC 24
Finished Oct 15 09:48:44 AM UTC 24
Peak memory 177796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3631250390 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_fib_smoke.3631250390
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/31.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/32.prim_lfsr_fib_smoke.381309445
Short name T142
Test name
Test status
Simulation time 1370990000 ps
CPU time 1.8 seconds
Started Oct 15 09:48:35 AM UTC 24
Finished Oct 15 09:48:44 AM UTC 24
Peak memory 177760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=381309445 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_f
ib.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_fib_smoke.381309445
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/32.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/33.prim_lfsr_fib_smoke.3941222067
Short name T145
Test name
Test status
Simulation time 1555710000 ps
CPU time 1.97 seconds
Started Oct 15 09:48:35 AM UTC 24
Finished Oct 15 09:48:45 AM UTC 24
Peak memory 177796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3941222067 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_fib_smoke.3941222067
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/33.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/34.prim_lfsr_fib_smoke.909884426
Short name T146
Test name
Test status
Simulation time 1589610000 ps
CPU time 1.84 seconds
Started Oct 15 09:48:35 AM UTC 24
Finished Oct 15 09:48:46 AM UTC 24
Peak memory 177760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=909884426 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_f
ib.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_fib_smoke.909884426
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/34.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/35.prim_lfsr_fib_smoke.3652028264
Short name T144
Test name
Test status
Simulation time 1345710000 ps
CPU time 1.73 seconds
Started Oct 15 09:48:36 AM UTC 24
Finished Oct 15 09:48:45 AM UTC 24
Peak memory 177792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3652028264 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_fib_smoke.3652028264
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/35.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/36.prim_lfsr_fib_smoke.3695926254
Short name T149
Test name
Test status
Simulation time 1382830000 ps
CPU time 1.83 seconds
Started Oct 15 09:48:37 AM UTC 24
Finished Oct 15 09:48:47 AM UTC 24
Peak memory 177796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3695926254 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_fib_smoke.3695926254
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/36.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/37.prim_lfsr_fib_smoke.545679672
Short name T154
Test name
Test status
Simulation time 1600430000 ps
CPU time 1.95 seconds
Started Oct 15 09:48:37 AM UTC 24
Finished Oct 15 09:48:48 AM UTC 24
Peak memory 177760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=545679672 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_f
ib.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_fib_smoke.545679672
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/37.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/38.prim_lfsr_fib_smoke.2779369492
Short name T152
Test name
Test status
Simulation time 1532710000 ps
CPU time 2.04 seconds
Started Oct 15 09:48:37 AM UTC 24
Finished Oct 15 09:48:48 AM UTC 24
Peak memory 177792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2779369492 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_fib_smoke.2779369492
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/38.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/39.prim_lfsr_fib_smoke.1493618391
Short name T148
Test name
Test status
Simulation time 1383110000 ps
CPU time 1.79 seconds
Started Oct 15 09:48:37 AM UTC 24
Finished Oct 15 09:48:47 AM UTC 24
Peak memory 177796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1493618391 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_fib_smoke.1493618391
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/39.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/4.prim_lfsr_fib_smoke.203105368
Short name T123
Test name
Test status
Simulation time 1478770000 ps
CPU time 1.91 seconds
Started Oct 15 09:48:32 AM UTC 24
Finished Oct 15 09:48:43 AM UTC 24
Peak memory 177760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=203105368 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_f
ib.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_fib_smoke.203105368
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/4.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/40.prim_lfsr_fib_smoke.4035206661
Short name T151
Test name
Test status
Simulation time 1521030000 ps
CPU time 1.91 seconds
Started Oct 15 09:48:37 AM UTC 24
Finished Oct 15 09:48:48 AM UTC 24
Peak memory 177792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4035206661 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_fib_smoke.4035206661
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/40.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/41.prim_lfsr_fib_smoke.1812274991
Short name T153
Test name
Test status
Simulation time 1367630000 ps
CPU time 1.79 seconds
Started Oct 15 09:48:39 AM UTC 24
Finished Oct 15 09:48:48 AM UTC 24
Peak memory 177508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1812274991 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_fib_smoke.1812274991
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/41.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/42.prim_lfsr_fib_smoke.3519262525
Short name T150
Test name
Test status
Simulation time 1254170000 ps
CPU time 1.69 seconds
Started Oct 15 09:48:39 AM UTC 24
Finished Oct 15 09:48:47 AM UTC 24
Peak memory 177492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3519262525 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_fib_smoke.3519262525
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/42.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/43.prim_lfsr_fib_smoke.1966663773
Short name T156
Test name
Test status
Simulation time 1499670000 ps
CPU time 1.94 seconds
Started Oct 15 09:48:39 AM UTC 24
Finished Oct 15 09:48:49 AM UTC 24
Peak memory 177796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1966663773 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_fib_smoke.1966663773
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/43.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/44.prim_lfsr_fib_smoke.3043499650
Short name T155
Test name
Test status
Simulation time 1407210000 ps
CPU time 1.77 seconds
Started Oct 15 09:48:39 AM UTC 24
Finished Oct 15 09:48:48 AM UTC 24
Peak memory 177788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3043499650 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_fib_smoke.3043499650
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/44.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/45.prim_lfsr_fib_smoke.3958842178
Short name T157
Test name
Test status
Simulation time 1485830000 ps
CPU time 1.75 seconds
Started Oct 15 09:48:39 AM UTC 24
Finished Oct 15 09:48:49 AM UTC 24
Peak memory 177796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3958842178 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_fib_smoke.3958842178
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/45.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/46.prim_lfsr_fib_smoke.2992296527
Short name T147
Test name
Test status
Simulation time 1142170000 ps
CPU time 1.65 seconds
Started Oct 15 09:48:39 AM UTC 24
Finished Oct 15 09:48:47 AM UTC 24
Peak memory 177796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2992296527 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_fib_smoke.2992296527
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/46.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/47.prim_lfsr_fib_smoke.3188105255
Short name T159
Test name
Test status
Simulation time 1602770000 ps
CPU time 1.88 seconds
Started Oct 15 09:48:39 AM UTC 24
Finished Oct 15 09:48:49 AM UTC 24
Peak memory 177796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3188105255 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_fib_smoke.3188105255
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/47.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/48.prim_lfsr_fib_smoke.857128024
Short name T158
Test name
Test status
Simulation time 1480750000 ps
CPU time 1.85 seconds
Started Oct 15 09:48:39 AM UTC 24
Finished Oct 15 09:48:49 AM UTC 24
Peak memory 177760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=857128024 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_f
ib.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_fib_smoke.857128024
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/48.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/49.prim_lfsr_fib_smoke.1454009425
Short name T160
Test name
Test status
Simulation time 1492990000 ps
CPU time 1.89 seconds
Started Oct 15 09:48:40 AM UTC 24
Finished Oct 15 09:48:50 AM UTC 24
Peak memory 177796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1454009425 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_fib_smoke.1454009425
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/49.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/5.prim_lfsr_fib_smoke.2783678557
Short name T6
Test name
Test status
Simulation time 1311530000 ps
CPU time 1.84 seconds
Started Oct 15 09:48:33 AM UTC 24
Finished Oct 15 09:48:42 AM UTC 24
Peak memory 177764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2783678557 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_fib_smoke.2783678557
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/5.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/6.prim_lfsr_fib_smoke.2274549363
Short name T135
Test name
Test status
Simulation time 1583010000 ps
CPU time 1.8 seconds
Started Oct 15 09:48:33 AM UTC 24
Finished Oct 15 09:48:44 AM UTC 24
Peak memory 177764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2274549363 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_fib_smoke.2274549363
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/6.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/7.prim_lfsr_fib_smoke.2461003298
Short name T137
Test name
Test status
Simulation time 1570950000 ps
CPU time 2.07 seconds
Started Oct 15 09:48:33 AM UTC 24
Finished Oct 15 09:48:44 AM UTC 24
Peak memory 177764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2461003298 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_fib_smoke.2461003298
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/7.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/8.prim_lfsr_fib_smoke.959224163
Short name T129
Test name
Test status
Simulation time 1520070000 ps
CPU time 1.88 seconds
Started Oct 15 09:48:33 AM UTC 24
Finished Oct 15 09:48:44 AM UTC 24
Peak memory 177796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=959224163 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_f
ib.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_fib_smoke.959224163
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/8.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_fib/9.prim_lfsr_fib_smoke.2464476434
Short name T29
Test name
Test status
Simulation time 1428830000 ps
CPU time 1.74 seconds
Started Oct 15 09:48:33 AM UTC 24
Finished Oct 15 09:48:43 AM UTC 24
Peak memory 177736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_8_fib/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2464476434 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
fib.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_fib_smoke.2464476434
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/9.prim_lfsr_fib_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/0.prim_lfsr_gal_smoke.3103589569
Short name T42
Test name
Test status
Simulation time 1488090000 ps
CPU time 1.88 seconds
Started Oct 15 09:48:17 AM UTC 24
Finished Oct 15 09:48:30 AM UTC 24
Peak memory 177728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3103589569 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 0.prim_lfsr_gal_smoke.3103589569
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/0.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/1.prim_lfsr_gal_smoke.769350748
Short name T50
Test name
Test status
Simulation time 1577950000 ps
CPU time 1.81 seconds
Started Oct 15 09:48:17 AM UTC 24
Finished Oct 15 09:48:31 AM UTC 24
Peak memory 177760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=769350748 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_g
al.vdb -cm_log /dev/null -cm_name 1.prim_lfsr_gal_smoke.769350748
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/1.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/10.prim_lfsr_gal_smoke.2904784285
Short name T53
Test name
Test status
Simulation time 1557610000 ps
CPU time 1.91 seconds
Started Oct 15 09:48:17 AM UTC 24
Finished Oct 15 09:48:31 AM UTC 24
Peak memory 177760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2904784285 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 10.prim_lfsr_gal_smoke.2904784285
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/10.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/11.prim_lfsr_gal_smoke.2164436422
Short name T47
Test name
Test status
Simulation time 1460590000 ps
CPU time 1.9 seconds
Started Oct 15 09:48:17 AM UTC 24
Finished Oct 15 09:48:30 AM UTC 24
Peak memory 177760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2164436422 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 11.prim_lfsr_gal_smoke.2164436422
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/11.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/12.prim_lfsr_gal_smoke.2783986334
Short name T57
Test name
Test status
Simulation time 1613910000 ps
CPU time 1.81 seconds
Started Oct 15 09:48:17 AM UTC 24
Finished Oct 15 09:48:32 AM UTC 24
Peak memory 177760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2783986334 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 12.prim_lfsr_gal_smoke.2783986334
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/12.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/14.prim_lfsr_gal_smoke.632709679
Short name T9
Test name
Test status
Simulation time 1318150000 ps
CPU time 1.72 seconds
Started Oct 15 09:48:17 AM UTC 24
Finished Oct 15 09:48:29 AM UTC 24
Peak memory 177728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=632709679 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_g
al.vdb -cm_log /dev/null -cm_name 14.prim_lfsr_gal_smoke.632709679
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/14.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/15.prim_lfsr_gal_smoke.1652894155
Short name T10
Test name
Test status
Simulation time 1327550000 ps
CPU time 1.75 seconds
Started Oct 15 09:48:17 AM UTC 24
Finished Oct 15 09:48:29 AM UTC 24
Peak memory 177476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1652894155 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 15.prim_lfsr_gal_smoke.1652894155
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/15.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/16.prim_lfsr_gal_smoke.1674279373
Short name T46
Test name
Test status
Simulation time 1452430000 ps
CPU time 1.78 seconds
Started Oct 15 09:48:17 AM UTC 24
Finished Oct 15 09:48:30 AM UTC 24
Peak memory 177760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1674279373 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 16.prim_lfsr_gal_smoke.1674279373
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/16.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/17.prim_lfsr_gal_smoke.265882668
Short name T44
Test name
Test status
Simulation time 1407030000 ps
CPU time 1.7 seconds
Started Oct 15 09:48:17 AM UTC 24
Finished Oct 15 09:48:30 AM UTC 24
Peak memory 177632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=265882668 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_g
al.vdb -cm_log /dev/null -cm_name 17.prim_lfsr_gal_smoke.265882668
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/17.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/18.prim_lfsr_gal_smoke.3268988708
Short name T12
Test name
Test status
Simulation time 1323090000 ps
CPU time 1.68 seconds
Started Oct 15 09:48:17 AM UTC 24
Finished Oct 15 09:48:30 AM UTC 24
Peak memory 177712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3268988708 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 18.prim_lfsr_gal_smoke.3268988708
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/18.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/19.prim_lfsr_gal_smoke.1016565072
Short name T13
Test name
Test status
Simulation time 1334470000 ps
CPU time 1.71 seconds
Started Oct 15 09:48:18 AM UTC 24
Finished Oct 15 09:48:30 AM UTC 24
Peak memory 177760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1016565072 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 19.prim_lfsr_gal_smoke.1016565072
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/19.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/2.prim_lfsr_gal_smoke.904211642
Short name T7
Test name
Test status
Simulation time 1350390000 ps
CPU time 1.78 seconds
Started Oct 15 09:48:17 AM UTC 24
Finished Oct 15 09:48:29 AM UTC 24
Peak memory 177760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=904211642 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_g
al.vdb -cm_log /dev/null -cm_name 2.prim_lfsr_gal_smoke.904211642
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/2.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/20.prim_lfsr_gal_smoke.825556102
Short name T48
Test name
Test status
Simulation time 1458790000 ps
CPU time 1.8 seconds
Started Oct 15 09:48:18 AM UTC 24
Finished Oct 15 09:48:31 AM UTC 24
Peak memory 177724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=825556102 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_g
al.vdb -cm_log /dev/null -cm_name 20.prim_lfsr_gal_smoke.825556102
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/20.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/21.prim_lfsr_gal_smoke.9228132
Short name T1
Test name
Test status
Simulation time 1171730000 ps
CPU time 1.54 seconds
Started Oct 15 09:48:18 AM UTC 24
Finished Oct 15 09:48:29 AM UTC 24
Peak memory 177764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9228132 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal
.vdb -cm_log /dev/null -cm_name 21.prim_lfsr_gal_smoke.9228132
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/21.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/22.prim_lfsr_gal_smoke.3415969220
Short name T56
Test name
Test status
Simulation time 1565770000 ps
CPU time 2 seconds
Started Oct 15 09:48:18 AM UTC 24
Finished Oct 15 09:48:31 AM UTC 24
Peak memory 177760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3415969220 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 22.prim_lfsr_gal_smoke.3415969220
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/22.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/23.prim_lfsr_gal_smoke.3187082928
Short name T49
Test name
Test status
Simulation time 1440170000 ps
CPU time 1.82 seconds
Started Oct 15 09:48:18 AM UTC 24
Finished Oct 15 09:48:31 AM UTC 24
Peak memory 177760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3187082928 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 23.prim_lfsr_gal_smoke.3187082928
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/23.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/24.prim_lfsr_gal_smoke.3200872253
Short name T45
Test name
Test status
Simulation time 1408130000 ps
CPU time 1.67 seconds
Started Oct 15 09:48:18 AM UTC 24
Finished Oct 15 09:48:30 AM UTC 24
Peak memory 177760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3200872253 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 24.prim_lfsr_gal_smoke.3200872253
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/24.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/25.prim_lfsr_gal_smoke.2837893542
Short name T55
Test name
Test status
Simulation time 1541290000 ps
CPU time 2.02 seconds
Started Oct 15 09:48:18 AM UTC 24
Finished Oct 15 09:48:31 AM UTC 24
Peak memory 177760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2837893542 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 25.prim_lfsr_gal_smoke.2837893542
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/25.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/26.prim_lfsr_gal_smoke.2722945881
Short name T54
Test name
Test status
Simulation time 1257150000 ps
CPU time 1.71 seconds
Started Oct 15 09:48:20 AM UTC 24
Finished Oct 15 09:48:31 AM UTC 24
Peak memory 177760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2722945881 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 26.prim_lfsr_gal_smoke.2722945881
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/26.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/27.prim_lfsr_gal_smoke.3076610606
Short name T60
Test name
Test status
Simulation time 1449950000 ps
CPU time 1.95 seconds
Started Oct 15 09:48:20 AM UTC 24
Finished Oct 15 09:48:32 AM UTC 24
Peak memory 177760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3076610606 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 27.prim_lfsr_gal_smoke.3076610606
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/27.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/28.prim_lfsr_gal_smoke.1418210133
Short name T59
Test name
Test status
Simulation time 1430310000 ps
CPU time 1.95 seconds
Started Oct 15 09:48:20 AM UTC 24
Finished Oct 15 09:48:32 AM UTC 24
Peak memory 177760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1418210133 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 28.prim_lfsr_gal_smoke.1418210133
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/28.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/29.prim_lfsr_gal_smoke.3755030158
Short name T61
Test name
Test status
Simulation time 1512470000 ps
CPU time 1.93 seconds
Started Oct 15 09:48:20 AM UTC 24
Finished Oct 15 09:48:33 AM UTC 24
Peak memory 177760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3755030158 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 29.prim_lfsr_gal_smoke.3755030158
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/29.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/3.prim_lfsr_gal_smoke.2680666258
Short name T41
Test name
Test status
Simulation time 1456410000 ps
CPU time 1.8 seconds
Started Oct 15 09:48:17 AM UTC 24
Finished Oct 15 09:48:30 AM UTC 24
Peak memory 177728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2680666258 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 3.prim_lfsr_gal_smoke.2680666258
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/3.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/30.prim_lfsr_gal_smoke.1781503602
Short name T58
Test name
Test status
Simulation time 1300490000 ps
CPU time 1.75 seconds
Started Oct 15 09:48:20 AM UTC 24
Finished Oct 15 09:48:32 AM UTC 24
Peak memory 177760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1781503602 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 30.prim_lfsr_gal_smoke.1781503602
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/30.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/31.prim_lfsr_gal_smoke.3998506987
Short name T63
Test name
Test status
Simulation time 1434070000 ps
CPU time 1.76 seconds
Started Oct 15 09:48:22 AM UTC 24
Finished Oct 15 09:48:34 AM UTC 24
Peak memory 177760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3998506987 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 31.prim_lfsr_gal_smoke.3998506987
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/31.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/32.prim_lfsr_gal_smoke.1453123139
Short name T64
Test name
Test status
Simulation time 1466770000 ps
CPU time 1.69 seconds
Started Oct 15 09:48:22 AM UTC 24
Finished Oct 15 09:48:35 AM UTC 24
Peak memory 177760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1453123139 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 32.prim_lfsr_gal_smoke.1453123139
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/32.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/33.prim_lfsr_gal_smoke.3196413061
Short name T62
Test name
Test status
Simulation time 1309710000 ps
CPU time 1.7 seconds
Started Oct 15 09:48:22 AM UTC 24
Finished Oct 15 09:48:33 AM UTC 24
Peak memory 177760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3196413061 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 33.prim_lfsr_gal_smoke.3196413061
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/33.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/34.prim_lfsr_gal_smoke.1645593396
Short name T71
Test name
Test status
Simulation time 1389910000 ps
CPU time 1.77 seconds
Started Oct 15 09:48:27 AM UTC 24
Finished Oct 15 09:48:37 AM UTC 24
Peak memory 177692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1645593396 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 34.prim_lfsr_gal_smoke.1645593396
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/34.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/35.prim_lfsr_gal_smoke.3926894695
Short name T65
Test name
Test status
Simulation time 1256090000 ps
CPU time 1.7 seconds
Started Oct 15 09:48:27 AM UTC 24
Finished Oct 15 09:48:37 AM UTC 24
Peak memory 177760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3926894695 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 35.prim_lfsr_gal_smoke.3926894695
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/35.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/36.prim_lfsr_gal_smoke.1017368306
Short name T72
Test name
Test status
Simulation time 1461630000 ps
CPU time 1.8 seconds
Started Oct 15 09:48:27 AM UTC 24
Finished Oct 15 09:48:38 AM UTC 24
Peak memory 177692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1017368306 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 36.prim_lfsr_gal_smoke.1017368306
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/36.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/37.prim_lfsr_gal_smoke.2897609950
Short name T76
Test name
Test status
Simulation time 1526270000 ps
CPU time 1.98 seconds
Started Oct 15 09:48:27 AM UTC 24
Finished Oct 15 09:48:38 AM UTC 24
Peak memory 177760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2897609950 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 37.prim_lfsr_gal_smoke.2897609950
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/37.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/38.prim_lfsr_gal_smoke.1030405888
Short name T73
Test name
Test status
Simulation time 1444150000 ps
CPU time 1.8 seconds
Started Oct 15 09:48:27 AM UTC 24
Finished Oct 15 09:48:38 AM UTC 24
Peak memory 177760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1030405888 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 38.prim_lfsr_gal_smoke.1030405888
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/38.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/39.prim_lfsr_gal_smoke.1402852482
Short name T69
Test name
Test status
Simulation time 1369770000 ps
CPU time 1.76 seconds
Started Oct 15 09:48:27 AM UTC 24
Finished Oct 15 09:48:37 AM UTC 24
Peak memory 177760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1402852482 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 39.prim_lfsr_gal_smoke.1402852482
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/39.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/4.prim_lfsr_gal_smoke.265413297
Short name T2
Test name
Test status
Simulation time 1268370000 ps
CPU time 1.72 seconds
Started Oct 15 09:48:17 AM UTC 24
Finished Oct 15 09:48:29 AM UTC 24
Peak memory 177724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=265413297 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_g
al.vdb -cm_log /dev/null -cm_name 4.prim_lfsr_gal_smoke.265413297
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/4.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/40.prim_lfsr_gal_smoke.93605104
Short name T77
Test name
Test status
Simulation time 1512990000 ps
CPU time 1.9 seconds
Started Oct 15 09:48:27 AM UTC 24
Finished Oct 15 09:48:38 AM UTC 24
Peak memory 177728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=93605104 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_ga
l.vdb -cm_log /dev/null -cm_name 40.prim_lfsr_gal_smoke.93605104
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/40.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/41.prim_lfsr_gal_smoke.3217960459
Short name T79
Test name
Test status
Simulation time 1570110000 ps
CPU time 1.97 seconds
Started Oct 15 09:48:27 AM UTC 24
Finished Oct 15 09:48:39 AM UTC 24
Peak memory 177760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3217960459 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 41.prim_lfsr_gal_smoke.3217960459
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/41.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/42.prim_lfsr_gal_smoke.3229883183
Short name T80
Test name
Test status
Simulation time 1583670000 ps
CPU time 1.91 seconds
Started Oct 15 09:48:27 AM UTC 24
Finished Oct 15 09:48:39 AM UTC 24
Peak memory 177760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3229883183 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 42.prim_lfsr_gal_smoke.3229883183
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/42.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/43.prim_lfsr_gal_smoke.1439588815
Short name T66
Test name
Test status
Simulation time 1252970000 ps
CPU time 1.71 seconds
Started Oct 15 09:48:27 AM UTC 24
Finished Oct 15 09:48:37 AM UTC 24
Peak memory 177760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1439588815 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 43.prim_lfsr_gal_smoke.1439588815
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/43.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/44.prim_lfsr_gal_smoke.3419004261
Short name T74
Test name
Test status
Simulation time 1428690000 ps
CPU time 1.78 seconds
Started Oct 15 09:48:27 AM UTC 24
Finished Oct 15 09:48:38 AM UTC 24
Peak memory 177760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3419004261 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 44.prim_lfsr_gal_smoke.3419004261
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/44.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/45.prim_lfsr_gal_smoke.4142159001
Short name T78
Test name
Test status
Simulation time 1526450000 ps
CPU time 1.96 seconds
Started Oct 15 09:48:27 AM UTC 24
Finished Oct 15 09:48:39 AM UTC 24
Peak memory 177756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4142159001 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 45.prim_lfsr_gal_smoke.4142159001
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/45.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/46.prim_lfsr_gal_smoke.2708093597
Short name T75
Test name
Test status
Simulation time 1447510000 ps
CPU time 1.77 seconds
Started Oct 15 09:48:27 AM UTC 24
Finished Oct 15 09:48:38 AM UTC 24
Peak memory 177760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2708093597 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 46.prim_lfsr_gal_smoke.2708093597
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/46.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/47.prim_lfsr_gal_smoke.771799632
Short name T67
Test name
Test status
Simulation time 1250970000 ps
CPU time 1.69 seconds
Started Oct 15 09:48:27 AM UTC 24
Finished Oct 15 09:48:37 AM UTC 24
Peak memory 177724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=771799632 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_g
al.vdb -cm_log /dev/null -cm_name 47.prim_lfsr_gal_smoke.771799632
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/47.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/48.prim_lfsr_gal_smoke.155802523
Short name T70
Test name
Test status
Simulation time 1280590000 ps
CPU time 1.86 seconds
Started Oct 15 09:48:27 AM UTC 24
Finished Oct 15 09:48:37 AM UTC 24
Peak memory 177724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=155802523 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_g
al.vdb -cm_log /dev/null -cm_name 48.prim_lfsr_gal_smoke.155802523
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/48.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/49.prim_lfsr_gal_smoke.3327309982
Short name T68
Test name
Test status
Simulation time 1228130000 ps
CPU time 1.69 seconds
Started Oct 15 09:48:27 AM UTC 24
Finished Oct 15 09:48:37 AM UTC 24
Peak memory 177760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3327309982 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 49.prim_lfsr_gal_smoke.3327309982
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/49.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/5.prim_lfsr_gal_smoke.935376137
Short name T3
Test name
Test status
Simulation time 1293490000 ps
CPU time 1.66 seconds
Started Oct 15 09:48:17 AM UTC 24
Finished Oct 15 09:48:29 AM UTC 24
Peak memory 177760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=935376137 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_g
al.vdb -cm_log /dev/null -cm_name 5.prim_lfsr_gal_smoke.935376137
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/5.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/6.prim_lfsr_gal_smoke.2818867720
Short name T52
Test name
Test status
Simulation time 1567350000 ps
CPU time 1.87 seconds
Started Oct 15 09:48:17 AM UTC 24
Finished Oct 15 09:48:31 AM UTC 24
Peak memory 177728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2818867720 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 6.prim_lfsr_gal_smoke.2818867720
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/6.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/7.prim_lfsr_gal_smoke.461852847
Short name T51
Test name
Test status
Simulation time 1536610000 ps
CPU time 1.91 seconds
Started Oct 15 09:48:17 AM UTC 24
Finished Oct 15 09:48:31 AM UTC 24
Peak memory 177760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=461852847 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_g
al.vdb -cm_log /dev/null -cm_name 7.prim_lfsr_gal_smoke.461852847
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/7.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/8.prim_lfsr_gal_smoke.1752158774
Short name T43
Test name
Test status
Simulation time 1428310000 ps
CPU time 1.81 seconds
Started Oct 15 09:48:17 AM UTC 24
Finished Oct 15 09:48:30 AM UTC 24
Peak memory 177728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1752158774 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 8.prim_lfsr_gal_smoke.1752158774
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/8.prim_lfsr_gal_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_gal/9.prim_lfsr_gal_smoke.3996021680
Short name T11
Test name
Test status
Simulation time 1353810000 ps
CPU time 1.94 seconds
Started Oct 15 09:48:17 AM UTC 24
Finished Oct 15 09:48:30 AM UTC 24
Peak memory 177728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/prim_lfsr_dw_8_gal/simv +prim_lfsr_use_default_seed=0 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3996021680 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ=
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/coverage/prim_lfsr_dw_8_
gal.vdb -cm_log /dev/null -cm_name 9.prim_lfsr_gal_smoke.3996021680
Directory /workspaces/repo/scratch/os_regression_2024_10_14/prim_lfsr-sim-vcs/9.prim_lfsr_gal_smoke/latest
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