| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 75.95 | 79.07 | 51.61 | 97.46 | 51.61 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 75.95 | 75.95 | 79.07 | 79.07 | 51.61 | 51.61 | 97.46 | 97.46 | 51.61 | 51.61 | 100.00 | 100.00 | /workspace/coverage/default/12.prim_present_test.3492499944 | ||
| Name |
|---|
| /workspace/coverage/default/0.prim_present_test.2033622794 |
| /workspace/coverage/default/1.prim_present_test.1661280118 |
| /workspace/coverage/default/10.prim_present_test.124811249 |
| /workspace/coverage/default/11.prim_present_test.291258785 |
| /workspace/coverage/default/13.prim_present_test.1883907460 |
| /workspace/coverage/default/14.prim_present_test.883420739 |
| /workspace/coverage/default/15.prim_present_test.2510473211 |
| /workspace/coverage/default/16.prim_present_test.1634841236 |
| /workspace/coverage/default/17.prim_present_test.4005955991 |
| /workspace/coverage/default/18.prim_present_test.1420284759 |
| /workspace/coverage/default/19.prim_present_test.3725853667 |
| /workspace/coverage/default/2.prim_present_test.156298461 |
| /workspace/coverage/default/20.prim_present_test.342948634 |
| /workspace/coverage/default/21.prim_present_test.2427113653 |
| /workspace/coverage/default/22.prim_present_test.3467898026 |
| /workspace/coverage/default/23.prim_present_test.1981398498 |
| /workspace/coverage/default/24.prim_present_test.3168942718 |
| /workspace/coverage/default/25.prim_present_test.1608996035 |
| /workspace/coverage/default/26.prim_present_test.984660292 |
| /workspace/coverage/default/27.prim_present_test.3174311949 |
| /workspace/coverage/default/28.prim_present_test.1113608443 |
| /workspace/coverage/default/29.prim_present_test.3623563489 |
| /workspace/coverage/default/3.prim_present_test.3854455828 |
| /workspace/coverage/default/30.prim_present_test.847019662 |
| /workspace/coverage/default/31.prim_present_test.3257180204 |
| /workspace/coverage/default/32.prim_present_test.2535246720 |
| /workspace/coverage/default/33.prim_present_test.3814184837 |
| /workspace/coverage/default/34.prim_present_test.2436636254 |
| /workspace/coverage/default/35.prim_present_test.883043875 |
| /workspace/coverage/default/36.prim_present_test.2434653113 |
| /workspace/coverage/default/37.prim_present_test.2635629563 |
| /workspace/coverage/default/38.prim_present_test.3466617081 |
| /workspace/coverage/default/39.prim_present_test.3596718982 |
| /workspace/coverage/default/4.prim_present_test.3162787183 |
| /workspace/coverage/default/40.prim_present_test.3953998423 |
| /workspace/coverage/default/41.prim_present_test.1078373174 |
| /workspace/coverage/default/42.prim_present_test.2022796015 |
| /workspace/coverage/default/43.prim_present_test.1496590315 |
| /workspace/coverage/default/44.prim_present_test.337361825 |
| /workspace/coverage/default/45.prim_present_test.1020684906 |
| /workspace/coverage/default/46.prim_present_test.721966960 |
| /workspace/coverage/default/47.prim_present_test.3747933802 |
| /workspace/coverage/default/48.prim_present_test.3747100029 |
| /workspace/coverage/default/49.prim_present_test.2961268100 |
| /workspace/coverage/default/5.prim_present_test.471202446 |
| /workspace/coverage/default/6.prim_present_test.1876769470 |
| /workspace/coverage/default/7.prim_present_test.1883516405 |
| /workspace/coverage/default/8.prim_present_test.1680625433 |
| /workspace/coverage/default/9.prim_present_test.892609742 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/22.prim_present_test.3467898026 | May 23 12:36:31 AM PDT 23 | May 23 12:39:39 AM PDT 23 | 3528600000 ps | ||
| T2 | /workspace/coverage/default/34.prim_present_test.2436636254 | May 23 12:36:40 AM PDT 23 | May 23 12:38:13 AM PDT 23 | 1865400000 ps | ||
| T3 | /workspace/coverage/default/13.prim_present_test.1883907460 | May 23 12:36:30 AM PDT 23 | May 23 12:39:42 AM PDT 23 | 3547600000 ps | ||
| T4 | /workspace/coverage/default/5.prim_present_test.471202446 | May 23 12:36:23 AM PDT 23 | May 23 12:39:06 AM PDT 23 | 3010400000 ps | ||
| T5 | /workspace/coverage/default/24.prim_present_test.3168942718 | May 23 12:36:37 AM PDT 23 | May 23 12:41:13 AM PDT 23 | 4928400000 ps | ||
| T6 | /workspace/coverage/default/12.prim_present_test.3492499944 | May 23 12:36:36 AM PDT 23 | May 23 12:38:05 AM PDT 23 | 1635800000 ps | ||
| T7 | /workspace/coverage/default/4.prim_present_test.3162787183 | May 23 12:36:20 AM PDT 23 | May 23 12:39:52 AM PDT 23 | 3886800000 ps | ||
| T8 | /workspace/coverage/default/28.prim_present_test.1113608443 | May 23 12:36:31 AM PDT 23 | May 23 12:37:36 AM PDT 23 | 1177800000 ps | ||
| T9 | /workspace/coverage/default/44.prim_present_test.337361825 | May 23 12:36:31 AM PDT 23 | May 23 12:37:31 AM PDT 23 | 1046200000 ps | ||
| T10 | /workspace/coverage/default/40.prim_present_test.3953998423 | May 23 12:36:39 AM PDT 23 | May 23 12:37:52 AM PDT 23 | 1272400000 ps | ||
| T11 | /workspace/coverage/default/1.prim_present_test.1661280118 | May 23 12:36:24 AM PDT 23 | May 23 12:38:13 AM PDT 23 | 1983000000 ps | ||
| T12 | /workspace/coverage/default/45.prim_present_test.1020684906 | May 23 12:36:44 AM PDT 23 | May 23 12:40:22 AM PDT 23 | 3961200000 ps | ||
| T13 | /workspace/coverage/default/38.prim_present_test.3466617081 | May 23 12:36:35 AM PDT 23 | May 23 12:40:20 AM PDT 23 | 4087000000 ps | ||
| T14 | /workspace/coverage/default/42.prim_present_test.2022796015 | May 23 12:36:35 AM PDT 23 | May 23 12:40:09 AM PDT 23 | 3841800000 ps | ||
| T15 | /workspace/coverage/default/41.prim_present_test.1078373174 | May 23 12:36:40 AM PDT 23 | May 23 12:39:01 AM PDT 23 | 2460200000 ps | ||
| T16 | /workspace/coverage/default/0.prim_present_test.2033622794 | May 23 12:36:23 AM PDT 23 | May 23 12:39:18 AM PDT 23 | 3225600000 ps | ||
| T17 | /workspace/coverage/default/23.prim_present_test.1981398498 | May 23 12:36:41 AM PDT 23 | May 23 12:40:18 AM PDT 23 | 3954200000 ps | ||
| T18 | /workspace/coverage/default/9.prim_present_test.892609742 | May 23 12:35:57 AM PDT 23 | May 23 12:39:42 AM PDT 23 | 4166400000 ps | ||
| T19 | /workspace/coverage/default/18.prim_present_test.1420284759 | May 23 12:36:35 AM PDT 23 | May 23 12:40:58 AM PDT 23 | 4903800000 ps | ||
| T20 | /workspace/coverage/default/48.prim_present_test.3747100029 | May 23 12:36:42 AM PDT 23 | May 23 12:39:55 AM PDT 23 | 3610600000 ps | ||
| T21 | /workspace/coverage/default/8.prim_present_test.1680625433 | May 23 12:36:20 AM PDT 23 | May 23 12:40:56 AM PDT 23 | 4976800000 ps | ||
| T22 | /workspace/coverage/default/16.prim_present_test.1634841236 | May 23 12:36:43 AM PDT 23 | May 23 12:38:49 AM PDT 23 | 2272000000 ps | ||
| T23 | /workspace/coverage/default/31.prim_present_test.3257180204 | May 23 12:36:30 AM PDT 23 | May 23 12:39:28 AM PDT 23 | 3329000000 ps | ||
| T24 | /workspace/coverage/default/21.prim_present_test.2427113653 | May 23 12:36:43 AM PDT 23 | May 23 12:38:53 AM PDT 23 | 2253400000 ps | ||
| T25 | /workspace/coverage/default/20.prim_present_test.342948634 | May 23 12:36:38 AM PDT 23 | May 23 12:40:14 AM PDT 23 | 3931000000 ps | ||
| T26 | /workspace/coverage/default/46.prim_present_test.721966960 | May 23 12:36:36 AM PDT 23 | May 23 12:40:46 AM PDT 23 | 4732400000 ps | ||
| T27 | /workspace/coverage/default/10.prim_present_test.124811249 | May 23 12:35:59 AM PDT 23 | May 23 12:38:19 AM PDT 23 | 2548800000 ps | ||
| T28 | /workspace/coverage/default/17.prim_present_test.4005955991 | May 23 12:36:32 AM PDT 23 | May 23 12:39:34 AM PDT 23 | 3313800000 ps | ||
| T29 | /workspace/coverage/default/11.prim_present_test.291258785 | May 23 12:36:23 AM PDT 23 | May 23 12:39:44 AM PDT 23 | 3724200000 ps | ||
| T30 | /workspace/coverage/default/2.prim_present_test.156298461 | May 23 12:36:14 AM PDT 23 | May 23 12:38:49 AM PDT 23 | 2892600000 ps | ||
| T31 | /workspace/coverage/default/26.prim_present_test.984660292 | May 23 12:36:44 AM PDT 23 | May 23 12:39:03 AM PDT 23 | 2535000000 ps | ||
| T32 | /workspace/coverage/default/47.prim_present_test.3747933802 | May 23 12:36:42 AM PDT 23 | May 23 12:38:16 AM PDT 23 | 1719600000 ps | ||
| T33 | /workspace/coverage/default/43.prim_present_test.1496590315 | May 23 12:36:31 AM PDT 23 | May 23 12:37:30 AM PDT 23 | 1077600000 ps | ||
| T34 | /workspace/coverage/default/36.prim_present_test.2434653113 | May 23 12:36:37 AM PDT 23 | May 23 12:38:51 AM PDT 23 | 2485000000 ps | ||
| T35 | /workspace/coverage/default/6.prim_present_test.1876769470 | May 23 12:36:09 AM PDT 23 | May 23 12:38:11 AM PDT 23 | 2214400000 ps | ||
| T36 | /workspace/coverage/default/3.prim_present_test.3854455828 | May 23 12:36:16 AM PDT 23 | May 23 12:38:08 AM PDT 23 | 2075000000 ps | ||
| T37 | /workspace/coverage/default/39.prim_present_test.3596718982 | May 23 12:36:36 AM PDT 23 | May 23 12:39:32 AM PDT 23 | 3266600000 ps | ||
| T38 | /workspace/coverage/default/33.prim_present_test.3814184837 | May 23 12:36:34 AM PDT 23 | May 23 12:38:25 AM PDT 23 | 2076800000 ps | ||
| T39 | /workspace/coverage/default/32.prim_present_test.2535246720 | May 23 12:36:43 AM PDT 23 | May 23 12:40:21 AM PDT 23 | 4017400000 ps | ||
| T40 | /workspace/coverage/default/30.prim_present_test.847019662 | May 23 12:36:37 AM PDT 23 | May 23 12:37:46 AM PDT 23 | 1258000000 ps | ||
| T41 | /workspace/coverage/default/15.prim_present_test.2510473211 | May 23 12:36:35 AM PDT 23 | May 23 12:37:55 AM PDT 23 | 1437800000 ps | ||
| T42 | /workspace/coverage/default/19.prim_present_test.3725853667 | May 23 12:36:32 AM PDT 23 | May 23 12:40:05 AM PDT 23 | 3866600000 ps | ||
| T43 | /workspace/coverage/default/37.prim_present_test.2635629563 | May 23 12:36:29 AM PDT 23 | May 23 12:39:23 AM PDT 23 | 3348400000 ps | ||
| T44 | /workspace/coverage/default/25.prim_present_test.1608996035 | May 23 12:36:34 AM PDT 23 | May 23 12:39:46 AM PDT 23 | 3596200000 ps | ||
| T45 | /workspace/coverage/default/14.prim_present_test.883420739 | May 23 12:36:33 AM PDT 23 | May 23 12:40:13 AM PDT 23 | 4187600000 ps | ||
| T46 | /workspace/coverage/default/35.prim_present_test.883043875 | May 23 12:36:44 AM PDT 23 | May 23 12:37:52 AM PDT 23 | 1245800000 ps | ||
| T47 | /workspace/coverage/default/49.prim_present_test.2961268100 | May 23 12:36:35 AM PDT 23 | May 23 12:39:42 AM PDT 23 | 3479400000 ps | ||
| T48 | /workspace/coverage/default/27.prim_present_test.3174311949 | May 23 12:36:29 AM PDT 23 | May 23 12:39:49 AM PDT 23 | 3644000000 ps | ||
| T49 | /workspace/coverage/default/29.prim_present_test.3623563489 | May 23 12:36:26 AM PDT 23 | May 23 12:40:19 AM PDT 23 | 4458400000 ps | ||
| T50 | /workspace/coverage/default/7.prim_present_test.1883516405 | May 23 12:36:23 AM PDT 23 | May 23 12:39:43 AM PDT 23 | 3674000000 ps |
| Test location | /workspace/coverage/default/12.prim_present_test.3492499944 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 1635800000 ps |
| CPU time | 82.66 seconds |
| Started | May 23 12:36:36 AM PDT 23 |
| Finished | May 23 12:38:05 AM PDT 23 |
| Peak memory | 155668 kb |
| Host | smart-1dcf15ff-bc3c-4011-9df0-9200c7bd7dc2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3492499944 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.3492499944 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/0.prim_present_test.2033622794 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 3225600000 ps |
| CPU time | 164.37 seconds |
| Started | May 23 12:36:23 AM PDT 23 |
| Finished | May 23 12:39:18 AM PDT 23 |
| Peak memory | 154512 kb |
| Host | smart-e408039a-08e6-4a0a-b0ab-cdd64cb290c5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2033622794 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.2033622794 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/1.prim_present_test.1661280118 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 1983000000 ps |
| CPU time | 101.19 seconds |
| Started | May 23 12:36:24 AM PDT 23 |
| Finished | May 23 12:38:13 AM PDT 23 |
| Peak memory | 155668 kb |
| Host | smart-a0bf22d2-4ee1-4e0d-92f2-644dadb63968 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1661280118 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.1661280118 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/10.prim_present_test.124811249 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 2548800000 ps |
| CPU time | 129.55 seconds |
| Started | May 23 12:35:59 AM PDT 23 |
| Finished | May 23 12:38:19 AM PDT 23 |
| Peak memory | 155660 kb |
| Host | smart-95d8464b-7fe7-4329-b48a-786fc68c3a2c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=124811249 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.124811249 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/11.prim_present_test.291258785 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 3724200000 ps |
| CPU time | 188.63 seconds |
| Started | May 23 12:36:23 AM PDT 23 |
| Finished | May 23 12:39:44 AM PDT 23 |
| Peak memory | 154636 kb |
| Host | smart-c6a0c663-b1ac-40e6-a30e-bd0fd1882d86 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=291258785 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.291258785 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.1883907460 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 3547600000 ps |
| CPU time | 178.45 seconds |
| Started | May 23 12:36:30 AM PDT 23 |
| Finished | May 23 12:39:42 AM PDT 23 |
| Peak memory | 155884 kb |
| Host | smart-7f49d8b2-2b4b-4660-9f18-f4d467b30439 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1883907460 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.1883907460 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.883420739 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 4187600000 ps |
| CPU time | 205.65 seconds |
| Started | May 23 12:36:33 AM PDT 23 |
| Finished | May 23 12:40:13 AM PDT 23 |
| Peak memory | 155660 kb |
| Host | smart-b8e96902-a721-4d31-88da-f298e3774939 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=883420739 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.883420739 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.2510473211 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 1437800000 ps |
| CPU time | 74.01 seconds |
| Started | May 23 12:36:35 AM PDT 23 |
| Finished | May 23 12:37:55 AM PDT 23 |
| Peak memory | 155572 kb |
| Host | smart-86861622-ac5d-4911-9c78-9c5873a4d77f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2510473211 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.2510473211 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.1634841236 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 2272000000 ps |
| CPU time | 117.02 seconds |
| Started | May 23 12:36:43 AM PDT 23 |
| Finished | May 23 12:38:49 AM PDT 23 |
| Peak memory | 155664 kb |
| Host | smart-fe5d26be-7f96-4e81-ad7e-e825a8d2dd93 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1634841236 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.1634841236 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.4005955991 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 3313800000 ps |
| CPU time | 169.7 seconds |
| Started | May 23 12:36:32 AM PDT 23 |
| Finished | May 23 12:39:34 AM PDT 23 |
| Peak memory | 155656 kb |
| Host | smart-8156c214-a496-4619-a7db-3867cebd3c1c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4005955991 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.4005955991 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.1420284759 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 4903800000 ps |
| CPU time | 247.21 seconds |
| Started | May 23 12:36:35 AM PDT 23 |
| Finished | May 23 12:40:58 AM PDT 23 |
| Peak memory | 155812 kb |
| Host | smart-1018997b-f254-4616-a682-e1bdc78a9650 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1420284759 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.1420284759 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.3725853667 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 3866600000 ps |
| CPU time | 198.63 seconds |
| Started | May 23 12:36:32 AM PDT 23 |
| Finished | May 23 12:40:05 AM PDT 23 |
| Peak memory | 155732 kb |
| Host | smart-3a45df5e-aee4-4b63-b3ce-30f3e60bcd5b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3725853667 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.3725853667 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.156298461 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 2892600000 ps |
| CPU time | 144.74 seconds |
| Started | May 23 12:36:14 AM PDT 23 |
| Finished | May 23 12:38:49 AM PDT 23 |
| Peak memory | 155660 kb |
| Host | smart-64e59bc8-1d61-4d86-b3c1-f32d5cec4d41 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=156298461 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.156298461 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.342948634 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 3931000000 ps |
| CPU time | 199.32 seconds |
| Started | May 23 12:36:38 AM PDT 23 |
| Finished | May 23 12:40:14 AM PDT 23 |
| Peak memory | 155680 kb |
| Host | smart-a16326f7-2872-4036-86ff-62055a935d7b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=342948634 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.342948634 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.2427113653 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 2253400000 ps |
| CPU time | 120.28 seconds |
| Started | May 23 12:36:43 AM PDT 23 |
| Finished | May 23 12:38:53 AM PDT 23 |
| Peak memory | 155660 kb |
| Host | smart-e4799be9-f16b-4682-8840-007e5dee9450 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2427113653 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.2427113653 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.3467898026 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 3528600000 ps |
| CPU time | 176.03 seconds |
| Started | May 23 12:36:31 AM PDT 23 |
| Finished | May 23 12:39:39 AM PDT 23 |
| Peak memory | 155660 kb |
| Host | smart-0247c23a-754e-4176-82b6-1165eaafa4b3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3467898026 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.3467898026 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.1981398498 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 3954200000 ps |
| CPU time | 202.2 seconds |
| Started | May 23 12:36:41 AM PDT 23 |
| Finished | May 23 12:40:18 AM PDT 23 |
| Peak memory | 155672 kb |
| Host | smart-f623723e-94c5-4bf2-82e3-bd6ab303f87a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1981398498 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.1981398498 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.3168942718 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 4928400000 ps |
| CPU time | 254.73 seconds |
| Started | May 23 12:36:37 AM PDT 23 |
| Finished | May 23 12:41:13 AM PDT 23 |
| Peak memory | 155776 kb |
| Host | smart-6759ff5e-0574-4901-9fb1-78b42ae8cd35 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3168942718 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.3168942718 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.1608996035 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 3596200000 ps |
| CPU time | 178.99 seconds |
| Started | May 23 12:36:34 AM PDT 23 |
| Finished | May 23 12:39:46 AM PDT 23 |
| Peak memory | 155656 kb |
| Host | smart-d2021f0b-2e27-4ce8-8f20-15a485134180 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1608996035 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.1608996035 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.984660292 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 2535000000 ps |
| CPU time | 128.89 seconds |
| Started | May 23 12:36:44 AM PDT 23 |
| Finished | May 23 12:39:03 AM PDT 23 |
| Peak memory | 155652 kb |
| Host | smart-0755cf48-cb17-43d1-81a8-db3fba517449 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=984660292 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.984660292 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.3174311949 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 3644000000 ps |
| CPU time | 186.13 seconds |
| Started | May 23 12:36:29 AM PDT 23 |
| Finished | May 23 12:39:49 AM PDT 23 |
| Peak memory | 155580 kb |
| Host | smart-b4cac747-fc5d-4432-bcc8-4441a99451dd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3174311949 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.3174311949 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.1113608443 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 1177800000 ps |
| CPU time | 59.86 seconds |
| Started | May 23 12:36:31 AM PDT 23 |
| Finished | May 23 12:37:36 AM PDT 23 |
| Peak memory | 155596 kb |
| Host | smart-fb1c6772-d3ca-479f-8f3a-dde1b097dc4c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1113608443 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.1113608443 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.3623563489 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 4458400000 ps |
| CPU time | 217.89 seconds |
| Started | May 23 12:36:26 AM PDT 23 |
| Finished | May 23 12:40:19 AM PDT 23 |
| Peak memory | 155888 kb |
| Host | smart-4c782715-fa75-43f9-b1fc-0a2a473e512b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3623563489 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.3623563489 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.3854455828 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 2075000000 ps |
| CPU time | 104.75 seconds |
| Started | May 23 12:36:16 AM PDT 23 |
| Finished | May 23 12:38:08 AM PDT 23 |
| Peak memory | 155600 kb |
| Host | smart-24f28857-6a33-4506-a281-0150670da6f0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3854455828 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.3854455828 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.847019662 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 1258000000 ps |
| CPU time | 64.83 seconds |
| Started | May 23 12:36:37 AM PDT 23 |
| Finished | May 23 12:37:46 AM PDT 23 |
| Peak memory | 155576 kb |
| Host | smart-8977ad21-cfa4-478e-affa-46c0b105e603 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=847019662 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.847019662 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.3257180204 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 3329000000 ps |
| CPU time | 165.18 seconds |
| Started | May 23 12:36:30 AM PDT 23 |
| Finished | May 23 12:39:28 AM PDT 23 |
| Peak memory | 155652 kb |
| Host | smart-72dd1f48-fbb6-4319-8a23-f0e0562d7abb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3257180204 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.3257180204 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.2535246720 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 4017400000 ps |
| CPU time | 204.17 seconds |
| Started | May 23 12:36:43 AM PDT 23 |
| Finished | May 23 12:40:21 AM PDT 23 |
| Peak memory | 155672 kb |
| Host | smart-44346e21-f2e9-441b-b33c-8badb3901804 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2535246720 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.2535246720 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.3814184837 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 2076800000 ps |
| CPU time | 104.95 seconds |
| Started | May 23 12:36:34 AM PDT 23 |
| Finished | May 23 12:38:25 AM PDT 23 |
| Peak memory | 155620 kb |
| Host | smart-f760d637-23fb-4e97-b700-09a8626f464b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3814184837 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.3814184837 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.2436636254 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 1865400000 ps |
| CPU time | 87.03 seconds |
| Started | May 23 12:36:40 AM PDT 23 |
| Finished | May 23 12:38:13 AM PDT 23 |
| Peak memory | 155600 kb |
| Host | smart-b8c11dd2-62a4-49ee-8b95-0d71859084b8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2436636254 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.2436636254 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.883043875 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 1245800000 ps |
| CPU time | 63.78 seconds |
| Started | May 23 12:36:44 AM PDT 23 |
| Finished | May 23 12:37:52 AM PDT 23 |
| Peak memory | 155596 kb |
| Host | smart-8628bec9-a0f9-4fb8-9566-5c26e684f662 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=883043875 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.883043875 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.2434653113 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 2485000000 ps |
| CPU time | 125.1 seconds |
| Started | May 23 12:36:37 AM PDT 23 |
| Finished | May 23 12:38:51 AM PDT 23 |
| Peak memory | 155668 kb |
| Host | smart-401adba3-bf27-4123-95f7-bbc1f459c6ab |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2434653113 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.2434653113 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.2635629563 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 3348400000 ps |
| CPU time | 162.74 seconds |
| Started | May 23 12:36:29 AM PDT 23 |
| Finished | May 23 12:39:23 AM PDT 23 |
| Peak memory | 155672 kb |
| Host | smart-bbc5e225-fcc1-445b-b42b-4926777ff89e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2635629563 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.2635629563 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.3466617081 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 4087000000 ps |
| CPU time | 209.56 seconds |
| Started | May 23 12:36:35 AM PDT 23 |
| Finished | May 23 12:40:20 AM PDT 23 |
| Peak memory | 155636 kb |
| Host | smart-d46fc383-f9da-4058-a987-6305e5ec4e92 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3466617081 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.3466617081 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.3596718982 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 3266600000 ps |
| CPU time | 165.07 seconds |
| Started | May 23 12:36:36 AM PDT 23 |
| Finished | May 23 12:39:32 AM PDT 23 |
| Peak memory | 155672 kb |
| Host | smart-899ad85b-b518-4174-973f-1106af533708 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3596718982 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.3596718982 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.3162787183 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 3886800000 ps |
| CPU time | 198.89 seconds |
| Started | May 23 12:36:20 AM PDT 23 |
| Finished | May 23 12:39:52 AM PDT 23 |
| Peak memory | 155728 kb |
| Host | smart-0b696187-4396-4395-b90b-4d23395e02fb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3162787183 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.3162787183 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.3953998423 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 1272400000 ps |
| CPU time | 67 seconds |
| Started | May 23 12:36:39 AM PDT 23 |
| Finished | May 23 12:37:52 AM PDT 23 |
| Peak memory | 155592 kb |
| Host | smart-182192d8-c7eb-4669-aed2-a461dd8c90cf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3953998423 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.3953998423 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.1078373174 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 2460200000 ps |
| CPU time | 130 seconds |
| Started | May 23 12:36:40 AM PDT 23 |
| Finished | May 23 12:39:01 AM PDT 23 |
| Peak memory | 155652 kb |
| Host | smart-5ac64ba1-97d6-407c-8558-81f8ac39f8c0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1078373174 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.1078373174 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.2022796015 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 3841800000 ps |
| CPU time | 198.64 seconds |
| Started | May 23 12:36:35 AM PDT 23 |
| Finished | May 23 12:40:09 AM PDT 23 |
| Peak memory | 155636 kb |
| Host | smart-27f5ec44-733f-41b9-8069-e4b10870eaa6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2022796015 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.2022796015 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.1496590315 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 1077600000 ps |
| CPU time | 54.51 seconds |
| Started | May 23 12:36:31 AM PDT 23 |
| Finished | May 23 12:37:30 AM PDT 23 |
| Peak memory | 155824 kb |
| Host | smart-5de18cd1-ba7e-4c67-8925-bab1e4fc0f16 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1496590315 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.1496590315 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.337361825 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 1046200000 ps |
| CPU time | 55.72 seconds |
| Started | May 23 12:36:31 AM PDT 23 |
| Finished | May 23 12:37:31 AM PDT 23 |
| Peak memory | 155664 kb |
| Host | smart-5ac107bd-ec89-45d6-bdd1-909bf0402038 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=337361825 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.337361825 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.1020684906 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 3961200000 ps |
| CPU time | 201.24 seconds |
| Started | May 23 12:36:44 AM PDT 23 |
| Finished | May 23 12:40:22 AM PDT 23 |
| Peak memory | 155668 kb |
| Host | smart-9272bf48-2e28-4770-be3d-4e57ccb81905 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1020684906 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.1020684906 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.721966960 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 4732400000 ps |
| CPU time | 233.52 seconds |
| Started | May 23 12:36:36 AM PDT 23 |
| Finished | May 23 12:40:46 AM PDT 23 |
| Peak memory | 155816 kb |
| Host | smart-d5f87f96-1cae-4a86-8b83-1ac84bb93697 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=721966960 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.721966960 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.3747933802 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 1719600000 ps |
| CPU time | 87.12 seconds |
| Started | May 23 12:36:42 AM PDT 23 |
| Finished | May 23 12:38:16 AM PDT 23 |
| Peak memory | 155600 kb |
| Host | smart-eb458479-c9c6-4ee3-a9e4-f64d9c43251e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3747933802 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.3747933802 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.3747100029 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 3610600000 ps |
| CPU time | 180.53 seconds |
| Started | May 23 12:36:42 AM PDT 23 |
| Finished | May 23 12:39:55 AM PDT 23 |
| Peak memory | 155660 kb |
| Host | smart-5064d4ea-6564-4628-b028-ab0c44389812 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3747100029 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.3747100029 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.2961268100 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 3479400000 ps |
| CPU time | 175.11 seconds |
| Started | May 23 12:36:35 AM PDT 23 |
| Finished | May 23 12:39:42 AM PDT 23 |
| Peak memory | 155672 kb |
| Host | smart-d81d9bbb-3b2a-4e97-86b5-3fc7c671aaea |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2961268100 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.2961268100 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.471202446 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 3010400000 ps |
| CPU time | 153.03 seconds |
| Started | May 23 12:36:23 AM PDT 23 |
| Finished | May 23 12:39:06 AM PDT 23 |
| Peak memory | 155660 kb |
| Host | smart-a7320225-43e3-4351-ad51-61d828c21e82 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=471202446 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.471202446 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.1876769470 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 2214400000 ps |
| CPU time | 113.63 seconds |
| Started | May 23 12:36:09 AM PDT 23 |
| Finished | May 23 12:38:11 AM PDT 23 |
| Peak memory | 155732 kb |
| Host | smart-7c8c56c6-88d5-4004-b262-fec3bd55cf33 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1876769470 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.1876769470 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.1883516405 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 3674000000 ps |
| CPU time | 188.63 seconds |
| Started | May 23 12:36:23 AM PDT 23 |
| Finished | May 23 12:39:43 AM PDT 23 |
| Peak memory | 155660 kb |
| Host | smart-f3f6e6fc-b50b-4976-8a84-1a4d1e696221 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1883516405 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.1883516405 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.1680625433 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 4976800000 ps |
| CPU time | 259.44 seconds |
| Started | May 23 12:36:20 AM PDT 23 |
| Finished | May 23 12:40:56 AM PDT 23 |
| Peak memory | 155868 kb |
| Host | smart-64df9591-74d8-4021-9046-67e7f5388018 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1680625433 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.1680625433 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.892609742 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 4166400000 ps |
| CPU time | 208.67 seconds |
| Started | May 23 12:35:57 AM PDT 23 |
| Finished | May 23 12:39:42 AM PDT 23 |
| Peak memory | 155660 kb |
| Host | smart-c105f201-46cf-4fe2-966c-f915c5f7ca98 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=892609742 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.892609742 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |