| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 75.95 | 79.07 | 51.61 | 97.46 | 51.61 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 75.95 | 75.95 | 79.07 | 79.07 | 51.61 | 51.61 | 97.46 | 97.46 | 51.61 | 51.61 | 100.00 | 100.00 | /workspace/coverage/default/12.prim_present_test.1881426 | ||
| Name |
|---|
| /workspace/coverage/default/0.prim_present_test.96681366 |
| /workspace/coverage/default/1.prim_present_test.2496543837 |
| /workspace/coverage/default/10.prim_present_test.2346889561 |
| /workspace/coverage/default/11.prim_present_test.3761612235 |
| /workspace/coverage/default/13.prim_present_test.1413962834 |
| /workspace/coverage/default/14.prim_present_test.1232886099 |
| /workspace/coverage/default/15.prim_present_test.107588838 |
| /workspace/coverage/default/16.prim_present_test.2573970983 |
| /workspace/coverage/default/17.prim_present_test.2304271126 |
| /workspace/coverage/default/18.prim_present_test.4264870481 |
| /workspace/coverage/default/19.prim_present_test.3218759941 |
| /workspace/coverage/default/2.prim_present_test.3479311203 |
| /workspace/coverage/default/20.prim_present_test.3986763991 |
| /workspace/coverage/default/21.prim_present_test.4111084937 |
| /workspace/coverage/default/22.prim_present_test.1392801499 |
| /workspace/coverage/default/23.prim_present_test.4274535655 |
| /workspace/coverage/default/24.prim_present_test.3100866353 |
| /workspace/coverage/default/25.prim_present_test.677577280 |
| /workspace/coverage/default/26.prim_present_test.1461450031 |
| /workspace/coverage/default/27.prim_present_test.2225745420 |
| /workspace/coverage/default/28.prim_present_test.1443772246 |
| /workspace/coverage/default/29.prim_present_test.2900197102 |
| /workspace/coverage/default/3.prim_present_test.1027665589 |
| /workspace/coverage/default/30.prim_present_test.1945167210 |
| /workspace/coverage/default/31.prim_present_test.2664339084 |
| /workspace/coverage/default/32.prim_present_test.2476343974 |
| /workspace/coverage/default/33.prim_present_test.1024712111 |
| /workspace/coverage/default/34.prim_present_test.2765879236 |
| /workspace/coverage/default/35.prim_present_test.613460339 |
| /workspace/coverage/default/36.prim_present_test.420065460 |
| /workspace/coverage/default/37.prim_present_test.2762535328 |
| /workspace/coverage/default/38.prim_present_test.4251043390 |
| /workspace/coverage/default/39.prim_present_test.3688593407 |
| /workspace/coverage/default/4.prim_present_test.3966199274 |
| /workspace/coverage/default/40.prim_present_test.3300460606 |
| /workspace/coverage/default/41.prim_present_test.764377745 |
| /workspace/coverage/default/42.prim_present_test.4148369356 |
| /workspace/coverage/default/43.prim_present_test.539758792 |
| /workspace/coverage/default/44.prim_present_test.2904360583 |
| /workspace/coverage/default/45.prim_present_test.402590675 |
| /workspace/coverage/default/46.prim_present_test.4219201548 |
| /workspace/coverage/default/47.prim_present_test.3911308511 |
| /workspace/coverage/default/48.prim_present_test.4259518628 |
| /workspace/coverage/default/49.prim_present_test.2695379461 |
| /workspace/coverage/default/5.prim_present_test.3879193743 |
| /workspace/coverage/default/6.prim_present_test.2110573057 |
| /workspace/coverage/default/7.prim_present_test.509351695 |
| /workspace/coverage/default/8.prim_present_test.50172087 |
| /workspace/coverage/default/9.prim_present_test.371612589 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/32.prim_present_test.2476343974 | May 26 02:41:04 AM PDT 23 | May 26 02:45:16 AM PDT 23 | 4666200000 ps | ||
| T2 | /workspace/coverage/default/23.prim_present_test.4274535655 | May 26 02:40:59 AM PDT 23 | May 26 02:45:07 AM PDT 23 | 4558400000 ps | ||
| T3 | /workspace/coverage/default/22.prim_present_test.1392801499 | May 26 02:41:04 AM PDT 23 | May 26 02:44:13 AM PDT 23 | 3313200000 ps | ||
| T4 | /workspace/coverage/default/38.prim_present_test.4251043390 | May 26 02:40:59 AM PDT 23 | May 26 02:42:06 AM PDT 23 | 1196000000 ps | ||
| T5 | /workspace/coverage/default/31.prim_present_test.2664339084 | May 26 02:40:59 AM PDT 23 | May 26 02:44:20 AM PDT 23 | 3704200000 ps | ||
| T6 | /workspace/coverage/default/42.prim_present_test.4148369356 | May 26 02:41:06 AM PDT 23 | May 26 02:43:56 AM PDT 23 | 3094000000 ps | ||
| T7 | /workspace/coverage/default/20.prim_present_test.3986763991 | May 26 02:40:59 AM PDT 23 | May 26 02:42:54 AM PDT 23 | 2073800000 ps | ||
| T8 | /workspace/coverage/default/12.prim_present_test.1881426 | May 26 02:41:00 AM PDT 23 | May 26 02:43:34 AM PDT 23 | 2833400000 ps | ||
| T9 | /workspace/coverage/default/34.prim_present_test.2765879236 | May 26 02:41:01 AM PDT 23 | May 26 02:43:35 AM PDT 23 | 2899200000 ps | ||
| T10 | /workspace/coverage/default/4.prim_present_test.3966199274 | May 26 02:40:02 AM PDT 23 | May 26 02:43:30 AM PDT 23 | 3788000000 ps | ||
| T11 | /workspace/coverage/default/24.prim_present_test.3100866353 | May 26 02:41:02 AM PDT 23 | May 26 02:43:27 AM PDT 23 | 2620400000 ps | ||
| T12 | /workspace/coverage/default/29.prim_present_test.2900197102 | May 26 02:40:59 AM PDT 23 | May 26 02:45:08 AM PDT 23 | 4560800000 ps | ||
| T13 | /workspace/coverage/default/6.prim_present_test.2110573057 | May 26 02:41:01 AM PDT 23 | May 26 02:42:07 AM PDT 23 | 1225000000 ps | ||
| T14 | /workspace/coverage/default/1.prim_present_test.2496543837 | May 26 02:40:27 AM PDT 23 | May 26 02:44:28 AM PDT 23 | 4217200000 ps | ||
| T15 | /workspace/coverage/default/14.prim_present_test.1232886099 | May 26 02:41:01 AM PDT 23 | May 26 02:44:31 AM PDT 23 | 3968400000 ps | ||
| T16 | /workspace/coverage/default/3.prim_present_test.1027665589 | May 26 02:40:24 AM PDT 23 | May 26 02:43:03 AM PDT 23 | 2811600000 ps | ||
| T17 | /workspace/coverage/default/39.prim_present_test.3688593407 | May 26 02:41:01 AM PDT 23 | May 26 02:42:09 AM PDT 23 | 1215600000 ps | ||
| T18 | /workspace/coverage/default/21.prim_present_test.4111084937 | May 26 02:41:02 AM PDT 23 | May 26 02:42:05 AM PDT 23 | 1162600000 ps | ||
| T19 | /workspace/coverage/default/40.prim_present_test.3300460606 | May 26 02:40:58 AM PDT 23 | May 26 02:44:10 AM PDT 23 | 3660000000 ps | ||
| T20 | /workspace/coverage/default/26.prim_present_test.1461450031 | May 26 02:41:01 AM PDT 23 | May 26 02:45:11 AM PDT 23 | 4408600000 ps | ||
| T21 | /workspace/coverage/default/35.prim_present_test.613460339 | May 26 02:41:00 AM PDT 23 | May 26 02:44:04 AM PDT 23 | 3221600000 ps | ||
| T22 | /workspace/coverage/default/2.prim_present_test.3479311203 | May 26 02:40:26 AM PDT 23 | May 26 02:41:37 AM PDT 23 | 1308400000 ps | ||
| T23 | /workspace/coverage/default/16.prim_present_test.2573970983 | May 26 02:41:01 AM PDT 23 | May 26 02:45:26 AM PDT 23 | 4900200000 ps | ||
| T24 | /workspace/coverage/default/43.prim_present_test.539758792 | May 26 02:41:03 AM PDT 23 | May 26 02:42:38 AM PDT 23 | 1703400000 ps | ||
| T25 | /workspace/coverage/default/33.prim_present_test.1024712111 | May 26 02:41:08 AM PDT 23 | May 26 02:43:24 AM PDT 23 | 2468600000 ps | ||
| T26 | /workspace/coverage/default/27.prim_present_test.2225745420 | May 26 02:41:01 AM PDT 23 | May 26 02:44:51 AM PDT 23 | 4058800000 ps | ||
| T27 | /workspace/coverage/default/47.prim_present_test.3911308511 | May 26 02:41:00 AM PDT 23 | May 26 02:44:23 AM PDT 23 | 3817000000 ps | ||
| T28 | /workspace/coverage/default/0.prim_present_test.96681366 | May 26 02:40:27 AM PDT 23 | May 26 02:43:39 AM PDT 23 | 3370600000 ps | ||
| T29 | /workspace/coverage/default/9.prim_present_test.371612589 | May 26 02:40:54 AM PDT 23 | May 26 02:42:51 AM PDT 23 | 2164000000 ps | ||
| T30 | /workspace/coverage/default/37.prim_present_test.2762535328 | May 26 02:41:00 AM PDT 23 | May 26 02:43:47 AM PDT 23 | 2983800000 ps | ||
| T31 | /workspace/coverage/default/13.prim_present_test.1413962834 | May 26 02:40:59 AM PDT 23 | May 26 02:42:47 AM PDT 23 | 2017200000 ps | ||
| T32 | /workspace/coverage/default/41.prim_present_test.764377745 | May 26 02:41:03 AM PDT 23 | May 26 02:42:53 AM PDT 23 | 2034400000 ps | ||
| T33 | /workspace/coverage/default/7.prim_present_test.509351695 | May 26 02:41:02 AM PDT 23 | May 26 02:45:01 AM PDT 23 | 4315200000 ps | ||
| T34 | /workspace/coverage/default/15.prim_present_test.107588838 | May 26 02:41:09 AM PDT 23 | May 26 02:44:27 AM PDT 23 | 3619000000 ps | ||
| T35 | /workspace/coverage/default/36.prim_present_test.420065460 | May 26 02:40:54 AM PDT 23 | May 26 02:45:14 AM PDT 23 | 4622000000 ps | ||
| T36 | /workspace/coverage/default/8.prim_present_test.50172087 | May 26 02:40:58 AM PDT 23 | May 26 02:43:16 AM PDT 23 | 2569600000 ps | ||
| T37 | /workspace/coverage/default/28.prim_present_test.1443772246 | May 26 02:41:03 AM PDT 23 | May 26 02:44:52 AM PDT 23 | 4166200000 ps | ||
| T38 | /workspace/coverage/default/45.prim_present_test.402590675 | May 26 02:41:00 AM PDT 23 | May 26 02:45:22 AM PDT 23 | 4728600000 ps | ||
| T39 | /workspace/coverage/default/46.prim_present_test.4219201548 | May 26 02:40:59 AM PDT 23 | May 26 02:42:40 AM PDT 23 | 1876600000 ps | ||
| T40 | /workspace/coverage/default/19.prim_present_test.3218759941 | May 26 02:41:00 AM PDT 23 | May 26 02:44:23 AM PDT 23 | 3689600000 ps | ||
| T41 | /workspace/coverage/default/10.prim_present_test.2346889561 | May 26 02:41:01 AM PDT 23 | May 26 02:42:40 AM PDT 23 | 1768200000 ps | ||
| T42 | /workspace/coverage/default/25.prim_present_test.677577280 | May 26 02:40:53 AM PDT 23 | May 26 02:43:50 AM PDT 23 | 3266400000 ps | ||
| T43 | /workspace/coverage/default/44.prim_present_test.2904360583 | May 26 02:40:59 AM PDT 23 | May 26 02:42:48 AM PDT 23 | 2133600000 ps | ||
| T44 | /workspace/coverage/default/11.prim_present_test.3761612235 | May 26 02:41:01 AM PDT 23 | May 26 02:44:22 AM PDT 23 | 3513000000 ps | ||
| T45 | /workspace/coverage/default/5.prim_present_test.3879193743 | May 26 02:40:09 AM PDT 23 | May 26 02:41:49 AM PDT 23 | 1836600000 ps | ||
| T46 | /workspace/coverage/default/17.prim_present_test.2304271126 | May 26 02:41:00 AM PDT 23 | May 26 02:44:03 AM PDT 23 | 3412000000 ps | ||
| T47 | /workspace/coverage/default/30.prim_present_test.1945167210 | May 26 02:40:59 AM PDT 23 | May 26 02:43:55 AM PDT 23 | 3273000000 ps | ||
| T48 | /workspace/coverage/default/48.prim_present_test.4259518628 | May 26 02:40:59 AM PDT 23 | May 26 02:45:20 AM PDT 23 | 4825400000 ps | ||
| T49 | /workspace/coverage/default/18.prim_present_test.4264870481 | May 26 02:41:00 AM PDT 23 | May 26 02:45:04 AM PDT 23 | 4442600000 ps | ||
| T50 | /workspace/coverage/default/49.prim_present_test.2695379461 | May 26 02:41:06 AM PDT 23 | May 26 02:45:15 AM PDT 23 | 4597400000 ps |
| Test location | /workspace/coverage/default/12.prim_present_test.1881426 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 2833400000 ps |
| CPU time | 143.74 seconds |
| Started | May 26 02:41:00 AM PDT 23 |
| Finished | May 26 02:43:34 AM PDT 23 |
| Peak memory | 155792 kb |
| Host | smart-f7c08335-3f13-4875-9183-de052f28badf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1881426 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.1881426 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/0.prim_present_test.96681366 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 3370600000 ps |
| CPU time | 176.51 seconds |
| Started | May 26 02:40:27 AM PDT 23 |
| Finished | May 26 02:43:39 AM PDT 23 |
| Peak memory | 155776 kb |
| Host | smart-5cb30c42-3f7e-482b-ba1a-06d3290483d2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=96681366 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.96681366 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/1.prim_present_test.2496543837 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 4217200000 ps |
| CPU time | 220.99 seconds |
| Started | May 26 02:40:27 AM PDT 23 |
| Finished | May 26 02:44:28 AM PDT 23 |
| Peak memory | 155764 kb |
| Host | smart-62467435-0f0c-4c6b-a0e9-17266144328c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2496543837 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.2496543837 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/10.prim_present_test.2346889561 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 1768200000 ps |
| CPU time | 92.38 seconds |
| Started | May 26 02:41:01 AM PDT 23 |
| Finished | May 26 02:42:40 AM PDT 23 |
| Peak memory | 155732 kb |
| Host | smart-13668d60-3e19-460e-a2b0-4727ae881d54 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2346889561 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.2346889561 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/11.prim_present_test.3761612235 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 3513000000 ps |
| CPU time | 184.92 seconds |
| Started | May 26 02:41:01 AM PDT 23 |
| Finished | May 26 02:44:22 AM PDT 23 |
| Peak memory | 155776 kb |
| Host | smart-f2c31e5e-f26b-472b-afd2-93aba8a1d23b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3761612235 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.3761612235 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.1413962834 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 2017200000 ps |
| CPU time | 100.98 seconds |
| Started | May 26 02:40:59 AM PDT 23 |
| Finished | May 26 02:42:47 AM PDT 23 |
| Peak memory | 155724 kb |
| Host | smart-033d1419-2ee8-4f1a-a247-4de3b3e3a3ed |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1413962834 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.1413962834 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.1232886099 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 3968400000 ps |
| CPU time | 196.14 seconds |
| Started | May 26 02:41:01 AM PDT 23 |
| Finished | May 26 02:44:31 AM PDT 23 |
| Peak memory | 155728 kb |
| Host | smart-c62b15bb-cae7-40b3-8076-b91359011f1b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1232886099 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.1232886099 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.107588838 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 3619000000 ps |
| CPU time | 184.97 seconds |
| Started | May 26 02:41:09 AM PDT 23 |
| Finished | May 26 02:44:27 AM PDT 23 |
| Peak memory | 155772 kb |
| Host | smart-549de571-668d-44f2-ad04-f3acf7e2af90 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=107588838 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.107588838 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.2573970983 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 4900200000 ps |
| CPU time | 245.35 seconds |
| Started | May 26 02:41:01 AM PDT 23 |
| Finished | May 26 02:45:26 AM PDT 23 |
| Peak memory | 155976 kb |
| Host | smart-0f11b5ae-e43c-4417-b0be-d3ea5cc3f6c8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2573970983 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.2573970983 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.2304271126 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 3412000000 ps |
| CPU time | 171.05 seconds |
| Started | May 26 02:41:00 AM PDT 23 |
| Finished | May 26 02:44:03 AM PDT 23 |
| Peak memory | 155924 kb |
| Host | smart-17bc4cba-7b61-46cb-b855-5a33fd061a56 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2304271126 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.2304271126 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.4264870481 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 4442600000 ps |
| CPU time | 228.83 seconds |
| Started | May 26 02:41:00 AM PDT 23 |
| Finished | May 26 02:45:04 AM PDT 23 |
| Peak memory | 155912 kb |
| Host | smart-37efd8b3-9ff8-459e-9a21-299c4890adb3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4264870481 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.4264870481 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.3218759941 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 3689600000 ps |
| CPU time | 189.96 seconds |
| Started | May 26 02:41:00 AM PDT 23 |
| Finished | May 26 02:44:23 AM PDT 23 |
| Peak memory | 155708 kb |
| Host | smart-5a8f3e0f-91d5-4540-8054-3096804a91a0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3218759941 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.3218759941 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.3479311203 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 1308400000 ps |
| CPU time | 66.37 seconds |
| Started | May 26 02:40:26 AM PDT 23 |
| Finished | May 26 02:41:37 AM PDT 23 |
| Peak memory | 155680 kb |
| Host | smart-0bd2e14f-3968-4cc1-b6f9-07330070a829 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3479311203 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.3479311203 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.3986763991 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 2073800000 ps |
| CPU time | 107.97 seconds |
| Started | May 26 02:40:59 AM PDT 23 |
| Finished | May 26 02:42:54 AM PDT 23 |
| Peak memory | 155684 kb |
| Host | smart-d232ba60-fe7f-4ded-bbcf-3a6d693ded73 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3986763991 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.3986763991 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.4111084937 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 1162600000 ps |
| CPU time | 58.62 seconds |
| Started | May 26 02:41:02 AM PDT 23 |
| Finished | May 26 02:42:05 AM PDT 23 |
| Peak memory | 155636 kb |
| Host | smart-44798ae4-c138-4e44-9b15-540b9adcc388 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4111084937 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.4111084937 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.1392801499 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 3313200000 ps |
| CPU time | 173.8 seconds |
| Started | May 26 02:41:04 AM PDT 23 |
| Finished | May 26 02:44:13 AM PDT 23 |
| Peak memory | 155788 kb |
| Host | smart-be75fad3-3d7f-410e-bf95-5a1578ad2386 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1392801499 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.1392801499 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.4274535655 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 4558400000 ps |
| CPU time | 231.38 seconds |
| Started | May 26 02:40:59 AM PDT 23 |
| Finished | May 26 02:45:07 AM PDT 23 |
| Peak memory | 155940 kb |
| Host | smart-2b7e6820-04af-45ec-8056-b5a92bda8c59 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4274535655 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.4274535655 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.3100866353 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 2620400000 ps |
| CPU time | 135.62 seconds |
| Started | May 26 02:41:02 AM PDT 23 |
| Finished | May 26 02:43:27 AM PDT 23 |
| Peak memory | 155708 kb |
| Host | smart-40edb129-2d82-4347-8db9-d7c2aae10a9c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3100866353 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.3100866353 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.677577280 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 3266400000 ps |
| CPU time | 164.7 seconds |
| Started | May 26 02:40:53 AM PDT 23 |
| Finished | May 26 02:43:50 AM PDT 23 |
| Peak memory | 155788 kb |
| Host | smart-d5e796d2-69dd-4f70-b24e-cd4d0614401f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=677577280 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.677577280 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.1461450031 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 4408600000 ps |
| CPU time | 232.74 seconds |
| Started | May 26 02:41:01 AM PDT 23 |
| Finished | May 26 02:45:11 AM PDT 23 |
| Peak memory | 155952 kb |
| Host | smart-b1484969-6bc1-4090-911d-c05de33ea9e2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1461450031 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.1461450031 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.2225745420 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 4058800000 ps |
| CPU time | 213.78 seconds |
| Started | May 26 02:41:01 AM PDT 23 |
| Finished | May 26 02:44:51 AM PDT 23 |
| Peak memory | 155752 kb |
| Host | smart-98f15f89-eba3-4e0e-8d79-8e66987d98ff |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2225745420 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.2225745420 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.1443772246 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 4166200000 ps |
| CPU time | 215.15 seconds |
| Started | May 26 02:41:03 AM PDT 23 |
| Finished | May 26 02:44:52 AM PDT 23 |
| Peak memory | 155752 kb |
| Host | smart-f578b307-a4b8-4ead-a78e-b924acb455b3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1443772246 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.1443772246 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.2900197102 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 4560800000 ps |
| CPU time | 234.37 seconds |
| Started | May 26 02:40:59 AM PDT 23 |
| Finished | May 26 02:45:08 AM PDT 23 |
| Peak memory | 155940 kb |
| Host | smart-55edeaec-d157-4362-99c2-3e59761f8e51 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2900197102 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.2900197102 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.1027665589 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 2811600000 ps |
| CPU time | 147.97 seconds |
| Started | May 26 02:40:24 AM PDT 23 |
| Finished | May 26 02:43:03 AM PDT 23 |
| Peak memory | 155828 kb |
| Host | smart-766f7ca8-79a8-4ef8-8203-d8122a56fa8e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1027665589 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.1027665589 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.1945167210 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 3273000000 ps |
| CPU time | 165.16 seconds |
| Started | May 26 02:40:59 AM PDT 23 |
| Finished | May 26 02:43:55 AM PDT 23 |
| Peak memory | 155880 kb |
| Host | smart-e32d86d4-24c9-4106-b21a-dbe882225ffe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1945167210 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.1945167210 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.2664339084 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 3704200000 ps |
| CPU time | 187.94 seconds |
| Started | May 26 02:40:59 AM PDT 23 |
| Finished | May 26 02:44:20 AM PDT 23 |
| Peak memory | 155820 kb |
| Host | smart-a83d4cdb-79fd-49fe-914d-f1a8258dab3d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2664339084 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.2664339084 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.2476343974 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 4666200000 ps |
| CPU time | 235.86 seconds |
| Started | May 26 02:41:04 AM PDT 23 |
| Finished | May 26 02:45:16 AM PDT 23 |
| Peak memory | 155848 kb |
| Host | smart-57ab539f-a8a8-40d8-863d-75e0fe42fef7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2476343974 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.2476343974 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.1024712111 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 2468600000 ps |
| CPU time | 128.25 seconds |
| Started | May 26 02:41:08 AM PDT 23 |
| Finished | May 26 02:43:24 AM PDT 23 |
| Peak memory | 155788 kb |
| Host | smart-995babc4-62de-435f-9c28-cd35ad41ef41 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1024712111 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.1024712111 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.2765879236 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 2899200000 ps |
| CPU time | 144.31 seconds |
| Started | May 26 02:41:01 AM PDT 23 |
| Finished | May 26 02:43:35 AM PDT 23 |
| Peak memory | 155728 kb |
| Host | smart-d7107c8f-0c04-4d6a-9343-687b543afc6e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2765879236 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.2765879236 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.613460339 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 3221600000 ps |
| CPU time | 171.45 seconds |
| Started | May 26 02:41:00 AM PDT 23 |
| Finished | May 26 02:44:04 AM PDT 23 |
| Peak memory | 155796 kb |
| Host | smart-9cb754ca-5719-4cee-9aa3-84789255a89d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=613460339 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.613460339 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.420065460 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 4622000000 ps |
| CPU time | 241.9 seconds |
| Started | May 26 02:40:54 AM PDT 23 |
| Finished | May 26 02:45:14 AM PDT 23 |
| Peak memory | 155932 kb |
| Host | smart-00948c6c-9249-403d-aa06-6d6b1cfe5122 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=420065460 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.420065460 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.2762535328 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 2983800000 ps |
| CPU time | 155.44 seconds |
| Started | May 26 02:41:00 AM PDT 23 |
| Finished | May 26 02:43:47 AM PDT 23 |
| Peak memory | 155748 kb |
| Host | smart-8b454de4-48ba-40dd-bff0-57578e2a061b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2762535328 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.2762535328 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.4251043390 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 1196000000 ps |
| CPU time | 61.72 seconds |
| Started | May 26 02:40:59 AM PDT 23 |
| Finished | May 26 02:42:06 AM PDT 23 |
| Peak memory | 155712 kb |
| Host | smart-29ff0d1e-651c-46bd-90c6-23b3c22a298c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4251043390 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.4251043390 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.3688593407 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 1215600000 ps |
| CPU time | 63.68 seconds |
| Started | May 26 02:41:01 AM PDT 23 |
| Finished | May 26 02:42:09 AM PDT 23 |
| Peak memory | 155732 kb |
| Host | smart-3ef95ef1-5a47-4697-b58e-6f4385dd20ed |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3688593407 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.3688593407 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.3966199274 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 3788000000 ps |
| CPU time | 195.59 seconds |
| Started | May 26 02:40:02 AM PDT 23 |
| Finished | May 26 02:43:30 AM PDT 23 |
| Peak memory | 155784 kb |
| Host | smart-5be0348f-31f2-4037-89bb-0ba41f9e6bb8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3966199274 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.3966199274 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.3300460606 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 3660000000 ps |
| CPU time | 180.83 seconds |
| Started | May 26 02:40:58 AM PDT 23 |
| Finished | May 26 02:44:10 AM PDT 23 |
| Peak memory | 155780 kb |
| Host | smart-5aacf555-e121-458a-a077-7b5b4b5dd8c2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3300460606 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.3300460606 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.764377745 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 2034400000 ps |
| CPU time | 102.79 seconds |
| Started | May 26 02:41:03 AM PDT 23 |
| Finished | May 26 02:42:53 AM PDT 23 |
| Peak memory | 155720 kb |
| Host | smart-24d7f911-7c6d-42df-b93d-afb731983a04 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=764377745 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.764377745 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.4148369356 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 3094000000 ps |
| CPU time | 158.95 seconds |
| Started | May 26 02:41:06 AM PDT 23 |
| Finished | May 26 02:43:56 AM PDT 23 |
| Peak memory | 155800 kb |
| Host | smart-8355e336-aeb9-494e-9058-b1b411d0b730 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4148369356 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.4148369356 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.539758792 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 1703400000 ps |
| CPU time | 88.22 seconds |
| Started | May 26 02:41:03 AM PDT 23 |
| Finished | May 26 02:42:38 AM PDT 23 |
| Peak memory | 155684 kb |
| Host | smart-326acc5a-6162-40f2-bd9d-4944c5a900a2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=539758792 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.539758792 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.2904360583 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 2133600000 ps |
| CPU time | 102.64 seconds |
| Started | May 26 02:40:59 AM PDT 23 |
| Finished | May 26 02:42:48 AM PDT 23 |
| Peak memory | 155676 kb |
| Host | smart-438397e3-621f-483b-82dc-0872e71cc6b3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2904360583 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.2904360583 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.402590675 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 4728600000 ps |
| CPU time | 240.76 seconds |
| Started | May 26 02:41:00 AM PDT 23 |
| Finished | May 26 02:45:22 AM PDT 23 |
| Peak memory | 155972 kb |
| Host | smart-7718164f-948a-497f-a848-c087ff0adb10 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=402590675 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.402590675 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.4219201548 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 1876600000 ps |
| CPU time | 93.8 seconds |
| Started | May 26 02:40:59 AM PDT 23 |
| Finished | May 26 02:42:40 AM PDT 23 |
| Peak memory | 155688 kb |
| Host | smart-2c5b9e07-fc2c-4c0e-abfb-b4c6ca04ebf2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4219201548 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.4219201548 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.3911308511 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 3817000000 ps |
| CPU time | 190 seconds |
| Started | May 26 02:41:00 AM PDT 23 |
| Finished | May 26 02:44:23 AM PDT 23 |
| Peak memory | 155772 kb |
| Host | smart-b72b3c4b-7a15-449f-9ad4-b8681138cd70 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3911308511 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.3911308511 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.4259518628 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 4825400000 ps |
| CPU time | 244.96 seconds |
| Started | May 26 02:40:59 AM PDT 23 |
| Finished | May 26 02:45:20 AM PDT 23 |
| Peak memory | 155924 kb |
| Host | smart-c166dbb3-bf5c-461a-b02a-d829fe422baf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4259518628 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.4259518628 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.2695379461 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 4597400000 ps |
| CPU time | 230.93 seconds |
| Started | May 26 02:41:06 AM PDT 23 |
| Finished | May 26 02:45:15 AM PDT 23 |
| Peak memory | 155940 kb |
| Host | smart-183ed16a-976d-4854-a2cf-300e6b722b92 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2695379461 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.2695379461 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.3879193743 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 1836600000 ps |
| CPU time | 94.02 seconds |
| Started | May 26 02:40:09 AM PDT 23 |
| Finished | May 26 02:41:49 AM PDT 23 |
| Peak memory | 155652 kb |
| Host | smart-34d513b5-e3c1-49b2-a232-2064a706f790 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3879193743 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.3879193743 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.2110573057 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 1225000000 ps |
| CPU time | 62.07 seconds |
| Started | May 26 02:41:01 AM PDT 23 |
| Finished | May 26 02:42:07 AM PDT 23 |
| Peak memory | 155700 kb |
| Host | smart-cfee6a4a-9a90-4131-9b6c-4b243c9a53c8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2110573057 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.2110573057 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.509351695 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 4315200000 ps |
| CPU time | 223.07 seconds |
| Started | May 26 02:41:02 AM PDT 23 |
| Finished | May 26 02:45:01 AM PDT 23 |
| Peak memory | 155960 kb |
| Host | smart-bef1253f-9174-4381-be8e-7947b818ef6e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=509351695 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.509351695 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.50172087 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 2569600000 ps |
| CPU time | 128.78 seconds |
| Started | May 26 02:40:58 AM PDT 23 |
| Finished | May 26 02:43:16 AM PDT 23 |
| Peak memory | 155824 kb |
| Host | smart-4765150a-7c57-4093-9bc1-5bb799bcaecd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=50172087 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.50172087 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.371612589 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 2164000000 ps |
| CPU time | 108.76 seconds |
| Started | May 26 02:40:54 AM PDT 23 |
| Finished | May 26 02:42:51 AM PDT 23 |
| Peak memory | 155776 kb |
| Host | smart-21b668f3-71aa-43a7-ad78-fe7ac209ea57 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=371612589 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.371612589 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |