| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 75.95 | 79.07 | 51.61 | 97.46 | 51.61 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 75.95 | 75.95 | 79.07 | 79.07 | 51.61 | 51.61 | 97.46 | 97.46 | 51.61 | 51.61 | 100.00 | 100.00 | /workspace/coverage/default/1.prim_present_test.1259459426 | ||
| Name |
|---|
| /workspace/coverage/default/0.prim_present_test.2172331366 |
| /workspace/coverage/default/10.prim_present_test.156035447 |
| /workspace/coverage/default/11.prim_present_test.2275118596 |
| /workspace/coverage/default/12.prim_present_test.2777965885 |
| /workspace/coverage/default/13.prim_present_test.796277040 |
| /workspace/coverage/default/14.prim_present_test.2798626420 |
| /workspace/coverage/default/15.prim_present_test.3995738921 |
| /workspace/coverage/default/16.prim_present_test.4145505535 |
| /workspace/coverage/default/17.prim_present_test.3011858606 |
| /workspace/coverage/default/18.prim_present_test.3576873370 |
| /workspace/coverage/default/19.prim_present_test.431488581 |
| /workspace/coverage/default/2.prim_present_test.582777784 |
| /workspace/coverage/default/20.prim_present_test.1809656016 |
| /workspace/coverage/default/21.prim_present_test.2746963315 |
| /workspace/coverage/default/22.prim_present_test.2407284505 |
| /workspace/coverage/default/23.prim_present_test.1329039268 |
| /workspace/coverage/default/24.prim_present_test.188765719 |
| /workspace/coverage/default/25.prim_present_test.1053401775 |
| /workspace/coverage/default/26.prim_present_test.1762993318 |
| /workspace/coverage/default/27.prim_present_test.1832856657 |
| /workspace/coverage/default/28.prim_present_test.530920227 |
| /workspace/coverage/default/29.prim_present_test.1902775567 |
| /workspace/coverage/default/3.prim_present_test.938907358 |
| /workspace/coverage/default/30.prim_present_test.226834698 |
| /workspace/coverage/default/31.prim_present_test.2610561518 |
| /workspace/coverage/default/32.prim_present_test.970548732 |
| /workspace/coverage/default/33.prim_present_test.3186726028 |
| /workspace/coverage/default/34.prim_present_test.946809372 |
| /workspace/coverage/default/35.prim_present_test.298845429 |
| /workspace/coverage/default/36.prim_present_test.4002715814 |
| /workspace/coverage/default/37.prim_present_test.1405771142 |
| /workspace/coverage/default/38.prim_present_test.1400393926 |
| /workspace/coverage/default/39.prim_present_test.792245488 |
| /workspace/coverage/default/4.prim_present_test.2678838975 |
| /workspace/coverage/default/40.prim_present_test.3565841858 |
| /workspace/coverage/default/41.prim_present_test.2351704531 |
| /workspace/coverage/default/42.prim_present_test.3262871431 |
| /workspace/coverage/default/43.prim_present_test.3929082534 |
| /workspace/coverage/default/44.prim_present_test.3881274817 |
| /workspace/coverage/default/45.prim_present_test.380391056 |
| /workspace/coverage/default/46.prim_present_test.3529847707 |
| /workspace/coverage/default/47.prim_present_test.2202404707 |
| /workspace/coverage/default/48.prim_present_test.797252979 |
| /workspace/coverage/default/49.prim_present_test.2525484639 |
| /workspace/coverage/default/5.prim_present_test.2204229957 |
| /workspace/coverage/default/6.prim_present_test.775356261 |
| /workspace/coverage/default/7.prim_present_test.3895214038 |
| /workspace/coverage/default/8.prim_present_test.2838952820 |
| /workspace/coverage/default/9.prim_present_test.1371227324 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/47.prim_present_test.2202404707 | May 29 01:55:39 AM PDT 23 | May 29 01:57:44 AM PDT 23 | 2341400000 ps | ||
| T2 | /workspace/coverage/default/21.prim_present_test.2746963315 | May 29 01:55:40 AM PDT 23 | May 29 01:59:44 AM PDT 23 | 4385000000 ps | ||
| T3 | /workspace/coverage/default/1.prim_present_test.1259459426 | May 29 01:55:36 AM PDT 23 | May 29 01:58:28 AM PDT 23 | 3096000000 ps | ||
| T4 | /workspace/coverage/default/43.prim_present_test.3929082534 | May 29 01:55:40 AM PDT 23 | May 29 01:57:10 AM PDT 23 | 1622200000 ps | ||
| T5 | /workspace/coverage/default/34.prim_present_test.946809372 | May 29 01:55:56 AM PDT 23 | May 29 01:57:55 AM PDT 23 | 2161600000 ps | ||
| T6 | /workspace/coverage/default/44.prim_present_test.3881274817 | May 29 01:55:40 AM PDT 23 | May 29 01:58:25 AM PDT 23 | 3117800000 ps | ||
| T7 | /workspace/coverage/default/49.prim_present_test.2525484639 | May 29 01:55:41 AM PDT 23 | May 29 01:59:07 AM PDT 23 | 3694800000 ps | ||
| T8 | /workspace/coverage/default/17.prim_present_test.3011858606 | May 29 01:55:43 AM PDT 23 | May 29 01:58:35 AM PDT 23 | 3047600000 ps | ||
| T9 | /workspace/coverage/default/15.prim_present_test.3995738921 | May 29 01:55:37 AM PDT 23 | May 29 01:57:01 AM PDT 23 | 1519600000 ps | ||
| T10 | /workspace/coverage/default/41.prim_present_test.2351704531 | May 29 01:55:44 AM PDT 23 | May 29 01:59:22 AM PDT 23 | 4033000000 ps | ||
| T11 | /workspace/coverage/default/39.prim_present_test.792245488 | May 29 01:55:38 AM PDT 23 | May 29 01:57:13 AM PDT 23 | 1642200000 ps | ||
| T12 | /workspace/coverage/default/38.prim_present_test.1400393926 | May 29 01:55:38 AM PDT 23 | May 29 01:56:38 AM PDT 23 | 1069600000 ps | ||
| T13 | /workspace/coverage/default/16.prim_present_test.4145505535 | May 29 01:55:42 AM PDT 23 | May 29 01:58:27 AM PDT 23 | 2985200000 ps | ||
| T14 | /workspace/coverage/default/5.prim_present_test.2204229957 | May 29 01:55:40 AM PDT 23 | May 29 01:58:35 AM PDT 23 | 3170800000 ps | ||
| T15 | /workspace/coverage/default/32.prim_present_test.970548732 | May 29 01:55:43 AM PDT 23 | May 29 01:57:42 AM PDT 23 | 2170600000 ps | ||
| T16 | /workspace/coverage/default/18.prim_present_test.3576873370 | May 29 01:55:47 AM PDT 23 | May 29 01:57:19 AM PDT 23 | 1607600000 ps | ||
| T17 | /workspace/coverage/default/8.prim_present_test.2838952820 | May 29 01:55:45 AM PDT 23 | May 29 01:58:24 AM PDT 23 | 2921400000 ps | ||
| T18 | /workspace/coverage/default/4.prim_present_test.2678838975 | May 29 01:55:41 AM PDT 23 | May 29 01:59:42 AM PDT 23 | 4277000000 ps | ||
| T19 | /workspace/coverage/default/33.prim_present_test.3186726028 | May 29 01:55:38 AM PDT 23 | May 29 02:00:09 AM PDT 23 | 4910600000 ps | ||
| T20 | /workspace/coverage/default/26.prim_present_test.1762993318 | May 29 01:55:41 AM PDT 23 | May 29 01:57:47 AM PDT 23 | 2338600000 ps | ||
| T21 | /workspace/coverage/default/31.prim_present_test.2610561518 | May 29 01:55:39 AM PDT 23 | May 29 01:59:38 AM PDT 23 | 4282800000 ps | ||
| T22 | /workspace/coverage/default/20.prim_present_test.1809656016 | May 29 01:55:39 AM PDT 23 | May 29 01:59:27 AM PDT 23 | 4152200000 ps | ||
| T23 | /workspace/coverage/default/27.prim_present_test.1832856657 | May 29 01:55:45 AM PDT 23 | May 29 01:57:14 AM PDT 23 | 1619400000 ps | ||
| T24 | /workspace/coverage/default/2.prim_present_test.582777784 | May 29 01:55:42 AM PDT 23 | May 29 01:57:01 AM PDT 23 | 1391400000 ps | ||
| T25 | /workspace/coverage/default/46.prim_present_test.3529847707 | May 29 01:55:57 AM PDT 23 | May 29 01:57:35 AM PDT 23 | 1785000000 ps | ||
| T26 | /workspace/coverage/default/14.prim_present_test.2798626420 | May 29 01:55:42 AM PDT 23 | May 29 01:58:28 AM PDT 23 | 2914400000 ps | ||
| T27 | /workspace/coverage/default/12.prim_present_test.2777965885 | May 29 01:55:44 AM PDT 23 | May 29 01:56:42 AM PDT 23 | 1018000000 ps | ||
| T28 | /workspace/coverage/default/23.prim_present_test.1329039268 | May 29 01:55:37 AM PDT 23 | May 29 01:57:31 AM PDT 23 | 2037400000 ps | ||
| T29 | /workspace/coverage/default/28.prim_present_test.530920227 | May 29 01:55:37 AM PDT 23 | May 29 01:58:01 AM PDT 23 | 2484200000 ps | ||
| T30 | /workspace/coverage/default/24.prim_present_test.188765719 | May 29 01:55:43 AM PDT 23 | May 29 02:00:06 AM PDT 23 | 4760400000 ps | ||
| T31 | /workspace/coverage/default/10.prim_present_test.156035447 | May 29 01:55:37 AM PDT 23 | May 29 01:57:00 AM PDT 23 | 1503200000 ps | ||
| T32 | /workspace/coverage/default/19.prim_present_test.431488581 | May 29 01:55:43 AM PDT 23 | May 29 01:59:20 AM PDT 23 | 3897000000 ps | ||
| T33 | /workspace/coverage/default/40.prim_present_test.3565841858 | May 29 01:55:42 AM PDT 23 | May 29 02:00:15 AM PDT 23 | 4948800000 ps | ||
| T34 | /workspace/coverage/default/9.prim_present_test.1371227324 | May 29 01:55:45 AM PDT 23 | May 29 01:59:24 AM PDT 23 | 3918800000 ps | ||
| T35 | /workspace/coverage/default/30.prim_present_test.226834698 | May 29 01:55:46 AM PDT 23 | May 29 01:56:57 AM PDT 23 | 1218800000 ps | ||
| T36 | /workspace/coverage/default/37.prim_present_test.1405771142 | May 29 01:55:42 AM PDT 23 | May 29 01:58:33 AM PDT 23 | 3010600000 ps | ||
| T37 | /workspace/coverage/default/35.prim_present_test.298845429 | May 29 01:55:38 AM PDT 23 | May 29 02:00:22 AM PDT 23 | 4957600000 ps | ||
| T38 | /workspace/coverage/default/11.prim_present_test.2275118596 | May 29 01:55:51 AM PDT 23 | May 29 02:00:33 AM PDT 23 | 5000200000 ps | ||
| T39 | /workspace/coverage/default/7.prim_present_test.3895214038 | May 29 01:55:39 AM PDT 23 | May 29 01:57:35 AM PDT 23 | 2140600000 ps | ||
| T40 | /workspace/coverage/default/42.prim_present_test.3262871431 | May 29 01:55:39 AM PDT 23 | May 29 01:59:41 AM PDT 23 | 4307200000 ps | ||
| T41 | /workspace/coverage/default/45.prim_present_test.380391056 | May 29 01:55:51 AM PDT 23 | May 29 01:57:27 AM PDT 23 | 1748800000 ps | ||
| T42 | /workspace/coverage/default/25.prim_present_test.1053401775 | May 29 01:55:40 AM PDT 23 | May 29 01:57:51 AM PDT 23 | 2354600000 ps | ||
| T43 | /workspace/coverage/default/0.prim_present_test.2172331366 | May 29 01:55:42 AM PDT 23 | May 29 01:59:31 AM PDT 23 | 4269600000 ps | ||
| T44 | /workspace/coverage/default/6.prim_present_test.775356261 | May 29 01:55:42 AM PDT 23 | May 29 01:58:14 AM PDT 23 | 2698400000 ps | ||
| T45 | /workspace/coverage/default/48.prim_present_test.797252979 | May 29 01:55:37 AM PDT 23 | May 29 01:57:36 AM PDT 23 | 2194200000 ps | ||
| T46 | /workspace/coverage/default/36.prim_present_test.4002715814 | May 29 01:55:42 AM PDT 23 | May 29 01:57:56 AM PDT 23 | 2349400000 ps | ||
| T47 | /workspace/coverage/default/29.prim_present_test.1902775567 | May 29 01:55:38 AM PDT 23 | May 29 01:57:44 AM PDT 23 | 2245600000 ps | ||
| T48 | /workspace/coverage/default/3.prim_present_test.938907358 | May 29 01:55:57 AM PDT 23 | May 29 02:00:07 AM PDT 23 | 4596200000 ps | ||
| T49 | /workspace/coverage/default/13.prim_present_test.796277040 | May 29 01:55:58 AM PDT 23 | May 29 01:57:38 AM PDT 23 | 1836600000 ps | ||
| T50 | /workspace/coverage/default/22.prim_present_test.2407284505 | May 29 01:55:48 AM PDT 23 | May 29 01:59:42 AM PDT 23 | 4372400000 ps |
| Test location | /workspace/coverage/default/1.prim_present_test.1259459426 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 3096000000 ps |
| CPU time | 160.6 seconds |
| Started | May 29 01:55:36 AM PDT 23 |
| Finished | May 29 01:58:28 AM PDT 23 |
| Peak memory | 155760 kb |
| Host | smart-65a24334-74a0-465c-92dd-cea54efddc97 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1259459426 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.1259459426 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/0.prim_present_test.2172331366 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 4269600000 ps |
| CPU time | 214.59 seconds |
| Started | May 29 01:55:42 AM PDT 23 |
| Finished | May 29 01:59:31 AM PDT 23 |
| Peak memory | 155768 kb |
| Host | smart-e80cf1df-7157-42b7-8caa-808a1616a101 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2172331366 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.2172331366 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/10.prim_present_test.156035447 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 1503200000 ps |
| CPU time | 78.48 seconds |
| Started | May 29 01:55:37 AM PDT 23 |
| Finished | May 29 01:57:00 AM PDT 23 |
| Peak memory | 155696 kb |
| Host | smart-1e8fefb2-7818-422b-bd78-cdd90d6e8e51 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=156035447 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.156035447 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/11.prim_present_test.2275118596 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 5000200000 ps |
| CPU time | 260.82 seconds |
| Started | May 29 01:55:51 AM PDT 23 |
| Finished | May 29 02:00:33 AM PDT 23 |
| Peak memory | 155904 kb |
| Host | smart-b1b0e3de-1b6f-43ff-a47b-95bd22f50a83 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2275118596 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.2275118596 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.2777965885 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 1018000000 ps |
| CPU time | 53.92 seconds |
| Started | May 29 01:55:44 AM PDT 23 |
| Finished | May 29 01:56:42 AM PDT 23 |
| Peak memory | 155716 kb |
| Host | smart-6c3a51f5-a15e-4197-b463-dccfd17a644f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2777965885 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.2777965885 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.796277040 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 1836600000 ps |
| CPU time | 94.44 seconds |
| Started | May 29 01:55:58 AM PDT 23 |
| Finished | May 29 01:57:38 AM PDT 23 |
| Peak memory | 155636 kb |
| Host | smart-06c7d2da-d0ce-4ffd-8932-6e44549f4f12 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=796277040 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.796277040 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.2798626420 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 2914400000 ps |
| CPU time | 154.2 seconds |
| Started | May 29 01:55:42 AM PDT 23 |
| Finished | May 29 01:58:28 AM PDT 23 |
| Peak memory | 155740 kb |
| Host | smart-2dd2a31b-74bc-4dc0-b5fc-432c474cf46c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2798626420 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.2798626420 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.3995738921 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 1519600000 ps |
| CPU time | 78.96 seconds |
| Started | May 29 01:55:37 AM PDT 23 |
| Finished | May 29 01:57:01 AM PDT 23 |
| Peak memory | 155640 kb |
| Host | smart-7175eede-321f-4356-b0d6-38ad1d16e5c7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3995738921 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.3995738921 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.4145505535 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 2985200000 ps |
| CPU time | 154.87 seconds |
| Started | May 29 01:55:42 AM PDT 23 |
| Finished | May 29 01:58:27 AM PDT 23 |
| Peak memory | 155772 kb |
| Host | smart-ab18a73a-0398-4c9d-ba17-14bdf8d70b98 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4145505535 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.4145505535 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.3011858606 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 3047600000 ps |
| CPU time | 160.09 seconds |
| Started | May 29 01:55:43 AM PDT 23 |
| Finished | May 29 01:58:35 AM PDT 23 |
| Peak memory | 155764 kb |
| Host | smart-c5744ea4-afe2-4e6b-8b4c-a95f3dc16041 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3011858606 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.3011858606 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.3576873370 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 1607600000 ps |
| CPU time | 85.44 seconds |
| Started | May 29 01:55:47 AM PDT 23 |
| Finished | May 29 01:57:19 AM PDT 23 |
| Peak memory | 155716 kb |
| Host | smart-e52df688-ee22-4d47-97c7-1169f5c953d0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3576873370 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.3576873370 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.431488581 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 3897000000 ps |
| CPU time | 203.21 seconds |
| Started | May 29 01:55:43 AM PDT 23 |
| Finished | May 29 01:59:20 AM PDT 23 |
| Peak memory | 155768 kb |
| Host | smart-38166481-cb85-4934-a727-37689121b80e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=431488581 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.431488581 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.582777784 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 1391400000 ps |
| CPU time | 74.12 seconds |
| Started | May 29 01:55:42 AM PDT 23 |
| Finished | May 29 01:57:01 AM PDT 23 |
| Peak memory | 155672 kb |
| Host | smart-3ef8fe47-5198-4d50-a622-5f4f92bef965 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=582777784 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.582777784 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.1809656016 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 4152200000 ps |
| CPU time | 214.3 seconds |
| Started | May 29 01:55:39 AM PDT 23 |
| Finished | May 29 01:59:27 AM PDT 23 |
| Peak memory | 155776 kb |
| Host | smart-ddd28253-2e54-4dd1-95f2-2f0c2b4a329d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1809656016 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.1809656016 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.2746963315 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 4385000000 ps |
| CPU time | 227.3 seconds |
| Started | May 29 01:55:40 AM PDT 23 |
| Finished | May 29 01:59:44 AM PDT 23 |
| Peak memory | 155880 kb |
| Host | smart-a8de5289-bee1-4527-bf11-bfddfb967fa6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2746963315 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.2746963315 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.2407284505 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 4372400000 ps |
| CPU time | 219.98 seconds |
| Started | May 29 01:55:48 AM PDT 23 |
| Finished | May 29 01:59:42 AM PDT 23 |
| Peak memory | 155836 kb |
| Host | smart-6abd3930-3ab2-47f3-b116-31e2edaa24c3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2407284505 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.2407284505 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.1329039268 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 2037400000 ps |
| CPU time | 106.29 seconds |
| Started | May 29 01:55:37 AM PDT 23 |
| Finished | May 29 01:57:31 AM PDT 23 |
| Peak memory | 155720 kb |
| Host | smart-fbeda799-a162-49a7-a69f-6910110f2da7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1329039268 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.1329039268 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.188765719 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 4760400000 ps |
| CPU time | 246.36 seconds |
| Started | May 29 01:55:43 AM PDT 23 |
| Finished | May 29 02:00:06 AM PDT 23 |
| Peak memory | 155908 kb |
| Host | smart-268384d8-adad-4bab-899e-172045580cd7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=188765719 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.188765719 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.1053401775 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 2354600000 ps |
| CPU time | 122.89 seconds |
| Started | May 29 01:55:40 AM PDT 23 |
| Finished | May 29 01:57:51 AM PDT 23 |
| Peak memory | 155728 kb |
| Host | smart-66716eaf-58f7-4c9c-af9b-e41446d85d97 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1053401775 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.1053401775 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.1762993318 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 2338600000 ps |
| CPU time | 118.33 seconds |
| Started | May 29 01:55:41 AM PDT 23 |
| Finished | May 29 01:57:47 AM PDT 23 |
| Peak memory | 155764 kb |
| Host | smart-75a4b36f-58fb-4124-b7ef-6465fc797ea4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1762993318 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.1762993318 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.1832856657 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 1619400000 ps |
| CPU time | 83.25 seconds |
| Started | May 29 01:55:45 AM PDT 23 |
| Finished | May 29 01:57:14 AM PDT 23 |
| Peak memory | 155672 kb |
| Host | smart-8cf84e3d-fddb-462f-8a0d-3d9862361f6e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1832856657 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.1832856657 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.530920227 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 2484200000 ps |
| CPU time | 132.74 seconds |
| Started | May 29 01:55:37 AM PDT 23 |
| Finished | May 29 01:58:01 AM PDT 23 |
| Peak memory | 155756 kb |
| Host | smart-4ebb247e-55e3-4cc9-9b3c-56becb9eb45f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=530920227 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.530920227 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.1902775567 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 2245600000 ps |
| CPU time | 117.69 seconds |
| Started | May 29 01:55:38 AM PDT 23 |
| Finished | May 29 01:57:44 AM PDT 23 |
| Peak memory | 155676 kb |
| Host | smart-6fbc1fe7-5ac1-4cde-9d0a-31e238c670b7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1902775567 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.1902775567 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.938907358 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 4596200000 ps |
| CPU time | 234.03 seconds |
| Started | May 29 01:55:57 AM PDT 23 |
| Finished | May 29 02:00:07 AM PDT 23 |
| Peak memory | 155832 kb |
| Host | smart-f5597465-8d26-4906-98e1-d76d9d9130e6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=938907358 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.938907358 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.226834698 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 1218800000 ps |
| CPU time | 65.44 seconds |
| Started | May 29 01:55:46 AM PDT 23 |
| Finished | May 29 01:56:57 AM PDT 23 |
| Peak memory | 155664 kb |
| Host | smart-b76f1d78-d9cb-495f-b67b-06b591836569 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=226834698 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.226834698 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.2610561518 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 4282800000 ps |
| CPU time | 221.94 seconds |
| Started | May 29 01:55:39 AM PDT 23 |
| Finished | May 29 01:59:38 AM PDT 23 |
| Peak memory | 155740 kb |
| Host | smart-a8651895-8dbb-47fb-9e23-63285539cf8b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2610561518 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.2610561518 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.970548732 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 2170600000 ps |
| CPU time | 111.57 seconds |
| Started | May 29 01:55:43 AM PDT 23 |
| Finished | May 29 01:57:42 AM PDT 23 |
| Peak memory | 155768 kb |
| Host | smart-cd3590b7-f67f-4206-b29b-e2a9fa4ee2cc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=970548732 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.970548732 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.3186726028 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 4910600000 ps |
| CPU time | 253.66 seconds |
| Started | May 29 01:55:38 AM PDT 23 |
| Finished | May 29 02:00:09 AM PDT 23 |
| Peak memory | 155916 kb |
| Host | smart-e44866ee-1070-4d65-9103-d2d02aadf8ac |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3186726028 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.3186726028 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.946809372 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 2161600000 ps |
| CPU time | 111.38 seconds |
| Started | May 29 01:55:56 AM PDT 23 |
| Finished | May 29 01:57:55 AM PDT 23 |
| Peak memory | 155772 kb |
| Host | smart-c25571fa-a1db-4d7f-83f3-d6f573e25e59 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=946809372 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.946809372 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.298845429 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 4957600000 ps |
| CPU time | 262.53 seconds |
| Started | May 29 01:55:38 AM PDT 23 |
| Finished | May 29 02:00:22 AM PDT 23 |
| Peak memory | 155888 kb |
| Host | smart-e0a02ba4-f3ae-4a3f-8f03-850417816469 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=298845429 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.298845429 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.4002715814 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 2349400000 ps |
| CPU time | 126.14 seconds |
| Started | May 29 01:55:42 AM PDT 23 |
| Finished | May 29 01:57:56 AM PDT 23 |
| Peak memory | 155740 kb |
| Host | smart-52fdfa5e-f83b-4d85-8f4f-4632d88471d5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4002715814 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.4002715814 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.1405771142 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 3010600000 ps |
| CPU time | 160.2 seconds |
| Started | May 29 01:55:42 AM PDT 23 |
| Finished | May 29 01:58:33 AM PDT 23 |
| Peak memory | 155772 kb |
| Host | smart-bfe7c8d1-8223-412d-8356-5ddcf33951fc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1405771142 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.1405771142 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.1400393926 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 1069600000 ps |
| CPU time | 55.3 seconds |
| Started | May 29 01:55:38 AM PDT 23 |
| Finished | May 29 01:56:38 AM PDT 23 |
| Peak memory | 155692 kb |
| Host | smart-ac80d5a4-0eab-4690-9d5a-5e5ef7fdc382 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1400393926 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.1400393926 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.792245488 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 1642200000 ps |
| CPU time | 88.13 seconds |
| Started | May 29 01:55:38 AM PDT 23 |
| Finished | May 29 01:57:13 AM PDT 23 |
| Peak memory | 155672 kb |
| Host | smart-a41e4830-49db-47f3-872b-c7a85440fac0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=792245488 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.792245488 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.2678838975 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 4277000000 ps |
| CPU time | 224.08 seconds |
| Started | May 29 01:55:41 AM PDT 23 |
| Finished | May 29 01:59:42 AM PDT 23 |
| Peak memory | 155756 kb |
| Host | smart-0c95095c-f9b5-45dd-8b1d-89ecebe76f65 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2678838975 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.2678838975 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.3565841858 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 4948800000 ps |
| CPU time | 255.45 seconds |
| Started | May 29 01:55:42 AM PDT 23 |
| Finished | May 29 02:00:15 AM PDT 23 |
| Peak memory | 155912 kb |
| Host | smart-6bdae3fe-d88e-4cc8-80a8-13cf55fd8ae7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3565841858 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.3565841858 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.2351704531 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 4033000000 ps |
| CPU time | 205.16 seconds |
| Started | May 29 01:55:44 AM PDT 23 |
| Finished | May 29 01:59:22 AM PDT 23 |
| Peak memory | 155692 kb |
| Host | smart-9d9e1241-9331-41b4-9d7f-6131e5ca09e1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2351704531 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.2351704531 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.3262871431 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 4307200000 ps |
| CPU time | 225.61 seconds |
| Started | May 29 01:55:39 AM PDT 23 |
| Finished | May 29 01:59:41 AM PDT 23 |
| Peak memory | 155880 kb |
| Host | smart-adb95779-58a6-4cde-8976-d9d8220e571f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3262871431 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.3262871431 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.3929082534 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 1622200000 ps |
| CPU time | 83.77 seconds |
| Started | May 29 01:55:40 AM PDT 23 |
| Finished | May 29 01:57:10 AM PDT 23 |
| Peak memory | 155700 kb |
| Host | smart-240ab10d-35bd-4e0c-92c9-7bb2b52beadc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3929082534 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.3929082534 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.3881274817 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 3117800000 ps |
| CPU time | 155.73 seconds |
| Started | May 29 01:55:40 AM PDT 23 |
| Finished | May 29 01:58:25 AM PDT 23 |
| Peak memory | 155732 kb |
| Host | smart-861e1818-9136-4fba-978a-b846d365483a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3881274817 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.3881274817 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.380391056 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 1748800000 ps |
| CPU time | 89.04 seconds |
| Started | May 29 01:55:51 AM PDT 23 |
| Finished | May 29 01:57:27 AM PDT 23 |
| Peak memory | 155620 kb |
| Host | smart-8f0e085e-fc62-4e82-abdb-5b68ca70683a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=380391056 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.380391056 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.3529847707 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 1785000000 ps |
| CPU time | 91.7 seconds |
| Started | May 29 01:55:57 AM PDT 23 |
| Finished | May 29 01:57:35 AM PDT 23 |
| Peak memory | 155636 kb |
| Host | smart-ff3569b4-5864-481b-9da0-08385c1d2335 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3529847707 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.3529847707 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.2202404707 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 2341400000 ps |
| CPU time | 117.38 seconds |
| Started | May 29 01:55:39 AM PDT 23 |
| Finished | May 29 01:57:44 AM PDT 23 |
| Peak memory | 155728 kb |
| Host | smart-896a30e7-4278-47ad-b465-30d4a88f917c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2202404707 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.2202404707 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.797252979 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 2194200000 ps |
| CPU time | 111.09 seconds |
| Started | May 29 01:55:37 AM PDT 23 |
| Finished | May 29 01:57:36 AM PDT 23 |
| Peak memory | 155768 kb |
| Host | smart-fb94888f-6e3c-4a5f-ae96-34f2f9ee037d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=797252979 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.797252979 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.2525484639 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 3694800000 ps |
| CPU time | 189.59 seconds |
| Started | May 29 01:55:41 AM PDT 23 |
| Finished | May 29 01:59:07 AM PDT 23 |
| Peak memory | 155864 kb |
| Host | smart-cac1b9b6-0dd3-4682-a4b4-aa40059dcd21 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2525484639 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.2525484639 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.2204229957 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 3170800000 ps |
| CPU time | 162.34 seconds |
| Started | May 29 01:55:40 AM PDT 23 |
| Finished | May 29 01:58:35 AM PDT 23 |
| Peak memory | 155728 kb |
| Host | smart-b385a307-0944-4345-a0f5-092538604c01 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2204229957 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.2204229957 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.775356261 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 2698400000 ps |
| CPU time | 143 seconds |
| Started | May 29 01:55:42 AM PDT 23 |
| Finished | May 29 01:58:14 AM PDT 23 |
| Peak memory | 155764 kb |
| Host | smart-8c4b5435-cc2a-44b6-b471-a183a6461f3e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=775356261 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.775356261 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.3895214038 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 2140600000 ps |
| CPU time | 109.05 seconds |
| Started | May 29 01:55:39 AM PDT 23 |
| Finished | May 29 01:57:35 AM PDT 23 |
| Peak memory | 155708 kb |
| Host | smart-c3913c3a-6e65-4c1f-bdf7-491f3e93fc90 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3895214038 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.3895214038 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.2838952820 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 2921400000 ps |
| CPU time | 149.23 seconds |
| Started | May 29 01:55:45 AM PDT 23 |
| Finished | May 29 01:58:24 AM PDT 23 |
| Peak memory | 155748 kb |
| Host | smart-0aab0934-b771-4f90-9723-fac812f4ce73 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2838952820 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.2838952820 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.1371227324 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 3918800000 ps |
| CPU time | 205.78 seconds |
| Started | May 29 01:55:45 AM PDT 23 |
| Finished | May 29 01:59:24 AM PDT 23 |
| Peak memory | 155744 kb |
| Host | smart-021d0d8b-d559-424f-885e-670c618dd42c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1371227324 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.1371227324 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |