| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/0.prim_present_test.111113120567999225621796469697735131353890616676893247981471087288754120870520 | ||
| Name |
|---|
| /workspace/coverage/default/1.prim_present_test.99483666841577157006587576190010432501191485987142687114672681451114822305599 |
| /workspace/coverage/default/10.prim_present_test.99238024266638997445450133361128090915634003761607960264507318863968714717154 |
| /workspace/coverage/default/11.prim_present_test.33392503805247266554882850301094735634413493213690281692299520803138464356511 |
| /workspace/coverage/default/12.prim_present_test.64384122979719878113969787924715127267156773445078494517401365436244121372986 |
| /workspace/coverage/default/13.prim_present_test.384479589886125764486640558075227781567559922174300395067765823559323070538 |
| /workspace/coverage/default/14.prim_present_test.99618820087082819637591522954268926178434744598949289987828514642826636195646 |
| /workspace/coverage/default/15.prim_present_test.8513408794931029253518956915343503848156442501498004433216097454155007879367 |
| /workspace/coverage/default/16.prim_present_test.27510530954381042145327505510752659073343435139611249298124709313680319621348 |
| /workspace/coverage/default/17.prim_present_test.3814015956587722914175240676180584098751625217494565952172802214936605682781 |
| /workspace/coverage/default/18.prim_present_test.90536914562730750536753160524137731558317416599479171103652410236463530517064 |
| /workspace/coverage/default/19.prim_present_test.51024336313127676688164095797296617904434464656133071237989368864680724371761 |
| /workspace/coverage/default/2.prim_present_test.96229657550661172093209916585166757223152737971362382791008227685696996401411 |
| /workspace/coverage/default/20.prim_present_test.69536644194947598445895583451502868295572901643383811264358061825436497237230 |
| /workspace/coverage/default/21.prim_present_test.34871886328789795222035701730391678860311433366106475410466423260644593852836 |
| /workspace/coverage/default/22.prim_present_test.5504858373786102897119442397986911650539228160951481714532930833891300494748 |
| /workspace/coverage/default/23.prim_present_test.18339648536878484926651652889180899263371048504856462037029210689141766830300 |
| /workspace/coverage/default/24.prim_present_test.87007809723373963976456190172112039227074016134779119999682818742405165031156 |
| /workspace/coverage/default/25.prim_present_test.114363778829019649516572684743073436421551009500872900560444179101557069084220 |
| /workspace/coverage/default/26.prim_present_test.50566959098284175554476799781582464643900605313530498708345654255680150849845 |
| /workspace/coverage/default/27.prim_present_test.93064012724412767839190634562821569949809321329159717623896569108743597757764 |
| /workspace/coverage/default/28.prim_present_test.88926761336483159699893352546733610910652784793168789529561877735464704594754 |
| /workspace/coverage/default/29.prim_present_test.85076344122795924537177278912796989590201109117643769443943580804595950061836 |
| /workspace/coverage/default/3.prim_present_test.1663409839822874775906972676028898771399906599120425559639819286487798920987 |
| /workspace/coverage/default/30.prim_present_test.20032774394438201923970360756861096972513930611623677510079434728906725760179 |
| /workspace/coverage/default/31.prim_present_test.84486254996296547997382895796877251752552361312429565783155988445393275579552 |
| /workspace/coverage/default/32.prim_present_test.85457513449417130386630094532213127987890243651797308492554069504886532289515 |
| /workspace/coverage/default/33.prim_present_test.39178209069386804448994539654462943884703621089486654511037168023820490343332 |
| /workspace/coverage/default/34.prim_present_test.64914159285684022692846459672880226088075377351964542807855959227982774441516 |
| /workspace/coverage/default/35.prim_present_test.94731179985964456471440962879880938924407812216213982233140740572202089659635 |
| /workspace/coverage/default/36.prim_present_test.97822235994248400486750213039022282075766959300548933180277487501442003566820 |
| /workspace/coverage/default/37.prim_present_test.34838111514843195727007870029867716058441621335735162701326629889969135398719 |
| /workspace/coverage/default/38.prim_present_test.99724015643991431900371676186680723199382292477975233551951842222385442873362 |
| /workspace/coverage/default/39.prim_present_test.1614614565885697936341954803090932635872910980554892123820316754146048957960 |
| /workspace/coverage/default/4.prim_present_test.113677442156444026846049055771944859380942391430204455926501889135913534598016 |
| /workspace/coverage/default/40.prim_present_test.90404769639644742544180280443144008250556475957605425732504776897807227650379 |
| /workspace/coverage/default/41.prim_present_test.24757770056764601574334551004054884629745655275855527791039516800065266919802 |
| /workspace/coverage/default/42.prim_present_test.66930053854251010598890482354134167733561929431102470547343246588932738466092 |
| /workspace/coverage/default/43.prim_present_test.99516886280691617357177293125173961665297357179608562483613545865332498552499 |
| /workspace/coverage/default/44.prim_present_test.109901048316346498865387040521188282738783594328268082415897031844392456265474 |
| /workspace/coverage/default/45.prim_present_test.99808600986898102584893736942839343959495772828041107537039962326216173643038 |
| /workspace/coverage/default/46.prim_present_test.32449718764371363640177907750794444586475238559150376739568091440717143603816 |
| /workspace/coverage/default/47.prim_present_test.56516009183339821298314153577685998534065122129768445239729735527018814661646 |
| /workspace/coverage/default/48.prim_present_test.109717948904915160880845256322804257735575687281835312002916284904831766507088 |
| /workspace/coverage/default/49.prim_present_test.36049616849895685636071257250668565308552494466458110412871227810706058545804 |
| /workspace/coverage/default/5.prim_present_test.10257759222540995566932476934426584220099409370045183269932756468223088322010 |
| /workspace/coverage/default/6.prim_present_test.4997748220022618797714583977510690974308971673828926250875669070067802204670 |
| /workspace/coverage/default/7.prim_present_test.108693536320029843276560236748237465954734933561193574359155507339201660942671 |
| /workspace/coverage/default/8.prim_present_test.42221994785012735095312872634458329606218202198407485664670339060446483541742 |
| /workspace/coverage/default/9.prim_present_test.12683585628227828980837010313121829152293733685848289783859522923974671601694 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/0.prim_present_test.111113120567999225621796469697735131353890616676893247981471087288754120870520 | Nov 22 12:39:15 PM PST 23 | Nov 22 12:39:37 PM PST 23 | 3410620000 ps | ||
| T2 | /workspace/coverage/default/26.prim_present_test.50566959098284175554476799781582464643900605313530498708345654255680150849845 | Nov 22 12:39:24 PM PST 23 | Nov 22 12:39:54 PM PST 23 | 3410620000 ps | ||
| T3 | /workspace/coverage/default/15.prim_present_test.8513408794931029253518956915343503848156442501498004433216097454155007879367 | Nov 22 12:39:20 PM PST 23 | Nov 22 12:39:41 PM PST 23 | 3410620000 ps | ||
| T4 | /workspace/coverage/default/17.prim_present_test.3814015956587722914175240676180584098751625217494565952172802214936605682781 | Nov 22 12:39:24 PM PST 23 | Nov 22 12:39:51 PM PST 23 | 3410620000 ps | ||
| T5 | /workspace/coverage/default/19.prim_present_test.51024336313127676688164095797296617904434464656133071237989368864680724371761 | Nov 22 12:39:19 PM PST 23 | Nov 22 12:39:48 PM PST 23 | 3410620000 ps | ||
| T6 | /workspace/coverage/default/24.prim_present_test.87007809723373963976456190172112039227074016134779119999682818742405165031156 | Nov 22 12:39:17 PM PST 23 | Nov 22 12:39:43 PM PST 23 | 3410620000 ps | ||
| T7 | /workspace/coverage/default/11.prim_present_test.33392503805247266554882850301094735634413493213690281692299520803138464356511 | Nov 22 12:39:23 PM PST 23 | Nov 22 12:39:52 PM PST 23 | 3410620000 ps | ||
| T8 | /workspace/coverage/default/34.prim_present_test.64914159285684022692846459672880226088075377351964542807855959227982774441516 | Nov 22 12:39:17 PM PST 23 | Nov 22 12:39:45 PM PST 23 | 3410620000 ps | ||
| T9 | /workspace/coverage/default/14.prim_present_test.99618820087082819637591522954268926178434744598949289987828514642826636195646 | Nov 22 12:39:18 PM PST 23 | Nov 22 12:39:46 PM PST 23 | 3410620000 ps | ||
| T10 | /workspace/coverage/default/45.prim_present_test.99808600986898102584893736942839343959495772828041107537039962326216173643038 | Nov 22 12:39:37 PM PST 23 | Nov 22 12:40:03 PM PST 23 | 3410620000 ps | ||
| T11 | /workspace/coverage/default/5.prim_present_test.10257759222540995566932476934426584220099409370045183269932756468223088322010 | Nov 22 12:39:23 PM PST 23 | Nov 22 12:39:48 PM PST 23 | 3410620000 ps | ||
| T12 | /workspace/coverage/default/44.prim_present_test.109901048316346498865387040521188282738783594328268082415897031844392456265474 | Nov 22 12:39:37 PM PST 23 | Nov 22 12:40:03 PM PST 23 | 3410620000 ps | ||
| T13 | /workspace/coverage/default/38.prim_present_test.99724015643991431900371676186680723199382292477975233551951842222385442873362 | Nov 22 12:39:23 PM PST 23 | Nov 22 12:39:49 PM PST 23 | 3410620000 ps | ||
| T14 | /workspace/coverage/default/4.prim_present_test.113677442156444026846049055771944859380942391430204455926501889135913534598016 | Nov 22 12:39:21 PM PST 23 | Nov 22 12:39:43 PM PST 23 | 3410620000 ps | ||
| T15 | /workspace/coverage/default/8.prim_present_test.42221994785012735095312872634458329606218202198407485664670339060446483541742 | Nov 22 12:39:20 PM PST 23 | Nov 22 12:39:47 PM PST 23 | 3410620000 ps | ||
| T16 | /workspace/coverage/default/48.prim_present_test.109717948904915160880845256322804257735575687281835312002916284904831766507088 | Nov 22 12:39:37 PM PST 23 | Nov 22 12:40:04 PM PST 23 | 3410620000 ps | ||
| T17 | /workspace/coverage/default/30.prim_present_test.20032774394438201923970360756861096972513930611623677510079434728906725760179 | Nov 22 12:39:23 PM PST 23 | Nov 22 12:39:48 PM PST 23 | 3410620000 ps | ||
| T18 | /workspace/coverage/default/36.prim_present_test.97822235994248400486750213039022282075766959300548933180277487501442003566820 | Nov 22 12:39:16 PM PST 23 | Nov 22 12:39:41 PM PST 23 | 3410620000 ps | ||
| T19 | /workspace/coverage/default/41.prim_present_test.24757770056764601574334551004054884629745655275855527791039516800065266919802 | Nov 22 12:39:19 PM PST 23 | Nov 22 12:39:42 PM PST 23 | 3410620000 ps | ||
| T20 | /workspace/coverage/default/42.prim_present_test.66930053854251010598890482354134167733561929431102470547343246588932738466092 | Nov 22 12:39:22 PM PST 23 | Nov 22 12:39:46 PM PST 23 | 3410620000 ps | ||
| T21 | /workspace/coverage/default/25.prim_present_test.114363778829019649516572684743073436421551009500872900560444179101557069084220 | Nov 22 12:39:17 PM PST 23 | Nov 22 12:39:41 PM PST 23 | 3410620000 ps | ||
| T22 | /workspace/coverage/default/1.prim_present_test.99483666841577157006587576190010432501191485987142687114672681451114822305599 | Nov 22 12:39:15 PM PST 23 | Nov 22 12:39:36 PM PST 23 | 3410620000 ps | ||
| T23 | /workspace/coverage/default/47.prim_present_test.56516009183339821298314153577685998534065122129768445239729735527018814661646 | Nov 22 12:39:23 PM PST 23 | Nov 22 12:39:46 PM PST 23 | 3410620000 ps | ||
| T24 | /workspace/coverage/default/7.prim_present_test.108693536320029843276560236748237465954734933561193574359155507339201660942671 | Nov 22 12:39:24 PM PST 23 | Nov 22 12:39:52 PM PST 23 | 3410620000 ps | ||
| T25 | /workspace/coverage/default/21.prim_present_test.34871886328789795222035701730391678860311433366106475410466423260644593852836 | Nov 22 12:39:25 PM PST 23 | Nov 22 12:39:54 PM PST 23 | 3410620000 ps | ||
| T26 | /workspace/coverage/default/6.prim_present_test.4997748220022618797714583977510690974308971673828926250875669070067802204670 | Nov 22 12:39:18 PM PST 23 | Nov 22 12:39:40 PM PST 23 | 3410620000 ps | ||
| T27 | /workspace/coverage/default/46.prim_present_test.32449718764371363640177907750794444586475238559150376739568091440717143603816 | Nov 22 12:39:22 PM PST 23 | Nov 22 12:39:46 PM PST 23 | 3410620000 ps | ||
| T28 | /workspace/coverage/default/27.prim_present_test.93064012724412767839190634562821569949809321329159717623896569108743597757764 | Nov 22 12:39:19 PM PST 23 | Nov 22 12:39:46 PM PST 23 | 3410620000 ps | ||
| T29 | /workspace/coverage/default/12.prim_present_test.64384122979719878113969787924715127267156773445078494517401365436244121372986 | Nov 22 12:39:18 PM PST 23 | Nov 22 12:39:44 PM PST 23 | 3410620000 ps | ||
| T30 | /workspace/coverage/default/31.prim_present_test.84486254996296547997382895796877251752552361312429565783155988445393275579552 | Nov 22 12:39:31 PM PST 23 | Nov 22 12:39:59 PM PST 23 | 3410620000 ps | ||
| T31 | /workspace/coverage/default/13.prim_present_test.384479589886125764486640558075227781567559922174300395067765823559323070538 | Nov 22 12:39:24 PM PST 23 | Nov 22 12:39:51 PM PST 23 | 3410620000 ps | ||
| T32 | /workspace/coverage/default/37.prim_present_test.34838111514843195727007870029867716058441621335735162701326629889969135398719 | Nov 22 12:39:25 PM PST 23 | Nov 22 12:39:54 PM PST 23 | 3410620000 ps | ||
| T33 | /workspace/coverage/default/28.prim_present_test.88926761336483159699893352546733610910652784793168789529561877735464704594754 | Nov 22 12:39:23 PM PST 23 | Nov 22 12:39:47 PM PST 23 | 3410620000 ps | ||
| T34 | /workspace/coverage/default/29.prim_present_test.85076344122795924537177278912796989590201109117643769443943580804595950061836 | Nov 22 12:39:20 PM PST 23 | Nov 22 12:39:48 PM PST 23 | 3410620000 ps | ||
| T35 | /workspace/coverage/default/33.prim_present_test.39178209069386804448994539654462943884703621089486654511037168023820490343332 | Nov 22 12:39:31 PM PST 23 | Nov 22 12:39:59 PM PST 23 | 3410620000 ps | ||
| T36 | /workspace/coverage/default/49.prim_present_test.36049616849895685636071257250668565308552494466458110412871227810706058545804 | Nov 22 12:39:22 PM PST 23 | Nov 22 12:39:48 PM PST 23 | 3410620000 ps | ||
| T37 | /workspace/coverage/default/22.prim_present_test.5504858373786102897119442397986911650539228160951481714532930833891300494748 | Nov 22 12:39:18 PM PST 23 | Nov 22 12:39:43 PM PST 23 | 3410620000 ps | ||
| T38 | /workspace/coverage/default/20.prim_present_test.69536644194947598445895583451502868295572901643383811264358061825436497237230 | Nov 22 12:39:39 PM PST 23 | Nov 22 12:40:02 PM PST 23 | 3410620000 ps | ||
| T39 | /workspace/coverage/default/32.prim_present_test.85457513449417130386630094532213127987890243651797308492554069504886532289515 | Nov 22 12:39:29 PM PST 23 | Nov 22 12:39:51 PM PST 23 | 3410620000 ps | ||
| T40 | /workspace/coverage/default/2.prim_present_test.96229657550661172093209916585166757223152737971362382791008227685696996401411 | Nov 22 12:39:16 PM PST 23 | Nov 22 12:39:39 PM PST 23 | 3410620000 ps | ||
| T41 | /workspace/coverage/default/40.prim_present_test.90404769639644742544180280443144008250556475957605425732504776897807227650379 | Nov 22 12:39:37 PM PST 23 | Nov 22 12:40:03 PM PST 23 | 3410620000 ps | ||
| T42 | /workspace/coverage/default/39.prim_present_test.1614614565885697936341954803090932635872910980554892123820316754146048957960 | Nov 22 12:39:24 PM PST 23 | Nov 22 12:39:54 PM PST 23 | 3410620000 ps | ||
| T43 | /workspace/coverage/default/9.prim_present_test.12683585628227828980837010313121829152293733685848289783859522923974671601694 | Nov 22 12:39:18 PM PST 23 | Nov 22 12:39:47 PM PST 23 | 3410620000 ps | ||
| T44 | /workspace/coverage/default/43.prim_present_test.99516886280691617357177293125173961665297357179608562483613545865332498552499 | Nov 22 12:39:32 PM PST 23 | Nov 22 12:39:56 PM PST 23 | 3410620000 ps | ||
| T45 | /workspace/coverage/default/3.prim_present_test.1663409839822874775906972676028898771399906599120425559639819286487798920987 | Nov 22 12:39:22 PM PST 23 | Nov 22 12:39:43 PM PST 23 | 3410620000 ps | ||
| T46 | /workspace/coverage/default/35.prim_present_test.94731179985964456471440962879880938924407812216213982233140740572202089659635 | Nov 22 12:39:24 PM PST 23 | Nov 22 12:39:54 PM PST 23 | 3410620000 ps | ||
| T47 | /workspace/coverage/default/23.prim_present_test.18339648536878484926651652889180899263371048504856462037029210689141766830300 | Nov 22 12:39:18 PM PST 23 | Nov 22 12:39:47 PM PST 23 | 3410620000 ps | ||
| T48 | /workspace/coverage/default/18.prim_present_test.90536914562730750536753160524137731558317416599479171103652410236463530517064 | Nov 22 12:39:14 PM PST 23 | Nov 22 12:39:43 PM PST 23 | 3410620000 ps | ||
| T49 | /workspace/coverage/default/10.prim_present_test.99238024266638997445450133361128090915634003761607960264507318863968714717154 | Nov 22 12:39:24 PM PST 23 | Nov 22 12:39:47 PM PST 23 | 3410620000 ps | ||
| T50 | /workspace/coverage/default/16.prim_present_test.27510530954381042145327505510752659073343435139611249298124709313680319621348 | Nov 22 12:39:24 PM PST 23 | Nov 22 12:39:45 PM PST 23 | 3410620000 ps |
| Test location | /workspace/coverage/default/0.prim_present_test.111113120567999225621796469697735131353890616676893247981471087288754120870520 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 3410620000 ps |
| CPU time | 10.67 seconds |
| Started | Nov 22 12:39:15 PM PST 23 |
| Finished | Nov 22 12:39:37 PM PST 23 |
| Peak memory | 144596 kb |
| Host | smart-ce1fb0c7-3ea9-41cb-b486-0aeed99cc0f4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=111113120567999225621796469697735131353890616676893247981471087288754120870520 -assert nopostproc +UVM_TESTNAME= +UVM_TE ST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.11111 3120567999225621796469697735131353890616676893247981471087288754120870520 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/1.prim_present_test.99483666841577157006587576190010432501191485987142687114672681451114822305599 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 3410620000 ps |
| CPU time | 10.59 seconds |
| Started | Nov 22 12:39:15 PM PST 23 |
| Finished | Nov 22 12:39:36 PM PST 23 |
| Peak memory | 144676 kb |
| Host | smart-9fce4732-a67c-4f9b-a7b0-662ad248bc4e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=99483666841577157006587576190010432501191485987142687114672681451114822305599 -assert nopostproc +UVM_TESTNAME= +UVM_TES T_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.994836 66841577157006587576190010432501191485987142687114672681451114822305599 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/10.prim_present_test.99238024266638997445450133361128090915634003761607960264507318863968714717154 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 3410620000 ps |
| CPU time | 11.28 seconds |
| Started | Nov 22 12:39:24 PM PST 23 |
| Finished | Nov 22 12:39:47 PM PST 23 |
| Peak memory | 144672 kb |
| Host | smart-990c4786-3463-4eb7-97f6-8d94ca134030 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=99238024266638997445450133361128090915634003761607960264507318863968714717154 -assert nopostproc +UVM_TESTNAME= +UVM_TES T_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.99238 024266638997445450133361128090915634003761607960264507318863968714717154 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/11.prim_present_test.33392503805247266554882850301094735634413493213690281692299520803138464356511 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 3410620000 ps |
| CPU time | 14.24 seconds |
| Started | Nov 22 12:39:23 PM PST 23 |
| Finished | Nov 22 12:39:52 PM PST 23 |
| Peak memory | 144604 kb |
| Host | smart-598331d0-8cb3-4a64-9f12-8b43e9a92a04 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=33392503805247266554882850301094735634413493213690281692299520803138464356511 -assert nopostproc +UVM_TESTNAME= +UVM_TES T_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.33392 503805247266554882850301094735634413493213690281692299520803138464356511 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.64384122979719878113969787924715127267156773445078494517401365436244121372986 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 3410620000 ps |
| CPU time | 12.38 seconds |
| Started | Nov 22 12:39:18 PM PST 23 |
| Finished | Nov 22 12:39:44 PM PST 23 |
| Peak memory | 144632 kb |
| Host | smart-9b0c1d0a-02c0-44c7-be44-767b23651b7b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=64384122979719878113969787924715127267156773445078494517401365436244121372986 -assert nopostproc +UVM_TESTNAME= +UVM_TES T_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.64384 122979719878113969787924715127267156773445078494517401365436244121372986 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.384479589886125764486640558075227781567559922174300395067765823559323070538 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 3410620000 ps |
| CPU time | 13.25 seconds |
| Started | Nov 22 12:39:24 PM PST 23 |
| Finished | Nov 22 12:39:51 PM PST 23 |
| Peak memory | 144616 kb |
| Host | smart-de00c92c-5407-4779-9139-f363eb10db37 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=384479589886125764486640558075227781567559922174300395067765823559323070538 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_ SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.3844795 89886125764486640558075227781567559922174300395067765823559323070538 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.99618820087082819637591522954268926178434744598949289987828514642826636195646 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 3410620000 ps |
| CPU time | 14.02 seconds |
| Started | Nov 22 12:39:18 PM PST 23 |
| Finished | Nov 22 12:39:46 PM PST 23 |
| Peak memory | 144564 kb |
| Host | smart-01413c09-1d75-4505-ba86-db9224f9151f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=99618820087082819637591522954268926178434744598949289987828514642826636195646 -assert nopostproc +UVM_TESTNAME= +UVM_TES T_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.99618 820087082819637591522954268926178434744598949289987828514642826636195646 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.8513408794931029253518956915343503848156442501498004433216097454155007879367 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 3410620000 ps |
| CPU time | 10.18 seconds |
| Started | Nov 22 12:39:20 PM PST 23 |
| Finished | Nov 22 12:39:41 PM PST 23 |
| Peak memory | 144528 kb |
| Host | smart-efc707d3-0231-4e66-90df-61228bc3cf0a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=8513408794931029253518956915343503848156442501498004433216097454155007879367 -assert nopostproc +UVM_TESTNAME= +UVM_TEST _SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.851340 8794931029253518956915343503848156442501498004433216097454155007879367 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.27510530954381042145327505510752659073343435139611249298124709313680319621348 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 3410620000 ps |
| CPU time | 10.43 seconds |
| Started | Nov 22 12:39:24 PM PST 23 |
| Finished | Nov 22 12:39:45 PM PST 23 |
| Peak memory | 144580 kb |
| Host | smart-129628bb-36e1-4edc-b254-b9bcc71ef400 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=27510530954381042145327505510752659073343435139611249298124709313680319621348 -assert nopostproc +UVM_TESTNAME= +UVM_TES T_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.27510 530954381042145327505510752659073343435139611249298124709313680319621348 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.3814015956587722914175240676180584098751625217494565952172802214936605682781 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 3410620000 ps |
| CPU time | 13.42 seconds |
| Started | Nov 22 12:39:24 PM PST 23 |
| Finished | Nov 22 12:39:51 PM PST 23 |
| Peak memory | 144516 kb |
| Host | smart-e3f9d29f-991c-4e94-bb02-2809f3379405 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3814015956587722914175240676180584098751625217494565952172802214936605682781 -assert nopostproc +UVM_TESTNAME= +UVM_TEST _SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.381401 5956587722914175240676180584098751625217494565952172802214936605682781 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.90536914562730750536753160524137731558317416599479171103652410236463530517064 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 3410620000 ps |
| CPU time | 15.05 seconds |
| Started | Nov 22 12:39:14 PM PST 23 |
| Finished | Nov 22 12:39:43 PM PST 23 |
| Peak memory | 144696 kb |
| Host | smart-cf403bf1-6d23-46d7-abdd-e6410f229961 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=90536914562730750536753160524137731558317416599479171103652410236463530517064 -assert nopostproc +UVM_TESTNAME= +UVM_TES T_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.90536 914562730750536753160524137731558317416599479171103652410236463530517064 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.51024336313127676688164095797296617904434464656133071237989368864680724371761 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 3410620000 ps |
| CPU time | 13.79 seconds |
| Started | Nov 22 12:39:19 PM PST 23 |
| Finished | Nov 22 12:39:48 PM PST 23 |
| Peak memory | 144620 kb |
| Host | smart-0cda6296-a751-476f-b87e-57786a94482d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=51024336313127676688164095797296617904434464656133071237989368864680724371761 -assert nopostproc +UVM_TESTNAME= +UVM_TES T_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.51024 336313127676688164095797296617904434464656133071237989368864680724371761 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.96229657550661172093209916585166757223152737971362382791008227685696996401411 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 3410620000 ps |
| CPU time | 11.1 seconds |
| Started | Nov 22 12:39:16 PM PST 23 |
| Finished | Nov 22 12:39:39 PM PST 23 |
| Peak memory | 144604 kb |
| Host | smart-58cae69e-bbe4-4ae9-9242-73f5f8808924 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=96229657550661172093209916585166757223152737971362382791008227685696996401411 -assert nopostproc +UVM_TESTNAME= +UVM_TES T_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.962296 57550661172093209916585166757223152737971362382791008227685696996401411 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.69536644194947598445895583451502868295572901643383811264358061825436497237230 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 3410620000 ps |
| CPU time | 10.53 seconds |
| Started | Nov 22 12:39:39 PM PST 23 |
| Finished | Nov 22 12:40:02 PM PST 23 |
| Peak memory | 144640 kb |
| Host | smart-69b9584c-bbda-4fd6-911a-8923cc950388 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=69536644194947598445895583451502868295572901643383811264358061825436497237230 -assert nopostproc +UVM_TESTNAME= +UVM_TES T_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.69536 644194947598445895583451502868295572901643383811264358061825436497237230 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.34871886328789795222035701730391678860311433366106475410466423260644593852836 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 3410620000 ps |
| CPU time | 14.32 seconds |
| Started | Nov 22 12:39:25 PM PST 23 |
| Finished | Nov 22 12:39:54 PM PST 23 |
| Peak memory | 144588 kb |
| Host | smart-af25a06e-438c-4123-b44f-37a15056e83e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=34871886328789795222035701730391678860311433366106475410466423260644593852836 -assert nopostproc +UVM_TESTNAME= +UVM_TES T_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.34871 886328789795222035701730391678860311433366106475410466423260644593852836 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.5504858373786102897119442397986911650539228160951481714532930833891300494748 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 3410620000 ps |
| CPU time | 12.3 seconds |
| Started | Nov 22 12:39:18 PM PST 23 |
| Finished | Nov 22 12:39:43 PM PST 23 |
| Peak memory | 144660 kb |
| Host | smart-9ee4e9a2-6132-46cb-9bf0-9e86cad1df74 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=5504858373786102897119442397986911650539228160951481714532930833891300494748 -assert nopostproc +UVM_TESTNAME= +UVM_TEST _SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.550485 8373786102897119442397986911650539228160951481714532930833891300494748 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.18339648536878484926651652889180899263371048504856462037029210689141766830300 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 3410620000 ps |
| CPU time | 13.65 seconds |
| Started | Nov 22 12:39:18 PM PST 23 |
| Finished | Nov 22 12:39:47 PM PST 23 |
| Peak memory | 144620 kb |
| Host | smart-4c3b996b-1647-4837-8c82-d1b1a334dd30 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=18339648536878484926651652889180899263371048504856462037029210689141766830300 -assert nopostproc +UVM_TESTNAME= +UVM_TES T_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.18339 648536878484926651652889180899263371048504856462037029210689141766830300 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.87007809723373963976456190172112039227074016134779119999682818742405165031156 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 3410620000 ps |
| CPU time | 12.2 seconds |
| Started | Nov 22 12:39:17 PM PST 23 |
| Finished | Nov 22 12:39:43 PM PST 23 |
| Peak memory | 144488 kb |
| Host | smart-06ecdfee-dd7d-4585-b7c7-fe720344ec1d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=87007809723373963976456190172112039227074016134779119999682818742405165031156 -assert nopostproc +UVM_TESTNAME= +UVM_TES T_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.87007 809723373963976456190172112039227074016134779119999682818742405165031156 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.114363778829019649516572684743073436421551009500872900560444179101557069084220 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 3410620000 ps |
| CPU time | 11.48 seconds |
| Started | Nov 22 12:39:17 PM PST 23 |
| Finished | Nov 22 12:39:41 PM PST 23 |
| Peak memory | 144664 kb |
| Host | smart-3954f477-9726-4103-9c99-bf31b6e26826 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=114363778829019649516572684743073436421551009500872900560444179101557069084220 -assert nopostproc +UVM_TESTNAME= +UVM_TE ST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.1143 63778829019649516572684743073436421551009500872900560444179101557069084220 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.50566959098284175554476799781582464643900605313530498708345654255680150849845 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 3410620000 ps |
| CPU time | 14.71 seconds |
| Started | Nov 22 12:39:24 PM PST 23 |
| Finished | Nov 22 12:39:54 PM PST 23 |
| Peak memory | 144588 kb |
| Host | smart-2899c215-6d49-4bc5-8040-dbe1a3bbdc41 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=50566959098284175554476799781582464643900605313530498708345654255680150849845 -assert nopostproc +UVM_TESTNAME= +UVM_TES T_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.50566 959098284175554476799781582464643900605313530498708345654255680150849845 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.93064012724412767839190634562821569949809321329159717623896569108743597757764 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 3410620000 ps |
| CPU time | 12.95 seconds |
| Started | Nov 22 12:39:19 PM PST 23 |
| Finished | Nov 22 12:39:46 PM PST 23 |
| Peak memory | 144632 kb |
| Host | smart-70ee5022-74d3-4bac-98f8-5a77f8c8454f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=93064012724412767839190634562821569949809321329159717623896569108743597757764 -assert nopostproc +UVM_TESTNAME= +UVM_TES T_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.93064 012724412767839190634562821569949809321329159717623896569108743597757764 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.88926761336483159699893352546733610910652784793168789529561877735464704594754 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 3410620000 ps |
| CPU time | 12.17 seconds |
| Started | Nov 22 12:39:23 PM PST 23 |
| Finished | Nov 22 12:39:47 PM PST 23 |
| Peak memory | 144640 kb |
| Host | smart-b79bb1d1-42a2-4d54-9094-5aadc39b265e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=88926761336483159699893352546733610910652784793168789529561877735464704594754 -assert nopostproc +UVM_TESTNAME= +UVM_TES T_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.88926 761336483159699893352546733610910652784793168789529561877735464704594754 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.85076344122795924537177278912796989590201109117643769443943580804595950061836 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 3410620000 ps |
| CPU time | 13.65 seconds |
| Started | Nov 22 12:39:20 PM PST 23 |
| Finished | Nov 22 12:39:48 PM PST 23 |
| Peak memory | 144564 kb |
| Host | smart-6df49156-30c3-4299-b41e-c4e66ceaaac7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=85076344122795924537177278912796989590201109117643769443943580804595950061836 -assert nopostproc +UVM_TESTNAME= +UVM_TES T_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.85076 344122795924537177278912796989590201109117643769443943580804595950061836 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.1663409839822874775906972676028898771399906599120425559639819286487798920987 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 3410620000 ps |
| CPU time | 10.28 seconds |
| Started | Nov 22 12:39:22 PM PST 23 |
| Finished | Nov 22 12:39:43 PM PST 23 |
| Peak memory | 144528 kb |
| Host | smart-f676f2e3-6593-43ab-8f1d-f35d0012bfbf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1663409839822874775906972676028898771399906599120425559639819286487798920987 -assert nopostproc +UVM_TESTNAME= +UVM_TEST _SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.1663409 839822874775906972676028898771399906599120425559639819286487798920987 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.20032774394438201923970360756861096972513930611623677510079434728906725760179 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 3410620000 ps |
| CPU time | 12.56 seconds |
| Started | Nov 22 12:39:23 PM PST 23 |
| Finished | Nov 22 12:39:48 PM PST 23 |
| Peak memory | 144608 kb |
| Host | smart-15fa8ddb-4103-450f-863b-d5f5105e4b10 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=20032774394438201923970360756861096972513930611623677510079434728906725760179 -assert nopostproc +UVM_TESTNAME= +UVM_TES T_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.20032 774394438201923970360756861096972513930611623677510079434728906725760179 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.84486254996296547997382895796877251752552361312429565783155988445393275579552 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 3410620000 ps |
| CPU time | 13.64 seconds |
| Started | Nov 22 12:39:31 PM PST 23 |
| Finished | Nov 22 12:39:59 PM PST 23 |
| Peak memory | 144216 kb |
| Host | smart-d6a1a401-9794-40e6-a448-e0482d175e42 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=84486254996296547997382895796877251752552361312429565783155988445393275579552 -assert nopostproc +UVM_TESTNAME= +UVM_TES T_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.84486 254996296547997382895796877251752552361312429565783155988445393275579552 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.85457513449417130386630094532213127987890243651797308492554069504886532289515 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 3410620000 ps |
| CPU time | 10.68 seconds |
| Started | Nov 22 12:39:29 PM PST 23 |
| Finished | Nov 22 12:39:51 PM PST 23 |
| Peak memory | 144624 kb |
| Host | smart-499325d6-3338-47e6-9658-4daac0e835e2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=85457513449417130386630094532213127987890243651797308492554069504886532289515 -assert nopostproc +UVM_TESTNAME= +UVM_TES T_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.85457 513449417130386630094532213127987890243651797308492554069504886532289515 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.39178209069386804448994539654462943884703621089486654511037168023820490343332 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 3410620000 ps |
| CPU time | 13.29 seconds |
| Started | Nov 22 12:39:31 PM PST 23 |
| Finished | Nov 22 12:39:59 PM PST 23 |
| Peak memory | 144192 kb |
| Host | smart-0fa46ce2-d33c-471b-814f-e7a6d193fee9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=39178209069386804448994539654462943884703621089486654511037168023820490343332 -assert nopostproc +UVM_TESTNAME= +UVM_TES T_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.39178 209069386804448994539654462943884703621089486654511037168023820490343332 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.64914159285684022692846459672880226088075377351964542807855959227982774441516 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 3410620000 ps |
| CPU time | 13.14 seconds |
| Started | Nov 22 12:39:17 PM PST 23 |
| Finished | Nov 22 12:39:45 PM PST 23 |
| Peak memory | 144564 kb |
| Host | smart-723aa801-be52-4b6d-8600-123dc1052890 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=64914159285684022692846459672880226088075377351964542807855959227982774441516 -assert nopostproc +UVM_TESTNAME= +UVM_TES T_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.64914 159285684022692846459672880226088075377351964542807855959227982774441516 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.94731179985964456471440962879880938924407812216213982233140740572202089659635 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 3410620000 ps |
| CPU time | 14.89 seconds |
| Started | Nov 22 12:39:24 PM PST 23 |
| Finished | Nov 22 12:39:54 PM PST 23 |
| Peak memory | 144588 kb |
| Host | smart-34558c76-cc40-4d39-9086-19249a5181f9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=94731179985964456471440962879880938924407812216213982233140740572202089659635 -assert nopostproc +UVM_TESTNAME= +UVM_TES T_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.94731 179985964456471440962879880938924407812216213982233140740572202089659635 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.97822235994248400486750213039022282075766959300548933180277487501442003566820 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 3410620000 ps |
| CPU time | 11.44 seconds |
| Started | Nov 22 12:39:16 PM PST 23 |
| Finished | Nov 22 12:39:41 PM PST 23 |
| Peak memory | 144660 kb |
| Host | smart-0e88a402-f00d-426b-af16-b54f77980fb0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=97822235994248400486750213039022282075766959300548933180277487501442003566820 -assert nopostproc +UVM_TESTNAME= +UVM_TES T_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.97822 235994248400486750213039022282075766959300548933180277487501442003566820 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.34838111514843195727007870029867716058441621335735162701326629889969135398719 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 3410620000 ps |
| CPU time | 14.82 seconds |
| Started | Nov 22 12:39:25 PM PST 23 |
| Finished | Nov 22 12:39:54 PM PST 23 |
| Peak memory | 144588 kb |
| Host | smart-009051b2-d69c-4563-bbfd-11f8bfd4ac47 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=34838111514843195727007870029867716058441621335735162701326629889969135398719 -assert nopostproc +UVM_TESTNAME= +UVM_TES T_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.34838 111514843195727007870029867716058441621335735162701326629889969135398719 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.99724015643991431900371676186680723199382292477975233551951842222385442873362 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 3410620000 ps |
| CPU time | 12.52 seconds |
| Started | Nov 22 12:39:23 PM PST 23 |
| Finished | Nov 22 12:39:49 PM PST 23 |
| Peak memory | 144608 kb |
| Host | smart-af70af29-cd0d-4533-b02f-f64d475e4676 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=99724015643991431900371676186680723199382292477975233551951842222385442873362 -assert nopostproc +UVM_TESTNAME= +UVM_TES T_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.99724 015643991431900371676186680723199382292477975233551951842222385442873362 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.1614614565885697936341954803090932635872910980554892123820316754146048957960 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 3410620000 ps |
| CPU time | 15.04 seconds |
| Started | Nov 22 12:39:24 PM PST 23 |
| Finished | Nov 22 12:39:54 PM PST 23 |
| Peak memory | 144588 kb |
| Host | smart-2796c692-5292-4772-ad59-7c85c316ef30 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1614614565885697936341954803090932635872910980554892123820316754146048957960 -assert nopostproc +UVM_TESTNAME= +UVM_TEST _SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.161461 4565885697936341954803090932635872910980554892123820316754146048957960 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.113677442156444026846049055771944859380942391430204455926501889135913534598016 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 3410620000 ps |
| CPU time | 10.7 seconds |
| Started | Nov 22 12:39:21 PM PST 23 |
| Finished | Nov 22 12:39:43 PM PST 23 |
| Peak memory | 144664 kb |
| Host | smart-c701f8f5-b44d-4038-bc98-4e828f64daf1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=113677442156444026846049055771944859380942391430204455926501889135913534598016 -assert nopostproc +UVM_TESTNAME= +UVM_TE ST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.11367 7442156444026846049055771944859380942391430204455926501889135913534598016 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.90404769639644742544180280443144008250556475957605425732504776897807227650379 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 3410620000 ps |
| CPU time | 12.05 seconds |
| Started | Nov 22 12:39:37 PM PST 23 |
| Finished | Nov 22 12:40:03 PM PST 23 |
| Peak memory | 144528 kb |
| Host | smart-6c612c6c-ba8b-44b3-b4f2-7347481e738c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=90404769639644742544180280443144008250556475957605425732504776897807227650379 -assert nopostproc +UVM_TESTNAME= +UVM_TES T_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.90404 769639644742544180280443144008250556475957605425732504776897807227650379 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.24757770056764601574334551004054884629745655275855527791039516800065266919802 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 3410620000 ps |
| CPU time | 11.28 seconds |
| Started | Nov 22 12:39:19 PM PST 23 |
| Finished | Nov 22 12:39:42 PM PST 23 |
| Peak memory | 144580 kb |
| Host | smart-e825e9a2-9f7e-4c16-8f11-9b08ec0da199 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=24757770056764601574334551004054884629745655275855527791039516800065266919802 -assert nopostproc +UVM_TESTNAME= +UVM_TES T_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.24757 770056764601574334551004054884629745655275855527791039516800065266919802 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.66930053854251010598890482354134167733561929431102470547343246588932738466092 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 3410620000 ps |
| CPU time | 12.33 seconds |
| Started | Nov 22 12:39:22 PM PST 23 |
| Finished | Nov 22 12:39:46 PM PST 23 |
| Peak memory | 144640 kb |
| Host | smart-d8b8d1b8-f915-415c-9aed-6829c46b2a74 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=66930053854251010598890482354134167733561929431102470547343246588932738466092 -assert nopostproc +UVM_TESTNAME= +UVM_TES T_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.66930 053854251010598890482354134167733561929431102470547343246588932738466092 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.99516886280691617357177293125173961665297357179608562483613545865332498552499 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 3410620000 ps |
| CPU time | 11.65 seconds |
| Started | Nov 22 12:39:32 PM PST 23 |
| Finished | Nov 22 12:39:56 PM PST 23 |
| Peak memory | 144580 kb |
| Host | smart-c210e0ef-c721-4676-b00d-83ec389eb44e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=99516886280691617357177293125173961665297357179608562483613545865332498552499 -assert nopostproc +UVM_TESTNAME= +UVM_TES T_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.99516 886280691617357177293125173961665297357179608562483613545865332498552499 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.109901048316346498865387040521188282738783594328268082415897031844392456265474 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 3410620000 ps |
| CPU time | 12.07 seconds |
| Started | Nov 22 12:39:37 PM PST 23 |
| Finished | Nov 22 12:40:03 PM PST 23 |
| Peak memory | 144520 kb |
| Host | smart-065805a8-37bf-42a5-8bdf-094d0a0ad66d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=109901048316346498865387040521188282738783594328268082415897031844392456265474 -assert nopostproc +UVM_TESTNAME= +UVM_TE ST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.1099 01048316346498865387040521188282738783594328268082415897031844392456265474 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.99808600986898102584893736942839343959495772828041107537039962326216173643038 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 3410620000 ps |
| CPU time | 12.49 seconds |
| Started | Nov 22 12:39:37 PM PST 23 |
| Finished | Nov 22 12:40:03 PM PST 23 |
| Peak memory | 144528 kb |
| Host | smart-05505ecd-d6e3-4a17-9a63-ef16b1c14a53 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=99808600986898102584893736942839343959495772828041107537039962326216173643038 -assert nopostproc +UVM_TESTNAME= +UVM_TES T_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.99808 600986898102584893736942839343959495772828041107537039962326216173643038 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.32449718764371363640177907750794444586475238559150376739568091440717143603816 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 3410620000 ps |
| CPU time | 11.85 seconds |
| Started | Nov 22 12:39:22 PM PST 23 |
| Finished | Nov 22 12:39:46 PM PST 23 |
| Peak memory | 144640 kb |
| Host | smart-8bc1b912-eec3-421b-adb8-9c07a08d5ae9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=32449718764371363640177907750794444586475238559150376739568091440717143603816 -assert nopostproc +UVM_TESTNAME= +UVM_TES T_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.32449 718764371363640177907750794444586475238559150376739568091440717143603816 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.56516009183339821298314153577685998534065122129768445239729735527018814661646 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 3410620000 ps |
| CPU time | 11.45 seconds |
| Started | Nov 22 12:39:23 PM PST 23 |
| Finished | Nov 22 12:39:46 PM PST 23 |
| Peak memory | 144580 kb |
| Host | smart-ddba5c86-cf4b-4f1f-ae75-d3992ea04990 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=56516009183339821298314153577685998534065122129768445239729735527018814661646 -assert nopostproc +UVM_TESTNAME= +UVM_TES T_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.56516 009183339821298314153577685998534065122129768445239729735527018814661646 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.109717948904915160880845256322804257735575687281835312002916284904831766507088 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 3410620000 ps |
| CPU time | 12.65 seconds |
| Started | Nov 22 12:39:37 PM PST 23 |
| Finished | Nov 22 12:40:04 PM PST 23 |
| Peak memory | 144520 kb |
| Host | smart-199fd943-5cd8-4763-be7b-76dc2811be27 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=109717948904915160880845256322804257735575687281835312002916284904831766507088 -assert nopostproc +UVM_TESTNAME= +UVM_TE ST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.1097 17948904915160880845256322804257735575687281835312002916284904831766507088 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.36049616849895685636071257250668565308552494466458110412871227810706058545804 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 3410620000 ps |
| CPU time | 12.97 seconds |
| Started | Nov 22 12:39:22 PM PST 23 |
| Finished | Nov 22 12:39:48 PM PST 23 |
| Peak memory | 144628 kb |
| Host | smart-1bfd465b-9008-453a-9b8e-42a4d8f2bd05 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=36049616849895685636071257250668565308552494466458110412871227810706058545804 -assert nopostproc +UVM_TESTNAME= +UVM_TES T_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.36049 616849895685636071257250668565308552494466458110412871227810706058545804 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.10257759222540995566932476934426584220099409370045183269932756468223088322010 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 3410620000 ps |
| CPU time | 12.47 seconds |
| Started | Nov 22 12:39:23 PM PST 23 |
| Finished | Nov 22 12:39:48 PM PST 23 |
| Peak memory | 144608 kb |
| Host | smart-8e618c5f-0a82-447a-b8f0-f0c769dcfd0c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=10257759222540995566932476934426584220099409370045183269932756468223088322010 -assert nopostproc +UVM_TESTNAME= +UVM_TES T_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.102577 59222540995566932476934426584220099409370045183269932756468223088322010 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.4997748220022618797714583977510690974308971673828926250875669070067802204670 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 3410620000 ps |
| CPU time | 10.57 seconds |
| Started | Nov 22 12:39:18 PM PST 23 |
| Finished | Nov 22 12:39:40 PM PST 23 |
| Peak memory | 144544 kb |
| Host | smart-ad04fdc3-2b83-49c9-a4d9-b005729314aa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4997748220022618797714583977510690974308971673828926250875669070067802204670 -assert nopostproc +UVM_TESTNAME= +UVM_TEST _SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.4997748 220022618797714583977510690974308971673828926250875669070067802204670 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.108693536320029843276560236748237465954734933561193574359155507339201660942671 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 3410620000 ps |
| CPU time | 14.35 seconds |
| Started | Nov 22 12:39:24 PM PST 23 |
| Finished | Nov 22 12:39:52 PM PST 23 |
| Peak memory | 144516 kb |
| Host | smart-e75cac9b-fc2e-4810-96b5-ca1d94d8f806 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=108693536320029843276560236748237465954734933561193574359155507339201660942671 -assert nopostproc +UVM_TESTNAME= +UVM_TE ST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.10869 3536320029843276560236748237465954734933561193574359155507339201660942671 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.42221994785012735095312872634458329606218202198407485664670339060446483541742 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 3410620000 ps |
| CPU time | 13.2 seconds |
| Started | Nov 22 12:39:20 PM PST 23 |
| Finished | Nov 22 12:39:47 PM PST 23 |
| Peak memory | 144636 kb |
| Host | smart-c46f7241-2083-42b8-b362-57c20432b32e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=42221994785012735095312872634458329606218202198407485664670339060446483541742 -assert nopostproc +UVM_TESTNAME= +UVM_TES T_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.422219 94785012735095312872634458329606218202198407485664670339060446483541742 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.12683585628227828980837010313121829152293733685848289783859522923974671601694 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 3410620000 ps |
| CPU time | 13.72 seconds |
| Started | Nov 22 12:39:18 PM PST 23 |
| Finished | Nov 22 12:39:47 PM PST 23 |
| Peak memory | 144620 kb |
| Host | smart-b5cea857-c673-4019-9c63-81c72a34a966 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=12683585628227828980837010313121829152293733685848289783859522923974671601694 -assert nopostproc +UVM_TESTNAME= +UVM_TES T_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.126835 85628227828980837010313121829152293733685848289783859522923974671601694 |
| Directory | /workspace/9.prim_present_test/latest |
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