| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/11.prim_present_test.2118017256 | ||
| Name |
|---|
| /workspace/coverage/default/0.prim_present_test.1629075761 |
| /workspace/coverage/default/1.prim_present_test.2897627006 |
| /workspace/coverage/default/10.prim_present_test.3125708924 |
| /workspace/coverage/default/12.prim_present_test.2809440477 |
| /workspace/coverage/default/13.prim_present_test.869576745 |
| /workspace/coverage/default/14.prim_present_test.1160175593 |
| /workspace/coverage/default/15.prim_present_test.1733555885 |
| /workspace/coverage/default/16.prim_present_test.1894638889 |
| /workspace/coverage/default/17.prim_present_test.3581201942 |
| /workspace/coverage/default/18.prim_present_test.423995763 |
| /workspace/coverage/default/19.prim_present_test.323648742 |
| /workspace/coverage/default/2.prim_present_test.66989064 |
| /workspace/coverage/default/20.prim_present_test.1942652811 |
| /workspace/coverage/default/21.prim_present_test.1352076715 |
| /workspace/coverage/default/22.prim_present_test.1179865327 |
| /workspace/coverage/default/23.prim_present_test.3123016028 |
| /workspace/coverage/default/24.prim_present_test.3330619934 |
| /workspace/coverage/default/25.prim_present_test.3008535581 |
| /workspace/coverage/default/26.prim_present_test.1998389294 |
| /workspace/coverage/default/27.prim_present_test.28188751 |
| /workspace/coverage/default/28.prim_present_test.3607462567 |
| /workspace/coverage/default/29.prim_present_test.2846872844 |
| /workspace/coverage/default/3.prim_present_test.1363398819 |
| /workspace/coverage/default/30.prim_present_test.4046169546 |
| /workspace/coverage/default/31.prim_present_test.4265188231 |
| /workspace/coverage/default/32.prim_present_test.54455398 |
| /workspace/coverage/default/33.prim_present_test.3922715823 |
| /workspace/coverage/default/34.prim_present_test.946605991 |
| /workspace/coverage/default/35.prim_present_test.3488454125 |
| /workspace/coverage/default/36.prim_present_test.3626470173 |
| /workspace/coverage/default/37.prim_present_test.3079968421 |
| /workspace/coverage/default/38.prim_present_test.2574392403 |
| /workspace/coverage/default/39.prim_present_test.537669375 |
| /workspace/coverage/default/4.prim_present_test.1005449154 |
| /workspace/coverage/default/40.prim_present_test.2506785834 |
| /workspace/coverage/default/41.prim_present_test.2597241766 |
| /workspace/coverage/default/42.prim_present_test.3665539828 |
| /workspace/coverage/default/43.prim_present_test.1698202371 |
| /workspace/coverage/default/44.prim_present_test.1280103109 |
| /workspace/coverage/default/45.prim_present_test.4047971422 |
| /workspace/coverage/default/46.prim_present_test.164008935 |
| /workspace/coverage/default/47.prim_present_test.507065908 |
| /workspace/coverage/default/48.prim_present_test.3770744267 |
| /workspace/coverage/default/49.prim_present_test.2201978459 |
| /workspace/coverage/default/5.prim_present_test.1421003893 |
| /workspace/coverage/default/6.prim_present_test.4106835601 |
| /workspace/coverage/default/7.prim_present_test.2336047384 |
| /workspace/coverage/default/8.prim_present_test.1014177591 |
| /workspace/coverage/default/9.prim_present_test.4059333727 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/37.prim_present_test.3079968421 | Dec 20 12:20:41 PM PST 23 | Dec 20 12:22:12 PM PST 23 | 13910940000 ps | ||
| T2 | /workspace/coverage/default/12.prim_present_test.2809440477 | Dec 20 12:19:12 PM PST 23 | Dec 20 12:20:07 PM PST 23 | 8130680000 ps | ||
| T3 | /workspace/coverage/default/4.prim_present_test.1005449154 | Dec 20 12:19:22 PM PST 23 | Dec 20 12:19:58 PM PST 23 | 4588000000 ps | ||
| T4 | /workspace/coverage/default/21.prim_present_test.1352076715 | Dec 20 12:19:27 PM PST 23 | Dec 20 12:19:54 PM PST 23 | 3835940000 ps | ||
| T5 | /workspace/coverage/default/17.prim_present_test.3581201942 | Dec 20 12:19:24 PM PST 23 | Dec 20 12:20:50 PM PST 23 | 15451020000 ps | ||
| T6 | /workspace/coverage/default/20.prim_present_test.1942652811 | Dec 20 12:18:58 PM PST 23 | Dec 20 12:19:31 PM PST 23 | 4497480000 ps | ||
| T7 | /workspace/coverage/default/19.prim_present_test.323648742 | Dec 20 12:20:03 PM PST 23 | Dec 20 12:21:20 PM PST 23 | 11897800000 ps | ||
| T8 | /workspace/coverage/default/26.prim_present_test.1998389294 | Dec 20 12:18:57 PM PST 23 | Dec 20 12:20:20 PM PST 23 | 14328200000 ps | ||
| T9 | /workspace/coverage/default/39.prim_present_test.537669375 | Dec 20 12:20:41 PM PST 23 | Dec 20 12:21:22 PM PST 23 | 5236520000 ps | ||
| T10 | /workspace/coverage/default/11.prim_present_test.2118017256 | Dec 20 12:20:30 PM PST 23 | Dec 20 12:21:16 PM PST 23 | 6527360000 ps | ||
| T11 | /workspace/coverage/default/6.prim_present_test.4106835601 | Dec 20 12:19:19 PM PST 23 | Dec 20 12:20:23 PM PST 23 | 9689980000 ps | ||
| T12 | /workspace/coverage/default/25.prim_present_test.3008535581 | Dec 20 12:20:04 PM PST 23 | Dec 20 12:20:44 PM PST 23 | 7556560000 ps | ||
| T13 | /workspace/coverage/default/32.prim_present_test.54455398 | Dec 20 12:20:05 PM PST 23 | Dec 20 12:21:19 PM PST 23 | 11353440000 ps | ||
| T14 | /workspace/coverage/default/40.prim_present_test.2506785834 | Dec 20 12:20:02 PM PST 23 | Dec 20 12:20:57 PM PST 23 | 9535600000 ps | ||
| T15 | /workspace/coverage/default/42.prim_present_test.3665539828 | Dec 20 12:20:07 PM PST 23 | Dec 20 12:21:22 PM PST 23 | 12230740000 ps | ||
| T16 | /workspace/coverage/default/7.prim_present_test.2336047384 | Dec 20 12:19:21 PM PST 23 | Dec 20 12:20:33 PM PST 23 | 9680680000 ps | ||
| T17 | /workspace/coverage/default/3.prim_present_test.1363398819 | Dec 20 12:19:11 PM PST 23 | Dec 20 12:20:46 PM PST 23 | 14441660000 ps | ||
| T18 | /workspace/coverage/default/0.prim_present_test.1629075761 | Dec 20 12:19:16 PM PST 23 | Dec 20 12:19:54 PM PST 23 | 5532880000 ps | ||
| T19 | /workspace/coverage/default/24.prim_present_test.3330619934 | Dec 20 12:20:10 PM PST 23 | Dec 20 12:21:28 PM PST 23 | 14018200000 ps | ||
| T20 | /workspace/coverage/default/15.prim_present_test.1733555885 | Dec 20 12:19:25 PM PST 23 | Dec 20 12:20:42 PM PST 23 | 12436580000 ps | ||
| T21 | /workspace/coverage/default/46.prim_present_test.164008935 | Dec 20 12:20:15 PM PST 23 | Dec 20 12:20:57 PM PST 23 | 6506900000 ps | ||
| T22 | /workspace/coverage/default/34.prim_present_test.946605991 | Dec 20 12:20:07 PM PST 23 | Dec 20 12:20:45 PM PST 23 | 5852800000 ps | ||
| T23 | /workspace/coverage/default/5.prim_present_test.1421003893 | Dec 20 12:19:15 PM PST 23 | Dec 20 12:19:37 PM PST 23 | 3427360000 ps | ||
| T24 | /workspace/coverage/default/23.prim_present_test.3123016028 | Dec 20 12:20:39 PM PST 23 | Dec 20 12:21:31 PM PST 23 | 7673740000 ps | ||
| T25 | /workspace/coverage/default/2.prim_present_test.66989064 | Dec 20 12:19:22 PM PST 23 | Dec 20 12:20:23 PM PST 23 | 8415260000 ps | ||
| T26 | /workspace/coverage/default/44.prim_present_test.1280103109 | Dec 20 12:20:06 PM PST 23 | Dec 20 12:21:05 PM PST 23 | 9030920000 ps | ||
| T27 | /workspace/coverage/default/38.prim_present_test.2574392403 | Dec 20 12:20:26 PM PST 23 | Dec 20 12:21:35 PM PST 23 | 10152500000 ps | ||
| T28 | /workspace/coverage/default/36.prim_present_test.3626470173 | Dec 20 12:20:11 PM PST 23 | Dec 20 12:20:54 PM PST 23 | 6240300000 ps | ||
| T29 | /workspace/coverage/default/14.prim_present_test.1160175593 | Dec 20 12:19:10 PM PST 23 | Dec 20 12:20:29 PM PST 23 | 13923340000 ps | ||
| T30 | /workspace/coverage/default/43.prim_present_test.1698202371 | Dec 20 12:20:11 PM PST 23 | Dec 20 12:21:23 PM PST 23 | 12320020000 ps | ||
| T31 | /workspace/coverage/default/35.prim_present_test.3488454125 | Dec 20 12:20:07 PM PST 23 | Dec 20 12:20:45 PM PST 23 | 5825520000 ps | ||
| T32 | /workspace/coverage/default/33.prim_present_test.3922715823 | Dec 20 12:20:28 PM PST 23 | Dec 20 12:21:50 PM PST 23 | 12241280000 ps | ||
| T33 | /workspace/coverage/default/9.prim_present_test.4059333727 | Dec 20 12:19:16 PM PST 23 | Dec 20 12:19:41 PM PST 23 | 3663580000 ps | ||
| T34 | /workspace/coverage/default/10.prim_present_test.3125708924 | Dec 20 12:20:08 PM PST 23 | Dec 20 12:21:08 PM PST 23 | 10824580000 ps | ||
| T35 | /workspace/coverage/default/48.prim_present_test.3770744267 | Dec 20 12:20:11 PM PST 23 | Dec 20 12:20:39 PM PST 23 | 4811200000 ps | ||
| T36 | /workspace/coverage/default/27.prim_present_test.28188751 | Dec 20 12:20:10 PM PST 23 | Dec 20 12:20:51 PM PST 23 | 5978040000 ps | ||
| T37 | /workspace/coverage/default/13.prim_present_test.869576745 | Dec 20 12:19:24 PM PST 23 | Dec 20 12:20:53 PM PST 23 | 15165200000 ps | ||
| T38 | /workspace/coverage/default/28.prim_present_test.3607462567 | Dec 20 12:20:05 PM PST 23 | Dec 20 12:20:49 PM PST 23 | 6717080000 ps | ||
| T39 | /workspace/coverage/default/22.prim_present_test.1179865327 | Dec 20 12:20:32 PM PST 23 | Dec 20 12:21:50 PM PST 23 | 14341840000 ps | ||
| T40 | /workspace/coverage/default/18.prim_present_test.423995763 | Dec 20 12:20:03 PM PST 23 | Dec 20 12:21:19 PM PST 23 | 11559900000 ps | ||
| T41 | /workspace/coverage/default/49.prim_present_test.2201978459 | Dec 20 12:20:11 PM PST 23 | Dec 20 12:21:26 PM PST 23 | 14439800000 ps | ||
| T42 | /workspace/coverage/default/45.prim_present_test.4047971422 | Dec 20 12:20:11 PM PST 23 | Dec 20 12:21:05 PM PST 23 | 8373720000 ps | ||
| T43 | /workspace/coverage/default/8.prim_present_test.1014177591 | Dec 20 12:19:21 PM PST 23 | Dec 20 12:20:01 PM PST 23 | 5919760000 ps | ||
| T44 | /workspace/coverage/default/47.prim_present_test.507065908 | Dec 20 12:20:14 PM PST 23 | Dec 20 12:21:06 PM PST 23 | 8667600000 ps | ||
| T45 | /workspace/coverage/default/16.prim_present_test.1894638889 | Dec 20 12:19:28 PM PST 23 | Dec 20 12:20:32 PM PST 23 | 9531880000 ps | ||
| T46 | /workspace/coverage/default/41.prim_present_test.2597241766 | Dec 20 12:20:11 PM PST 23 | Dec 20 12:20:57 PM PST 23 | 6878900000 ps | ||
| T47 | /workspace/coverage/default/30.prim_present_test.4046169546 | Dec 20 12:20:11 PM PST 23 | Dec 20 12:21:13 PM PST 23 | 10132660000 ps | ||
| T48 | /workspace/coverage/default/31.prim_present_test.4265188231 | Dec 20 12:20:11 PM PST 23 | Dec 20 12:20:57 PM PST 23 | 6908040000 ps | ||
| T49 | /workspace/coverage/default/29.prim_present_test.2846872844 | Dec 20 12:20:42 PM PST 23 | Dec 20 12:21:40 PM PST 23 | 8666980000 ps | ||
| T50 | /workspace/coverage/default/1.prim_present_test.2897627006 | Dec 20 12:19:16 PM PST 23 | Dec 20 12:20:40 PM PST 23 | 14039280000 ps |
| Test location | /workspace/coverage/default/11.prim_present_test.2118017256 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 6527360000 ps |
| CPU time | 22.7 seconds |
| Started | Dec 20 12:20:30 PM PST 23 |
| Finished | Dec 20 12:21:16 PM PST 23 |
| Peak memory | 144760 kb |
| Host | smart-13d9cfb8-1045-45c4-98b7-b52d370dfcae |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2118017256 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.2118017256 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/0.prim_present_test.1629075761 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 5532880000 ps |
| CPU time | 19.91 seconds |
| Started | Dec 20 12:19:16 PM PST 23 |
| Finished | Dec 20 12:19:54 PM PST 23 |
| Peak memory | 144692 kb |
| Host | smart-c2cf8b6b-ae10-47be-87f7-66ad5c264744 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1629075761 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.1629075761 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/1.prim_present_test.2897627006 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 14039280000 ps |
| CPU time | 46.04 seconds |
| Started | Dec 20 12:19:16 PM PST 23 |
| Finished | Dec 20 12:20:40 PM PST 23 |
| Peak memory | 144764 kb |
| Host | smart-1bbe9808-0313-459d-babc-23643dd307a3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2897627006 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.2897627006 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/10.prim_present_test.3125708924 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 10824580000 ps |
| CPU time | 32.73 seconds |
| Started | Dec 20 12:20:08 PM PST 23 |
| Finished | Dec 20 12:21:08 PM PST 23 |
| Peak memory | 144768 kb |
| Host | smart-ecaff35f-6ef0-4d10-ae31-579f2c3492d5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3125708924 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.3125708924 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.2809440477 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 8130680000 ps |
| CPU time | 29.69 seconds |
| Started | Dec 20 12:19:12 PM PST 23 |
| Finished | Dec 20 12:20:07 PM PST 23 |
| Peak memory | 144696 kb |
| Host | smart-20ffe662-6811-44dd-8b2e-6fc6c16e0cee |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2809440477 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.2809440477 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.869576745 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 15165200000 ps |
| CPU time | 48.27 seconds |
| Started | Dec 20 12:19:24 PM PST 23 |
| Finished | Dec 20 12:20:53 PM PST 23 |
| Peak memory | 144772 kb |
| Host | smart-27bff252-638e-4fbf-a868-eb01cf341ad2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=869576745 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.869576745 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.1160175593 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 13923340000 ps |
| CPU time | 43.09 seconds |
| Started | Dec 20 12:19:10 PM PST 23 |
| Finished | Dec 20 12:20:29 PM PST 23 |
| Peak memory | 146188 kb |
| Host | smart-a3fbe462-4623-40f7-9b7f-ab15c48accc6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1160175593 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.1160175593 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.1733555885 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 12436580000 ps |
| CPU time | 41.82 seconds |
| Started | Dec 20 12:19:25 PM PST 23 |
| Finished | Dec 20 12:20:42 PM PST 23 |
| Peak memory | 144808 kb |
| Host | smart-7772a37b-e778-499a-8ee6-61803b585226 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1733555885 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.1733555885 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.1894638889 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 9531880000 ps |
| CPU time | 33.77 seconds |
| Started | Dec 20 12:19:28 PM PST 23 |
| Finished | Dec 20 12:20:32 PM PST 23 |
| Peak memory | 144796 kb |
| Host | smart-31182aaf-49d9-4189-b28f-a1d43f4b05dd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1894638889 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.1894638889 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.3581201942 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 15451020000 ps |
| CPU time | 47.22 seconds |
| Started | Dec 20 12:19:24 PM PST 23 |
| Finished | Dec 20 12:20:50 PM PST 23 |
| Peak memory | 144800 kb |
| Host | smart-19c5d8e1-f2af-4ca0-9bf7-c20ef05f3fd0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3581201942 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.3581201942 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.423995763 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 11559900000 ps |
| CPU time | 41.86 seconds |
| Started | Dec 20 12:20:03 PM PST 23 |
| Finished | Dec 20 12:21:19 PM PST 23 |
| Peak memory | 144772 kb |
| Host | smart-e39eecfd-c15d-4dc0-87f0-cff883b71e47 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=423995763 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.423995763 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.323648742 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 11897800000 ps |
| CPU time | 41.26 seconds |
| Started | Dec 20 12:20:03 PM PST 23 |
| Finished | Dec 20 12:21:20 PM PST 23 |
| Peak memory | 144756 kb |
| Host | smart-62e72222-f7ed-4c75-8384-16fa7cce9247 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=323648742 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.323648742 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.66989064 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 8415260000 ps |
| CPU time | 32.05 seconds |
| Started | Dec 20 12:19:22 PM PST 23 |
| Finished | Dec 20 12:20:23 PM PST 23 |
| Peak memory | 144808 kb |
| Host | smart-dd17a9d9-be8f-45bd-9b04-cc855aeabf31 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=66989064 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.66989064 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.1942652811 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 4497480000 ps |
| CPU time | 15.65 seconds |
| Started | Dec 20 12:18:58 PM PST 23 |
| Finished | Dec 20 12:19:31 PM PST 23 |
| Peak memory | 146176 kb |
| Host | smart-8155aea1-3e80-4675-bf19-9a1f2cb398a2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1942652811 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.1942652811 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.1352076715 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 3835940000 ps |
| CPU time | 14.33 seconds |
| Started | Dec 20 12:19:27 PM PST 23 |
| Finished | Dec 20 12:19:54 PM PST 23 |
| Peak memory | 144660 kb |
| Host | smart-5148fb26-e901-4451-870f-9daa678127c2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1352076715 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.1352076715 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.1179865327 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 14341840000 ps |
| CPU time | 41.28 seconds |
| Started | Dec 20 12:20:32 PM PST 23 |
| Finished | Dec 20 12:21:50 PM PST 23 |
| Peak memory | 144772 kb |
| Host | smart-9beacf66-8cf3-4025-b083-09aac45e6bc4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1179865327 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.1179865327 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.3123016028 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 7673740000 ps |
| CPU time | 25.94 seconds |
| Started | Dec 20 12:20:39 PM PST 23 |
| Finished | Dec 20 12:21:31 PM PST 23 |
| Peak memory | 144760 kb |
| Host | smart-a1f59320-258d-4b00-bef4-09d3a011b0d0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3123016028 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.3123016028 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.3330619934 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 14018200000 ps |
| CPU time | 42.19 seconds |
| Started | Dec 20 12:20:10 PM PST 23 |
| Finished | Dec 20 12:21:28 PM PST 23 |
| Peak memory | 144748 kb |
| Host | smart-fba21084-37d8-4c6e-bfca-0d7a5f5c963f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3330619934 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.3330619934 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.3008535581 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 7556560000 ps |
| CPU time | 21.73 seconds |
| Started | Dec 20 12:20:04 PM PST 23 |
| Finished | Dec 20 12:20:44 PM PST 23 |
| Peak memory | 144772 kb |
| Host | smart-7dd451dc-670a-4bbf-a1ef-94c3d6b9ff9b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3008535581 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.3008535581 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.1998389294 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 14328200000 ps |
| CPU time | 43.19 seconds |
| Started | Dec 20 12:18:57 PM PST 23 |
| Finished | Dec 20 12:20:20 PM PST 23 |
| Peak memory | 144832 kb |
| Host | smart-8d7601ed-b1ce-4bfc-98bc-23b83f7a1708 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1998389294 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.1998389294 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.28188751 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 5978040000 ps |
| CPU time | 21.04 seconds |
| Started | Dec 20 12:20:10 PM PST 23 |
| Finished | Dec 20 12:20:51 PM PST 23 |
| Peak memory | 144744 kb |
| Host | smart-f25f4acd-84dc-404e-afc1-d4646b128576 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=28188751 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.28188751 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.3607462567 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 6717080000 ps |
| CPU time | 23.5 seconds |
| Started | Dec 20 12:20:05 PM PST 23 |
| Finished | Dec 20 12:20:49 PM PST 23 |
| Peak memory | 144744 kb |
| Host | smart-ddec8921-970e-42f0-bc7b-4ebb1c3c0b76 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3607462567 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.3607462567 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.2846872844 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 8666980000 ps |
| CPU time | 29.5 seconds |
| Started | Dec 20 12:20:42 PM PST 23 |
| Finished | Dec 20 12:21:40 PM PST 23 |
| Peak memory | 144744 kb |
| Host | smart-c1466036-4ef9-44ac-b7f7-ad727399f5b1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2846872844 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.2846872844 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.1363398819 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 14441660000 ps |
| CPU time | 50.67 seconds |
| Started | Dec 20 12:19:11 PM PST 23 |
| Finished | Dec 20 12:20:46 PM PST 23 |
| Peak memory | 144692 kb |
| Host | smart-d8b10421-c3c1-43fd-bb0f-c7a422ebfcf9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1363398819 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.1363398819 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.4046169546 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 10132660000 ps |
| CPU time | 33.55 seconds |
| Started | Dec 20 12:20:11 PM PST 23 |
| Finished | Dec 20 12:21:13 PM PST 23 |
| Peak memory | 143672 kb |
| Host | smart-89ef0133-e542-4d27-8eeb-e03922fe0b97 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4046169546 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.4046169546 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.4265188231 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 6908040000 ps |
| CPU time | 25.37 seconds |
| Started | Dec 20 12:20:11 PM PST 23 |
| Finished | Dec 20 12:20:57 PM PST 23 |
| Peak memory | 144788 kb |
| Host | smart-251f1d43-64eb-4ca9-8041-6eb60151acc1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4265188231 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.4265188231 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.54455398 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 11353440000 ps |
| CPU time | 39.64 seconds |
| Started | Dec 20 12:20:05 PM PST 23 |
| Finished | Dec 20 12:21:19 PM PST 23 |
| Peak memory | 144756 kb |
| Host | smart-b4dab8b7-f3cc-49da-8643-8a230d34589a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=54455398 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.54455398 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.3922715823 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 12241280000 ps |
| CPU time | 42.14 seconds |
| Started | Dec 20 12:20:28 PM PST 23 |
| Finished | Dec 20 12:21:50 PM PST 23 |
| Peak memory | 144744 kb |
| Host | smart-70caa596-912c-4e9a-9a51-86078e7f094e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3922715823 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.3922715823 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.946605991 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 5852800000 ps |
| CPU time | 20.3 seconds |
| Started | Dec 20 12:20:07 PM PST 23 |
| Finished | Dec 20 12:20:45 PM PST 23 |
| Peak memory | 144756 kb |
| Host | smart-2d143af1-788b-402e-854f-b74763049e05 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=946605991 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.946605991 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.3488454125 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 5825520000 ps |
| CPU time | 20.25 seconds |
| Started | Dec 20 12:20:07 PM PST 23 |
| Finished | Dec 20 12:20:45 PM PST 23 |
| Peak memory | 144748 kb |
| Host | smart-3b9395eb-60ba-4413-b2b3-ccf0cd5e3e06 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3488454125 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.3488454125 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.3626470173 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 6240300000 ps |
| CPU time | 22.77 seconds |
| Started | Dec 20 12:20:11 PM PST 23 |
| Finished | Dec 20 12:20:54 PM PST 23 |
| Peak memory | 143584 kb |
| Host | smart-3ad08f7a-2830-490e-9db3-195319baaf0e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3626470173 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.3626470173 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.3079968421 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 13910940000 ps |
| CPU time | 46.56 seconds |
| Started | Dec 20 12:20:41 PM PST 23 |
| Finished | Dec 20 12:22:12 PM PST 23 |
| Peak memory | 144752 kb |
| Host | smart-c5a69583-619f-458c-8994-f4faed623d8d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3079968421 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.3079968421 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.2574392403 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 10152500000 ps |
| CPU time | 34.09 seconds |
| Started | Dec 20 12:20:26 PM PST 23 |
| Finished | Dec 20 12:21:35 PM PST 23 |
| Peak memory | 144752 kb |
| Host | smart-1a1eb291-f659-41c8-844d-1d43f7708e9a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2574392403 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.2574392403 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.537669375 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 5236520000 ps |
| CPU time | 18.79 seconds |
| Started | Dec 20 12:20:41 PM PST 23 |
| Finished | Dec 20 12:21:22 PM PST 23 |
| Peak memory | 144764 kb |
| Host | smart-9ddccd6c-e5bb-4934-8bb7-afcef40d8095 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=537669375 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.537669375 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.1005449154 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 4588000000 ps |
| CPU time | 18.47 seconds |
| Started | Dec 20 12:19:22 PM PST 23 |
| Finished | Dec 20 12:19:58 PM PST 23 |
| Peak memory | 144804 kb |
| Host | smart-754980af-237b-4ab2-a2aa-c30da3e086d5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1005449154 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.1005449154 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.2506785834 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 9535600000 ps |
| CPU time | 29.89 seconds |
| Started | Dec 20 12:20:02 PM PST 23 |
| Finished | Dec 20 12:20:57 PM PST 23 |
| Peak memory | 144752 kb |
| Host | smart-3983a84b-860c-4588-8d3a-1cb6173fa1d0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2506785834 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.2506785834 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.2597241766 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 6878900000 ps |
| CPU time | 24.04 seconds |
| Started | Dec 20 12:20:11 PM PST 23 |
| Finished | Dec 20 12:20:57 PM PST 23 |
| Peak memory | 144744 kb |
| Host | smart-94a8d1af-2597-4109-9cac-d0f89102b55b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2597241766 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.2597241766 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.3665539828 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 12230740000 ps |
| CPU time | 40.8 seconds |
| Started | Dec 20 12:20:07 PM PST 23 |
| Finished | Dec 20 12:21:22 PM PST 23 |
| Peak memory | 144748 kb |
| Host | smart-e67ae95a-e466-4402-9f5b-95c3c4e794ad |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3665539828 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.3665539828 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.1698202371 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 12320020000 ps |
| CPU time | 38.83 seconds |
| Started | Dec 20 12:20:11 PM PST 23 |
| Finished | Dec 20 12:21:23 PM PST 23 |
| Peak memory | 144744 kb |
| Host | smart-3863fab4-6ef9-497d-8d6f-20f204759fdc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1698202371 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.1698202371 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.1280103109 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 9030920000 ps |
| CPU time | 31.19 seconds |
| Started | Dec 20 12:20:06 PM PST 23 |
| Finished | Dec 20 12:21:05 PM PST 23 |
| Peak memory | 144744 kb |
| Host | smart-10b168cc-92c4-4fda-8051-229ea515cee0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1280103109 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.1280103109 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.4047971422 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 8373720000 ps |
| CPU time | 29 seconds |
| Started | Dec 20 12:20:11 PM PST 23 |
| Finished | Dec 20 12:21:05 PM PST 23 |
| Peak memory | 144744 kb |
| Host | smart-556f159f-966f-479c-a6ad-d35ec84a89e6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4047971422 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.4047971422 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.164008935 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 6506900000 ps |
| CPU time | 22.99 seconds |
| Started | Dec 20 12:20:15 PM PST 23 |
| Finished | Dec 20 12:20:57 PM PST 23 |
| Peak memory | 144772 kb |
| Host | smart-d1884639-8188-45fd-bd26-c6e2b3525b1a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=164008935 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.164008935 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.507065908 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 8667600000 ps |
| CPU time | 27.41 seconds |
| Started | Dec 20 12:20:14 PM PST 23 |
| Finished | Dec 20 12:21:06 PM PST 23 |
| Peak memory | 144776 kb |
| Host | smart-f4a69562-d358-44c7-87a2-bf71f0f5fa4b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=507065908 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.507065908 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.3770744267 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 4811200000 ps |
| CPU time | 14.55 seconds |
| Started | Dec 20 12:20:11 PM PST 23 |
| Finished | Dec 20 12:20:39 PM PST 23 |
| Peak memory | 144748 kb |
| Host | smart-17bc5873-ae55-4ad8-bdf8-af122f88408e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3770744267 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.3770744267 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.2201978459 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 14439800000 ps |
| CPU time | 40.31 seconds |
| Started | Dec 20 12:20:11 PM PST 23 |
| Finished | Dec 20 12:21:26 PM PST 23 |
| Peak memory | 144748 kb |
| Host | smart-26a2bdd3-9219-48ac-8928-f3458c5fd237 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2201978459 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.2201978459 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.1421003893 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 3427360000 ps |
| CPU time | 11.57 seconds |
| Started | Dec 20 12:19:15 PM PST 23 |
| Finished | Dec 20 12:19:37 PM PST 23 |
| Peak memory | 144628 kb |
| Host | smart-faf265f7-27a7-4e6b-8126-ddee7e839fc1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1421003893 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.1421003893 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.4106835601 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 9689980000 ps |
| CPU time | 35.03 seconds |
| Started | Dec 20 12:19:19 PM PST 23 |
| Finished | Dec 20 12:20:23 PM PST 23 |
| Peak memory | 144692 kb |
| Host | smart-3eca769c-b17c-4fb6-977e-df0076516eea |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4106835601 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.4106835601 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.2336047384 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 9680680000 ps |
| CPU time | 37.23 seconds |
| Started | Dec 20 12:19:21 PM PST 23 |
| Finished | Dec 20 12:20:33 PM PST 23 |
| Peak memory | 144804 kb |
| Host | smart-d5bac7ac-0d1e-4bf9-9220-b6d3efa296f5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2336047384 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.2336047384 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.1014177591 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 5919760000 ps |
| CPU time | 21.05 seconds |
| Started | Dec 20 12:19:21 PM PST 23 |
| Finished | Dec 20 12:20:01 PM PST 23 |
| Peak memory | 144772 kb |
| Host | smart-074769ad-b9e3-4ae6-8e89-8be22d3a0b5d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1014177591 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.1014177591 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.4059333727 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 3663580000 ps |
| CPU time | 13.05 seconds |
| Started | Dec 20 12:19:16 PM PST 23 |
| Finished | Dec 20 12:19:41 PM PST 23 |
| Peak memory | 144628 kb |
| Host | smart-81804f2a-36ce-4644-9958-2e4cb5876f22 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4059333727 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.4059333727 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |