| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/0.prim_present_test.2142288719 | ||
| Name |
|---|
| /workspace/coverage/default/1.prim_present_test.1291207355 |
| /workspace/coverage/default/10.prim_present_test.133576325 |
| /workspace/coverage/default/11.prim_present_test.175859472 |
| /workspace/coverage/default/12.prim_present_test.2755076300 |
| /workspace/coverage/default/13.prim_present_test.3514987933 |
| /workspace/coverage/default/14.prim_present_test.274853904 |
| /workspace/coverage/default/15.prim_present_test.2672609740 |
| /workspace/coverage/default/16.prim_present_test.1128252605 |
| /workspace/coverage/default/17.prim_present_test.2074830566 |
| /workspace/coverage/default/18.prim_present_test.6709727 |
| /workspace/coverage/default/19.prim_present_test.3423616403 |
| /workspace/coverage/default/2.prim_present_test.98945958 |
| /workspace/coverage/default/20.prim_present_test.3229224741 |
| /workspace/coverage/default/21.prim_present_test.2705829072 |
| /workspace/coverage/default/22.prim_present_test.425646044 |
| /workspace/coverage/default/23.prim_present_test.2639331619 |
| /workspace/coverage/default/24.prim_present_test.3471657959 |
| /workspace/coverage/default/25.prim_present_test.1601093873 |
| /workspace/coverage/default/26.prim_present_test.831430276 |
| /workspace/coverage/default/27.prim_present_test.2927433614 |
| /workspace/coverage/default/28.prim_present_test.558867278 |
| /workspace/coverage/default/29.prim_present_test.2675623151 |
| /workspace/coverage/default/3.prim_present_test.1762312172 |
| /workspace/coverage/default/30.prim_present_test.3391043156 |
| /workspace/coverage/default/31.prim_present_test.2991503294 |
| /workspace/coverage/default/32.prim_present_test.4197492427 |
| /workspace/coverage/default/33.prim_present_test.1344395670 |
| /workspace/coverage/default/34.prim_present_test.4161834257 |
| /workspace/coverage/default/35.prim_present_test.2694065412 |
| /workspace/coverage/default/36.prim_present_test.995419746 |
| /workspace/coverage/default/37.prim_present_test.3711759683 |
| /workspace/coverage/default/38.prim_present_test.3793608439 |
| /workspace/coverage/default/39.prim_present_test.1755618760 |
| /workspace/coverage/default/4.prim_present_test.661515952 |
| /workspace/coverage/default/40.prim_present_test.3730992816 |
| /workspace/coverage/default/41.prim_present_test.3866856448 |
| /workspace/coverage/default/42.prim_present_test.21414883 |
| /workspace/coverage/default/43.prim_present_test.1394534595 |
| /workspace/coverage/default/44.prim_present_test.1201693231 |
| /workspace/coverage/default/45.prim_present_test.635853369 |
| /workspace/coverage/default/46.prim_present_test.3355270599 |
| /workspace/coverage/default/47.prim_present_test.142327376 |
| /workspace/coverage/default/48.prim_present_test.2771504910 |
| /workspace/coverage/default/49.prim_present_test.812406785 |
| /workspace/coverage/default/5.prim_present_test.1256955203 |
| /workspace/coverage/default/6.prim_present_test.3796404553 |
| /workspace/coverage/default/7.prim_present_test.3673968366 |
| /workspace/coverage/default/8.prim_present_test.1998476671 |
| /workspace/coverage/default/9.prim_present_test.1541644548 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/0.prim_present_test.2142288719 | Dec 24 12:19:15 PM PST 23 | Dec 24 12:20:08 PM PST 23 | 7875860000 ps | ||
| T2 | /workspace/coverage/default/23.prim_present_test.2639331619 | Dec 24 12:19:21 PM PST 23 | Dec 24 12:20:49 PM PST 23 | 12811060000 ps | ||
| T3 | /workspace/coverage/default/28.prim_present_test.558867278 | Dec 24 12:23:10 PM PST 23 | Dec 24 12:24:15 PM PST 23 | 9815220000 ps | ||
| T4 | /workspace/coverage/default/29.prim_present_test.2675623151 | Dec 24 12:20:25 PM PST 23 | Dec 24 12:21:54 PM PST 23 | 14731820000 ps | ||
| T5 | /workspace/coverage/default/36.prim_present_test.995419746 | Dec 24 12:29:19 PM PST 23 | Dec 24 12:30:14 PM PST 23 | 8422080000 ps | ||
| T6 | /workspace/coverage/default/38.prim_present_test.3793608439 | Dec 24 12:19:30 PM PST 23 | Dec 24 12:20:09 PM PST 23 | 5381600000 ps | ||
| T7 | /workspace/coverage/default/41.prim_present_test.3866856448 | Dec 24 12:22:13 PM PST 23 | Dec 24 12:23:22 PM PST 23 | 10394920000 ps | ||
| T8 | /workspace/coverage/default/19.prim_present_test.3423616403 | Dec 24 12:19:25 PM PST 23 | Dec 24 12:20:07 PM PST 23 | 6299200000 ps | ||
| T9 | /workspace/coverage/default/8.prim_present_test.1998476671 | Dec 24 12:19:22 PM PST 23 | Dec 24 12:20:09 PM PST 23 | 5909840000 ps | ||
| T10 | /workspace/coverage/default/1.prim_present_test.1291207355 | Dec 24 12:19:22 PM PST 23 | Dec 24 12:20:07 PM PST 23 | 6448620000 ps | ||
| T11 | /workspace/coverage/default/7.prim_present_test.3673968366 | Dec 24 12:21:11 PM PST 23 | Dec 24 12:22:08 PM PST 23 | 7123800000 ps | ||
| T12 | /workspace/coverage/default/26.prim_present_test.831430276 | Dec 24 12:19:59 PM PST 23 | Dec 24 12:21:37 PM PST 23 | 14543340000 ps | ||
| T13 | /workspace/coverage/default/48.prim_present_test.2771504910 | Dec 24 12:20:31 PM PST 23 | Dec 24 12:21:09 PM PST 23 | 6465980000 ps | ||
| T14 | /workspace/coverage/default/2.prim_present_test.98945958 | Dec 24 12:19:24 PM PST 23 | Dec 24 12:20:12 PM PST 23 | 7041960000 ps | ||
| T15 | /workspace/coverage/default/9.prim_present_test.1541644548 | Dec 24 12:19:15 PM PST 23 | Dec 24 12:19:39 PM PST 23 | 3656760000 ps | ||
| T16 | /workspace/coverage/default/11.prim_present_test.175859472 | Dec 24 12:19:23 PM PST 23 | Dec 24 12:20:58 PM PST 23 | 14711980000 ps | ||
| T17 | /workspace/coverage/default/15.prim_present_test.2672609740 | Dec 24 12:21:23 PM PST 23 | Dec 24 12:22:19 PM PST 23 | 8562200000 ps | ||
| T18 | /workspace/coverage/default/40.prim_present_test.3730992816 | Dec 24 12:20:02 PM PST 23 | Dec 24 12:20:33 PM PST 23 | 5218540000 ps | ||
| T19 | /workspace/coverage/default/10.prim_present_test.133576325 | Dec 24 12:21:11 PM PST 23 | Dec 24 12:21:45 PM PST 23 | 4143460000 ps | ||
| T20 | /workspace/coverage/default/47.prim_present_test.142327376 | Dec 24 12:24:22 PM PST 23 | Dec 24 12:25:12 PM PST 23 | 6178920000 ps | ||
| T21 | /workspace/coverage/default/45.prim_present_test.635853369 | Dec 24 12:22:46 PM PST 23 | Dec 24 12:23:57 PM PST 23 | 11105440000 ps | ||
| T22 | /workspace/coverage/default/46.prim_present_test.3355270599 | Dec 24 12:25:37 PM PST 23 | Dec 24 12:26:49 PM PST 23 | 11710560000 ps | ||
| T23 | /workspace/coverage/default/32.prim_present_test.4197492427 | Dec 24 12:20:59 PM PST 23 | Dec 24 12:21:28 PM PST 23 | 4603500000 ps | ||
| T24 | /workspace/coverage/default/20.prim_present_test.3229224741 | Dec 24 12:21:23 PM PST 23 | Dec 24 12:22:04 PM PST 23 | 5768480000 ps | ||
| T25 | /workspace/coverage/default/21.prim_present_test.2705829072 | Dec 24 12:19:24 PM PST 23 | Dec 24 12:20:47 PM PST 23 | 12853220000 ps | ||
| T26 | /workspace/coverage/default/31.prim_present_test.2991503294 | Dec 24 12:26:56 PM PST 23 | Dec 24 12:28:05 PM PST 23 | 11974060000 ps | ||
| T27 | /workspace/coverage/default/14.prim_present_test.274853904 | Dec 24 12:19:23 PM PST 23 | Dec 24 12:19:53 PM PST 23 | 4499960000 ps | ||
| T28 | /workspace/coverage/default/3.prim_present_test.1762312172 | Dec 24 12:20:43 PM PST 23 | Dec 24 12:21:53 PM PST 23 | 12145800000 ps | ||
| T29 | /workspace/coverage/default/34.prim_present_test.4161834257 | Dec 24 12:21:45 PM PST 23 | Dec 24 12:23:31 PM PST 23 | 14454680000 ps | ||
| T30 | /workspace/coverage/default/42.prim_present_test.21414883 | Dec 24 12:20:49 PM PST 23 | Dec 24 12:22:18 PM PST 23 | 14055400000 ps | ||
| T31 | /workspace/coverage/default/16.prim_present_test.1128252605 | Dec 24 12:19:25 PM PST 23 | Dec 24 12:21:02 PM PST 23 | 14158940000 ps | ||
| T32 | /workspace/coverage/default/6.prim_present_test.3796404553 | Dec 24 12:19:23 PM PST 23 | Dec 24 12:20:47 PM PST 23 | 10703060000 ps | ||
| T33 | /workspace/coverage/default/37.prim_present_test.3711759683 | Dec 24 12:24:07 PM PST 23 | Dec 24 12:24:40 PM PST 23 | 5081520000 ps | ||
| T34 | /workspace/coverage/default/30.prim_present_test.3391043156 | Dec 24 12:25:42 PM PST 23 | Dec 24 12:27:02 PM PST 23 | 13817940000 ps | ||
| T35 | /workspace/coverage/default/27.prim_present_test.2927433614 | Dec 24 12:19:25 PM PST 23 | Dec 24 12:20:38 PM PST 23 | 11303220000 ps | ||
| T36 | /workspace/coverage/default/25.prim_present_test.1601093873 | Dec 24 12:21:11 PM PST 23 | Dec 24 12:22:03 PM PST 23 | 6701580000 ps | ||
| T37 | /workspace/coverage/default/33.prim_present_test.1344395670 | Dec 24 12:27:08 PM PST 23 | Dec 24 12:27:50 PM PST 23 | 6036320000 ps | ||
| T38 | /workspace/coverage/default/35.prim_present_test.2694065412 | Dec 24 12:24:22 PM PST 23 | Dec 24 12:25:52 PM PST 23 | 12657300000 ps | ||
| T39 | /workspace/coverage/default/44.prim_present_test.1201693231 | Dec 24 12:23:41 PM PST 23 | Dec 24 12:24:52 PM PST 23 | 11833320000 ps | ||
| T40 | /workspace/coverage/default/22.prim_present_test.425646044 | Dec 24 12:19:13 PM PST 23 | Dec 24 12:20:40 PM PST 23 | 15250140000 ps | ||
| T41 | /workspace/coverage/default/13.prim_present_test.3514987933 | Dec 24 12:19:22 PM PST 23 | Dec 24 12:20:48 PM PST 23 | 10921300000 ps | ||
| T42 | /workspace/coverage/default/5.prim_present_test.1256955203 | Dec 24 12:21:11 PM PST 23 | Dec 24 12:21:57 PM PST 23 | 5852800000 ps | ||
| T43 | /workspace/coverage/default/39.prim_present_test.1755618760 | Dec 24 12:22:14 PM PST 23 | Dec 24 12:23:09 PM PST 23 | 8098440000 ps | ||
| T44 | /workspace/coverage/default/24.prim_present_test.3471657959 | Dec 24 12:19:14 PM PST 23 | Dec 24 12:19:50 PM PST 23 | 6208680000 ps | ||
| T45 | /workspace/coverage/default/12.prim_present_test.2755076300 | Dec 24 12:19:25 PM PST 23 | Dec 24 12:20:28 PM PST 23 | 9486000000 ps | ||
| T46 | /workspace/coverage/default/4.prim_present_test.661515952 | Dec 24 12:21:11 PM PST 23 | Dec 24 12:22:28 PM PST 23 | 9665180000 ps | ||
| T47 | /workspace/coverage/default/49.prim_present_test.812406785 | Dec 24 12:25:45 PM PST 23 | Dec 24 12:26:39 PM PST 23 | 8853600000 ps | ||
| T48 | /workspace/coverage/default/18.prim_present_test.6709727 | Dec 24 12:19:22 PM PST 23 | Dec 24 12:19:44 PM PST 23 | 3236400000 ps | ||
| T49 | /workspace/coverage/default/43.prim_present_test.1394534595 | Dec 24 12:19:27 PM PST 23 | Dec 24 12:21:07 PM PST 23 | 14615260000 ps | ||
| T50 | /workspace/coverage/default/17.prim_present_test.2074830566 | Dec 24 12:19:24 PM PST 23 | Dec 24 12:20:06 PM PST 23 | 6190700000 ps |
| Test location | /workspace/coverage/default/0.prim_present_test.2142288719 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 7875860000 ps |
| CPU time | 28.89 seconds |
| Started | Dec 24 12:19:15 PM PST 23 |
| Finished | Dec 24 12:20:08 PM PST 23 |
| Peak memory | 142840 kb |
| Host | smart-fe730808-e62b-4466-bc27-864a91ae807f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2142288719 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.2142288719 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/1.prim_present_test.1291207355 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 6448620000 ps |
| CPU time | 23.78 seconds |
| Started | Dec 24 12:19:22 PM PST 23 |
| Finished | Dec 24 12:20:07 PM PST 23 |
| Peak memory | 144360 kb |
| Host | smart-a789ea3a-abc1-429a-bad3-be7130bcaee6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1291207355 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.1291207355 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/10.prim_present_test.133576325 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 4143460000 ps |
| CPU time | 17.38 seconds |
| Started | Dec 24 12:21:11 PM PST 23 |
| Finished | Dec 24 12:21:45 PM PST 23 |
| Peak memory | 142124 kb |
| Host | smart-2bf734b7-7eea-4057-ab11-43fa1655d35f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=133576325 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.133576325 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/11.prim_present_test.175859472 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 14711980000 ps |
| CPU time | 51.8 seconds |
| Started | Dec 24 12:19:23 PM PST 23 |
| Finished | Dec 24 12:20:58 PM PST 23 |
| Peak memory | 144836 kb |
| Host | smart-27a3baee-5b03-4c1d-877f-a974bcf2dd81 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=175859472 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.175859472 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.2755076300 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 9486000000 ps |
| CPU time | 33.96 seconds |
| Started | Dec 24 12:19:25 PM PST 23 |
| Finished | Dec 24 12:20:28 PM PST 23 |
| Peak memory | 144736 kb |
| Host | smart-58cc0ef9-5bfa-463b-9448-471e21a333b2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2755076300 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.2755076300 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.3514987933 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 10921300000 ps |
| CPU time | 45.32 seconds |
| Started | Dec 24 12:19:22 PM PST 23 |
| Finished | Dec 24 12:20:48 PM PST 23 |
| Peak memory | 144348 kb |
| Host | smart-c6abbbe5-a482-4085-bdf8-53f40b30a1d0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3514987933 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.3514987933 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.274853904 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 4499960000 ps |
| CPU time | 16.18 seconds |
| Started | Dec 24 12:19:23 PM PST 23 |
| Finished | Dec 24 12:19:53 PM PST 23 |
| Peak memory | 144832 kb |
| Host | smart-bbe0a3c7-bb3b-4b85-b407-cb66ee81efc2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=274853904 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.274853904 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.2672609740 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 8562200000 ps |
| CPU time | 29.87 seconds |
| Started | Dec 24 12:21:23 PM PST 23 |
| Finished | Dec 24 12:22:19 PM PST 23 |
| Peak memory | 143048 kb |
| Host | smart-f3580d24-7d94-4642-b0d1-b82c49fc335b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2672609740 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.2672609740 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.1128252605 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 14158940000 ps |
| CPU time | 51.66 seconds |
| Started | Dec 24 12:19:25 PM PST 23 |
| Finished | Dec 24 12:21:02 PM PST 23 |
| Peak memory | 144364 kb |
| Host | smart-bc6f2dac-9b95-41c0-a5bf-8cac69ebe9fc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1128252605 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.1128252605 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.2074830566 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 6190700000 ps |
| CPU time | 22.72 seconds |
| Started | Dec 24 12:19:24 PM PST 23 |
| Finished | Dec 24 12:20:06 PM PST 23 |
| Peak memory | 144844 kb |
| Host | smart-0d52c6e9-6b36-4ba5-b8df-b7cbcb5f1904 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2074830566 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.2074830566 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.6709727 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 3236400000 ps |
| CPU time | 11.78 seconds |
| Started | Dec 24 12:19:22 PM PST 23 |
| Finished | Dec 24 12:19:44 PM PST 23 |
| Peak memory | 144712 kb |
| Host | smart-4c29492b-eead-40df-a1eb-3555cdd85b8e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=6709727 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.6709727 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.3423616403 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 6299200000 ps |
| CPU time | 22.49 seconds |
| Started | Dec 24 12:19:25 PM PST 23 |
| Finished | Dec 24 12:20:07 PM PST 23 |
| Peak memory | 144736 kb |
| Host | smart-5db246ea-27f1-4d2e-bc5d-a3040d1d9e1f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3423616403 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.3423616403 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.98945958 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 7041960000 ps |
| CPU time | 25.88 seconds |
| Started | Dec 24 12:19:24 PM PST 23 |
| Finished | Dec 24 12:20:12 PM PST 23 |
| Peak memory | 144844 kb |
| Host | smart-9abd3c23-c479-49b1-a555-0eb41a32c60d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=98945958 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.98945958 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.3229224741 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 5768480000 ps |
| CPU time | 21.63 seconds |
| Started | Dec 24 12:21:23 PM PST 23 |
| Finished | Dec 24 12:22:04 PM PST 23 |
| Peak memory | 143616 kb |
| Host | smart-61c2dc19-4d29-4539-bfe4-bddc076cdad8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3229224741 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.3229224741 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.2705829072 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 12853220000 ps |
| CPU time | 45.4 seconds |
| Started | Dec 24 12:19:24 PM PST 23 |
| Finished | Dec 24 12:20:47 PM PST 23 |
| Peak memory | 144844 kb |
| Host | smart-828dfa0e-3bae-4ab4-b031-fb129e6e0015 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2705829072 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.2705829072 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.425646044 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 15250140000 ps |
| CPU time | 46.52 seconds |
| Started | Dec 24 12:19:13 PM PST 23 |
| Finished | Dec 24 12:20:40 PM PST 23 |
| Peak memory | 144500 kb |
| Host | smart-2c89fc0a-58a2-42b0-9c33-17bfeed94fe4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=425646044 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.425646044 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.2639331619 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 12811060000 ps |
| CPU time | 47.05 seconds |
| Started | Dec 24 12:19:21 PM PST 23 |
| Finished | Dec 24 12:20:49 PM PST 23 |
| Peak memory | 144736 kb |
| Host | smart-b3fa7fc8-9e22-46d9-b088-0f6f9e45af77 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2639331619 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.2639331619 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.3471657959 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 6208680000 ps |
| CPU time | 19.12 seconds |
| Started | Dec 24 12:19:14 PM PST 23 |
| Finished | Dec 24 12:19:50 PM PST 23 |
| Peak memory | 144496 kb |
| Host | smart-1e85a61f-d47b-437c-b867-8b8c896384b3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3471657959 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.3471657959 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.1601093873 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 6701580000 ps |
| CPU time | 27.33 seconds |
| Started | Dec 24 12:21:11 PM PST 23 |
| Finished | Dec 24 12:22:03 PM PST 23 |
| Peak memory | 141152 kb |
| Host | smart-1a331597-8076-4062-98bf-3bf2eaf418d9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1601093873 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.1601093873 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.831430276 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 14543340000 ps |
| CPU time | 52.77 seconds |
| Started | Dec 24 12:19:59 PM PST 23 |
| Finished | Dec 24 12:21:37 PM PST 23 |
| Peak memory | 144732 kb |
| Host | smart-f95f3296-5a4a-42c3-b9f8-9d6370bc9ea4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=831430276 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.831430276 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.2927433614 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 11303220000 ps |
| CPU time | 40.2 seconds |
| Started | Dec 24 12:19:25 PM PST 23 |
| Finished | Dec 24 12:20:38 PM PST 23 |
| Peak memory | 144844 kb |
| Host | smart-2b0d9877-41d9-4560-97cc-d48afeeb6285 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2927433614 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.2927433614 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.558867278 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 9815220000 ps |
| CPU time | 35.43 seconds |
| Started | Dec 24 12:23:10 PM PST 23 |
| Finished | Dec 24 12:24:15 PM PST 23 |
| Peak memory | 144592 kb |
| Host | smart-3e5d4692-c8cc-4591-95dd-30f655f9d420 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=558867278 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.558867278 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.2675623151 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 14731820000 ps |
| CPU time | 47.89 seconds |
| Started | Dec 24 12:20:25 PM PST 23 |
| Finished | Dec 24 12:21:54 PM PST 23 |
| Peak memory | 144568 kb |
| Host | smart-0a654a5b-597b-432a-a6b7-1857060d0c65 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2675623151 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.2675623151 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.1762312172 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 12145800000 ps |
| CPU time | 38.5 seconds |
| Started | Dec 24 12:20:43 PM PST 23 |
| Finished | Dec 24 12:21:53 PM PST 23 |
| Peak memory | 144324 kb |
| Host | smart-62f32b7e-43f0-449a-8aaf-e3052d1593b5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1762312172 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.1762312172 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.3391043156 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 13817940000 ps |
| CPU time | 42.89 seconds |
| Started | Dec 24 12:25:42 PM PST 23 |
| Finished | Dec 24 12:27:02 PM PST 23 |
| Peak memory | 144160 kb |
| Host | smart-66c732a6-1c3d-439e-86ec-b135818bf717 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3391043156 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.3391043156 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.2991503294 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 11974060000 ps |
| CPU time | 35.88 seconds |
| Started | Dec 24 12:26:56 PM PST 23 |
| Finished | Dec 24 12:28:05 PM PST 23 |
| Peak memory | 144252 kb |
| Host | smart-7e74b0a3-891d-427f-aa40-8683c184c932 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2991503294 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.2991503294 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.4197492427 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 4603500000 ps |
| CPU time | 15.41 seconds |
| Started | Dec 24 12:20:59 PM PST 23 |
| Finished | Dec 24 12:21:28 PM PST 23 |
| Peak memory | 144612 kb |
| Host | smart-443e8d18-cec5-4f93-ba9e-5dd5ae6c7f1b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4197492427 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.4197492427 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.1344395670 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 6036320000 ps |
| CPU time | 20.8 seconds |
| Started | Dec 24 12:27:08 PM PST 23 |
| Finished | Dec 24 12:27:50 PM PST 23 |
| Peak memory | 144020 kb |
| Host | smart-9417e83a-2640-46ac-a366-d3c482771713 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1344395670 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.1344395670 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.4161834257 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 14454680000 ps |
| CPU time | 56.64 seconds |
| Started | Dec 24 12:21:45 PM PST 23 |
| Finished | Dec 24 12:23:31 PM PST 23 |
| Peak memory | 144180 kb |
| Host | smart-7ab612ff-f886-4964-b6b2-898c00d83e7d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4161834257 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.4161834257 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.2694065412 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 12657300000 ps |
| CPU time | 43.71 seconds |
| Started | Dec 24 12:24:22 PM PST 23 |
| Finished | Dec 24 12:25:52 PM PST 23 |
| Peak memory | 144092 kb |
| Host | smart-d88ebb9c-d259-41b2-8573-ef3afda5bf13 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2694065412 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.2694065412 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.995419746 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 8422080000 ps |
| CPU time | 25.33 seconds |
| Started | Dec 24 12:29:19 PM PST 23 |
| Finished | Dec 24 12:30:14 PM PST 23 |
| Peak memory | 143084 kb |
| Host | smart-4b7592af-8187-4cc5-8e48-c484b706f5fd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=995419746 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.995419746 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.3711759683 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 5081520000 ps |
| CPU time | 17.79 seconds |
| Started | Dec 24 12:24:07 PM PST 23 |
| Finished | Dec 24 12:24:40 PM PST 23 |
| Peak memory | 142416 kb |
| Host | smart-a10198f3-aef4-46af-aee3-65428f45b48f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3711759683 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.3711759683 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.3793608439 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 5381600000 ps |
| CPU time | 20.66 seconds |
| Started | Dec 24 12:19:30 PM PST 23 |
| Finished | Dec 24 12:20:09 PM PST 23 |
| Peak memory | 144132 kb |
| Host | smart-7a50742f-3d83-4c86-8d69-d7f24bfcf469 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3793608439 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.3793608439 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.1755618760 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 8098440000 ps |
| CPU time | 27.93 seconds |
| Started | Dec 24 12:22:14 PM PST 23 |
| Finished | Dec 24 12:23:09 PM PST 23 |
| Peak memory | 144540 kb |
| Host | smart-26e19ce1-98a3-4aa8-883a-76d5c9155bdf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1755618760 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.1755618760 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.661515952 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 9665180000 ps |
| CPU time | 39.99 seconds |
| Started | Dec 24 12:21:11 PM PST 23 |
| Finished | Dec 24 12:22:28 PM PST 23 |
| Peak memory | 141480 kb |
| Host | smart-f87aa37b-4602-4279-99a7-ad8bbbf45de3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=661515952 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.661515952 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.3730992816 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 5218540000 ps |
| CPU time | 16.46 seconds |
| Started | Dec 24 12:20:02 PM PST 23 |
| Finished | Dec 24 12:20:33 PM PST 23 |
| Peak memory | 144576 kb |
| Host | smart-92a91632-4047-4e4e-90d0-df2dce0b6c74 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3730992816 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.3730992816 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.3866856448 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 10394920000 ps |
| CPU time | 35.17 seconds |
| Started | Dec 24 12:22:13 PM PST 23 |
| Finished | Dec 24 12:23:22 PM PST 23 |
| Peak memory | 144840 kb |
| Host | smart-d4a30234-5eb7-4b17-aad7-021471b41c93 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3866856448 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.3866856448 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.21414883 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 14055400000 ps |
| CPU time | 48.6 seconds |
| Started | Dec 24 12:20:49 PM PST 23 |
| Finished | Dec 24 12:22:18 PM PST 23 |
| Peak memory | 144604 kb |
| Host | smart-2ef928ed-f925-4b1d-907c-b1e4554c4a11 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=21414883 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.21414883 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.1394534595 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 14615260000 ps |
| CPU time | 54.36 seconds |
| Started | Dec 24 12:19:27 PM PST 23 |
| Finished | Dec 24 12:21:07 PM PST 23 |
| Peak memory | 144364 kb |
| Host | smart-a46225e6-c726-4938-830d-0edcfcecd550 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1394534595 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.1394534595 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.1201693231 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 11833320000 ps |
| CPU time | 39.06 seconds |
| Started | Dec 24 12:23:41 PM PST 23 |
| Finished | Dec 24 12:24:52 PM PST 23 |
| Peak memory | 144556 kb |
| Host | smart-05179750-a376-4808-9e33-5bc6c473a10f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1201693231 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.1201693231 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.635853369 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 11105440000 ps |
| CPU time | 38.81 seconds |
| Started | Dec 24 12:22:46 PM PST 23 |
| Finished | Dec 24 12:23:57 PM PST 23 |
| Peak memory | 144588 kb |
| Host | smart-1ec96add-6b84-44e4-b245-d105a92f837a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=635853369 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.635853369 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.3355270599 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 11710560000 ps |
| CPU time | 38.68 seconds |
| Started | Dec 24 12:25:37 PM PST 23 |
| Finished | Dec 24 12:26:49 PM PST 23 |
| Peak memory | 144800 kb |
| Host | smart-cad28a26-a2cf-4462-a919-76c8cedea42e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3355270599 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.3355270599 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.142327376 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 6178920000 ps |
| CPU time | 22.06 seconds |
| Started | Dec 24 12:24:22 PM PST 23 |
| Finished | Dec 24 12:25:12 PM PST 23 |
| Peak memory | 144096 kb |
| Host | smart-e6ba2782-8ad8-475d-ae15-a89f92ef8b1e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=142327376 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.142327376 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.2771504910 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 6465980000 ps |
| CPU time | 20.88 seconds |
| Started | Dec 24 12:20:31 PM PST 23 |
| Finished | Dec 24 12:21:09 PM PST 23 |
| Peak memory | 144608 kb |
| Host | smart-64e26292-a82c-4e98-87b8-c134ed147629 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2771504910 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.2771504910 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.812406785 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 8853600000 ps |
| CPU time | 28.94 seconds |
| Started | Dec 24 12:25:45 PM PST 23 |
| Finished | Dec 24 12:26:39 PM PST 23 |
| Peak memory | 144152 kb |
| Host | smart-898acc15-7e3f-4e42-9e5e-62ddd69d86b3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=812406785 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.812406785 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.1256955203 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 5852800000 ps |
| CPU time | 23.96 seconds |
| Started | Dec 24 12:21:11 PM PST 23 |
| Finished | Dec 24 12:21:57 PM PST 23 |
| Peak memory | 142328 kb |
| Host | smart-872e55a2-054d-49a6-bc41-9298818fb30b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1256955203 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.1256955203 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.3796404553 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 10703060000 ps |
| CPU time | 44.34 seconds |
| Started | Dec 24 12:19:23 PM PST 23 |
| Finished | Dec 24 12:20:47 PM PST 23 |
| Peak memory | 144356 kb |
| Host | smart-1325bcf0-9083-4387-a2a6-2f45b525f546 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3796404553 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.3796404553 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.3673968366 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 7123800000 ps |
| CPU time | 29.69 seconds |
| Started | Dec 24 12:21:11 PM PST 23 |
| Finished | Dec 24 12:22:08 PM PST 23 |
| Peak memory | 141844 kb |
| Host | smart-a16f1ca4-8ce1-44eb-9a3b-5c190aad8348 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3673968366 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.3673968366 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.1998476671 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 5909840000 ps |
| CPU time | 24.55 seconds |
| Started | Dec 24 12:19:22 PM PST 23 |
| Finished | Dec 24 12:20:09 PM PST 23 |
| Peak memory | 144344 kb |
| Host | smart-1d17bdae-f5e0-4c86-a6c8-6e6fc26e3113 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1998476671 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.1998476671 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.1541644548 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 3656760000 ps |
| CPU time | 13.24 seconds |
| Started | Dec 24 12:19:15 PM PST 23 |
| Finished | Dec 24 12:19:39 PM PST 23 |
| Peak memory | 143316 kb |
| Host | smart-a934c1c9-4e64-43ca-9fda-9e93b4ba8435 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1541644548 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.1541644548 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |