Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.83 90.41 100.00 98.73 100.00 100.00


Total tests in report: 50
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
97.83 97.83 90.41 90.41 100.00 100.00 98.73 98.73 100.00 100.00 100.00 100.00 /workspace/coverage/default/17.prim_present_test.2409293874

Tests that do not contribute to grading

Name
/workspace/coverage/default/0.prim_present_test.688650622
/workspace/coverage/default/1.prim_present_test.4214406369
/workspace/coverage/default/10.prim_present_test.911481692
/workspace/coverage/default/11.prim_present_test.269011272
/workspace/coverage/default/12.prim_present_test.3093932980
/workspace/coverage/default/13.prim_present_test.3869666704
/workspace/coverage/default/14.prim_present_test.1744684473
/workspace/coverage/default/15.prim_present_test.305734372
/workspace/coverage/default/16.prim_present_test.3947502334
/workspace/coverage/default/18.prim_present_test.4186246436
/workspace/coverage/default/19.prim_present_test.2246775226
/workspace/coverage/default/2.prim_present_test.1757662651
/workspace/coverage/default/20.prim_present_test.2627224198
/workspace/coverage/default/21.prim_present_test.2316682395
/workspace/coverage/default/22.prim_present_test.1978554743
/workspace/coverage/default/23.prim_present_test.910425994
/workspace/coverage/default/24.prim_present_test.3085003894
/workspace/coverage/default/25.prim_present_test.3258445382
/workspace/coverage/default/26.prim_present_test.1556464641
/workspace/coverage/default/27.prim_present_test.2691266585
/workspace/coverage/default/28.prim_present_test.2360733040
/workspace/coverage/default/29.prim_present_test.1168240356
/workspace/coverage/default/3.prim_present_test.1739589000
/workspace/coverage/default/30.prim_present_test.2095739660
/workspace/coverage/default/31.prim_present_test.2017154784
/workspace/coverage/default/32.prim_present_test.1647464242
/workspace/coverage/default/33.prim_present_test.3252018837
/workspace/coverage/default/34.prim_present_test.2722680318
/workspace/coverage/default/35.prim_present_test.2231702653
/workspace/coverage/default/36.prim_present_test.2929011835
/workspace/coverage/default/37.prim_present_test.3824747158
/workspace/coverage/default/38.prim_present_test.2946347281
/workspace/coverage/default/39.prim_present_test.697414623
/workspace/coverage/default/4.prim_present_test.3660988574
/workspace/coverage/default/40.prim_present_test.3479194099
/workspace/coverage/default/41.prim_present_test.640495774
/workspace/coverage/default/42.prim_present_test.3638520539
/workspace/coverage/default/43.prim_present_test.3567604856
/workspace/coverage/default/44.prim_present_test.1407712520
/workspace/coverage/default/45.prim_present_test.2029717840
/workspace/coverage/default/46.prim_present_test.1338477658
/workspace/coverage/default/47.prim_present_test.3500157214
/workspace/coverage/default/48.prim_present_test.1677755953
/workspace/coverage/default/49.prim_present_test.650939457
/workspace/coverage/default/5.prim_present_test.2382341098
/workspace/coverage/default/6.prim_present_test.553738672
/workspace/coverage/default/7.prim_present_test.2726038023
/workspace/coverage/default/8.prim_present_test.967058600
/workspace/coverage/default/9.prim_present_test.1124035327



Total test records in report: 50
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/34.prim_present_test.2722680318 Dec 27 12:31:26 PM PST 23 Dec 27 12:32:57 PM PST 23 7397840000 ps
T2 /workspace/coverage/default/8.prim_present_test.967058600 Dec 27 12:31:25 PM PST 23 Dec 27 12:32:56 PM PST 23 7389780000 ps
T3 /workspace/coverage/default/20.prim_present_test.2627224198 Dec 27 12:31:21 PM PST 23 Dec 27 12:32:45 PM PST 23 6076620000 ps
T4 /workspace/coverage/default/21.prim_present_test.2316682395 Dec 27 12:33:27 PM PST 23 Dec 27 12:34:42 PM PST 23 8836240000 ps
T5 /workspace/coverage/default/22.prim_present_test.1978554743 Dec 27 12:31:36 PM PST 23 Dec 27 12:33:22 PM PST 23 10217600000 ps
T6 /workspace/coverage/default/7.prim_present_test.2726038023 Dec 27 12:31:21 PM PST 23 Dec 27 12:33:03 PM PST 23 9471740000 ps
T7 /workspace/coverage/default/17.prim_present_test.2409293874 Dec 27 12:31:31 PM PST 23 Dec 27 12:33:06 PM PST 23 6432500000 ps
T8 /workspace/coverage/default/4.prim_present_test.3660988574 Dec 27 12:33:44 PM PST 23 Dec 27 12:34:43 PM PST 23 7550360000 ps
T9 /workspace/coverage/default/26.prim_present_test.1556464641 Dec 27 12:33:56 PM PST 23 Dec 27 12:34:57 PM PST 23 7443720000 ps
T10 /workspace/coverage/default/38.prim_present_test.2946347281 Dec 27 12:31:26 PM PST 23 Dec 27 12:33:19 PM PST 23 10429020000 ps
T11 /workspace/coverage/default/28.prim_present_test.2360733040 Dec 27 12:31:25 PM PST 23 Dec 27 12:33:06 PM PST 23 9564740000 ps
T12 /workspace/coverage/default/43.prim_present_test.3567604856 Dec 27 12:31:26 PM PST 23 Dec 27 12:32:52 PM PST 23 5263800000 ps
T13 /workspace/coverage/default/6.prim_present_test.553738672 Dec 27 12:31:23 PM PST 23 Dec 27 12:33:42 PM PST 23 15207360000 ps
T14 /workspace/coverage/default/15.prim_present_test.305734372 Dec 27 12:31:25 PM PST 23 Dec 27 12:32:36 PM PST 23 4054800000 ps
T15 /workspace/coverage/default/19.prim_present_test.2246775226 Dec 27 12:32:48 PM PST 23 Dec 27 12:33:59 PM PST 23 6958260000 ps
T16 /workspace/coverage/default/10.prim_present_test.911481692 Dec 27 12:31:22 PM PST 23 Dec 27 12:33:06 PM PST 23 8487180000 ps
T17 /workspace/coverage/default/40.prim_present_test.3479194099 Dec 27 12:31:46 PM PST 23 Dec 27 12:33:25 PM PST 23 9149960000 ps
T18 /workspace/coverage/default/39.prim_present_test.697414623 Dec 27 12:31:57 PM PST 23 Dec 27 12:33:11 PM PST 23 5142900000 ps
T19 /workspace/coverage/default/3.prim_present_test.1739589000 Dec 27 12:31:21 PM PST 23 Dec 27 12:33:18 PM PST 23 12059000000 ps
T20 /workspace/coverage/default/37.prim_present_test.3824747158 Dec 27 12:31:41 PM PST 23 Dec 27 12:33:31 PM PST 23 11699400000 ps
T21 /workspace/coverage/default/44.prim_present_test.1407712520 Dec 27 12:34:05 PM PST 23 Dec 27 12:34:51 PM PST 23 5678580000 ps
T22 /workspace/coverage/default/11.prim_present_test.269011272 Dec 27 12:31:21 PM PST 23 Dec 27 12:33:24 PM PST 23 13961160000 ps
T23 /workspace/coverage/default/47.prim_present_test.3500157214 Dec 27 12:32:48 PM PST 23 Dec 27 12:34:47 PM PST 23 15368560000 ps
T24 /workspace/coverage/default/41.prim_present_test.640495774 Dec 27 12:31:26 PM PST 23 Dec 27 12:32:56 PM PST 23 7630960000 ps
T25 /workspace/coverage/default/9.prim_present_test.1124035327 Dec 27 12:31:21 PM PST 23 Dec 27 12:32:36 PM PST 23 4114940000 ps
T26 /workspace/coverage/default/31.prim_present_test.2017154784 Dec 27 12:31:48 PM PST 23 Dec 27 12:33:19 PM PST 23 8113940000 ps
T27 /workspace/coverage/default/35.prim_present_test.2231702653 Dec 27 12:31:29 PM PST 23 Dec 27 12:33:37 PM PST 23 13003880000 ps
T28 /workspace/coverage/default/42.prim_present_test.3638520539 Dec 27 12:31:33 PM PST 23 Dec 27 12:33:22 PM PST 23 9233040000 ps
T29 /workspace/coverage/default/29.prim_present_test.1168240356 Dec 27 12:31:26 PM PST 23 Dec 27 12:33:38 PM PST 23 14184360000 ps
T30 /workspace/coverage/default/46.prim_present_test.1338477658 Dec 27 12:31:20 PM PST 23 Dec 27 12:33:00 PM PST 23 9367580000 ps
T31 /workspace/coverage/default/16.prim_present_test.3947502334 Dec 27 12:31:43 PM PST 23 Dec 27 12:33:26 PM PST 23 9974560000 ps
T32 /workspace/coverage/default/25.prim_present_test.3258445382 Dec 27 12:31:20 PM PST 23 Dec 27 12:33:09 PM PST 23 10296340000 ps
T33 /workspace/coverage/default/12.prim_present_test.3093932980 Dec 27 12:31:37 PM PST 23 Dec 27 12:33:31 PM PST 23 12207800000 ps
T34 /workspace/coverage/default/14.prim_present_test.1744684473 Dec 27 12:31:36 PM PST 23 Dec 27 12:33:27 PM PST 23 11657860000 ps
T35 /workspace/coverage/default/5.prim_present_test.2382341098 Dec 27 12:33:37 PM PST 23 Dec 27 12:34:38 PM PST 23 7618560000 ps
T36 /workspace/coverage/default/2.prim_present_test.1757662651 Dec 27 12:31:32 PM PST 23 Dec 27 12:32:51 PM PST 23 5136080000 ps
T37 /workspace/coverage/default/23.prim_present_test.910425994 Dec 27 12:31:16 PM PST 23 Dec 27 12:33:19 PM PST 23 13189880000 ps
T38 /workspace/coverage/default/36.prim_present_test.2929011835 Dec 27 12:31:37 PM PST 23 Dec 27 12:33:06 PM PST 23 6951440000 ps
T39 /workspace/coverage/default/18.prim_present_test.4186246436 Dec 27 12:31:35 PM PST 23 Dec 27 12:32:51 PM PST 23 4625200000 ps
T40 /workspace/coverage/default/13.prim_present_test.3869666704 Dec 27 12:31:20 PM PST 23 Dec 27 12:32:40 PM PST 23 4790740000 ps
T41 /workspace/coverage/default/1.prim_present_test.4214406369 Dec 27 12:31:20 PM PST 23 Dec 27 12:33:32 PM PST 23 15214800000 ps
T42 /workspace/coverage/default/24.prim_present_test.3085003894 Dec 27 12:32:53 PM PST 23 Dec 27 12:34:41 PM PST 23 12481840000 ps
T43 /workspace/coverage/default/30.prim_present_test.2095739660 Dec 27 12:31:25 PM PST 23 Dec 27 12:33:20 PM PST 23 10913240000 ps
T44 /workspace/coverage/default/48.prim_present_test.1677755953 Dec 27 12:31:22 PM PST 23 Dec 27 12:33:34 PM PST 23 14958740000 ps
T45 /workspace/coverage/default/27.prim_present_test.2691266585 Dec 27 12:32:52 PM PST 23 Dec 27 12:34:35 PM PST 23 11587800000 ps
T46 /workspace/coverage/default/0.prim_present_test.688650622 Dec 27 12:31:38 PM PST 23 Dec 27 12:33:12 PM PST 23 6629660000 ps
T47 /workspace/coverage/default/32.prim_present_test.1647464242 Dec 27 12:33:26 PM PST 23 Dec 27 12:35:05 PM PST 23 13041080000 ps
T48 /workspace/coverage/default/33.prim_present_test.3252018837 Dec 27 12:31:48 PM PST 23 Dec 27 12:33:07 PM PST 23 6053680000 ps
T49 /workspace/coverage/default/49.prim_present_test.650939457 Dec 27 12:31:22 PM PST 23 Dec 27 12:32:39 PM PST 23 4026900000 ps
T50 /workspace/coverage/default/45.prim_present_test.2029717840 Dec 27 12:31:38 PM PST 23 Dec 27 12:33:05 PM PST 23 6570140000 ps

Test location /workspace/coverage/default/17.prim_present_test.2409293874
Short name T7
Test name
Test status
Simulation time 6432500000 ps
CPU time 24.62 seconds
Started Dec 27 12:31:31 PM PST 23
Finished Dec 27 12:33:06 PM PST 23
Peak memory 144748 kb
Host smart-9107b5ac-8b69-4f00-bec5-685bfc724673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409293874 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.2409293874
Directory /workspace/17.prim_present_test/latest

Test location /workspace/coverage/default/0.prim_present_test.688650622
Short name T46
Test name
Test status
Simulation time 6629660000 ps
CPU time 23.62 seconds
Started Dec 27 12:31:38 PM PST 23
Finished Dec 27 12:33:12 PM PST 23
Peak memory 144744 kb
Host smart-7b42b730-1a0f-4623-84af-523ba0b19e02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688650622 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.688650622
Directory /workspace/0.prim_present_test/latest

Test location /workspace/coverage/default/1.prim_present_test.4214406369
Short name T41
Test name
Test status
Simulation time 15214800000 ps
CPU time 44.44 seconds
Started Dec 27 12:31:20 PM PST 23
Finished Dec 27 12:33:32 PM PST 23
Peak memory 144708 kb
Host smart-ce7f2208-a6a0-4821-957d-864ed02c04aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214406369 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.4214406369
Directory /workspace/1.prim_present_test/latest

Test location /workspace/coverage/default/10.prim_present_test.911481692
Short name T16
Test name
Test status
Simulation time 8487180000 ps
CPU time 29.42 seconds
Started Dec 27 12:31:22 PM PST 23
Finished Dec 27 12:33:06 PM PST 23
Peak memory 144652 kb
Host smart-5e1a9073-e54e-4353-99f2-161be40ae546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911481692 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.911481692
Directory /workspace/10.prim_present_test/latest

Test location /workspace/coverage/default/11.prim_present_test.269011272
Short name T22
Test name
Test status
Simulation time 13961160000 ps
CPU time 39.93 seconds
Started Dec 27 12:31:21 PM PST 23
Finished Dec 27 12:33:24 PM PST 23
Peak memory 144668 kb
Host smart-891b916b-c029-4746-a16f-3982c59a61da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269011272 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.269011272
Directory /workspace/11.prim_present_test/latest

Test location /workspace/coverage/default/12.prim_present_test.3093932980
Short name T33
Test name
Test status
Simulation time 12207800000 ps
CPU time 35.24 seconds
Started Dec 27 12:31:37 PM PST 23
Finished Dec 27 12:33:31 PM PST 23
Peak memory 144664 kb
Host smart-f120b81d-068a-4b14-9d6a-055f7a4de0bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093932980 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.3093932980
Directory /workspace/12.prim_present_test/latest

Test location /workspace/coverage/default/13.prim_present_test.3869666704
Short name T40
Test name
Test status
Simulation time 4790740000 ps
CPU time 16.35 seconds
Started Dec 27 12:31:20 PM PST 23
Finished Dec 27 12:32:40 PM PST 23
Peak memory 144644 kb
Host smart-8dbfbbc9-c338-452a-858e-57e87f155ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869666704 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.3869666704
Directory /workspace/13.prim_present_test/latest

Test location /workspace/coverage/default/14.prim_present_test.1744684473
Short name T34
Test name
Test status
Simulation time 11657860000 ps
CPU time 33.42 seconds
Started Dec 27 12:31:36 PM PST 23
Finished Dec 27 12:33:27 PM PST 23
Peak memory 144732 kb
Host smart-ad8d1bc0-b185-4027-8868-9cc30886a8d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744684473 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.1744684473
Directory /workspace/14.prim_present_test/latest

Test location /workspace/coverage/default/15.prim_present_test.305734372
Short name T14
Test name
Test status
Simulation time 4054800000 ps
CPU time 11.85 seconds
Started Dec 27 12:31:25 PM PST 23
Finished Dec 27 12:32:36 PM PST 23
Peak memory 144472 kb
Host smart-dd718a2f-3522-4a81-8c52-a8cd44cdea59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305734372 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.305734372
Directory /workspace/15.prim_present_test/latest

Test location /workspace/coverage/default/16.prim_present_test.3947502334
Short name T31
Test name
Test status
Simulation time 9974560000 ps
CPU time 29.7 seconds
Started Dec 27 12:31:43 PM PST 23
Finished Dec 27 12:33:26 PM PST 23
Peak memory 144720 kb
Host smart-cf59339c-70e0-4539-b80c-097891739c7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947502334 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.3947502334
Directory /workspace/16.prim_present_test/latest

Test location /workspace/coverage/default/18.prim_present_test.4186246436
Short name T39
Test name
Test status
Simulation time 4625200000 ps
CPU time 14.31 seconds
Started Dec 27 12:31:35 PM PST 23
Finished Dec 27 12:32:51 PM PST 23
Peak memory 144652 kb
Host smart-a6579f09-2a13-4345-9bcb-5db24c36928e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186246436 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.4186246436
Directory /workspace/18.prim_present_test/latest

Test location /workspace/coverage/default/19.prim_present_test.2246775226
Short name T15
Test name
Test status
Simulation time 6958260000 ps
CPU time 20 seconds
Started Dec 27 12:32:48 PM PST 23
Finished Dec 27 12:33:59 PM PST 23
Peak memory 142760 kb
Host smart-170a96f8-660f-4f91-88ec-edb2c04613bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246775226 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.2246775226
Directory /workspace/19.prim_present_test/latest

Test location /workspace/coverage/default/2.prim_present_test.1757662651
Short name T36
Test name
Test status
Simulation time 5136080000 ps
CPU time 15.38 seconds
Started Dec 27 12:31:32 PM PST 23
Finished Dec 27 12:32:51 PM PST 23
Peak memory 144728 kb
Host smart-1b571537-d3ce-4ccf-ae05-3e32136eff78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757662651 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.1757662651
Directory /workspace/2.prim_present_test/latest

Test location /workspace/coverage/default/20.prim_present_test.2627224198
Short name T3
Test name
Test status
Simulation time 6076620000 ps
CPU time 18.34 seconds
Started Dec 27 12:31:21 PM PST 23
Finished Dec 27 12:32:45 PM PST 23
Peak memory 144736 kb
Host smart-5ba08da6-a56e-4ea6-8d4a-8f79e2fa156b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627224198 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.2627224198
Directory /workspace/20.prim_present_test/latest

Test location /workspace/coverage/default/21.prim_present_test.2316682395
Short name T4
Test name
Test status
Simulation time 8836240000 ps
CPU time 29.43 seconds
Started Dec 27 12:33:27 PM PST 23
Finished Dec 27 12:34:42 PM PST 23
Peak memory 144436 kb
Host smart-2cf6e17f-c91d-4a1b-af35-46ee3afe8f5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316682395 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.2316682395
Directory /workspace/21.prim_present_test/latest

Test location /workspace/coverage/default/22.prim_present_test.1978554743
Short name T5
Test name
Test status
Simulation time 10217600000 ps
CPU time 30.32 seconds
Started Dec 27 12:31:36 PM PST 23
Finished Dec 27 12:33:22 PM PST 23
Peak memory 144632 kb
Host smart-8cf8f988-167b-47c8-a525-703ec3ad63b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978554743 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.1978554743
Directory /workspace/22.prim_present_test/latest

Test location /workspace/coverage/default/23.prim_present_test.910425994
Short name T37
Test name
Test status
Simulation time 13189880000 ps
CPU time 40.4 seconds
Started Dec 27 12:31:16 PM PST 23
Finished Dec 27 12:33:19 PM PST 23
Peak memory 144620 kb
Host smart-09f6dfdc-a228-4d1b-8c3b-700b3d75dbbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910425994 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.910425994
Directory /workspace/23.prim_present_test/latest

Test location /workspace/coverage/default/24.prim_present_test.3085003894
Short name T42
Test name
Test status
Simulation time 12481840000 ps
CPU time 40.89 seconds
Started Dec 27 12:32:53 PM PST 23
Finished Dec 27 12:34:41 PM PST 23
Peak memory 144324 kb
Host smart-48ab4f67-28e6-4659-8dbe-a456917d7f52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085003894 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.3085003894
Directory /workspace/24.prim_present_test/latest

Test location /workspace/coverage/default/25.prim_present_test.3258445382
Short name T32
Test name
Test status
Simulation time 10296340000 ps
CPU time 32.55 seconds
Started Dec 27 12:31:20 PM PST 23
Finished Dec 27 12:33:09 PM PST 23
Peak memory 144664 kb
Host smart-80f86f87-1751-46bb-a656-de4762f1eb88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258445382 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.3258445382
Directory /workspace/25.prim_present_test/latest

Test location /workspace/coverage/default/26.prim_present_test.1556464641
Short name T9
Test name
Test status
Simulation time 7443720000 ps
CPU time 24.72 seconds
Started Dec 27 12:33:56 PM PST 23
Finished Dec 27 12:34:57 PM PST 23
Peak memory 144588 kb
Host smart-c9ba8564-f743-4ca0-88bc-0af4a7e8bbda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556464641 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.1556464641
Directory /workspace/26.prim_present_test/latest

Test location /workspace/coverage/default/27.prim_present_test.2691266585
Short name T45
Test name
Test status
Simulation time 11587800000 ps
CPU time 38.34 seconds
Started Dec 27 12:32:52 PM PST 23
Finished Dec 27 12:34:35 PM PST 23
Peak memory 143648 kb
Host smart-bd4934bf-e267-49fe-9c9e-53593f904d76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691266585 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.2691266585
Directory /workspace/27.prim_present_test/latest

Test location /workspace/coverage/default/28.prim_present_test.2360733040
Short name T11
Test name
Test status
Simulation time 9564740000 ps
CPU time 27.6 seconds
Started Dec 27 12:31:25 PM PST 23
Finished Dec 27 12:33:06 PM PST 23
Peak memory 144628 kb
Host smart-39fa32fe-f991-4c3f-9c44-5f18accda32c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360733040 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.2360733040
Directory /workspace/28.prim_present_test/latest

Test location /workspace/coverage/default/29.prim_present_test.1168240356
Short name T29
Test name
Test status
Simulation time 14184360000 ps
CPU time 45.45 seconds
Started Dec 27 12:31:26 PM PST 23
Finished Dec 27 12:33:38 PM PST 23
Peak memory 144664 kb
Host smart-8156efa3-aec9-4a90-8a6e-88a429fbe643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168240356 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.1168240356
Directory /workspace/29.prim_present_test/latest

Test location /workspace/coverage/default/3.prim_present_test.1739589000
Short name T19
Test name
Test status
Simulation time 12059000000 ps
CPU time 36.6 seconds
Started Dec 27 12:31:21 PM PST 23
Finished Dec 27 12:33:18 PM PST 23
Peak memory 144628 kb
Host smart-645ff85d-29d1-43a7-9cab-7a9364771790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739589000 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.1739589000
Directory /workspace/3.prim_present_test/latest

Test location /workspace/coverage/default/30.prim_present_test.2095739660
Short name T43
Test name
Test status
Simulation time 10913240000 ps
CPU time 35.79 seconds
Started Dec 27 12:31:25 PM PST 23
Finished Dec 27 12:33:20 PM PST 23
Peak memory 144748 kb
Host smart-748143bd-2691-468f-a86b-64c891d194e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095739660 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.2095739660
Directory /workspace/30.prim_present_test/latest

Test location /workspace/coverage/default/31.prim_present_test.2017154784
Short name T26
Test name
Test status
Simulation time 8113940000 ps
CPU time 23.61 seconds
Started Dec 27 12:31:48 PM PST 23
Finished Dec 27 12:33:19 PM PST 23
Peak memory 144628 kb
Host smart-fb399af2-3b92-4e1e-9464-2042dca371db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017154784 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.2017154784
Directory /workspace/31.prim_present_test/latest

Test location /workspace/coverage/default/32.prim_present_test.1647464242
Short name T47
Test name
Test status
Simulation time 13041080000 ps
CPU time 42.56 seconds
Started Dec 27 12:33:26 PM PST 23
Finished Dec 27 12:35:05 PM PST 23
Peak memory 144356 kb
Host smart-237cd55e-b969-49b7-969d-fa515f2b1dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647464242 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.1647464242
Directory /workspace/32.prim_present_test/latest

Test location /workspace/coverage/default/33.prim_present_test.3252018837
Short name T48
Test name
Test status
Simulation time 6053680000 ps
CPU time 17.82 seconds
Started Dec 27 12:31:48 PM PST 23
Finished Dec 27 12:33:07 PM PST 23
Peak memory 144596 kb
Host smart-7fc8fa8a-a3b2-4e31-b7ca-4fe3da35249a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252018837 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.3252018837
Directory /workspace/33.prim_present_test/latest

Test location /workspace/coverage/default/34.prim_present_test.2722680318
Short name T1
Test name
Test status
Simulation time 7397840000 ps
CPU time 22.38 seconds
Started Dec 27 12:31:26 PM PST 23
Finished Dec 27 12:32:57 PM PST 23
Peak memory 144660 kb
Host smart-026dc87a-c62e-4052-86c8-d8c6bf2ed02e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722680318 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.2722680318
Directory /workspace/34.prim_present_test/latest

Test location /workspace/coverage/default/35.prim_present_test.2231702653
Short name T27
Test name
Test status
Simulation time 13003880000 ps
CPU time 42.19 seconds
Started Dec 27 12:31:29 PM PST 23
Finished Dec 27 12:33:37 PM PST 23
Peak memory 144664 kb
Host smart-43683cdc-4b29-41c2-8fd2-444c7a4bffff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231702653 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.2231702653
Directory /workspace/35.prim_present_test/latest

Test location /workspace/coverage/default/36.prim_present_test.2929011835
Short name T38
Test name
Test status
Simulation time 6951440000 ps
CPU time 20.72 seconds
Started Dec 27 12:31:37 PM PST 23
Finished Dec 27 12:33:06 PM PST 23
Peak memory 144644 kb
Host smart-396114c8-4041-41d7-a52b-1e0b45abeaa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929011835 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.2929011835
Directory /workspace/36.prim_present_test/latest

Test location /workspace/coverage/default/37.prim_present_test.3824747158
Short name T20
Test name
Test status
Simulation time 11699400000 ps
CPU time 33.43 seconds
Started Dec 27 12:31:41 PM PST 23
Finished Dec 27 12:33:31 PM PST 23
Peak memory 144644 kb
Host smart-d9339dfb-d784-4df7-aa95-f7ff1a79fc82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824747158 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.3824747158
Directory /workspace/37.prim_present_test/latest

Test location /workspace/coverage/default/38.prim_present_test.2946347281
Short name T10
Test name
Test status
Simulation time 10429020000 ps
CPU time 35.37 seconds
Started Dec 27 12:31:26 PM PST 23
Finished Dec 27 12:33:19 PM PST 23
Peak memory 144664 kb
Host smart-f1adc021-41e7-4192-9080-7fe806957ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946347281 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.2946347281
Directory /workspace/38.prim_present_test/latest

Test location /workspace/coverage/default/39.prim_present_test.697414623
Short name T18
Test name
Test status
Simulation time 5142900000 ps
CPU time 15.94 seconds
Started Dec 27 12:31:57 PM PST 23
Finished Dec 27 12:33:11 PM PST 23
Peak memory 144684 kb
Host smart-fa5ee790-c5fc-4270-9432-358842240628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697414623 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.697414623
Directory /workspace/39.prim_present_test/latest

Test location /workspace/coverage/default/4.prim_present_test.3660988574
Short name T8
Test name
Test status
Simulation time 7550360000 ps
CPU time 24.46 seconds
Started Dec 27 12:33:44 PM PST 23
Finished Dec 27 12:34:43 PM PST 23
Peak memory 144400 kb
Host smart-4a135f37-d868-4107-afdf-eae6f6f8cbd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660988574 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.3660988574
Directory /workspace/4.prim_present_test/latest

Test location /workspace/coverage/default/40.prim_present_test.3479194099
Short name T17
Test name
Test status
Simulation time 9149960000 ps
CPU time 28.4 seconds
Started Dec 27 12:31:46 PM PST 23
Finished Dec 27 12:33:25 PM PST 23
Peak memory 144660 kb
Host smart-1ded071e-4473-4676-adbf-0da0f1100a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479194099 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.3479194099
Directory /workspace/40.prim_present_test/latest

Test location /workspace/coverage/default/41.prim_present_test.640495774
Short name T24
Test name
Test status
Simulation time 7630960000 ps
CPU time 21.8 seconds
Started Dec 27 12:31:26 PM PST 23
Finished Dec 27 12:32:56 PM PST 23
Peak memory 144660 kb
Host smart-e60e118a-93b3-4a71-96b2-701110a67220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640495774 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.640495774
Directory /workspace/41.prim_present_test/latest

Test location /workspace/coverage/default/42.prim_present_test.3638520539
Short name T28
Test name
Test status
Simulation time 9233040000 ps
CPU time 31.31 seconds
Started Dec 27 12:31:33 PM PST 23
Finished Dec 27 12:33:22 PM PST 23
Peak memory 144744 kb
Host smart-cf22b798-3ffa-4716-839f-8a5d5db4d1c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638520539 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.3638520539
Directory /workspace/42.prim_present_test/latest

Test location /workspace/coverage/default/43.prim_present_test.3567604856
Short name T12
Test name
Test status
Simulation time 5263800000 ps
CPU time 19.56 seconds
Started Dec 27 12:31:26 PM PST 23
Finished Dec 27 12:32:52 PM PST 23
Peak memory 144748 kb
Host smart-86c0c92e-24db-4819-b93e-581eb24ca44b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567604856 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.3567604856
Directory /workspace/43.prim_present_test/latest

Test location /workspace/coverage/default/44.prim_present_test.1407712520
Short name T21
Test name
Test status
Simulation time 5678580000 ps
CPU time 16.95 seconds
Started Dec 27 12:34:05 PM PST 23
Finished Dec 27 12:34:51 PM PST 23
Peak memory 144648 kb
Host smart-b9ea9b56-2821-4a80-8ebf-1cccb75db661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407712520 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.1407712520
Directory /workspace/44.prim_present_test/latest

Test location /workspace/coverage/default/45.prim_present_test.2029717840
Short name T50
Test name
Test status
Simulation time 6570140000 ps
CPU time 19.52 seconds
Started Dec 27 12:31:38 PM PST 23
Finished Dec 27 12:33:05 PM PST 23
Peak memory 144616 kb
Host smart-fcbc6965-854f-4462-9085-49ff3ba47182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029717840 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.2029717840
Directory /workspace/45.prim_present_test/latest

Test location /workspace/coverage/default/46.prim_present_test.1338477658
Short name T30
Test name
Test status
Simulation time 9367580000 ps
CPU time 28.38 seconds
Started Dec 27 12:31:20 PM PST 23
Finished Dec 27 12:33:00 PM PST 23
Peak memory 144648 kb
Host smart-363762bc-2b3d-4b50-95d1-757fe34b1862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338477658 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.1338477658
Directory /workspace/46.prim_present_test/latest

Test location /workspace/coverage/default/47.prim_present_test.3500157214
Short name T23
Test name
Test status
Simulation time 15368560000 ps
CPU time 47.17 seconds
Started Dec 27 12:32:48 PM PST 23
Finished Dec 27 12:34:47 PM PST 23
Peak memory 142716 kb
Host smart-3b3869c6-9afa-4de5-a8f5-70f21a42b784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500157214 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.3500157214
Directory /workspace/47.prim_present_test/latest

Test location /workspace/coverage/default/48.prim_present_test.1677755953
Short name T44
Test name
Test status
Simulation time 14958740000 ps
CPU time 44.5 seconds
Started Dec 27 12:31:22 PM PST 23
Finished Dec 27 12:33:34 PM PST 23
Peak memory 144644 kb
Host smart-3d612d60-db74-451d-9c91-66e24e491502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677755953 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.1677755953
Directory /workspace/48.prim_present_test/latest

Test location /workspace/coverage/default/49.prim_present_test.650939457
Short name T49
Test name
Test status
Simulation time 4026900000 ps
CPU time 13.97 seconds
Started Dec 27 12:31:22 PM PST 23
Finished Dec 27 12:32:39 PM PST 23
Peak memory 144536 kb
Host smart-bdc55b33-a5a1-4a6f-ab7e-b167b11fc6a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650939457 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.650939457
Directory /workspace/49.prim_present_test/latest

Test location /workspace/coverage/default/5.prim_present_test.2382341098
Short name T35
Test name
Test status
Simulation time 7618560000 ps
CPU time 25.06 seconds
Started Dec 27 12:33:37 PM PST 23
Finished Dec 27 12:34:38 PM PST 23
Peak memory 144132 kb
Host smart-c639d9e3-cbc0-4b35-911e-b4c0bca29fbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382341098 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.2382341098
Directory /workspace/5.prim_present_test/latest

Test location /workspace/coverage/default/6.prim_present_test.553738672
Short name T13
Test name
Test status
Simulation time 15207360000 ps
CPU time 48.5 seconds
Started Dec 27 12:31:23 PM PST 23
Finished Dec 27 12:33:42 PM PST 23
Peak memory 144616 kb
Host smart-d11239b2-945b-4b41-b6b7-95939ca86270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553738672 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.553738672
Directory /workspace/6.prim_present_test/latest

Test location /workspace/coverage/default/7.prim_present_test.2726038023
Short name T6
Test name
Test status
Simulation time 9471740000 ps
CPU time 28.08 seconds
Started Dec 27 12:31:21 PM PST 23
Finished Dec 27 12:33:03 PM PST 23
Peak memory 144668 kb
Host smart-950cced9-7d72-4167-a94e-fd79761d03dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726038023 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.2726038023
Directory /workspace/7.prim_present_test/latest

Test location /workspace/coverage/default/8.prim_present_test.967058600
Short name T2
Test name
Test status
Simulation time 7389780000 ps
CPU time 22 seconds
Started Dec 27 12:31:25 PM PST 23
Finished Dec 27 12:32:56 PM PST 23
Peak memory 144632 kb
Host smart-2601d16a-743a-4e83-9a04-ed6159a9c37b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967058600 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.967058600
Directory /workspace/8.prim_present_test/latest

Test location /workspace/coverage/default/9.prim_present_test.1124035327
Short name T25
Test name
Test status
Simulation time 4114940000 ps
CPU time 13.84 seconds
Started Dec 27 12:31:21 PM PST 23
Finished Dec 27 12:32:36 PM PST 23
Peak memory 144492 kb
Host smart-c5019d69-8665-4726-b582-568c792b6005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124035327 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.1124035327
Directory /workspace/9.prim_present_test/latest
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