Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.83 90.41 100.00 98.73 100.00 100.00


Total tests in report: 50
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
97.83 97.83 90.41 90.41 100.00 100.00 98.73 98.73 100.00 100.00 100.00 100.00 /workspace/coverage/default/22.prim_present_test.4057280016

Tests that do not contribute to grading

Name
/workspace/coverage/default/0.prim_present_test.705618080
/workspace/coverage/default/1.prim_present_test.3438949456
/workspace/coverage/default/10.prim_present_test.635893734
/workspace/coverage/default/11.prim_present_test.2664786237
/workspace/coverage/default/12.prim_present_test.3607148451
/workspace/coverage/default/13.prim_present_test.2977663238
/workspace/coverage/default/14.prim_present_test.2302328428
/workspace/coverage/default/15.prim_present_test.4230390779
/workspace/coverage/default/16.prim_present_test.845763010
/workspace/coverage/default/17.prim_present_test.1276805174
/workspace/coverage/default/18.prim_present_test.3936246084
/workspace/coverage/default/19.prim_present_test.399022447
/workspace/coverage/default/2.prim_present_test.430133879
/workspace/coverage/default/20.prim_present_test.2324934955
/workspace/coverage/default/21.prim_present_test.2637440590
/workspace/coverage/default/23.prim_present_test.1350831802
/workspace/coverage/default/24.prim_present_test.2795775685
/workspace/coverage/default/25.prim_present_test.2551344263
/workspace/coverage/default/26.prim_present_test.3245359335
/workspace/coverage/default/27.prim_present_test.3675420020
/workspace/coverage/default/28.prim_present_test.937121168
/workspace/coverage/default/29.prim_present_test.369402204
/workspace/coverage/default/3.prim_present_test.1810626775
/workspace/coverage/default/30.prim_present_test.3054308405
/workspace/coverage/default/31.prim_present_test.2439561868
/workspace/coverage/default/32.prim_present_test.3498265702
/workspace/coverage/default/33.prim_present_test.1165089778
/workspace/coverage/default/34.prim_present_test.100987696
/workspace/coverage/default/35.prim_present_test.4026041692
/workspace/coverage/default/36.prim_present_test.3600492151
/workspace/coverage/default/37.prim_present_test.19795377
/workspace/coverage/default/38.prim_present_test.227138444
/workspace/coverage/default/39.prim_present_test.2203850377
/workspace/coverage/default/4.prim_present_test.3018355666
/workspace/coverage/default/40.prim_present_test.1723333973
/workspace/coverage/default/41.prim_present_test.201015195
/workspace/coverage/default/42.prim_present_test.447573938
/workspace/coverage/default/43.prim_present_test.2177731455
/workspace/coverage/default/44.prim_present_test.3465213016
/workspace/coverage/default/45.prim_present_test.3726847195
/workspace/coverage/default/46.prim_present_test.790651916
/workspace/coverage/default/47.prim_present_test.2951157398
/workspace/coverage/default/48.prim_present_test.619425763
/workspace/coverage/default/49.prim_present_test.936371835
/workspace/coverage/default/5.prim_present_test.2701668263
/workspace/coverage/default/6.prim_present_test.398247859
/workspace/coverage/default/7.prim_present_test.733601016
/workspace/coverage/default/8.prim_present_test.1157489422
/workspace/coverage/default/9.prim_present_test.2003157018



Total test records in report: 50
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/22.prim_present_test.4057280016 Dec 31 12:40:19 PM PST 23 Dec 31 12:40:50 PM PST 23 4424940000 ps
T2 /workspace/coverage/default/25.prim_present_test.2551344263 Dec 31 12:40:03 PM PST 23 Dec 31 12:41:34 PM PST 23 15033140000 ps
T3 /workspace/coverage/default/37.prim_present_test.19795377 Dec 31 12:39:57 PM PST 23 Dec 31 12:40:47 PM PST 23 8143080000 ps
T4 /workspace/coverage/default/30.prim_present_test.3054308405 Dec 31 12:40:23 PM PST 23 Dec 31 12:41:20 PM PST 23 8914360000 ps
T5 /workspace/coverage/default/5.prim_present_test.2701668263 Dec 31 12:40:03 PM PST 23 Dec 31 12:40:53 PM PST 23 7526800000 ps
T6 /workspace/coverage/default/7.prim_present_test.733601016 Dec 31 12:39:46 PM PST 23 Dec 31 12:40:41 PM PST 23 9741440000 ps
T7 /workspace/coverage/default/43.prim_present_test.2177731455 Dec 31 12:40:05 PM PST 23 Dec 31 12:41:26 PM PST 23 14587980000 ps
T8 /workspace/coverage/default/45.prim_present_test.3726847195 Dec 31 12:40:10 PM PST 23 Dec 31 12:40:35 PM PST 23 4240800000 ps
T9 /workspace/coverage/default/41.prim_present_test.201015195 Dec 31 12:39:56 PM PST 23 Dec 31 12:40:18 PM PST 23 3436040000 ps
T10 /workspace/coverage/default/26.prim_present_test.3245359335 Dec 31 12:39:45 PM PST 23 Dec 31 12:40:42 PM PST 23 8924900000 ps
T11 /workspace/coverage/default/14.prim_present_test.2302328428 Dec 31 12:40:09 PM PST 23 Dec 31 12:41:01 PM PST 23 8562200000 ps
T12 /workspace/coverage/default/4.prim_present_test.3018355666 Dec 31 12:40:30 PM PST 23 Dec 31 12:41:53 PM PST 23 13683400000 ps
T13 /workspace/coverage/default/39.prim_present_test.2203850377 Dec 31 12:40:01 PM PST 23 Dec 31 12:41:15 PM PST 23 10695620000 ps
T14 /workspace/coverage/default/17.prim_present_test.1276805174 Dec 31 12:40:09 PM PST 23 Dec 31 12:41:58 PM PST 23 14333780000 ps
T15 /workspace/coverage/default/48.prim_present_test.619425763 Dec 31 12:40:14 PM PST 23 Dec 31 12:40:41 PM PST 23 4005200000 ps
T16 /workspace/coverage/default/11.prim_present_test.2664786237 Dec 31 12:40:11 PM PST 23 Dec 31 12:40:37 PM PST 23 4478880000 ps
T17 /workspace/coverage/default/24.prim_present_test.2795775685 Dec 31 12:40:12 PM PST 23 Dec 31 12:40:49 PM PST 23 6332680000 ps
T18 /workspace/coverage/default/29.prim_present_test.369402204 Dec 31 12:39:53 PM PST 23 Dec 31 12:40:15 PM PST 23 3599720000 ps
T19 /workspace/coverage/default/9.prim_present_test.2003157018 Dec 31 12:40:00 PM PST 23 Dec 31 12:41:19 PM PST 23 13976660000 ps
T20 /workspace/coverage/default/46.prim_present_test.790651916 Dec 31 12:39:50 PM PST 23 Dec 31 12:40:43 PM PST 23 8235460000 ps
T21 /workspace/coverage/default/40.prim_present_test.1723333973 Dec 31 12:40:24 PM PST 23 Dec 31 12:41:40 PM PST 23 11887880000 ps
T22 /workspace/coverage/default/21.prim_present_test.2637440590 Dec 31 12:40:04 PM PST 23 Dec 31 12:41:31 PM PST 23 15177600000 ps
T23 /workspace/coverage/default/10.prim_present_test.635893734 Dec 31 12:40:08 PM PST 23 Dec 31 12:40:40 PM PST 23 5776540000 ps
T24 /workspace/coverage/default/32.prim_present_test.3498265702 Dec 31 12:40:13 PM PST 23 Dec 31 12:40:38 PM PST 23 3609020000 ps
T25 /workspace/coverage/default/28.prim_present_test.937121168 Dec 31 12:40:04 PM PST 23 Dec 31 12:40:51 PM PST 23 8743240000 ps
T26 /workspace/coverage/default/16.prim_present_test.845763010 Dec 31 12:40:04 PM PST 23 Dec 31 12:41:10 PM PST 23 11275320000 ps
T27 /workspace/coverage/default/23.prim_present_test.1350831802 Dec 31 12:40:13 PM PST 23 Dec 31 12:41:15 PM PST 23 9378740000 ps
T28 /workspace/coverage/default/27.prim_present_test.3675420020 Dec 31 12:40:02 PM PST 23 Dec 31 12:41:04 PM PST 23 11576640000 ps
T29 /workspace/coverage/default/3.prim_present_test.1810626775 Dec 31 12:40:09 PM PST 23 Dec 31 12:41:14 PM PST 23 11029180000 ps
T30 /workspace/coverage/default/13.prim_present_test.2977663238 Dec 31 12:40:02 PM PST 23 Dec 31 12:40:59 PM PST 23 9984480000 ps
T31 /workspace/coverage/default/19.prim_present_test.399022447 Dec 31 12:39:59 PM PST 23 Dec 31 12:40:22 PM PST 23 3589800000 ps
T32 /workspace/coverage/default/2.prim_present_test.430133879 Dec 31 12:39:58 PM PST 23 Dec 31 12:41:19 PM PST 23 14533420000 ps
T33 /workspace/coverage/default/18.prim_present_test.3936246084 Dec 31 12:40:09 PM PST 23 Dec 31 12:40:38 PM PST 23 4840960000 ps
T34 /workspace/coverage/default/1.prim_present_test.3438949456 Dec 31 12:40:09 PM PST 23 Dec 31 12:41:30 PM PST 23 14206060000 ps
T35 /workspace/coverage/default/20.prim_present_test.2324934955 Dec 31 12:39:54 PM PST 23 Dec 31 12:41:09 PM PST 23 13719980000 ps
T36 /workspace/coverage/default/6.prim_present_test.398247859 Dec 31 12:39:50 PM PST 23 Dec 31 12:40:11 PM PST 23 3569960000 ps
T37 /workspace/coverage/default/44.prim_present_test.3465213016 Dec 31 12:40:02 PM PST 23 Dec 31 12:40:46 PM PST 23 7846720000 ps
T38 /workspace/coverage/default/35.prim_present_test.4026041692 Dec 31 12:39:50 PM PST 23 Dec 31 12:41:00 PM PST 23 10721660000 ps
T39 /workspace/coverage/default/15.prim_present_test.4230390779 Dec 31 12:40:10 PM PST 23 Dec 31 12:40:44 PM PST 23 5697800000 ps
T40 /workspace/coverage/default/38.prim_present_test.227138444 Dec 31 12:39:47 PM PST 23 Dec 31 12:41:01 PM PST 23 11375140000 ps
T41 /workspace/coverage/default/36.prim_present_test.3600492151 Dec 31 12:40:12 PM PST 23 Dec 31 12:41:39 PM PST 23 14689040000 ps
T42 /workspace/coverage/default/8.prim_present_test.1157489422 Dec 31 12:39:47 PM PST 23 Dec 31 12:40:39 PM PST 23 8843680000 ps
T43 /workspace/coverage/default/47.prim_present_test.2951157398 Dec 31 12:40:14 PM PST 23 Dec 31 12:41:24 PM PST 23 12119760000 ps
T44 /workspace/coverage/default/42.prim_present_test.447573938 Dec 31 12:40:05 PM PST 23 Dec 31 12:40:40 PM PST 23 6380420000 ps
T45 /workspace/coverage/default/49.prim_present_test.936371835 Dec 31 12:40:09 PM PST 23 Dec 31 12:40:29 PM PST 23 3160760000 ps
T46 /workspace/coverage/default/31.prim_present_test.2439561868 Dec 31 12:40:19 PM PST 23 Dec 31 12:41:19 PM PST 23 9448800000 ps
T47 /workspace/coverage/default/0.prim_present_test.705618080 Dec 31 12:40:06 PM PST 23 Dec 31 12:40:33 PM PST 23 4384020000 ps
T48 /workspace/coverage/default/33.prim_present_test.1165089778 Dec 31 12:40:09 PM PST 23 Dec 31 12:40:43 PM PST 23 5810020000 ps
T49 /workspace/coverage/default/34.prim_present_test.100987696 Dec 31 12:39:57 PM PST 23 Dec 31 12:41:27 PM PST 23 15445440000 ps
T50 /workspace/coverage/default/12.prim_present_test.3607148451 Dec 31 12:40:27 PM PST 23 Dec 31 12:41:41 PM PST 23 12519040000 ps

Test location /workspace/coverage/default/22.prim_present_test.4057280016
Short name T1
Test name
Test status
Simulation time 4424940000 ps
CPU time 15.07 seconds
Started Dec 31 12:40:19 PM PST 23
Finished Dec 31 12:40:50 PM PST 23
Peak memory 144608 kb
Host smart-fbcf4a73-10d8-4c93-a2e7-3b646fea29a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057280016 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.4057280016
Directory /workspace/22.prim_present_test/latest

Test location /workspace/coverage/default/0.prim_present_test.705618080
Short name T47
Test name
Test status
Simulation time 4384020000 ps
CPU time 14.89 seconds
Started Dec 31 12:40:06 PM PST 23
Finished Dec 31 12:40:33 PM PST 23
Peak memory 144636 kb
Host smart-0b12bd17-0732-498b-b4e9-abf1c92aa007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705618080 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.705618080
Directory /workspace/0.prim_present_test/latest

Test location /workspace/coverage/default/1.prim_present_test.3438949456
Short name T34
Test name
Test status
Simulation time 14206060000 ps
CPU time 43.83 seconds
Started Dec 31 12:40:09 PM PST 23
Finished Dec 31 12:41:30 PM PST 23
Peak memory 144656 kb
Host smart-6fb7f5b1-2650-42c2-b1a1-3a2fd4c084e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438949456 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.3438949456
Directory /workspace/1.prim_present_test/latest

Test location /workspace/coverage/default/10.prim_present_test.635893734
Short name T23
Test name
Test status
Simulation time 5776540000 ps
CPU time 17.72 seconds
Started Dec 31 12:40:08 PM PST 23
Finished Dec 31 12:40:40 PM PST 23
Peak memory 144632 kb
Host smart-48493a7e-3e38-4924-98bf-5b93ad8d522f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635893734 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.635893734
Directory /workspace/10.prim_present_test/latest

Test location /workspace/coverage/default/11.prim_present_test.2664786237
Short name T16
Test name
Test status
Simulation time 4478880000 ps
CPU time 14.07 seconds
Started Dec 31 12:40:11 PM PST 23
Finished Dec 31 12:40:37 PM PST 23
Peak memory 144728 kb
Host smart-2b1c5c86-e2e2-4314-93dd-80b9a999da42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664786237 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.2664786237
Directory /workspace/11.prim_present_test/latest

Test location /workspace/coverage/default/12.prim_present_test.3607148451
Short name T50
Test name
Test status
Simulation time 12519040000 ps
CPU time 39.4 seconds
Started Dec 31 12:40:27 PM PST 23
Finished Dec 31 12:41:41 PM PST 23
Peak memory 144612 kb
Host smart-9f8d787c-2763-4b74-bc24-80c150145710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607148451 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.3607148451
Directory /workspace/12.prim_present_test/latest

Test location /workspace/coverage/default/13.prim_present_test.2977663238
Short name T30
Test name
Test status
Simulation time 9984480000 ps
CPU time 31.33 seconds
Started Dec 31 12:40:02 PM PST 23
Finished Dec 31 12:40:59 PM PST 23
Peak memory 144676 kb
Host smart-1a3c80a9-480a-4285-88dd-ad3482040fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977663238 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.2977663238
Directory /workspace/13.prim_present_test/latest

Test location /workspace/coverage/default/14.prim_present_test.2302328428
Short name T11
Test name
Test status
Simulation time 8562200000 ps
CPU time 27.18 seconds
Started Dec 31 12:40:09 PM PST 23
Finished Dec 31 12:41:01 PM PST 23
Peak memory 144692 kb
Host smart-217faac0-e0c2-4c8e-b1c3-caff0a6ba4d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302328428 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.2302328428
Directory /workspace/14.prim_present_test/latest

Test location /workspace/coverage/default/15.prim_present_test.4230390779
Short name T39
Test name
Test status
Simulation time 5697800000 ps
CPU time 18.49 seconds
Started Dec 31 12:40:10 PM PST 23
Finished Dec 31 12:40:44 PM PST 23
Peak memory 144636 kb
Host smart-fd200e71-063e-4c71-a9c8-e34c388391c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230390779 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.4230390779
Directory /workspace/15.prim_present_test/latest

Test location /workspace/coverage/default/16.prim_present_test.845763010
Short name T26
Test name
Test status
Simulation time 11275320000 ps
CPU time 35.74 seconds
Started Dec 31 12:40:04 PM PST 23
Finished Dec 31 12:41:10 PM PST 23
Peak memory 144672 kb
Host smart-51d8b577-15ee-48be-9fcb-b7aefc96a369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845763010 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.845763010
Directory /workspace/16.prim_present_test/latest

Test location /workspace/coverage/default/17.prim_present_test.1276805174
Short name T14
Test name
Test status
Simulation time 14333780000 ps
CPU time 57.79 seconds
Started Dec 31 12:40:09 PM PST 23
Finished Dec 31 12:41:58 PM PST 23
Peak memory 144692 kb
Host smart-c89c706d-468a-4ca1-be17-d5c30914ebde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276805174 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.1276805174
Directory /workspace/17.prim_present_test/latest

Test location /workspace/coverage/default/18.prim_present_test.3936246084
Short name T33
Test name
Test status
Simulation time 4840960000 ps
CPU time 15.02 seconds
Started Dec 31 12:40:09 PM PST 23
Finished Dec 31 12:40:38 PM PST 23
Peak memory 144720 kb
Host smart-7a03188a-ab01-414a-8e25-e36e23cbe86f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936246084 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.3936246084
Directory /workspace/18.prim_present_test/latest

Test location /workspace/coverage/default/19.prim_present_test.399022447
Short name T31
Test name
Test status
Simulation time 3589800000 ps
CPU time 12.25 seconds
Started Dec 31 12:39:59 PM PST 23
Finished Dec 31 12:40:22 PM PST 23
Peak memory 144524 kb
Host smart-699d33c5-91b7-44d7-8574-455685bb86d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399022447 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.399022447
Directory /workspace/19.prim_present_test/latest

Test location /workspace/coverage/default/2.prim_present_test.430133879
Short name T32
Test name
Test status
Simulation time 14533420000 ps
CPU time 43.37 seconds
Started Dec 31 12:39:58 PM PST 23
Finished Dec 31 12:41:19 PM PST 23
Peak memory 144632 kb
Host smart-d7fcd159-31fc-4838-9424-f4d966b9ea4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430133879 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.430133879
Directory /workspace/2.prim_present_test/latest

Test location /workspace/coverage/default/20.prim_present_test.2324934955
Short name T35
Test name
Test status
Simulation time 13719980000 ps
CPU time 40.86 seconds
Started Dec 31 12:39:54 PM PST 23
Finished Dec 31 12:41:09 PM PST 23
Peak memory 144628 kb
Host smart-527558f2-6aaa-4cc4-880c-1365dc761e14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324934955 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.2324934955
Directory /workspace/20.prim_present_test/latest

Test location /workspace/coverage/default/21.prim_present_test.2637440590
Short name T22
Test name
Test status
Simulation time 15177600000 ps
CPU time 47.7 seconds
Started Dec 31 12:40:04 PM PST 23
Finished Dec 31 12:41:31 PM PST 23
Peak memory 144656 kb
Host smart-35ab4648-ac3a-43d9-83fd-5d7ef833a31e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637440590 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.2637440590
Directory /workspace/21.prim_present_test/latest

Test location /workspace/coverage/default/23.prim_present_test.1350831802
Short name T27
Test name
Test status
Simulation time 9378740000 ps
CPU time 34.31 seconds
Started Dec 31 12:40:13 PM PST 23
Finished Dec 31 12:41:15 PM PST 23
Peak memory 144724 kb
Host smart-5da4cb3c-c151-4a90-8c12-926d6239bf7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350831802 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.1350831802
Directory /workspace/23.prim_present_test/latest

Test location /workspace/coverage/default/24.prim_present_test.2795775685
Short name T17
Test name
Test status
Simulation time 6332680000 ps
CPU time 20.03 seconds
Started Dec 31 12:40:12 PM PST 23
Finished Dec 31 12:40:49 PM PST 23
Peak memory 144664 kb
Host smart-ac494e62-1006-4dde-9ba8-83c5d94f2192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795775685 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.2795775685
Directory /workspace/24.prim_present_test/latest

Test location /workspace/coverage/default/25.prim_present_test.2551344263
Short name T2
Test name
Test status
Simulation time 15033140000 ps
CPU time 49.59 seconds
Started Dec 31 12:40:03 PM PST 23
Finished Dec 31 12:41:34 PM PST 23
Peak memory 144580 kb
Host smart-aa189147-49cc-4b14-9697-0e4db54ffb15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551344263 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.2551344263
Directory /workspace/25.prim_present_test/latest

Test location /workspace/coverage/default/26.prim_present_test.3245359335
Short name T10
Test name
Test status
Simulation time 8924900000 ps
CPU time 30.52 seconds
Started Dec 31 12:39:45 PM PST 23
Finished Dec 31 12:40:42 PM PST 23
Peak memory 144680 kb
Host smart-d8212630-3ae2-4d3f-a343-558e060ecff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245359335 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.3245359335
Directory /workspace/26.prim_present_test/latest

Test location /workspace/coverage/default/27.prim_present_test.3675420020
Short name T28
Test name
Test status
Simulation time 11576640000 ps
CPU time 33.44 seconds
Started Dec 31 12:40:02 PM PST 23
Finished Dec 31 12:41:04 PM PST 23
Peak memory 144692 kb
Host smart-fdd62097-e1e7-4f1b-93a5-b0e337bc4a7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675420020 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.3675420020
Directory /workspace/27.prim_present_test/latest

Test location /workspace/coverage/default/28.prim_present_test.937121168
Short name T25
Test name
Test status
Simulation time 8743240000 ps
CPU time 25.22 seconds
Started Dec 31 12:40:04 PM PST 23
Finished Dec 31 12:40:51 PM PST 23
Peak memory 144684 kb
Host smart-8086e81f-a745-4ebc-adec-88bb93a40717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937121168 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.937121168
Directory /workspace/28.prim_present_test/latest

Test location /workspace/coverage/default/29.prim_present_test.369402204
Short name T18
Test name
Test status
Simulation time 3599720000 ps
CPU time 12.05 seconds
Started Dec 31 12:39:53 PM PST 23
Finished Dec 31 12:40:15 PM PST 23
Peak memory 144520 kb
Host smart-61e78dff-49db-4f5e-8d49-b4a87c0fa156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369402204 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.369402204
Directory /workspace/29.prim_present_test/latest

Test location /workspace/coverage/default/3.prim_present_test.1810626775
Short name T29
Test name
Test status
Simulation time 11029180000 ps
CPU time 35.07 seconds
Started Dec 31 12:40:09 PM PST 23
Finished Dec 31 12:41:14 PM PST 23
Peak memory 144660 kb
Host smart-108b6032-d4b7-44be-bd2d-545e8051f8fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810626775 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.1810626775
Directory /workspace/3.prim_present_test/latest

Test location /workspace/coverage/default/30.prim_present_test.3054308405
Short name T4
Test name
Test status
Simulation time 8914360000 ps
CPU time 29.63 seconds
Started Dec 31 12:40:23 PM PST 23
Finished Dec 31 12:41:20 PM PST 23
Peak memory 144612 kb
Host smart-1759ad24-c1cf-4c0c-ab95-0fd83c1dbb0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054308405 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.3054308405
Directory /workspace/30.prim_present_test/latest

Test location /workspace/coverage/default/31.prim_present_test.2439561868
Short name T46
Test name
Test status
Simulation time 9448800000 ps
CPU time 31.04 seconds
Started Dec 31 12:40:19 PM PST 23
Finished Dec 31 12:41:19 PM PST 23
Peak memory 144580 kb
Host smart-e6d02453-ae6d-4fe3-9234-2c1d1172e487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439561868 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.2439561868
Directory /workspace/31.prim_present_test/latest

Test location /workspace/coverage/default/32.prim_present_test.3498265702
Short name T24
Test name
Test status
Simulation time 3609020000 ps
CPU time 13.04 seconds
Started Dec 31 12:40:13 PM PST 23
Finished Dec 31 12:40:38 PM PST 23
Peak memory 144600 kb
Host smart-6b46653f-c5ca-4b57-a9f4-5887763d7d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498265702 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.3498265702
Directory /workspace/32.prim_present_test/latest

Test location /workspace/coverage/default/33.prim_present_test.1165089778
Short name T48
Test name
Test status
Simulation time 5810020000 ps
CPU time 17.86 seconds
Started Dec 31 12:40:09 PM PST 23
Finished Dec 31 12:40:43 PM PST 23
Peak memory 144640 kb
Host smart-6bb5b793-1b52-4961-96fc-a96bf1c1efc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165089778 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.1165089778
Directory /workspace/33.prim_present_test/latest

Test location /workspace/coverage/default/34.prim_present_test.100987696
Short name T49
Test name
Test status
Simulation time 15445440000 ps
CPU time 48.12 seconds
Started Dec 31 12:39:57 PM PST 23
Finished Dec 31 12:41:27 PM PST 23
Peak memory 144632 kb
Host smart-94637027-10cf-4c13-ae0d-640fa43cc2c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100987696 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.100987696
Directory /workspace/34.prim_present_test/latest

Test location /workspace/coverage/default/35.prim_present_test.4026041692
Short name T38
Test name
Test status
Simulation time 10721660000 ps
CPU time 38.35 seconds
Started Dec 31 12:39:50 PM PST 23
Finished Dec 31 12:41:00 PM PST 23
Peak memory 144680 kb
Host smart-d6311aae-bf60-4ce2-b01f-4a318ce18894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026041692 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.4026041692
Directory /workspace/35.prim_present_test/latest

Test location /workspace/coverage/default/36.prim_present_test.3600492151
Short name T41
Test name
Test status
Simulation time 14689040000 ps
CPU time 47.13 seconds
Started Dec 31 12:40:12 PM PST 23
Finished Dec 31 12:41:39 PM PST 23
Peak memory 144676 kb
Host smart-cb35553a-dcc5-45d2-ad45-b629f7c649ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600492151 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.3600492151
Directory /workspace/36.prim_present_test/latest

Test location /workspace/coverage/default/37.prim_present_test.19795377
Short name T3
Test name
Test status
Simulation time 8143080000 ps
CPU time 26.94 seconds
Started Dec 31 12:39:57 PM PST 23
Finished Dec 31 12:40:47 PM PST 23
Peak memory 144732 kb
Host smart-8ee5c208-0ddb-4003-b993-27a314bbff17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19795377 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.19795377
Directory /workspace/37.prim_present_test/latest

Test location /workspace/coverage/default/38.prim_present_test.227138444
Short name T40
Test name
Test status
Simulation time 11375140000 ps
CPU time 40.07 seconds
Started Dec 31 12:39:47 PM PST 23
Finished Dec 31 12:41:01 PM PST 23
Peak memory 144676 kb
Host smart-cc510978-89ab-4109-a1a3-d3f9e57df9de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227138444 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.227138444
Directory /workspace/38.prim_present_test/latest

Test location /workspace/coverage/default/39.prim_present_test.2203850377
Short name T13
Test name
Test status
Simulation time 10695620000 ps
CPU time 39.5 seconds
Started Dec 31 12:40:01 PM PST 23
Finished Dec 31 12:41:15 PM PST 23
Peak memory 144668 kb
Host smart-7c00c101-8cb9-4110-bab8-bee2dafd3aa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203850377 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.2203850377
Directory /workspace/39.prim_present_test/latest

Test location /workspace/coverage/default/4.prim_present_test.3018355666
Short name T12
Test name
Test status
Simulation time 13683400000 ps
CPU time 42.87 seconds
Started Dec 31 12:40:30 PM PST 23
Finished Dec 31 12:41:53 PM PST 23
Peak memory 144652 kb
Host smart-e7255e69-ea9e-4e3b-9cf6-19b7b4ad15a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018355666 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.3018355666
Directory /workspace/4.prim_present_test/latest

Test location /workspace/coverage/default/40.prim_present_test.1723333973
Short name T21
Test name
Test status
Simulation time 11887880000 ps
CPU time 40.57 seconds
Started Dec 31 12:40:24 PM PST 23
Finished Dec 31 12:41:40 PM PST 23
Peak memory 144660 kb
Host smart-630b6d4f-b999-4831-b7a0-9f401f428371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723333973 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.1723333973
Directory /workspace/40.prim_present_test/latest

Test location /workspace/coverage/default/41.prim_present_test.201015195
Short name T9
Test name
Test status
Simulation time 3436040000 ps
CPU time 12.02 seconds
Started Dec 31 12:39:56 PM PST 23
Finished Dec 31 12:40:18 PM PST 23
Peak memory 144524 kb
Host smart-eff4c45c-50bd-42dd-b449-b957d3ad804a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201015195 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.201015195
Directory /workspace/41.prim_present_test/latest

Test location /workspace/coverage/default/42.prim_present_test.447573938
Short name T44
Test name
Test status
Simulation time 6380420000 ps
CPU time 19.13 seconds
Started Dec 31 12:40:05 PM PST 23
Finished Dec 31 12:40:40 PM PST 23
Peak memory 144676 kb
Host smart-bd6e5247-fffd-4999-9555-eac34713fe22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447573938 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.447573938
Directory /workspace/42.prim_present_test/latest

Test location /workspace/coverage/default/43.prim_present_test.2177731455
Short name T7
Test name
Test status
Simulation time 14587980000 ps
CPU time 44.72 seconds
Started Dec 31 12:40:05 PM PST 23
Finished Dec 31 12:41:26 PM PST 23
Peak memory 144736 kb
Host smart-f93149ed-380b-4225-9e15-d40b845da0c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177731455 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.2177731455
Directory /workspace/43.prim_present_test/latest

Test location /workspace/coverage/default/44.prim_present_test.3465213016
Short name T37
Test name
Test status
Simulation time 7846720000 ps
CPU time 23.87 seconds
Started Dec 31 12:40:02 PM PST 23
Finished Dec 31 12:40:46 PM PST 23
Peak memory 144680 kb
Host smart-49abf080-0d4f-4fa3-854d-fe02ecf967fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465213016 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.3465213016
Directory /workspace/44.prim_present_test/latest

Test location /workspace/coverage/default/45.prim_present_test.3726847195
Short name T8
Test name
Test status
Simulation time 4240800000 ps
CPU time 13.42 seconds
Started Dec 31 12:40:10 PM PST 23
Finished Dec 31 12:40:35 PM PST 23
Peak memory 144472 kb
Host smart-28699b23-96a7-4b05-8b42-01f124f2088b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726847195 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.3726847195
Directory /workspace/45.prim_present_test/latest

Test location /workspace/coverage/default/46.prim_present_test.790651916
Short name T20
Test name
Test status
Simulation time 8235460000 ps
CPU time 28.33 seconds
Started Dec 31 12:39:50 PM PST 23
Finished Dec 31 12:40:43 PM PST 23
Peak memory 144648 kb
Host smart-3386bb1d-6923-4f28-a714-bf55a75b5598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790651916 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.790651916
Directory /workspace/46.prim_present_test/latest

Test location /workspace/coverage/default/47.prim_present_test.2951157398
Short name T43
Test name
Test status
Simulation time 12119760000 ps
CPU time 37.33 seconds
Started Dec 31 12:40:14 PM PST 23
Finished Dec 31 12:41:24 PM PST 23
Peak memory 144652 kb
Host smart-e780d14a-db5c-43cb-89b2-a85d3f6c9c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951157398 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.2951157398
Directory /workspace/47.prim_present_test/latest

Test location /workspace/coverage/default/48.prim_present_test.619425763
Short name T15
Test name
Test status
Simulation time 4005200000 ps
CPU time 14.05 seconds
Started Dec 31 12:40:14 PM PST 23
Finished Dec 31 12:40:41 PM PST 23
Peak memory 144512 kb
Host smart-01203bb9-ff27-47b0-8cb3-a6e34dd351b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619425763 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.619425763
Directory /workspace/48.prim_present_test/latest

Test location /workspace/coverage/default/49.prim_present_test.936371835
Short name T45
Test name
Test status
Simulation time 3160760000 ps
CPU time 10.32 seconds
Started Dec 31 12:40:09 PM PST 23
Finished Dec 31 12:40:29 PM PST 23
Peak memory 144520 kb
Host smart-976e62f1-3a86-434d-a373-6c5a0da336d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936371835 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.936371835
Directory /workspace/49.prim_present_test/latest

Test location /workspace/coverage/default/5.prim_present_test.2701668263
Short name T5
Test name
Test status
Simulation time 7526800000 ps
CPU time 26.88 seconds
Started Dec 31 12:40:03 PM PST 23
Finished Dec 31 12:40:53 PM PST 23
Peak memory 144652 kb
Host smart-027caf7a-c365-4bef-9063-6b29767e943d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701668263 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.2701668263
Directory /workspace/5.prim_present_test/latest

Test location /workspace/coverage/default/6.prim_present_test.398247859
Short name T36
Test name
Test status
Simulation time 3569960000 ps
CPU time 11.33 seconds
Started Dec 31 12:39:50 PM PST 23
Finished Dec 31 12:40:11 PM PST 23
Peak memory 144528 kb
Host smart-d63498f4-420f-46cb-bcaf-c8118a3602d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398247859 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.398247859
Directory /workspace/6.prim_present_test/latest

Test location /workspace/coverage/default/7.prim_present_test.733601016
Short name T6
Test name
Test status
Simulation time 9741440000 ps
CPU time 30.11 seconds
Started Dec 31 12:39:46 PM PST 23
Finished Dec 31 12:40:41 PM PST 23
Peak memory 144652 kb
Host smart-ff4a52aa-dc84-4a8b-b9ed-018c0b6dcb6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733601016 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.733601016
Directory /workspace/7.prim_present_test/latest

Test location /workspace/coverage/default/8.prim_present_test.1157489422
Short name T42
Test name
Test status
Simulation time 8843680000 ps
CPU time 28.77 seconds
Started Dec 31 12:39:47 PM PST 23
Finished Dec 31 12:40:39 PM PST 23
Peak memory 144688 kb
Host smart-7b3e3aa9-b105-4fa7-ad5a-a915344da551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157489422 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.1157489422
Directory /workspace/8.prim_present_test/latest

Test location /workspace/coverage/default/9.prim_present_test.2003157018
Short name T19
Test name
Test status
Simulation time 13976660000 ps
CPU time 43.38 seconds
Started Dec 31 12:40:00 PM PST 23
Finished Dec 31 12:41:19 PM PST 23
Peak memory 144672 kb
Host smart-6d433622-7414-4131-b73e-c69c916f7b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003157018 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.2003157018
Directory /workspace/9.prim_present_test/latest
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