| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/1.prim_present_test.3901634463 | ||
| Name |
|---|
| /workspace/coverage/default/0.prim_present_test.3082822533 |
| /workspace/coverage/default/10.prim_present_test.1414853910 |
| /workspace/coverage/default/11.prim_present_test.3628166176 |
| /workspace/coverage/default/12.prim_present_test.3033713900 |
| /workspace/coverage/default/13.prim_present_test.3239381869 |
| /workspace/coverage/default/14.prim_present_test.3146305316 |
| /workspace/coverage/default/15.prim_present_test.2611361039 |
| /workspace/coverage/default/16.prim_present_test.2501652634 |
| /workspace/coverage/default/17.prim_present_test.1645167033 |
| /workspace/coverage/default/18.prim_present_test.1093474931 |
| /workspace/coverage/default/19.prim_present_test.3735365592 |
| /workspace/coverage/default/2.prim_present_test.2241810256 |
| /workspace/coverage/default/20.prim_present_test.2640187807 |
| /workspace/coverage/default/21.prim_present_test.2540802431 |
| /workspace/coverage/default/22.prim_present_test.968014710 |
| /workspace/coverage/default/23.prim_present_test.1927245361 |
| /workspace/coverage/default/24.prim_present_test.1991331667 |
| /workspace/coverage/default/25.prim_present_test.558076352 |
| /workspace/coverage/default/26.prim_present_test.1266166838 |
| /workspace/coverage/default/27.prim_present_test.686483009 |
| /workspace/coverage/default/28.prim_present_test.960455596 |
| /workspace/coverage/default/29.prim_present_test.2852370976 |
| /workspace/coverage/default/3.prim_present_test.1596189355 |
| /workspace/coverage/default/30.prim_present_test.40146711 |
| /workspace/coverage/default/31.prim_present_test.2104360532 |
| /workspace/coverage/default/32.prim_present_test.2463854644 |
| /workspace/coverage/default/33.prim_present_test.2059948215 |
| /workspace/coverage/default/34.prim_present_test.751216474 |
| /workspace/coverage/default/35.prim_present_test.118712288 |
| /workspace/coverage/default/36.prim_present_test.2725514673 |
| /workspace/coverage/default/37.prim_present_test.176457097 |
| /workspace/coverage/default/38.prim_present_test.1347114419 |
| /workspace/coverage/default/39.prim_present_test.2370805130 |
| /workspace/coverage/default/4.prim_present_test.3101591587 |
| /workspace/coverage/default/40.prim_present_test.2075086365 |
| /workspace/coverage/default/41.prim_present_test.3655730921 |
| /workspace/coverage/default/42.prim_present_test.2413923764 |
| /workspace/coverage/default/43.prim_present_test.137489451 |
| /workspace/coverage/default/44.prim_present_test.2808255144 |
| /workspace/coverage/default/45.prim_present_test.2519600844 |
| /workspace/coverage/default/46.prim_present_test.724182927 |
| /workspace/coverage/default/47.prim_present_test.2006623943 |
| /workspace/coverage/default/48.prim_present_test.2573591056 |
| /workspace/coverage/default/49.prim_present_test.1296657489 |
| /workspace/coverage/default/5.prim_present_test.3975786844 |
| /workspace/coverage/default/6.prim_present_test.3771218893 |
| /workspace/coverage/default/7.prim_present_test.2952418843 |
| /workspace/coverage/default/8.prim_present_test.1387150237 |
| /workspace/coverage/default/9.prim_present_test.2654800058 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/41.prim_present_test.3655730921 | Jan 03 12:20:57 PM PST 24 | Jan 03 12:21:55 PM PST 24 | 7544160000 ps | ||
| T2 | /workspace/coverage/default/1.prim_present_test.3901634463 | Jan 03 12:21:07 PM PST 24 | Jan 03 12:22:34 PM PST 24 | 9955340000 ps | ||
| T3 | /workspace/coverage/default/22.prim_present_test.968014710 | Jan 03 12:20:57 PM PST 24 | Jan 03 12:21:30 PM PST 24 | 3685280000 ps | ||
| T4 | /workspace/coverage/default/29.prim_present_test.2852370976 | Jan 03 12:21:08 PM PST 24 | Jan 03 12:22:23 PM PST 24 | 8001720000 ps | ||
| T5 | /workspace/coverage/default/38.prim_present_test.1347114419 | Jan 03 12:21:08 PM PST 24 | Jan 03 12:22:07 PM PST 24 | 5624020000 ps | ||
| T6 | /workspace/coverage/default/12.prim_present_test.3033713900 | Jan 03 12:21:08 PM PST 24 | Jan 03 12:21:59 PM PST 24 | 3933280000 ps | ||
| T7 | /workspace/coverage/default/8.prim_present_test.1387150237 | Jan 03 12:21:08 PM PST 24 | Jan 03 12:22:03 PM PST 24 | 5108180000 ps | ||
| T8 | /workspace/coverage/default/20.prim_present_test.2640187807 | Jan 03 12:21:08 PM PST 24 | Jan 03 12:21:58 PM PST 24 | 4030620000 ps | ||
| T9 | /workspace/coverage/default/45.prim_present_test.2519600844 | Jan 03 12:21:08 PM PST 24 | Jan 03 12:22:53 PM PST 24 | 12116660000 ps | ||
| T10 | /workspace/coverage/default/37.prim_present_test.176457097 | Jan 03 12:21:10 PM PST 24 | Jan 03 12:22:33 PM PST 24 | 9218160000 ps | ||
| T11 | /workspace/coverage/default/42.prim_present_test.2413923764 | Jan 03 12:20:59 PM PST 24 | Jan 03 12:22:21 PM PST 24 | 10548680000 ps | ||
| T12 | /workspace/coverage/default/46.prim_present_test.724182927 | Jan 03 12:21:18 PM PST 24 | Jan 03 12:22:50 PM PST 24 | 14418720000 ps | ||
| T13 | /workspace/coverage/default/32.prim_present_test.2463854644 | Jan 03 12:21:09 PM PST 24 | Jan 03 12:22:25 PM PST 24 | 8071160000 ps | ||
| T14 | /workspace/coverage/default/19.prim_present_test.3735365592 | Jan 03 12:21:09 PM PST 24 | Jan 03 12:23:09 PM PST 24 | 15174500000 ps | ||
| T15 | /workspace/coverage/default/35.prim_present_test.118712288 | Jan 03 12:20:58 PM PST 24 | Jan 03 12:22:02 PM PST 24 | 7722720000 ps | ||
| T16 | /workspace/coverage/default/5.prim_present_test.3975786844 | Jan 03 12:21:10 PM PST 24 | Jan 03 12:22:34 PM PST 24 | 9955340000 ps | ||
| T17 | /workspace/coverage/default/44.prim_present_test.2808255144 | Jan 03 12:21:09 PM PST 24 | Jan 03 12:22:29 PM PST 24 | 8430760000 ps | ||
| T18 | /workspace/coverage/default/26.prim_present_test.1266166838 | Jan 03 12:21:05 PM PST 24 | Jan 03 12:23:07 PM PST 24 | 14859540000 ps | ||
| T19 | /workspace/coverage/default/9.prim_present_test.2654800058 | Jan 03 12:21:07 PM PST 24 | Jan 03 12:22:25 PM PST 24 | 8428900000 ps | ||
| T20 | /workspace/coverage/default/13.prim_present_test.3239381869 | Jan 03 12:21:06 PM PST 24 | Jan 03 12:22:03 PM PST 24 | 5081520000 ps | ||
| T21 | /workspace/coverage/default/31.prim_present_test.2104360532 | Jan 03 12:20:57 PM PST 24 | Jan 03 12:21:50 PM PST 24 | 6620360000 ps | ||
| T22 | /workspace/coverage/default/23.prim_present_test.1927245361 | Jan 03 12:21:09 PM PST 24 | Jan 03 12:22:16 PM PST 24 | 7226100000 ps | ||
| T23 | /workspace/coverage/default/30.prim_present_test.40146711 | Jan 03 12:21:10 PM PST 24 | Jan 03 12:22:57 PM PST 24 | 12984660000 ps | ||
| T24 | /workspace/coverage/default/47.prim_present_test.2006623943 | Jan 03 12:21:07 PM PST 24 | Jan 03 12:22:25 PM PST 24 | 8240420000 ps | ||
| T25 | /workspace/coverage/default/33.prim_present_test.2059948215 | Jan 03 12:21:05 PM PST 24 | Jan 03 12:22:13 PM PST 24 | 7660720000 ps | ||
| T26 | /workspace/coverage/default/36.prim_present_test.2725514673 | Jan 03 12:20:58 PM PST 24 | Jan 03 12:22:06 PM PST 24 | 8245380000 ps | ||
| T27 | /workspace/coverage/default/3.prim_present_test.1596189355 | Jan 03 12:21:08 PM PST 24 | Jan 03 12:23:07 PM PST 24 | 15459700000 ps | ||
| T28 | /workspace/coverage/default/48.prim_present_test.2573591056 | Jan 03 12:21:06 PM PST 24 | Jan 03 12:22:03 PM PST 24 | 5106940000 ps | ||
| T29 | /workspace/coverage/default/43.prim_present_test.137489451 | Jan 03 12:21:09 PM PST 24 | Jan 03 12:21:53 PM PST 24 | 3344280000 ps | ||
| T30 | /workspace/coverage/default/4.prim_present_test.3101591587 | Jan 03 12:21:06 PM PST 24 | Jan 03 12:23:08 PM PST 24 | 14808080000 ps | ||
| T31 | /workspace/coverage/default/7.prim_present_test.2952418843 | Jan 03 12:21:12 PM PST 24 | Jan 03 12:22:34 PM PST 24 | 7752480000 ps | ||
| T32 | /workspace/coverage/default/28.prim_present_test.960455596 | Jan 03 12:21:10 PM PST 24 | Jan 03 12:23:06 PM PST 24 | 14797540000 ps | ||
| T33 | /workspace/coverage/default/40.prim_present_test.2075086365 | Jan 03 12:21:09 PM PST 24 | Jan 03 12:22:09 PM PST 24 | 5490720000 ps | ||
| T34 | /workspace/coverage/default/16.prim_present_test.2501652634 | Jan 03 12:21:06 PM PST 24 | Jan 03 12:23:19 PM PST 24 | 15118700000 ps | ||
| T35 | /workspace/coverage/default/25.prim_present_test.558076352 | Jan 03 12:21:08 PM PST 24 | Jan 03 12:22:11 PM PST 24 | 5864580000 ps | ||
| T36 | /workspace/coverage/default/21.prim_present_test.2540802431 | Jan 03 12:21:06 PM PST 24 | Jan 03 12:22:57 PM PST 24 | 12336760000 ps | ||
| T37 | /workspace/coverage/default/18.prim_present_test.1093474931 | Jan 03 12:21:08 PM PST 24 | Jan 03 12:22:48 PM PST 24 | 12298940000 ps | ||
| T38 | /workspace/coverage/default/11.prim_present_test.3628166176 | Jan 03 12:20:57 PM PST 24 | Jan 03 12:21:46 PM PST 24 | 5812500000 ps | ||
| T39 | /workspace/coverage/default/14.prim_present_test.3146305316 | Jan 03 12:21:05 PM PST 24 | Jan 03 12:21:50 PM PST 24 | 4562580000 ps | ||
| T40 | /workspace/coverage/default/6.prim_present_test.3771218893 | Jan 03 12:21:09 PM PST 24 | Jan 03 12:22:30 PM PST 24 | 9123300000 ps | ||
| T41 | /workspace/coverage/default/49.prim_present_test.1296657489 | Jan 03 12:21:09 PM PST 24 | Jan 03 12:22:07 PM PST 24 | 5211720000 ps | ||
| T42 | /workspace/coverage/default/2.prim_present_test.2241810256 | Jan 03 12:21:06 PM PST 24 | Jan 03 12:22:00 PM PST 24 | 4267460000 ps | ||
| T43 | /workspace/coverage/default/34.prim_present_test.751216474 | Jan 03 12:20:56 PM PST 24 | Jan 03 12:21:56 PM PST 24 | 7604920000 ps | ||
| T44 | /workspace/coverage/default/24.prim_present_test.1991331667 | Jan 03 12:21:08 PM PST 24 | Jan 03 12:22:47 PM PST 24 | 11854400000 ps | ||
| T45 | /workspace/coverage/default/39.prim_present_test.2370805130 | Jan 03 12:20:59 PM PST 24 | Jan 03 12:22:21 PM PST 24 | 10502180000 ps | ||
| T46 | /workspace/coverage/default/17.prim_present_test.1645167033 | Jan 03 12:21:10 PM PST 24 | Jan 03 12:22:05 PM PST 24 | 6580680000 ps | ||
| T47 | /workspace/coverage/default/27.prim_present_test.686483009 | Jan 03 12:21:11 PM PST 24 | Jan 03 12:21:57 PM PST 24 | 3272360000 ps | ||
| T48 | /workspace/coverage/default/15.prim_present_test.2611361039 | Jan 03 12:21:08 PM PST 24 | Jan 03 12:22:41 PM PST 24 | 11360880000 ps | ||
| T49 | /workspace/coverage/default/10.prim_present_test.1414853910 | Jan 03 12:21:07 PM PST 24 | Jan 03 12:21:56 PM PST 24 | 4177560000 ps | ||
| T50 | /workspace/coverage/default/0.prim_present_test.3082822533 | Jan 03 12:21:08 PM PST 24 | Jan 03 12:22:45 PM PST 24 | 11646080000 ps |
| Test location | /workspace/coverage/default/1.prim_present_test.3901634463 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 9955340000 ps |
| CPU time | 36.21 seconds |
| Started | Jan 03 12:21:07 PM PST 24 |
| Finished | Jan 03 12:22:34 PM PST 24 |
| Peak memory | 142692 kb |
| Host | smart-d8a7a25c-d5ec-4df8-920a-c3dca6073c33 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3901634463 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.3901634463 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/0.prim_present_test.3082822533 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 11646080000 ps |
| CPU time | 40.78 seconds |
| Started | Jan 03 12:21:08 PM PST 24 |
| Finished | Jan 03 12:22:45 PM PST 24 |
| Peak memory | 144052 kb |
| Host | smart-e2a6c0fc-2fea-4c80-9c18-fd8b4fa23b0b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3082822533 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.3082822533 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/10.prim_present_test.1414853910 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 4177560000 ps |
| CPU time | 15.49 seconds |
| Started | Jan 03 12:21:07 PM PST 24 |
| Finished | Jan 03 12:21:56 PM PST 24 |
| Peak memory | 142968 kb |
| Host | smart-486ecf1f-a7d1-4690-94d7-9693a2101fbb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1414853910 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.1414853910 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/11.prim_present_test.3628166176 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 5812500000 ps |
| CPU time | 21.85 seconds |
| Started | Jan 03 12:20:57 PM PST 24 |
| Finished | Jan 03 12:21:46 PM PST 24 |
| Peak memory | 144648 kb |
| Host | smart-c2a2e483-ea9c-4d5c-9886-6203ef05ebb2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3628166176 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.3628166176 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.3033713900 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 3933280000 ps |
| CPU time | 15.79 seconds |
| Started | Jan 03 12:21:08 PM PST 24 |
| Finished | Jan 03 12:21:59 PM PST 24 |
| Peak memory | 142396 kb |
| Host | smart-39e89ca8-05b8-43dc-9fda-c0efe528d0c8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3033713900 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.3033713900 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.3239381869 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 5081520000 ps |
| CPU time | 19.35 seconds |
| Started | Jan 03 12:21:06 PM PST 24 |
| Finished | Jan 03 12:22:03 PM PST 24 |
| Peak memory | 142240 kb |
| Host | smart-9490aa37-3b82-4771-b4e3-0e0a6448aa05 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3239381869 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.3239381869 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.3146305316 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 4562580000 ps |
| CPU time | 17.97 seconds |
| Started | Jan 03 12:21:05 PM PST 24 |
| Finished | Jan 03 12:21:50 PM PST 24 |
| Peak memory | 146180 kb |
| Host | smart-92ad4632-8b54-426e-bfa2-b0f0058289e8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3146305316 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.3146305316 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.2611361039 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 11360880000 ps |
| CPU time | 39.38 seconds |
| Started | Jan 03 12:21:08 PM PST 24 |
| Finished | Jan 03 12:22:41 PM PST 24 |
| Peak memory | 144564 kb |
| Host | smart-5082cdac-fda4-45d9-a66c-bc97a599675d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2611361039 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.2611361039 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.2501652634 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 15118700000 ps |
| CPU time | 59.69 seconds |
| Started | Jan 03 12:21:06 PM PST 24 |
| Finished | Jan 03 12:23:19 PM PST 24 |
| Peak memory | 146180 kb |
| Host | smart-e48f1f0a-a100-43ad-8dbd-4a5eb62091d9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2501652634 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.2501652634 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.1645167033 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 6580680000 ps |
| CPU time | 19.56 seconds |
| Started | Jan 03 12:21:10 PM PST 24 |
| Finished | Jan 03 12:22:05 PM PST 24 |
| Peak memory | 142848 kb |
| Host | smart-0419be8d-6d4c-415f-ac3a-1890ba751796 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1645167033 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.1645167033 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.1093474931 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 12298940000 ps |
| CPU time | 43.14 seconds |
| Started | Jan 03 12:21:08 PM PST 24 |
| Finished | Jan 03 12:22:48 PM PST 24 |
| Peak memory | 144056 kb |
| Host | smart-606c5b8c-488e-4d1e-95c8-16e94f832e16 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1093474931 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.1093474931 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.3735365592 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 15174500000 ps |
| CPU time | 54.22 seconds |
| Started | Jan 03 12:21:09 PM PST 24 |
| Finished | Jan 03 12:23:09 PM PST 24 |
| Peak memory | 143408 kb |
| Host | smart-98701a8e-8e8a-461f-bc70-92692367f065 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3735365592 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.3735365592 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.2241810256 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 4267460000 ps |
| CPU time | 17.43 seconds |
| Started | Jan 03 12:21:06 PM PST 24 |
| Finished | Jan 03 12:22:00 PM PST 24 |
| Peak memory | 144648 kb |
| Host | smart-2a8b47c9-3871-42f3-a1b7-027973133180 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2241810256 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.2241810256 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.2640187807 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 4030620000 ps |
| CPU time | 15.25 seconds |
| Started | Jan 03 12:21:08 PM PST 24 |
| Finished | Jan 03 12:21:58 PM PST 24 |
| Peak memory | 144376 kb |
| Host | smart-3b464175-43cf-431e-9316-e031f6063a98 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2640187807 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.2640187807 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.2540802431 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 12336760000 ps |
| CPU time | 48.36 seconds |
| Started | Jan 03 12:21:06 PM PST 24 |
| Finished | Jan 03 12:22:57 PM PST 24 |
| Peak memory | 144792 kb |
| Host | smart-e85ed7d5-8b9e-4b68-b508-e0fbe1239b32 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2540802431 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.2540802431 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.968014710 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 3685280000 ps |
| CPU time | 12.77 seconds |
| Started | Jan 03 12:20:57 PM PST 24 |
| Finished | Jan 03 12:21:30 PM PST 24 |
| Peak memory | 144512 kb |
| Host | smart-6f37b25b-6df9-4694-9deb-8344d3ac1a52 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=968014710 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.968014710 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.1927245361 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 7226100000 ps |
| CPU time | 25.29 seconds |
| Started | Jan 03 12:21:09 PM PST 24 |
| Finished | Jan 03 12:22:16 PM PST 24 |
| Peak memory | 144644 kb |
| Host | smart-bf98e64d-dd65-44c9-bba8-97d5849bbba3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1927245361 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.1927245361 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.1991331667 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 11854400000 ps |
| CPU time | 42.35 seconds |
| Started | Jan 03 12:21:08 PM PST 24 |
| Finished | Jan 03 12:22:47 PM PST 24 |
| Peak memory | 144024 kb |
| Host | smart-406a04ea-bfd5-49ab-9ec8-40eab22ecfa9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1991331667 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.1991331667 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.558076352 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 5864580000 ps |
| CPU time | 22.64 seconds |
| Started | Jan 03 12:21:08 PM PST 24 |
| Finished | Jan 03 12:22:11 PM PST 24 |
| Peak memory | 142756 kb |
| Host | smart-567ae4f1-683c-4381-926c-447479855191 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=558076352 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.558076352 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.1266166838 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 14859540000 ps |
| CPU time | 59.35 seconds |
| Started | Jan 03 12:21:05 PM PST 24 |
| Finished | Jan 03 12:23:07 PM PST 24 |
| Peak memory | 146180 kb |
| Host | smart-90386dbc-bb42-4274-9997-06e0cd401445 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1266166838 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.1266166838 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.686483009 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 3272360000 ps |
| CPU time | 13.75 seconds |
| Started | Jan 03 12:21:11 PM PST 24 |
| Finished | Jan 03 12:21:57 PM PST 24 |
| Peak memory | 144680 kb |
| Host | smart-7b155d5b-0be4-4ffa-807e-1d9fae44e6bc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=686483009 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.686483009 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.960455596 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 14797540000 ps |
| CPU time | 52.88 seconds |
| Started | Jan 03 12:21:10 PM PST 24 |
| Finished | Jan 03 12:23:06 PM PST 24 |
| Peak memory | 144420 kb |
| Host | smart-a179ad99-f594-45aa-9161-dfe1ccee8db0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=960455596 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.960455596 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.2852370976 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 8001720000 ps |
| CPU time | 29.69 seconds |
| Started | Jan 03 12:21:08 PM PST 24 |
| Finished | Jan 03 12:22:23 PM PST 24 |
| Peak memory | 144036 kb |
| Host | smart-458f81b8-465c-4eb6-8a1d-16fe88b25a1d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2852370976 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.2852370976 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.1596189355 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 15459700000 ps |
| CPU time | 53.39 seconds |
| Started | Jan 03 12:21:08 PM PST 24 |
| Finished | Jan 03 12:23:07 PM PST 24 |
| Peak memory | 144572 kb |
| Host | smart-59eb7455-44e1-4085-a03b-84d2be0a42fd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1596189355 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.1596189355 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.40146711 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 12984660000 ps |
| CPU time | 47.33 seconds |
| Started | Jan 03 12:21:10 PM PST 24 |
| Finished | Jan 03 12:22:57 PM PST 24 |
| Peak memory | 143408 kb |
| Host | smart-526a91e4-311d-4e9b-b8b0-7b72f3df11bf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=40146711 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.40146711 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.2104360532 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 6620360000 ps |
| CPU time | 23.49 seconds |
| Started | Jan 03 12:20:57 PM PST 24 |
| Finished | Jan 03 12:21:50 PM PST 24 |
| Peak memory | 144648 kb |
| Host | smart-0ea8a837-01f0-436c-8449-296b3a0b001e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2104360532 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.2104360532 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.2463854644 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 8071160000 ps |
| CPU time | 29.59 seconds |
| Started | Jan 03 12:21:09 PM PST 24 |
| Finished | Jan 03 12:22:25 PM PST 24 |
| Peak memory | 144424 kb |
| Host | smart-1755eaaf-b5d2-4461-8348-2ddc6d9a6c3d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2463854644 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.2463854644 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.2059948215 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 7660720000 ps |
| CPU time | 30.61 seconds |
| Started | Jan 03 12:21:05 PM PST 24 |
| Finished | Jan 03 12:22:13 PM PST 24 |
| Peak memory | 144792 kb |
| Host | smart-9db4f902-3c14-4424-887a-e87b38e4b210 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2059948215 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.2059948215 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.751216474 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 7604920000 ps |
| CPU time | 27.22 seconds |
| Started | Jan 03 12:20:56 PM PST 24 |
| Finished | Jan 03 12:21:56 PM PST 24 |
| Peak memory | 144648 kb |
| Host | smart-451a293a-7dd0-46fa-86ef-5b9557f032f2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=751216474 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.751216474 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.118712288 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 7722720000 ps |
| CPU time | 30.01 seconds |
| Started | Jan 03 12:20:58 PM PST 24 |
| Finished | Jan 03 12:22:02 PM PST 24 |
| Peak memory | 142848 kb |
| Host | smart-28982efe-7575-4125-9233-844ef4e988ee |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=118712288 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.118712288 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.2725514673 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 8245380000 ps |
| CPU time | 32.09 seconds |
| Started | Jan 03 12:20:58 PM PST 24 |
| Finished | Jan 03 12:22:06 PM PST 24 |
| Peak memory | 144620 kb |
| Host | smart-c984ad77-ac34-410d-82a5-8fba1e087d70 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2725514673 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.2725514673 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.176457097 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 9218160000 ps |
| CPU time | 34.54 seconds |
| Started | Jan 03 12:21:10 PM PST 24 |
| Finished | Jan 03 12:22:33 PM PST 24 |
| Peak memory | 144208 kb |
| Host | smart-e510e684-2301-43ef-895c-5c6fff66bd51 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=176457097 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.176457097 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.1347114419 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 5624020000 ps |
| CPU time | 20.77 seconds |
| Started | Jan 03 12:21:08 PM PST 24 |
| Finished | Jan 03 12:22:07 PM PST 24 |
| Peak memory | 144056 kb |
| Host | smart-cb34eb69-ee4f-4452-82f9-4c7612d2d6b2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1347114419 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.1347114419 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.2370805130 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 10502180000 ps |
| CPU time | 39.55 seconds |
| Started | Jan 03 12:20:59 PM PST 24 |
| Finished | Jan 03 12:22:21 PM PST 24 |
| Peak memory | 144584 kb |
| Host | smart-4d5c04d2-3d9a-48cd-a054-3cf8b76f64db |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2370805130 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.2370805130 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.3101591587 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 14808080000 ps |
| CPU time | 59.47 seconds |
| Started | Jan 03 12:21:06 PM PST 24 |
| Finished | Jan 03 12:23:08 PM PST 24 |
| Peak memory | 144780 kb |
| Host | smart-7e8f84f7-6e21-47bd-a4f5-909963f4c98b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3101591587 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.3101591587 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.2075086365 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 5490720000 ps |
| CPU time | 21.23 seconds |
| Started | Jan 03 12:21:09 PM PST 24 |
| Finished | Jan 03 12:22:09 PM PST 24 |
| Peak memory | 143204 kb |
| Host | smart-c52023b8-1b29-4da7-9e62-690243f07e2c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2075086365 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.2075086365 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.3655730921 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 7544160000 ps |
| CPU time | 26.32 seconds |
| Started | Jan 03 12:20:57 PM PST 24 |
| Finished | Jan 03 12:21:55 PM PST 24 |
| Peak memory | 144648 kb |
| Host | smart-26ca9a17-5461-43c8-a140-1ff46a321123 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3655730921 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.3655730921 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.2413923764 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 10548680000 ps |
| CPU time | 39.82 seconds |
| Started | Jan 03 12:20:59 PM PST 24 |
| Finished | Jan 03 12:22:21 PM PST 24 |
| Peak memory | 142432 kb |
| Host | smart-3bf4500d-99bb-4d09-82f2-7b009dacc03c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2413923764 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.2413923764 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.137489451 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 3344280000 ps |
| CPU time | 12.55 seconds |
| Started | Jan 03 12:21:09 PM PST 24 |
| Finished | Jan 03 12:21:53 PM PST 24 |
| Peak memory | 144420 kb |
| Host | smart-c73645f3-cd89-4d4a-8635-cafcb6cf63f9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=137489451 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.137489451 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.2808255144 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 8430760000 ps |
| CPU time | 31.72 seconds |
| Started | Jan 03 12:21:09 PM PST 24 |
| Finished | Jan 03 12:22:29 PM PST 24 |
| Peak memory | 143400 kb |
| Host | smart-73cc4de2-807e-4707-ba53-744f81cfb662 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2808255144 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.2808255144 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.2519600844 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 12116660000 ps |
| CPU time | 45.31 seconds |
| Started | Jan 03 12:21:08 PM PST 24 |
| Finished | Jan 03 12:22:53 PM PST 24 |
| Peak memory | 143056 kb |
| Host | smart-4686540c-c90a-4553-9547-2841ba6e5477 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2519600844 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.2519600844 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.724182927 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 14418720000 ps |
| CPU time | 42.83 seconds |
| Started | Jan 03 12:21:18 PM PST 24 |
| Finished | Jan 03 12:22:50 PM PST 24 |
| Peak memory | 144544 kb |
| Host | smart-1f51dce8-0ada-4e47-a3b5-69fb08c158f1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=724182927 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.724182927 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.2006623943 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 8240420000 ps |
| CPU time | 31.17 seconds |
| Started | Jan 03 12:21:07 PM PST 24 |
| Finished | Jan 03 12:22:25 PM PST 24 |
| Peak memory | 142672 kb |
| Host | smart-6b32e17a-1f40-463f-8dbb-2a7e5f2102af |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2006623943 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.2006623943 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.2573591056 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 5106940000 ps |
| CPU time | 19.18 seconds |
| Started | Jan 03 12:21:06 PM PST 24 |
| Finished | Jan 03 12:22:03 PM PST 24 |
| Peak memory | 142352 kb |
| Host | smart-7eed9839-dc8f-417d-ac53-90e41cfc7be8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2573591056 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.2573591056 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.1296657489 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 5211720000 ps |
| CPU time | 20.07 seconds |
| Started | Jan 03 12:21:09 PM PST 24 |
| Finished | Jan 03 12:22:07 PM PST 24 |
| Peak memory | 144084 kb |
| Host | smart-badc1901-b59e-437e-89bc-8f9f983641e2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1296657489 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.1296657489 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.3975786844 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 9955340000 ps |
| CPU time | 35.38 seconds |
| Started | Jan 03 12:21:10 PM PST 24 |
| Finished | Jan 03 12:22:34 PM PST 24 |
| Peak memory | 144484 kb |
| Host | smart-8016f6f9-5efa-4974-96ff-573c992c055c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3975786844 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.3975786844 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.3771218893 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 9123300000 ps |
| CPU time | 33.15 seconds |
| Started | Jan 03 12:21:09 PM PST 24 |
| Finished | Jan 03 12:22:30 PM PST 24 |
| Peak memory | 144532 kb |
| Host | smart-131b5beb-598b-4ffb-8439-98d53479763d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3771218893 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.3771218893 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.2952418843 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 7752480000 ps |
| CPU time | 33.39 seconds |
| Started | Jan 03 12:21:12 PM PST 24 |
| Finished | Jan 03 12:22:34 PM PST 24 |
| Peak memory | 144780 kb |
| Host | smart-58f4301b-bd84-4469-9812-8219010ba0e4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2952418843 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.2952418843 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.1387150237 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 5108180000 ps |
| CPU time | 18.24 seconds |
| Started | Jan 03 12:21:08 PM PST 24 |
| Finished | Jan 03 12:22:03 PM PST 24 |
| Peak memory | 144540 kb |
| Host | smart-5b5c1608-c508-4a02-b18a-41bbdfedcc18 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1387150237 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.1387150237 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.2654800058 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 8428900000 ps |
| CPU time | 31.3 seconds |
| Started | Jan 03 12:21:07 PM PST 24 |
| Finished | Jan 03 12:22:25 PM PST 24 |
| Peak memory | 142552 kb |
| Host | smart-e11e193b-b5e5-48a7-ac61-2403a7bad36f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2654800058 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.2654800058 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |