| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/1.prim_present_test.3335099378 | ||
| Name |
|---|
| /workspace/coverage/default/0.prim_present_test.398963709 |
| /workspace/coverage/default/10.prim_present_test.2336934372 |
| /workspace/coverage/default/11.prim_present_test.2254913079 |
| /workspace/coverage/default/12.prim_present_test.2399201452 |
| /workspace/coverage/default/13.prim_present_test.2111355175 |
| /workspace/coverage/default/14.prim_present_test.2602312368 |
| /workspace/coverage/default/15.prim_present_test.2859277440 |
| /workspace/coverage/default/19.prim_present_test.2003950575 |
| /workspace/coverage/default/2.prim_present_test.793582664 |
| /workspace/coverage/default/20.prim_present_test.459470368 |
| /workspace/coverage/default/21.prim_present_test.3580897584 |
| /workspace/coverage/default/22.prim_present_test.219146680 |
| /workspace/coverage/default/25.prim_present_test.216001808 |
| /workspace/coverage/default/26.prim_present_test.1068850237 |
| /workspace/coverage/default/27.prim_present_test.2930806934 |
| /workspace/coverage/default/28.prim_present_test.233616733 |
| /workspace/coverage/default/29.prim_present_test.2438469684 |
| /workspace/coverage/default/3.prim_present_test.3856052056 |
| /workspace/coverage/default/30.prim_present_test.21651642 |
| /workspace/coverage/default/31.prim_present_test.386086886 |
| /workspace/coverage/default/33.prim_present_test.1998612691 |
| /workspace/coverage/default/34.prim_present_test.18281041 |
| /workspace/coverage/default/35.prim_present_test.4199746482 |
| /workspace/coverage/default/37.prim_present_test.4000431611 |
| /workspace/coverage/default/38.prim_present_test.2921729559 |
| /workspace/coverage/default/39.prim_present_test.2986632928 |
| /workspace/coverage/default/4.prim_present_test.4024592810 |
| /workspace/coverage/default/40.prim_present_test.367681789 |
| /workspace/coverage/default/41.prim_present_test.4175918660 |
| /workspace/coverage/default/42.prim_present_test.3909095382 |
| /workspace/coverage/default/44.prim_present_test.3711947840 |
| /workspace/coverage/default/45.prim_present_test.109794433 |
| /workspace/coverage/default/46.prim_present_test.4194643354 |
| /workspace/coverage/default/47.prim_present_test.3375603593 |
| /workspace/coverage/default/48.prim_present_test.3633332116 |
| /workspace/coverage/default/49.prim_present_test.1075023192 |
| /workspace/coverage/default/5.prim_present_test.1949755288 |
| /workspace/coverage/default/6.prim_present_test.2109237289 |
| /workspace/coverage/default/7.prim_present_test.3648964393 |
| /workspace/coverage/default/8.prim_present_test.3467860221 |
| /workspace/coverage/default/9.prim_present_test.690369148 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/1.prim_present_test.3335099378 | Jan 07 12:27:53 PM PST 24 | Jan 07 12:29:28 PM PST 24 | 3957460000 ps | ||
| T2 | /workspace/coverage/default/49.prim_present_test.1075023192 | Jan 07 12:30:18 PM PST 24 | Jan 07 12:33:00 PM PST 24 | 8936060000 ps | ||
| T3 | /workspace/coverage/default/25.prim_present_test.216001808 | Jan 07 12:33:02 PM PST 24 | Jan 07 12:35:26 PM PST 24 | 11234400000 ps | ||
| T4 | /workspace/coverage/default/4.prim_present_test.4024592810 | Jan 07 12:28:57 PM PST 24 | Jan 07 12:31:03 PM PST 24 | 5495680000 ps | ||
| T5 | /workspace/coverage/default/31.prim_present_test.386086886 | Jan 07 12:25:38 PM PST 24 | Jan 07 12:27:24 PM PST 24 | 8673180000 ps | ||
| T6 | /workspace/coverage/default/48.prim_present_test.3633332116 | Jan 07 12:26:29 PM PST 24 | Jan 07 12:29:11 PM PST 24 | 14871320000 ps | ||
| T7 | /workspace/coverage/default/44.prim_present_test.3711947840 | Jan 07 12:30:32 PM PST 24 | Jan 07 12:33:22 PM PST 24 | 14863260000 ps | ||
| T8 | /workspace/coverage/default/22.prim_present_test.219146680 | Jan 07 12:30:29 PM PST 24 | Jan 07 12:33:04 PM PST 24 | 12859420000 ps | ||
| T9 | /workspace/coverage/default/28.prim_present_test.233616733 | Jan 07 12:25:58 PM PST 24 | Jan 07 12:27:15 PM PST 24 | 3505480000 ps | ||
| T10 | /workspace/coverage/default/6.prim_present_test.2109237289 | Jan 07 12:32:46 PM PST 24 | Jan 07 12:34:30 PM PST 24 | 3292820000 ps | ||
| T11 | /workspace/coverage/default/42.prim_present_test.3909095382 | Jan 07 12:31:36 PM PST 24 | Jan 07 12:34:25 PM PST 24 | 10945480000 ps | ||
| T12 | /workspace/coverage/default/21.prim_present_test.3580897584 | Jan 07 12:30:37 PM PST 24 | Jan 07 12:33:11 PM PST 24 | 12581660000 ps | ||
| T13 | /workspace/coverage/default/10.prim_present_test.2336934372 | Jan 07 12:31:48 PM PST 24 | Jan 07 12:33:39 PM PST 24 | 6416380000 ps | ||
| T14 | /workspace/coverage/default/2.prim_present_test.793582664 | Jan 07 12:31:25 PM PST 24 | Jan 07 12:33:22 PM PST 24 | 4207940000 ps | ||
| T15 | /workspace/coverage/default/9.prim_present_test.690369148 | Jan 07 12:28:48 PM PST 24 | Jan 07 12:30:48 PM PST 24 | 7391640000 ps | ||
| T16 | /workspace/coverage/default/33.prim_present_test.1998612691 | Jan 07 12:32:21 PM PST 24 | Jan 07 12:35:13 PM PST 24 | 13645580000 ps | ||
| T17 | /workspace/coverage/default/29.prim_present_test.2438469684 | Jan 07 12:25:07 PM PST 24 | Jan 07 12:27:24 PM PST 24 | 13118580000 ps | ||
| T18 | /workspace/coverage/default/35.prim_present_test.4199746482 | Jan 07 12:29:35 PM PST 24 | Jan 07 12:32:38 PM PST 24 | 14108100000 ps | ||
| T19 | /workspace/coverage/default/15.prim_present_test.2859277440 | Jan 07 12:26:32 PM PST 24 | Jan 07 12:28:21 PM PST 24 | 7330260000 ps | ||
| T20 | /workspace/coverage/default/3.prim_present_test.3856052056 | Jan 07 12:24:05 PM PST 24 | Jan 07 12:25:16 PM PST 24 | 9681300000 ps | ||
| T21 | /workspace/coverage/default/41.prim_present_test.4175918660 | Jan 07 12:26:21 PM PST 24 | Jan 07 12:28:23 PM PST 24 | 10673920000 ps | ||
| T22 | /workspace/coverage/default/14.prim_present_test.2602312368 | Jan 07 12:24:10 PM PST 24 | Jan 07 12:25:23 PM PST 24 | 9788560000 ps | ||
| T23 | /workspace/coverage/default/39.prim_present_test.2986632928 | Jan 07 12:29:09 PM PST 24 | Jan 07 12:31:38 PM PST 24 | 13891720000 ps | ||
| T24 | /workspace/coverage/default/47.prim_present_test.3375603593 | Jan 07 12:30:02 PM PST 24 | Jan 07 12:33:16 PM PST 24 | 12800520000 ps | ||
| T25 | /workspace/coverage/default/0.prim_present_test.398963709 | Jan 07 12:33:47 PM PST 24 | Jan 07 12:36:06 PM PST 24 | 8363800000 ps | ||
| T26 | /workspace/coverage/default/13.prim_present_test.2111355175 | Jan 07 12:27:53 PM PST 24 | Jan 07 12:29:52 PM PST 24 | 8508880000 ps | ||
| T27 | /workspace/coverage/default/34.prim_present_test.18281041 | Jan 07 12:28:41 PM PST 24 | Jan 07 12:30:47 PM PST 24 | 9774920000 ps | ||
| T28 | /workspace/coverage/default/37.prim_present_test.4000431611 | Jan 07 12:29:35 PM PST 24 | Jan 07 12:31:59 PM PST 24 | 6594320000 ps | ||
| T29 | /workspace/coverage/default/20.prim_present_test.459470368 | Jan 07 12:31:19 PM PST 24 | Jan 07 12:33:51 PM PST 24 | 13088820000 ps | ||
| T30 | /workspace/coverage/default/8.prim_present_test.3467860221 | Jan 07 12:27:39 PM PST 24 | Jan 07 12:29:18 PM PST 24 | 7279420000 ps | ||
| T31 | /workspace/coverage/default/45.prim_present_test.109794433 | Jan 07 12:26:28 PM PST 24 | Jan 07 12:28:55 PM PST 24 | 11947400000 ps | ||
| T32 | /workspace/coverage/default/12.prim_present_test.2399201452 | Jan 07 12:28:33 PM PST 24 | Jan 07 12:31:07 PM PST 24 | 12661020000 ps | ||
| T33 | /workspace/coverage/default/38.prim_present_test.2921729559 | Jan 07 12:29:08 PM PST 24 | Jan 07 12:31:51 PM PST 24 | 12877400000 ps | ||
| T34 | /workspace/coverage/default/46.prim_present_test.4194643354 | Jan 07 12:26:27 PM PST 24 | Jan 07 12:28:00 PM PST 24 | 4099440000 ps | ||
| T35 | /workspace/coverage/default/7.prim_present_test.3648964393 | Jan 07 12:28:35 PM PST 24 | Jan 07 12:31:13 PM PST 24 | 15147220000 ps | ||
| T36 | /workspace/coverage/default/19.prim_present_test.2003950575 | Jan 07 12:32:53 PM PST 24 | Jan 07 12:34:51 PM PST 24 | 5221640000 ps | ||
| T37 | /workspace/coverage/default/27.prim_present_test.2930806934 | Jan 07 12:30:42 PM PST 24 | Jan 07 12:32:38 PM PST 24 | 8530580000 ps | ||
| T38 | /workspace/coverage/default/5.prim_present_test.1949755288 | Jan 07 12:28:33 PM PST 24 | Jan 07 12:30:12 PM PST 24 | 3836560000 ps | ||
| T39 | /workspace/coverage/default/11.prim_present_test.2254913079 | Jan 07 12:28:57 PM PST 24 | Jan 07 12:31:42 PM PST 24 | 9949760000 ps | ||
| T40 | /workspace/coverage/default/30.prim_present_test.21651642 | Jan 07 12:26:50 PM PST 24 | Jan 07 12:29:34 PM PST 24 | 15326400000 ps | ||
| T41 | /workspace/coverage/default/26.prim_present_test.1068850237 | Jan 07 12:27:13 PM PST 24 | Jan 07 12:28:55 PM PST 24 | 5751740000 ps | ||
| T42 | /workspace/coverage/default/40.prim_present_test.367681789 | Jan 07 12:26:05 PM PST 24 | Jan 07 12:27:39 PM PST 24 | 4759740000 ps |
| Test location | /workspace/coverage/default/1.prim_present_test.3335099378 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 3957460000 ps |
| CPU time | 12.66 seconds |
| Started | Jan 07 12:27:53 PM PST 24 |
| Finished | Jan 07 12:29:28 PM PST 24 |
| Peak memory | 144472 kb |
| Host | smart-0061fa6b-3426-4221-b5d1-ee24ae4c2d2a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3335099378 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.3335099378 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/0.prim_present_test.398963709 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 8363800000 ps |
| CPU time | 22.97 seconds |
| Started | Jan 07 12:33:47 PM PST 24 |
| Finished | Jan 07 12:36:06 PM PST 24 |
| Peak memory | 143716 kb |
| Host | smart-fd72ddb3-e6a1-49cf-9ab0-69f014208abc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=398963709 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.398963709 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/10.prim_present_test.2336934372 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 6416380000 ps |
| CPU time | 18.35 seconds |
| Started | Jan 07 12:31:48 PM PST 24 |
| Finished | Jan 07 12:33:39 PM PST 24 |
| Peak memory | 144332 kb |
| Host | smart-1178386f-8e0f-4de7-b929-18fa2da38f83 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2336934372 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.2336934372 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/11.prim_present_test.2254913079 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 9949760000 ps |
| CPU time | 30.18 seconds |
| Started | Jan 07 12:28:57 PM PST 24 |
| Finished | Jan 07 12:31:42 PM PST 24 |
| Peak memory | 144400 kb |
| Host | smart-ba1a5eb1-32c5-4ba3-a91c-be1b8c10124b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2254913079 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.2254913079 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.2399201452 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 12661020000 ps |
| CPU time | 45.32 seconds |
| Started | Jan 07 12:28:33 PM PST 24 |
| Finished | Jan 07 12:31:07 PM PST 24 |
| Peak memory | 143028 kb |
| Host | smart-77d4b220-1125-49ad-b77e-3f18d56a9fdb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2399201452 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.2399201452 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.2111355175 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 8508880000 ps |
| CPU time | 25.96 seconds |
| Started | Jan 07 12:27:53 PM PST 24 |
| Finished | Jan 07 12:29:52 PM PST 24 |
| Peak memory | 144608 kb |
| Host | smart-f88d0b62-8307-4cc3-bbf7-fc98306f1e3c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2111355175 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.2111355175 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.2602312368 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 9788560000 ps |
| CPU time | 29.93 seconds |
| Started | Jan 07 12:24:10 PM PST 24 |
| Finished | Jan 07 12:25:23 PM PST 24 |
| Peak memory | 144620 kb |
| Host | smart-df94ed3f-468f-4fce-8c3f-803649cbca7b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2602312368 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.2602312368 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.2859277440 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 7330260000 ps |
| CPU time | 21.28 seconds |
| Started | Jan 07 12:26:32 PM PST 24 |
| Finished | Jan 07 12:28:21 PM PST 24 |
| Peak memory | 143320 kb |
| Host | smart-7fc6d55f-680a-42aa-bd08-3e8e27207dab |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2859277440 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.2859277440 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.2003950575 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 5221640000 ps |
| CPU time | 16.07 seconds |
| Started | Jan 07 12:32:53 PM PST 24 |
| Finished | Jan 07 12:34:51 PM PST 24 |
| Peak memory | 144352 kb |
| Host | smart-fe0fa716-081c-46b9-8970-8537f2d9aed1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2003950575 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.2003950575 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.793582664 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 4207940000 ps |
| CPU time | 12.55 seconds |
| Started | Jan 07 12:31:25 PM PST 24 |
| Finished | Jan 07 12:33:22 PM PST 24 |
| Peak memory | 143596 kb |
| Host | smart-5a95ba24-cf84-4c30-867f-614e3e1aac66 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=793582664 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.793582664 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.459470368 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 13088820000 ps |
| CPU time | 36.39 seconds |
| Started | Jan 07 12:31:19 PM PST 24 |
| Finished | Jan 07 12:33:51 PM PST 24 |
| Peak memory | 144424 kb |
| Host | smart-00c5769a-e648-46ea-abf1-f5d9a2ad288d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=459470368 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.459470368 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.3580897584 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 12581660000 ps |
| CPU time | 33.71 seconds |
| Started | Jan 07 12:30:37 PM PST 24 |
| Finished | Jan 07 12:33:11 PM PST 24 |
| Peak memory | 143544 kb |
| Host | smart-593552ea-35a6-42f0-9c3f-11a35cb0f996 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3580897584 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.3580897584 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.219146680 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 12859420000 ps |
| CPU time | 36.26 seconds |
| Started | Jan 07 12:30:29 PM PST 24 |
| Finished | Jan 07 12:33:04 PM PST 24 |
| Peak memory | 143092 kb |
| Host | smart-de0fbb6a-423e-458c-abc3-affecb64c0af |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=219146680 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.219146680 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.216001808 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 11234400000 ps |
| CPU time | 31.22 seconds |
| Started | Jan 07 12:33:02 PM PST 24 |
| Finished | Jan 07 12:35:26 PM PST 24 |
| Peak memory | 144372 kb |
| Host | smart-22b77f73-d739-45d2-8210-75661773f098 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=216001808 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.216001808 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.1068850237 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 5751740000 ps |
| CPU time | 17.14 seconds |
| Started | Jan 07 12:27:13 PM PST 24 |
| Finished | Jan 07 12:28:55 PM PST 24 |
| Peak memory | 144628 kb |
| Host | smart-020cffd9-3a29-4234-af1a-66541d1902c9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1068850237 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.1068850237 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.2930806934 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 8530580000 ps |
| CPU time | 22.99 seconds |
| Started | Jan 07 12:30:42 PM PST 24 |
| Finished | Jan 07 12:32:38 PM PST 24 |
| Peak memory | 143724 kb |
| Host | smart-49c92f41-ec25-420b-a18c-2663c41486ac |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2930806934 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.2930806934 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.233616733 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 3505480000 ps |
| CPU time | 9.81 seconds |
| Started | Jan 07 12:25:58 PM PST 24 |
| Finished | Jan 07 12:27:15 PM PST 24 |
| Peak memory | 143984 kb |
| Host | smart-7ad4b6c7-ef58-4dac-8aa6-d747930203c0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=233616733 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.233616733 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.2438469684 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 13118580000 ps |
| CPU time | 38.47 seconds |
| Started | Jan 07 12:25:07 PM PST 24 |
| Finished | Jan 07 12:27:24 PM PST 24 |
| Peak memory | 144620 kb |
| Host | smart-4047ac31-7255-4b95-8b15-dff3a85156d7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2438469684 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.2438469684 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.3856052056 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 9681300000 ps |
| CPU time | 29.65 seconds |
| Started | Jan 07 12:24:05 PM PST 24 |
| Finished | Jan 07 12:25:16 PM PST 24 |
| Peak memory | 144768 kb |
| Host | smart-dd0fed7f-53bf-45a7-8d18-6901f89b9e19 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3856052056 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.3856052056 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.21651642 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 15326400000 ps |
| CPU time | 48.19 seconds |
| Started | Jan 07 12:26:50 PM PST 24 |
| Finished | Jan 07 12:29:34 PM PST 24 |
| Peak memory | 144740 kb |
| Host | smart-43de8ddf-cb8b-40c3-80f7-03e994188756 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=21651642 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.21651642 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.386086886 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 8673180000 ps |
| CPU time | 25.14 seconds |
| Started | Jan 07 12:25:38 PM PST 24 |
| Finished | Jan 07 12:27:24 PM PST 24 |
| Peak memory | 144324 kb |
| Host | smart-132d1acf-06c6-4579-8688-19803b8e3bbd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=386086886 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.386086886 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.1998612691 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 13645580000 ps |
| CPU time | 38.39 seconds |
| Started | Jan 07 12:32:21 PM PST 24 |
| Finished | Jan 07 12:35:13 PM PST 24 |
| Peak memory | 144408 kb |
| Host | smart-953a0ee7-091c-4f2b-9cbd-f848e7f4b334 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1998612691 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.1998612691 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.18281041 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 9774920000 ps |
| CPU time | 26.87 seconds |
| Started | Jan 07 12:28:41 PM PST 24 |
| Finished | Jan 07 12:30:47 PM PST 24 |
| Peak memory | 144192 kb |
| Host | smart-fc7b5788-f1d3-4594-b8b0-5eb6b1362a9f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=18281041 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.18281041 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.4199746482 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 14108100000 ps |
| CPU time | 47.43 seconds |
| Started | Jan 07 12:29:35 PM PST 24 |
| Finished | Jan 07 12:32:38 PM PST 24 |
| Peak memory | 144248 kb |
| Host | smart-75c86e7f-881e-4b7e-9cd1-d5351572ff33 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4199746482 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.4199746482 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.4000431611 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 6594320000 ps |
| CPU time | 26.37 seconds |
| Started | Jan 07 12:29:35 PM PST 24 |
| Finished | Jan 07 12:31:59 PM PST 24 |
| Peak memory | 144204 kb |
| Host | smart-0c8685e3-527a-48a6-8327-21832548485b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4000431611 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.4000431611 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.2921729559 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 12877400000 ps |
| CPU time | 40.19 seconds |
| Started | Jan 07 12:29:08 PM PST 24 |
| Finished | Jan 07 12:31:51 PM PST 24 |
| Peak memory | 143956 kb |
| Host | smart-04c936d6-b609-49c0-b35f-7d0916cb6cb2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2921729559 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.2921729559 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.2986632928 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 13891720000 ps |
| CPU time | 41.96 seconds |
| Started | Jan 07 12:29:09 PM PST 24 |
| Finished | Jan 07 12:31:38 PM PST 24 |
| Peak memory | 143692 kb |
| Host | smart-00e25f71-9d88-4cbd-b572-6a499e47f2d2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2986632928 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.2986632928 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.4024592810 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 5495680000 ps |
| CPU time | 19.96 seconds |
| Started | Jan 07 12:28:57 PM PST 24 |
| Finished | Jan 07 12:31:03 PM PST 24 |
| Peak memory | 144320 kb |
| Host | smart-94c4513c-501c-41f0-8694-b5e32fcab066 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4024592810 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.4024592810 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.367681789 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 4759740000 ps |
| CPU time | 14.17 seconds |
| Started | Jan 07 12:26:05 PM PST 24 |
| Finished | Jan 07 12:27:39 PM PST 24 |
| Peak memory | 144232 kb |
| Host | smart-3300e9a4-4e2a-424d-8af4-3044dbb51fcf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=367681789 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.367681789 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.4175918660 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 10673920000 ps |
| CPU time | 31.61 seconds |
| Started | Jan 07 12:26:21 PM PST 24 |
| Finished | Jan 07 12:28:23 PM PST 24 |
| Peak memory | 144400 kb |
| Host | smart-8fdaeed9-74af-42b9-8b56-a125a05df5c6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4175918660 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.4175918660 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.3909095382 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 10945480000 ps |
| CPU time | 30.01 seconds |
| Started | Jan 07 12:31:36 PM PST 24 |
| Finished | Jan 07 12:34:25 PM PST 24 |
| Peak memory | 144396 kb |
| Host | smart-816c2c14-d1c5-443b-a91d-cfc8608d850d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3909095382 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.3909095382 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.3711947840 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 14863260000 ps |
| CPU time | 48.94 seconds |
| Started | Jan 07 12:30:32 PM PST 24 |
| Finished | Jan 07 12:33:22 PM PST 24 |
| Peak memory | 144324 kb |
| Host | smart-2c13083d-fcd0-4757-8a11-2664300ffc0e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3711947840 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.3711947840 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.109794433 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 11947400000 ps |
| CPU time | 43.04 seconds |
| Started | Jan 07 12:26:28 PM PST 24 |
| Finished | Jan 07 12:28:55 PM PST 24 |
| Peak memory | 144368 kb |
| Host | smart-2e5292f0-7594-46e3-9d82-80e50eab5e1f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=109794433 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.109794433 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.4194643354 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 4099440000 ps |
| CPU time | 12.16 seconds |
| Started | Jan 07 12:26:27 PM PST 24 |
| Finished | Jan 07 12:28:00 PM PST 24 |
| Peak memory | 144252 kb |
| Host | smart-cf288488-1d6a-4e91-a2f7-87658fbd515e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4194643354 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.4194643354 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.3375603593 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 12800520000 ps |
| CPU time | 42.44 seconds |
| Started | Jan 07 12:30:02 PM PST 24 |
| Finished | Jan 07 12:33:16 PM PST 24 |
| Peak memory | 144312 kb |
| Host | smart-3b51969c-b9fd-4fb4-add0-eeac2683cbae |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3375603593 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.3375603593 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.3633332116 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 14871320000 ps |
| CPU time | 51.12 seconds |
| Started | Jan 07 12:26:29 PM PST 24 |
| Finished | Jan 07 12:29:11 PM PST 24 |
| Peak memory | 144368 kb |
| Host | smart-5f240675-0aab-4a78-ad96-a49d0e7de90e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3633332116 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.3633332116 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.1075023192 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 8936060000 ps |
| CPU time | 25.33 seconds |
| Started | Jan 07 12:30:18 PM PST 24 |
| Finished | Jan 07 12:33:00 PM PST 24 |
| Peak memory | 144360 kb |
| Host | smart-209e0bc1-5846-4fea-b85f-2995631d7e9c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1075023192 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.1075023192 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.1949755288 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 3836560000 ps |
| CPU time | 15.67 seconds |
| Started | Jan 07 12:28:33 PM PST 24 |
| Finished | Jan 07 12:30:12 PM PST 24 |
| Peak memory | 143016 kb |
| Host | smart-7d8ab059-ff89-49d0-ac1a-bf7532f6e01d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1949755288 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.1949755288 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.2109237289 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 3292820000 ps |
| CPU time | 9.47 seconds |
| Started | Jan 07 12:32:46 PM PST 24 |
| Finished | Jan 07 12:34:30 PM PST 24 |
| Peak memory | 144232 kb |
| Host | smart-0b904eb8-dd6c-4c8d-a053-96ea09b9f5ca |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2109237289 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.2109237289 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.3648964393 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 15147220000 ps |
| CPU time | 50.55 seconds |
| Started | Jan 07 12:28:35 PM PST 24 |
| Finished | Jan 07 12:31:13 PM PST 24 |
| Peak memory | 143516 kb |
| Host | smart-b27145a1-7838-4e4f-ba02-500170626d96 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3648964393 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.3648964393 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.3467860221 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 7279420000 ps |
| CPU time | 21.14 seconds |
| Started | Jan 07 12:27:39 PM PST 24 |
| Finished | Jan 07 12:29:18 PM PST 24 |
| Peak memory | 144652 kb |
| Host | smart-26878a6d-95a2-457e-8884-ded63a4ab6e1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3467860221 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.3467860221 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.690369148 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 7391640000 ps |
| CPU time | 29.58 seconds |
| Started | Jan 07 12:28:48 PM PST 24 |
| Finished | Jan 07 12:30:48 PM PST 24 |
| Peak memory | 144300 kb |
| Host | smart-987882c2-1a45-4f44-bc1a-74ef58314bad |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=690369148 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.690369148 |
| Directory | /workspace/9.prim_present_test/latest |
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