| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/10.prim_present_test.1929952947 | ||
| Name |
|---|
| /workspace/coverage/default/0.prim_present_test.839273603 |
| /workspace/coverage/default/1.prim_present_test.163268645 |
| /workspace/coverage/default/11.prim_present_test.1938443765 |
| /workspace/coverage/default/12.prim_present_test.3381976756 |
| /workspace/coverage/default/13.prim_present_test.3819709928 |
| /workspace/coverage/default/14.prim_present_test.4057423008 |
| /workspace/coverage/default/15.prim_present_test.1980946406 |
| /workspace/coverage/default/16.prim_present_test.3004905 |
| /workspace/coverage/default/17.prim_present_test.2620483309 |
| /workspace/coverage/default/18.prim_present_test.3996613961 |
| /workspace/coverage/default/19.prim_present_test.2443509088 |
| /workspace/coverage/default/2.prim_present_test.1447875874 |
| /workspace/coverage/default/20.prim_present_test.3445849282 |
| /workspace/coverage/default/21.prim_present_test.3540066933 |
| /workspace/coverage/default/22.prim_present_test.1486113923 |
| /workspace/coverage/default/23.prim_present_test.3897349743 |
| /workspace/coverage/default/24.prim_present_test.4093944333 |
| /workspace/coverage/default/25.prim_present_test.2666054521 |
| /workspace/coverage/default/26.prim_present_test.2077732710 |
| /workspace/coverage/default/27.prim_present_test.3794279915 |
| /workspace/coverage/default/28.prim_present_test.2168200646 |
| /workspace/coverage/default/29.prim_present_test.3753153991 |
| /workspace/coverage/default/3.prim_present_test.2022429897 |
| /workspace/coverage/default/30.prim_present_test.2527487992 |
| /workspace/coverage/default/31.prim_present_test.1300625401 |
| /workspace/coverage/default/32.prim_present_test.3383199046 |
| /workspace/coverage/default/33.prim_present_test.43944071 |
| /workspace/coverage/default/34.prim_present_test.2917727636 |
| /workspace/coverage/default/35.prim_present_test.2193607990 |
| /workspace/coverage/default/36.prim_present_test.3497784293 |
| /workspace/coverage/default/37.prim_present_test.2767743130 |
| /workspace/coverage/default/38.prim_present_test.455817561 |
| /workspace/coverage/default/39.prim_present_test.2809695662 |
| /workspace/coverage/default/4.prim_present_test.1637055241 |
| /workspace/coverage/default/40.prim_present_test.4016015092 |
| /workspace/coverage/default/41.prim_present_test.3790671035 |
| /workspace/coverage/default/42.prim_present_test.3884027218 |
| /workspace/coverage/default/43.prim_present_test.2754286023 |
| /workspace/coverage/default/44.prim_present_test.2191688008 |
| /workspace/coverage/default/45.prim_present_test.3461649121 |
| /workspace/coverage/default/46.prim_present_test.1782937327 |
| /workspace/coverage/default/47.prim_present_test.1272096261 |
| /workspace/coverage/default/48.prim_present_test.668855666 |
| /workspace/coverage/default/49.prim_present_test.394551917 |
| /workspace/coverage/default/5.prim_present_test.3226238323 |
| /workspace/coverage/default/6.prim_present_test.3033895421 |
| /workspace/coverage/default/7.prim_present_test.2381619110 |
| /workspace/coverage/default/8.prim_present_test.122056449 |
| /workspace/coverage/default/9.prim_present_test.185770083 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/37.prim_present_test.2767743130 | Jan 10 12:23:08 PM PST 24 | Jan 10 12:24:49 PM PST 24 | 14189940000 ps | ||
| T2 | /workspace/coverage/default/10.prim_present_test.1929952947 | Jan 10 12:25:29 PM PST 24 | Jan 10 12:26:19 PM PST 24 | 7821920000 ps | ||
| T3 | /workspace/coverage/default/34.prim_present_test.2917727636 | Jan 10 12:22:40 PM PST 24 | Jan 10 12:23:56 PM PST 24 | 12620720000 ps | ||
| T4 | /workspace/coverage/default/28.prim_present_test.2168200646 | Jan 10 12:28:02 PM PST 24 | Jan 10 12:29:34 PM PST 24 | 10499080000 ps | ||
| T5 | /workspace/coverage/default/13.prim_present_test.3819709928 | Jan 10 12:28:31 PM PST 24 | Jan 10 12:29:15 PM PST 24 | 5549620000 ps | ||
| T6 | /workspace/coverage/default/44.prim_present_test.2191688008 | Jan 10 12:21:55 PM PST 24 | Jan 10 12:22:34 PM PST 24 | 5737480000 ps | ||
| T7 | /workspace/coverage/default/14.prim_present_test.4057423008 | Jan 10 12:31:50 PM PST 24 | Jan 10 12:33:26 PM PST 24 | 9221260000 ps | ||
| T8 | /workspace/coverage/default/49.prim_present_test.394551917 | Jan 10 12:28:31 PM PST 24 | Jan 10 12:29:32 PM PST 24 | 8600640000 ps | ||
| T9 | /workspace/coverage/default/29.prim_present_test.3753153991 | Jan 10 12:27:46 PM PST 24 | Jan 10 12:29:14 PM PST 24 | 11397460000 ps | ||
| T10 | /workspace/coverage/default/27.prim_present_test.3794279915 | Jan 10 12:29:11 PM PST 24 | Jan 10 12:30:26 PM PST 24 | 10354620000 ps | ||
| T11 | /workspace/coverage/default/23.prim_present_test.3897349743 | Jan 10 12:21:36 PM PST 24 | Jan 10 12:23:13 PM PST 24 | 13075180000 ps | ||
| T12 | /workspace/coverage/default/5.prim_present_test.3226238323 | Jan 10 12:21:36 PM PST 24 | Jan 10 12:23:10 PM PST 24 | 12439680000 ps | ||
| T13 | /workspace/coverage/default/15.prim_present_test.1980946406 | Jan 10 12:27:03 PM PST 24 | Jan 10 12:27:36 PM PST 24 | 3971720000 ps | ||
| T14 | /workspace/coverage/default/36.prim_present_test.3497784293 | Jan 10 12:28:31 PM PST 24 | Jan 10 12:29:54 PM PST 24 | 12899100000 ps | ||
| T15 | /workspace/coverage/default/6.prim_present_test.3033895421 | Jan 10 12:21:53 PM PST 24 | Jan 10 12:22:47 PM PST 24 | 8162300000 ps | ||
| T16 | /workspace/coverage/default/8.prim_present_test.122056449 | Jan 10 12:26:54 PM PST 24 | Jan 10 12:28:10 PM PST 24 | 12467580000 ps | ||
| T17 | /workspace/coverage/default/33.prim_present_test.43944071 | Jan 10 12:23:11 PM PST 24 | Jan 10 12:23:52 PM PST 24 | 5681680000 ps | ||
| T18 | /workspace/coverage/default/7.prim_present_test.2381619110 | Jan 10 12:25:01 PM PST 24 | Jan 10 12:26:13 PM PST 24 | 12359700000 ps | ||
| T19 | /workspace/coverage/default/43.prim_present_test.2754286023 | Jan 10 12:28:03 PM PST 24 | Jan 10 12:29:38 PM PST 24 | 11069480000 ps | ||
| T20 | /workspace/coverage/default/40.prim_present_test.4016015092 | Jan 10 12:26:42 PM PST 24 | Jan 10 12:27:27 PM PST 24 | 7300500000 ps | ||
| T21 | /workspace/coverage/default/42.prim_present_test.3884027218 | Jan 10 12:25:58 PM PST 24 | Jan 10 12:26:59 PM PST 24 | 10030980000 ps | ||
| T22 | /workspace/coverage/default/39.prim_present_test.2809695662 | Jan 10 12:22:39 PM PST 24 | Jan 10 12:23:13 PM PST 24 | 5115000000 ps | ||
| T23 | /workspace/coverage/default/17.prim_present_test.2620483309 | Jan 10 12:27:02 PM PST 24 | Jan 10 12:28:05 PM PST 24 | 9169180000 ps | ||
| T24 | /workspace/coverage/default/16.prim_present_test.3004905 | Jan 10 12:21:57 PM PST 24 | Jan 10 12:22:25 PM PST 24 | 3734260000 ps | ||
| T25 | /workspace/coverage/default/24.prim_present_test.4093944333 | Jan 10 12:27:03 PM PST 24 | Jan 10 12:27:53 PM PST 24 | 6944000000 ps | ||
| T26 | /workspace/coverage/default/19.prim_present_test.2443509088 | Jan 10 12:30:55 PM PST 24 | Jan 10 12:32:37 PM PST 24 | 10815280000 ps | ||
| T27 | /workspace/coverage/default/9.prim_present_test.185770083 | Jan 10 12:28:07 PM PST 24 | Jan 10 12:29:03 PM PST 24 | 7003520000 ps | ||
| T28 | /workspace/coverage/default/1.prim_present_test.163268645 | Jan 10 12:28:07 PM PST 24 | Jan 10 12:29:25 PM PST 24 | 10865500000 ps | ||
| T29 | /workspace/coverage/default/20.prim_present_test.3445849282 | Jan 10 12:28:03 PM PST 24 | Jan 10 12:29:19 PM PST 24 | 8340860000 ps | ||
| T30 | /workspace/coverage/default/31.prim_present_test.1300625401 | Jan 10 12:21:55 PM PST 24 | Jan 10 12:23:02 PM PST 24 | 10210160000 ps | ||
| T31 | /workspace/coverage/default/18.prim_present_test.3996613961 | Jan 10 12:28:18 PM PST 24 | Jan 10 12:29:50 PM PST 24 | 15165820000 ps | ||
| T32 | /workspace/coverage/default/26.prim_present_test.2077732710 | Jan 10 12:23:18 PM PST 24 | Jan 10 12:23:47 PM PST 24 | 3517880000 ps | ||
| T33 | /workspace/coverage/default/2.prim_present_test.1447875874 | Jan 10 12:25:48 PM PST 24 | Jan 10 12:26:28 PM PST 24 | 7413340000 ps | ||
| T34 | /workspace/coverage/default/47.prim_present_test.1272096261 | Jan 10 12:26:33 PM PST 24 | Jan 10 12:27:24 PM PST 24 | 8033960000 ps | ||
| T35 | /workspace/coverage/default/41.prim_present_test.3790671035 | Jan 10 12:25:45 PM PST 24 | Jan 10 12:26:11 PM PST 24 | 4231500000 ps | ||
| T36 | /workspace/coverage/default/35.prim_present_test.2193607990 | Jan 10 12:28:02 PM PST 24 | Jan 10 12:29:35 PM PST 24 | 10704300000 ps | ||
| T37 | /workspace/coverage/default/11.prim_present_test.1938443765 | Jan 10 12:23:02 PM PST 24 | Jan 10 12:23:53 PM PST 24 | 8490900000 ps | ||
| T38 | /workspace/coverage/default/32.prim_present_test.3383199046 | Jan 10 12:22:08 PM PST 24 | Jan 10 12:22:44 PM PST 24 | 6953300000 ps | ||
| T39 | /workspace/coverage/default/25.prim_present_test.2666054521 | Jan 10 12:21:35 PM PST 24 | Jan 10 12:21:58 PM PST 24 | 3622660000 ps | ||
| T40 | /workspace/coverage/default/12.prim_present_test.3381976756 | Jan 10 12:24:05 PM PST 24 | Jan 10 12:25:30 PM PST 24 | 11918880000 ps | ||
| T41 | /workspace/coverage/default/22.prim_present_test.1486113923 | Jan 10 12:21:40 PM PST 24 | Jan 10 12:22:04 PM PST 24 | 3951260000 ps | ||
| T42 | /workspace/coverage/default/21.prim_present_test.3540066933 | Jan 10 12:28:01 PM PST 24 | Jan 10 12:29:06 PM PST 24 | 6585020000 ps | ||
| T43 | /workspace/coverage/default/4.prim_present_test.1637055241 | Jan 10 12:28:51 PM PST 24 | Jan 10 12:30:32 PM PST 24 | 15061040000 ps | ||
| T44 | /workspace/coverage/default/38.prim_present_test.455817561 | Jan 10 12:23:24 PM PST 24 | Jan 10 12:24:21 PM PST 24 | 8466720000 ps | ||
| T45 | /workspace/coverage/default/30.prim_present_test.2527487992 | Jan 10 12:28:01 PM PST 24 | Jan 10 12:29:32 PM PST 24 | 10132040000 ps | ||
| T46 | /workspace/coverage/default/3.prim_present_test.2022429897 | Jan 10 12:31:45 PM PST 24 | Jan 10 12:32:56 PM PST 24 | 3643120000 ps | ||
| T47 | /workspace/coverage/default/46.prim_present_test.1782937327 | Jan 10 12:26:35 PM PST 24 | Jan 10 12:27:01 PM PST 24 | 4317060000 ps | ||
| T48 | /workspace/coverage/default/48.prim_present_test.668855666 | Jan 10 12:29:52 PM PST 24 | Jan 10 12:30:45 PM PST 24 | 3308940000 ps | ||
| T49 | /workspace/coverage/default/45.prim_present_test.3461649121 | Jan 10 12:23:11 PM PST 24 | Jan 10 12:24:17 PM PST 24 | 9465540000 ps | ||
| T50 | /workspace/coverage/default/0.prim_present_test.839273603 | Jan 10 12:28:55 PM PST 24 | Jan 10 12:29:50 PM PST 24 | 6656320000 ps |
| Test location | /workspace/coverage/default/10.prim_present_test.1929952947 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 7821920000 ps |
| CPU time | 26.6 seconds |
| Started | Jan 10 12:25:29 PM PST 24 |
| Finished | Jan 10 12:26:19 PM PST 24 |
| Peak memory | 144636 kb |
| Host | smart-27601879-b352-41e4-94e6-3507a0fab083 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1929952947 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.1929952947 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/0.prim_present_test.839273603 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 6656320000 ps |
| CPU time | 20 seconds |
| Started | Jan 10 12:28:55 PM PST 24 |
| Finished | Jan 10 12:29:50 PM PST 24 |
| Peak memory | 144604 kb |
| Host | smart-25d33c2c-f71c-4f1e-8dd6-2691fc805422 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=839273603 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.839273603 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/1.prim_present_test.163268645 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 10865500000 ps |
| CPU time | 34.21 seconds |
| Started | Jan 10 12:28:07 PM PST 24 |
| Finished | Jan 10 12:29:25 PM PST 24 |
| Peak memory | 144624 kb |
| Host | smart-df05fa94-e3db-407a-aaad-4ac17d84c8a4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=163268645 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.163268645 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/11.prim_present_test.1938443765 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 8490900000 ps |
| CPU time | 27.74 seconds |
| Started | Jan 10 12:23:02 PM PST 24 |
| Finished | Jan 10 12:23:53 PM PST 24 |
| Peak memory | 144792 kb |
| Host | smart-2f806d0b-cbbf-4005-b9da-e2a668195fb2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1938443765 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.1938443765 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.3381976756 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 11918880000 ps |
| CPU time | 44 seconds |
| Started | Jan 10 12:24:05 PM PST 24 |
| Finished | Jan 10 12:25:30 PM PST 24 |
| Peak memory | 144820 kb |
| Host | smart-5fc45190-b6d5-4aba-9118-20ad9ef53008 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3381976756 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.3381976756 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.3819709928 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 5549620000 ps |
| CPU time | 18.66 seconds |
| Started | Jan 10 12:28:31 PM PST 24 |
| Finished | Jan 10 12:29:15 PM PST 24 |
| Peak memory | 144356 kb |
| Host | smart-50a89fa7-7669-4c5c-bd65-963c46c00d82 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3819709928 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.3819709928 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.4057423008 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 9221260000 ps |
| CPU time | 27.11 seconds |
| Started | Jan 10 12:31:50 PM PST 24 |
| Finished | Jan 10 12:33:26 PM PST 24 |
| Peak memory | 144368 kb |
| Host | smart-eb0081ac-0a44-494b-8d54-834c1b0576c8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4057423008 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.4057423008 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.1980946406 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 3971720000 ps |
| CPU time | 15.04 seconds |
| Started | Jan 10 12:27:03 PM PST 24 |
| Finished | Jan 10 12:27:36 PM PST 24 |
| Peak memory | 144428 kb |
| Host | smart-99f53fc6-0ffb-44e2-b051-5899d65e4c8e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1980946406 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.1980946406 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.3004905 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 3734260000 ps |
| CPU time | 14.88 seconds |
| Started | Jan 10 12:21:57 PM PST 24 |
| Finished | Jan 10 12:22:25 PM PST 24 |
| Peak memory | 144640 kb |
| Host | smart-5771f06c-9614-4793-abb9-0c5f5624c9ab |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3004905 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.3004905 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.2620483309 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 9169180000 ps |
| CPU time | 30.84 seconds |
| Started | Jan 10 12:27:02 PM PST 24 |
| Finished | Jan 10 12:28:05 PM PST 24 |
| Peak memory | 144560 kb |
| Host | smart-68550924-58d3-44e0-8b12-de358c45e23d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2620483309 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.2620483309 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.3996613961 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 15165820000 ps |
| CPU time | 43.75 seconds |
| Started | Jan 10 12:28:18 PM PST 24 |
| Finished | Jan 10 12:29:50 PM PST 24 |
| Peak memory | 144596 kb |
| Host | smart-30b4f7e6-8166-4384-b070-252bf4fba452 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3996613961 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.3996613961 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.2443509088 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 10815280000 ps |
| CPU time | 31.21 seconds |
| Started | Jan 10 12:30:55 PM PST 24 |
| Finished | Jan 10 12:32:37 PM PST 24 |
| Peak memory | 142904 kb |
| Host | smart-5e2c416f-5159-4a64-ae8b-2f4a952b45e8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2443509088 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.2443509088 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.1447875874 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 7413340000 ps |
| CPU time | 22.13 seconds |
| Started | Jan 10 12:25:48 PM PST 24 |
| Finished | Jan 10 12:26:28 PM PST 24 |
| Peak memory | 144620 kb |
| Host | smart-ad2a439f-7b3c-4c7e-b5bc-b8c73e83f2d9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1447875874 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.1447875874 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.3445849282 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 8340860000 ps |
| CPU time | 32.66 seconds |
| Started | Jan 10 12:28:03 PM PST 24 |
| Finished | Jan 10 12:29:19 PM PST 24 |
| Peak memory | 144456 kb |
| Host | smart-a2e2b371-7198-4e67-bba0-78e5b53d46f6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3445849282 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.3445849282 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.3540066933 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 6585020000 ps |
| CPU time | 26.94 seconds |
| Started | Jan 10 12:28:01 PM PST 24 |
| Finished | Jan 10 12:29:06 PM PST 24 |
| Peak memory | 144444 kb |
| Host | smart-ad607cc4-3da6-48e0-b3bf-50ba5dace438 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3540066933 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.3540066933 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.1486113923 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 3951260000 ps |
| CPU time | 12.11 seconds |
| Started | Jan 10 12:21:40 PM PST 24 |
| Finished | Jan 10 12:22:04 PM PST 24 |
| Peak memory | 144168 kb |
| Host | smart-f80b9553-2818-487d-8c73-ec5f051b6a29 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1486113923 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.1486113923 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.3897349743 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 13075180000 ps |
| CPU time | 51.01 seconds |
| Started | Jan 10 12:21:36 PM PST 24 |
| Finished | Jan 10 12:23:13 PM PST 24 |
| Peak memory | 144084 kb |
| Host | smart-15563513-8819-46be-8595-7de4fe34d583 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3897349743 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.3897349743 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.4093944333 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 6944000000 ps |
| CPU time | 24.19 seconds |
| Started | Jan 10 12:27:03 PM PST 24 |
| Finished | Jan 10 12:27:53 PM PST 24 |
| Peak memory | 144564 kb |
| Host | smart-733476cc-6217-498d-a806-abe4b175ec4d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4093944333 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.4093944333 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.2666054521 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 3622660000 ps |
| CPU time | 11.91 seconds |
| Started | Jan 10 12:21:35 PM PST 24 |
| Finished | Jan 10 12:21:58 PM PST 24 |
| Peak memory | 143852 kb |
| Host | smart-69ce2fd2-01cd-4081-b7cb-40c1165764de |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2666054521 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.2666054521 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.2077732710 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 3517880000 ps |
| CPU time | 11.32 seconds |
| Started | Jan 10 12:23:18 PM PST 24 |
| Finished | Jan 10 12:23:47 PM PST 24 |
| Peak memory | 144488 kb |
| Host | smart-2e2300d8-fc52-4831-86be-0bba526b80fa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2077732710 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.2077732710 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.3794279915 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 10354620000 ps |
| CPU time | 29.24 seconds |
| Started | Jan 10 12:29:11 PM PST 24 |
| Finished | Jan 10 12:30:26 PM PST 24 |
| Peak memory | 144284 kb |
| Host | smart-40cb779c-a58b-48d8-b080-5684f72c4523 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3794279915 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.3794279915 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.2168200646 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 10499080000 ps |
| CPU time | 42.04 seconds |
| Started | Jan 10 12:28:02 PM PST 24 |
| Finished | Jan 10 12:29:34 PM PST 24 |
| Peak memory | 144424 kb |
| Host | smart-7274642f-d452-4a9f-a4cf-c72163afad35 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2168200646 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.2168200646 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.3753153991 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 11397460000 ps |
| CPU time | 40.43 seconds |
| Started | Jan 10 12:27:46 PM PST 24 |
| Finished | Jan 10 12:29:14 PM PST 24 |
| Peak memory | 143164 kb |
| Host | smart-36f1063c-dc63-48a0-bdb8-a737853731c6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3753153991 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.3753153991 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.2022429897 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 3643120000 ps |
| CPU time | 13.36 seconds |
| Started | Jan 10 12:31:45 PM PST 24 |
| Finished | Jan 10 12:32:56 PM PST 24 |
| Peak memory | 144232 kb |
| Host | smart-ba9b35b2-e4b6-45df-ac68-837a1a4dbb6a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2022429897 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.2022429897 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.2527487992 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 10132040000 ps |
| CPU time | 40.35 seconds |
| Started | Jan 10 12:28:01 PM PST 24 |
| Finished | Jan 10 12:29:32 PM PST 24 |
| Peak memory | 144444 kb |
| Host | smart-6ffd57a7-6550-4e08-b5bd-9f48f310b4c9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2527487992 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.2527487992 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.1300625401 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 10210160000 ps |
| CPU time | 36.18 seconds |
| Started | Jan 10 12:21:55 PM PST 24 |
| Finished | Jan 10 12:23:02 PM PST 24 |
| Peak memory | 144792 kb |
| Host | smart-68cc89fb-9560-4d45-ada6-4079bc484042 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1300625401 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.1300625401 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.3383199046 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 6953300000 ps |
| CPU time | 20.4 seconds |
| Started | Jan 10 12:22:08 PM PST 24 |
| Finished | Jan 10 12:22:44 PM PST 24 |
| Peak memory | 144604 kb |
| Host | smart-bb61e9fc-2039-4011-aa81-aa1d8cb13fd0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3383199046 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.3383199046 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.43944071 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 5681680000 ps |
| CPU time | 18.61 seconds |
| Started | Jan 10 12:23:11 PM PST 24 |
| Finished | Jan 10 12:23:52 PM PST 24 |
| Peak memory | 144624 kb |
| Host | smart-8b1a890c-6f4e-4ca3-8bd1-2c696a5f936d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=43944071 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.43944071 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.2917727636 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 12620720000 ps |
| CPU time | 41.41 seconds |
| Started | Jan 10 12:22:40 PM PST 24 |
| Finished | Jan 10 12:23:56 PM PST 24 |
| Peak memory | 144700 kb |
| Host | smart-87353287-f0ac-4a7c-ad44-fcceb36c8ee3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2917727636 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.2917727636 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.2193607990 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 10704300000 ps |
| CPU time | 41.34 seconds |
| Started | Jan 10 12:28:02 PM PST 24 |
| Finished | Jan 10 12:29:35 PM PST 24 |
| Peak memory | 144444 kb |
| Host | smart-9d2f9798-bbea-4f84-b53a-f6c8dd327e7d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2193607990 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.2193607990 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.3497784293 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 12899100000 ps |
| CPU time | 40.29 seconds |
| Started | Jan 10 12:28:31 PM PST 24 |
| Finished | Jan 10 12:29:54 PM PST 24 |
| Peak memory | 144356 kb |
| Host | smart-9072ceee-b9c8-4f11-88c6-0f7c5e8235c1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3497784293 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.3497784293 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.2767743130 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 14189940000 ps |
| CPU time | 49.92 seconds |
| Started | Jan 10 12:23:08 PM PST 24 |
| Finished | Jan 10 12:24:49 PM PST 24 |
| Peak memory | 144824 kb |
| Host | smart-37a26d03-1c5b-4e26-98ef-b81cdae7412a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2767743130 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.2767743130 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.455817561 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 8466720000 ps |
| CPU time | 28.93 seconds |
| Started | Jan 10 12:23:24 PM PST 24 |
| Finished | Jan 10 12:24:21 PM PST 24 |
| Peak memory | 144672 kb |
| Host | smart-d8b290c5-797e-402f-bfae-aed73f0d6899 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=455817561 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.455817561 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.2809695662 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 5115000000 ps |
| CPU time | 18.77 seconds |
| Started | Jan 10 12:22:39 PM PST 24 |
| Finished | Jan 10 12:23:13 PM PST 24 |
| Peak memory | 144700 kb |
| Host | smart-51583f1e-b796-4b94-9503-440f2aaca939 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2809695662 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.2809695662 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.1637055241 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 15061040000 ps |
| CPU time | 46.62 seconds |
| Started | Jan 10 12:28:51 PM PST 24 |
| Finished | Jan 10 12:30:32 PM PST 24 |
| Peak memory | 144656 kb |
| Host | smart-40399542-1438-4ff9-b405-d06b07172282 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1637055241 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.1637055241 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.4016015092 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 7300500000 ps |
| CPU time | 22.1 seconds |
| Started | Jan 10 12:26:42 PM PST 24 |
| Finished | Jan 10 12:27:27 PM PST 24 |
| Peak memory | 144592 kb |
| Host | smart-637b1289-b434-4c1c-a620-f878595efd9e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4016015092 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.4016015092 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.3790671035 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 4231500000 ps |
| CPU time | 13.98 seconds |
| Started | Jan 10 12:25:45 PM PST 24 |
| Finished | Jan 10 12:26:11 PM PST 24 |
| Peak memory | 144536 kb |
| Host | smart-6648bf93-c715-4ae6-badb-9c7a8bbe01fb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3790671035 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.3790671035 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.3884027218 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 10030980000 ps |
| CPU time | 32.86 seconds |
| Started | Jan 10 12:25:58 PM PST 24 |
| Finished | Jan 10 12:26:59 PM PST 24 |
| Peak memory | 144792 kb |
| Host | smart-b89d5746-9d6c-4efc-aa85-c6e5a3a0e670 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3884027218 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.3884027218 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.2754286023 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 11069480000 ps |
| CPU time | 42.72 seconds |
| Started | Jan 10 12:28:03 PM PST 24 |
| Finished | Jan 10 12:29:38 PM PST 24 |
| Peak memory | 144456 kb |
| Host | smart-a3c7cd20-2386-414b-b49f-c84424eacbbf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2754286023 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.2754286023 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.2191688008 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 5737480000 ps |
| CPU time | 20.98 seconds |
| Started | Jan 10 12:21:55 PM PST 24 |
| Finished | Jan 10 12:22:34 PM PST 24 |
| Peak memory | 144792 kb |
| Host | smart-aa52de92-dd0c-4eb8-9ed8-7953b35442df |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2191688008 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.2191688008 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.3461649121 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 9465540000 ps |
| CPU time | 32.88 seconds |
| Started | Jan 10 12:23:11 PM PST 24 |
| Finished | Jan 10 12:24:17 PM PST 24 |
| Peak memory | 144636 kb |
| Host | smart-d7669077-6745-4a6e-91df-915685968b8f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3461649121 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.3461649121 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.1782937327 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 4317060000 ps |
| CPU time | 12.66 seconds |
| Started | Jan 10 12:26:35 PM PST 24 |
| Finished | Jan 10 12:27:01 PM PST 24 |
| Peak memory | 143444 kb |
| Host | smart-a4da0c58-28a3-4d79-84c7-0aa8a05d3fbe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1782937327 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.1782937327 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.1272096261 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 8033960000 ps |
| CPU time | 26.42 seconds |
| Started | Jan 10 12:26:33 PM PST 24 |
| Finished | Jan 10 12:27:24 PM PST 24 |
| Peak memory | 144648 kb |
| Host | smart-963679fb-116c-46ab-b621-e8375e753458 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1272096261 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.1272096261 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.668855666 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 3308940000 ps |
| CPU time | 9.52 seconds |
| Started | Jan 10 12:29:52 PM PST 24 |
| Finished | Jan 10 12:30:45 PM PST 24 |
| Peak memory | 144280 kb |
| Host | smart-ca6b85f7-722a-4825-b40e-e804ff92af6f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=668855666 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.668855666 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.394551917 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 8600640000 ps |
| CPU time | 28.04 seconds |
| Started | Jan 10 12:28:31 PM PST 24 |
| Finished | Jan 10 12:29:32 PM PST 24 |
| Peak memory | 144352 kb |
| Host | smart-76630323-c331-4061-a331-738818501776 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=394551917 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.394551917 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.3226238323 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 12439680000 ps |
| CPU time | 49.58 seconds |
| Started | Jan 10 12:21:36 PM PST 24 |
| Finished | Jan 10 12:23:10 PM PST 24 |
| Peak memory | 143568 kb |
| Host | smart-c9abb105-f708-4e01-a611-24978c33caf8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3226238323 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.3226238323 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.3033895421 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 8162300000 ps |
| CPU time | 29.49 seconds |
| Started | Jan 10 12:21:53 PM PST 24 |
| Finished | Jan 10 12:22:47 PM PST 24 |
| Peak memory | 144792 kb |
| Host | smart-d55a4b06-7a33-4f0f-a59b-2a1fc94f44e5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3033895421 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.3033895421 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.2381619110 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 12359700000 ps |
| CPU time | 39.69 seconds |
| Started | Jan 10 12:25:01 PM PST 24 |
| Finished | Jan 10 12:26:13 PM PST 24 |
| Peak memory | 144632 kb |
| Host | smart-14811c7a-07ff-45bb-a2c4-1fe16563ebe2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2381619110 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.2381619110 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.122056449 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 12467580000 ps |
| CPU time | 39.13 seconds |
| Started | Jan 10 12:26:54 PM PST 24 |
| Finished | Jan 10 12:28:10 PM PST 24 |
| Peak memory | 144648 kb |
| Host | smart-50cc97c4-30c9-4571-a7e1-2e00dbd2e959 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=122056449 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.122056449 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.185770083 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 7003520000 ps |
| CPU time | 21.61 seconds |
| Started | Jan 10 12:28:07 PM PST 24 |
| Finished | Jan 10 12:29:03 PM PST 24 |
| Peak memory | 144632 kb |
| Host | smart-1ced7413-a0d7-45d7-9095-d77eb7b49a90 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=185770083 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.185770083 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |