| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/17.prim_present_test.2469986118 | ||
| Name |
|---|
| /workspace/coverage/default/0.prim_present_test.2257532671 |
| /workspace/coverage/default/1.prim_present_test.1266884013 |
| /workspace/coverage/default/10.prim_present_test.1530865795 |
| /workspace/coverage/default/11.prim_present_test.3703010550 |
| /workspace/coverage/default/12.prim_present_test.382633389 |
| /workspace/coverage/default/13.prim_present_test.3786879982 |
| /workspace/coverage/default/14.prim_present_test.928279882 |
| /workspace/coverage/default/15.prim_present_test.2036320977 |
| /workspace/coverage/default/16.prim_present_test.136477551 |
| /workspace/coverage/default/18.prim_present_test.2324323806 |
| /workspace/coverage/default/19.prim_present_test.588284563 |
| /workspace/coverage/default/2.prim_present_test.871668718 |
| /workspace/coverage/default/20.prim_present_test.1085041723 |
| /workspace/coverage/default/21.prim_present_test.2574059009 |
| /workspace/coverage/default/22.prim_present_test.1509017089 |
| /workspace/coverage/default/23.prim_present_test.2711624455 |
| /workspace/coverage/default/24.prim_present_test.2443411206 |
| /workspace/coverage/default/25.prim_present_test.43896602 |
| /workspace/coverage/default/26.prim_present_test.1105523777 |
| /workspace/coverage/default/27.prim_present_test.3473433835 |
| /workspace/coverage/default/28.prim_present_test.3488463173 |
| /workspace/coverage/default/29.prim_present_test.3480054590 |
| /workspace/coverage/default/3.prim_present_test.3263981390 |
| /workspace/coverage/default/30.prim_present_test.4182215583 |
| /workspace/coverage/default/31.prim_present_test.3004125104 |
| /workspace/coverage/default/32.prim_present_test.2479516068 |
| /workspace/coverage/default/33.prim_present_test.110419531 |
| /workspace/coverage/default/34.prim_present_test.2626376553 |
| /workspace/coverage/default/35.prim_present_test.3655928292 |
| /workspace/coverage/default/36.prim_present_test.2061722693 |
| /workspace/coverage/default/37.prim_present_test.1364508068 |
| /workspace/coverage/default/38.prim_present_test.1103498050 |
| /workspace/coverage/default/39.prim_present_test.1607718764 |
| /workspace/coverage/default/4.prim_present_test.1068383133 |
| /workspace/coverage/default/40.prim_present_test.1449340464 |
| /workspace/coverage/default/41.prim_present_test.2786277 |
| /workspace/coverage/default/42.prim_present_test.405311363 |
| /workspace/coverage/default/43.prim_present_test.1889627936 |
| /workspace/coverage/default/44.prim_present_test.3925372160 |
| /workspace/coverage/default/45.prim_present_test.395120280 |
| /workspace/coverage/default/46.prim_present_test.195020073 |
| /workspace/coverage/default/47.prim_present_test.166980292 |
| /workspace/coverage/default/48.prim_present_test.990747867 |
| /workspace/coverage/default/49.prim_present_test.3480032709 |
| /workspace/coverage/default/5.prim_present_test.927218511 |
| /workspace/coverage/default/6.prim_present_test.962062716 |
| /workspace/coverage/default/7.prim_present_test.3060809346 |
| /workspace/coverage/default/8.prim_present_test.4110115585 |
| /workspace/coverage/default/9.prim_present_test.54018320 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/23.prim_present_test.2711624455 | Jan 14 12:16:05 PM PST 24 | Jan 14 12:16:32 PM PST 24 | 3315140000 ps | ||
| T2 | /workspace/coverage/default/6.prim_present_test.962062716 | Jan 14 12:16:09 PM PST 24 | Jan 14 12:17:13 PM PST 24 | 8738280000 ps | ||
| T3 | /workspace/coverage/default/18.prim_present_test.2324323806 | Jan 14 12:15:56 PM PST 24 | Jan 14 12:17:44 PM PST 24 | 13416800000 ps | ||
| T4 | /workspace/coverage/default/38.prim_present_test.1103498050 | Jan 14 12:16:02 PM PST 24 | Jan 14 12:17:42 PM PST 24 | 13312640000 ps | ||
| T5 | /workspace/coverage/default/25.prim_present_test.43896602 | Jan 14 12:16:05 PM PST 24 | Jan 14 12:16:48 PM PST 24 | 5617820000 ps | ||
| T6 | /workspace/coverage/default/22.prim_present_test.1509017089 | Jan 14 12:16:09 PM PST 24 | Jan 14 12:17:56 PM PST 24 | 15296640000 ps | ||
| T7 | /workspace/coverage/default/17.prim_present_test.2469986118 | Jan 14 12:15:55 PM PST 24 | Jan 14 12:17:41 PM PST 24 | 12930720000 ps | ||
| T8 | /workspace/coverage/default/4.prim_present_test.1068383133 | Jan 14 12:15:57 PM PST 24 | Jan 14 12:17:58 PM PST 24 | 15342520000 ps | ||
| T9 | /workspace/coverage/default/36.prim_present_test.2061722693 | Jan 14 12:16:05 PM PST 24 | Jan 14 12:17:30 PM PST 24 | 11082500000 ps | ||
| T10 | /workspace/coverage/default/43.prim_present_test.1889627936 | Jan 14 12:16:06 PM PST 24 | Jan 14 12:16:35 PM PST 24 | 4028760000 ps | ||
| T11 | /workspace/coverage/default/35.prim_present_test.3655928292 | Jan 14 12:16:06 PM PST 24 | Jan 14 12:17:02 PM PST 24 | 7870280000 ps | ||
| T12 | /workspace/coverage/default/49.prim_present_test.3480032709 | Jan 14 12:16:02 PM PST 24 | Jan 14 12:18:00 PM PST 24 | 14718800000 ps | ||
| T13 | /workspace/coverage/default/27.prim_present_test.3473433835 | Jan 14 12:16:03 PM PST 24 | Jan 14 12:16:44 PM PST 24 | 4738660000 ps | ||
| T14 | /workspace/coverage/default/40.prim_present_test.1449340464 | Jan 14 12:16:01 PM PST 24 | Jan 14 12:18:02 PM PST 24 | 14935800000 ps | ||
| T15 | /workspace/coverage/default/34.prim_present_test.2626376553 | Jan 14 12:16:06 PM PST 24 | Jan 14 12:17:20 PM PST 24 | 10424680000 ps | ||
| T16 | /workspace/coverage/default/46.prim_present_test.195020073 | Jan 14 12:16:01 PM PST 24 | Jan 14 12:17:26 PM PST 24 | 10185980000 ps | ||
| T17 | /workspace/coverage/default/19.prim_present_test.588284563 | Jan 14 12:15:57 PM PST 24 | Jan 14 12:17:04 PM PST 24 | 8144320000 ps | ||
| T18 | /workspace/coverage/default/15.prim_present_test.2036320977 | Jan 14 12:16:09 PM PST 24 | Jan 14 12:17:46 PM PST 24 | 13461440000 ps | ||
| T19 | /workspace/coverage/default/12.prim_present_test.382633389 | Jan 14 12:16:09 PM PST 24 | Jan 14 12:17:00 PM PST 24 | 6881380000 ps | ||
| T20 | /workspace/coverage/default/20.prim_present_test.1085041723 | Jan 14 12:16:09 PM PST 24 | Jan 14 12:17:43 PM PST 24 | 13075180000 ps | ||
| T21 | /workspace/coverage/default/42.prim_present_test.405311363 | Jan 14 12:16:06 PM PST 24 | Jan 14 12:17:31 PM PST 24 | 12016840000 ps | ||
| T22 | /workspace/coverage/default/26.prim_present_test.1105523777 | Jan 14 12:16:04 PM PST 24 | Jan 14 12:17:12 PM PST 24 | 8653340000 ps | ||
| T23 | /workspace/coverage/default/32.prim_present_test.2479516068 | Jan 14 12:16:02 PM PST 24 | Jan 14 12:16:57 PM PST 24 | 6577580000 ps | ||
| T24 | /workspace/coverage/default/10.prim_present_test.1530865795 | Jan 14 12:16:09 PM PST 24 | Jan 14 12:17:27 PM PST 24 | 10914480000 ps | ||
| T25 | /workspace/coverage/default/44.prim_present_test.3925372160 | Jan 14 12:16:05 PM PST 24 | Jan 14 12:16:32 PM PST 24 | 3369700000 ps | ||
| T26 | /workspace/coverage/default/7.prim_present_test.3060809346 | Jan 14 12:15:56 PM PST 24 | Jan 14 12:17:08 PM PST 24 | 8528100000 ps | ||
| T27 | /workspace/coverage/default/48.prim_present_test.990747867 | Jan 14 12:16:04 PM PST 24 | Jan 14 12:17:24 PM PST 24 | 10137620000 ps | ||
| T28 | /workspace/coverage/default/5.prim_present_test.927218511 | Jan 14 12:16:09 PM PST 24 | Jan 14 12:17:13 PM PST 24 | 8725880000 ps | ||
| T29 | /workspace/coverage/default/11.prim_present_test.3703010550 | Jan 14 12:16:09 PM PST 24 | Jan 14 12:17:51 PM PST 24 | 14422440000 ps | ||
| T30 | /workspace/coverage/default/9.prim_present_test.54018320 | Jan 14 12:16:01 PM PST 24 | Jan 14 12:17:15 PM PST 24 | 13442220000 ps | ||
| T31 | /workspace/coverage/default/30.prim_present_test.4182215583 | Jan 14 12:16:04 PM PST 24 | Jan 14 12:17:11 PM PST 24 | 8618000000 ps | ||
| T32 | /workspace/coverage/default/8.prim_present_test.4110115585 | Jan 14 12:15:56 PM PST 24 | Jan 14 12:17:06 PM PST 24 | 8397280000 ps | ||
| T33 | /workspace/coverage/default/28.prim_present_test.3488463173 | Jan 14 12:16:06 PM PST 24 | Jan 14 12:17:38 PM PST 24 | 13191120000 ps | ||
| T34 | /workspace/coverage/default/24.prim_present_test.2443411206 | Jan 14 12:16:02 PM PST 24 | Jan 14 12:16:49 PM PST 24 | 6208060000 ps | ||
| T35 | /workspace/coverage/default/2.prim_present_test.871668718 | Jan 14 12:15:44 PM PST 24 | Jan 14 12:16:32 PM PST 24 | 6247740000 ps | ||
| T36 | /workspace/coverage/default/47.prim_present_test.166980292 | Jan 14 12:16:01 PM PST 24 | Jan 14 12:17:45 PM PST 24 | 12293980000 ps | ||
| T37 | /workspace/coverage/default/1.prim_present_test.1266884013 | Jan 14 12:16:02 PM PST 24 | Jan 14 12:16:57 PM PST 24 | 10012380000 ps | ||
| T38 | /workspace/coverage/default/3.prim_present_test.3263981390 | Jan 14 12:15:57 PM PST 24 | Jan 14 12:17:46 PM PST 24 | 13599700000 ps | ||
| T39 | /workspace/coverage/default/13.prim_present_test.3786879982 | Jan 14 12:16:09 PM PST 24 | Jan 14 12:17:29 PM PST 24 | 11264160000 ps | ||
| T40 | /workspace/coverage/default/14.prim_present_test.928279882 | Jan 14 12:15:56 PM PST 24 | Jan 14 12:16:46 PM PST 24 | 5769720000 ps | ||
| T41 | /workspace/coverage/default/29.prim_present_test.3480054590 | Jan 14 12:16:04 PM PST 24 | Jan 14 12:16:43 PM PST 24 | 4720680000 ps | ||
| T42 | /workspace/coverage/default/16.prim_present_test.136477551 | Jan 14 12:15:55 PM PST 24 | Jan 14 12:17:19 PM PST 24 | 10350900000 ps | ||
| T43 | /workspace/coverage/default/37.prim_present_test.1364508068 | Jan 14 12:16:04 PM PST 24 | Jan 14 12:16:57 PM PST 24 | 6715840000 ps | ||
| T44 | /workspace/coverage/default/0.prim_present_test.2257532671 | Jan 14 12:16:09 PM PST 24 | Jan 14 12:17:18 PM PST 24 | 9569700000 ps | ||
| T45 | /workspace/coverage/default/41.prim_present_test.2786277 | Jan 14 12:16:06 PM PST 24 | Jan 14 12:17:34 PM PST 24 | 12500440000 ps | ||
| T46 | /workspace/coverage/default/31.prim_present_test.3004125104 | Jan 14 12:16:04 PM PST 24 | Jan 14 12:17:34 PM PST 24 | 11948020000 ps | ||
| T47 | /workspace/coverage/default/33.prim_present_test.110419531 | Jan 14 12:16:04 PM PST 24 | Jan 14 12:17:31 PM PST 24 | 11268500000 ps | ||
| T48 | /workspace/coverage/default/39.prim_present_test.1607718764 | Jan 14 12:16:02 PM PST 24 | Jan 14 12:17:26 PM PST 24 | 9889620000 ps | ||
| T49 | /workspace/coverage/default/45.prim_present_test.395120280 | Jan 14 12:16:06 PM PST 24 | Jan 14 12:17:33 PM PST 24 | 12320020000 ps | ||
| T50 | /workspace/coverage/default/21.prim_present_test.2574059009 | Jan 14 12:15:57 PM PST 24 | Jan 14 12:16:25 PM PST 24 | 3176260000 ps |
| Test location | /workspace/coverage/default/17.prim_present_test.2469986118 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 12930720000 ps |
| CPU time | 54.97 seconds |
| Started | Jan 14 12:15:55 PM PST 24 |
| Finished | Jan 14 12:17:41 PM PST 24 |
| Peak memory | 144656 kb |
| Host | smart-abc2c9a2-baab-4cbd-9936-6f3a38e21748 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2469986118 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.2469986118 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/0.prim_present_test.2257532671 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 9569700000 ps |
| CPU time | 36.66 seconds |
| Started | Jan 14 12:16:09 PM PST 24 |
| Finished | Jan 14 12:17:18 PM PST 24 |
| Peak memory | 144052 kb |
| Host | smart-5e024c00-c3e3-4505-8ce6-f32615679aca |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2257532671 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.2257532671 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/1.prim_present_test.1266884013 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 10012380000 ps |
| CPU time | 30.08 seconds |
| Started | Jan 14 12:16:02 PM PST 24 |
| Finished | Jan 14 12:16:57 PM PST 24 |
| Peak memory | 144040 kb |
| Host | smart-c9823d52-ce48-45c1-91cd-da73bb965e4c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1266884013 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.1266884013 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/10.prim_present_test.1530865795 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 10914480000 ps |
| CPU time | 41.52 seconds |
| Started | Jan 14 12:16:09 PM PST 24 |
| Finished | Jan 14 12:17:27 PM PST 24 |
| Peak memory | 143984 kb |
| Host | smart-fbb20328-00c8-427c-a347-27931651ddad |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1530865795 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.1530865795 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/11.prim_present_test.3703010550 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 14422440000 ps |
| CPU time | 54.76 seconds |
| Started | Jan 14 12:16:09 PM PST 24 |
| Finished | Jan 14 12:17:51 PM PST 24 |
| Peak memory | 144052 kb |
| Host | smart-42cfc10d-ab81-4d82-9690-499a72338c7e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3703010550 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.3703010550 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.382633389 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 6881380000 ps |
| CPU time | 27.21 seconds |
| Started | Jan 14 12:16:09 PM PST 24 |
| Finished | Jan 14 12:17:00 PM PST 24 |
| Peak memory | 143492 kb |
| Host | smart-c7541a98-b2e9-4119-a69f-4f34643d81c9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=382633389 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.382633389 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.3786879982 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 11264160000 ps |
| CPU time | 42.76 seconds |
| Started | Jan 14 12:16:09 PM PST 24 |
| Finished | Jan 14 12:17:29 PM PST 24 |
| Peak memory | 144052 kb |
| Host | smart-0b8f4405-a881-4935-9d8c-b3332bfb72a6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3786879982 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.3786879982 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.928279882 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 5769720000 ps |
| CPU time | 25.47 seconds |
| Started | Jan 14 12:15:56 PM PST 24 |
| Finished | Jan 14 12:16:46 PM PST 24 |
| Peak memory | 144672 kb |
| Host | smart-915e5e5a-50b4-44d1-90d1-58fc81462e7c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=928279882 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.928279882 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.2036320977 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 13461440000 ps |
| CPU time | 51.95 seconds |
| Started | Jan 14 12:16:09 PM PST 24 |
| Finished | Jan 14 12:17:46 PM PST 24 |
| Peak memory | 143680 kb |
| Host | smart-6e594809-43dc-40fc-88b5-253abba09952 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2036320977 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.2036320977 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.136477551 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 10350900000 ps |
| CPU time | 43.51 seconds |
| Started | Jan 14 12:15:55 PM PST 24 |
| Finished | Jan 14 12:17:19 PM PST 24 |
| Peak memory | 144660 kb |
| Host | smart-1dd92cb0-74a2-400b-ae2b-436f706c926a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=136477551 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.136477551 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.2324323806 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 13416800000 ps |
| CPU time | 56.69 seconds |
| Started | Jan 14 12:15:56 PM PST 24 |
| Finished | Jan 14 12:17:44 PM PST 24 |
| Peak memory | 142808 kb |
| Host | smart-c6d1a6ad-2627-46c5-b5d0-4b51420b0988 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2324323806 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.2324323806 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.588284563 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 8144320000 ps |
| CPU time | 35.14 seconds |
| Started | Jan 14 12:15:57 PM PST 24 |
| Finished | Jan 14 12:17:04 PM PST 24 |
| Peak memory | 144044 kb |
| Host | smart-0b55b6b4-e507-4975-8452-5eaa9fa7edf1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=588284563 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.588284563 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.871668718 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 6247740000 ps |
| CPU time | 24.69 seconds |
| Started | Jan 14 12:15:44 PM PST 24 |
| Finished | Jan 14 12:16:32 PM PST 24 |
| Peak memory | 144124 kb |
| Host | smart-697fecd5-43a2-424c-8fab-b13186fcfcec |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=871668718 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.871668718 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.1085041723 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 13075180000 ps |
| CPU time | 50.47 seconds |
| Started | Jan 14 12:16:09 PM PST 24 |
| Finished | Jan 14 12:17:43 PM PST 24 |
| Peak memory | 143656 kb |
| Host | smart-714d9709-acc0-46c4-9cce-fa8f3a217fad |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1085041723 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.1085041723 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.2574059009 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 3176260000 ps |
| CPU time | 14.11 seconds |
| Started | Jan 14 12:15:57 PM PST 24 |
| Finished | Jan 14 12:16:25 PM PST 24 |
| Peak memory | 144508 kb |
| Host | smart-d64c97df-e834-4295-aa94-5c2e1129acf2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2574059009 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.2574059009 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.1509017089 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 15296640000 ps |
| CPU time | 57.98 seconds |
| Started | Jan 14 12:16:09 PM PST 24 |
| Finished | Jan 14 12:17:56 PM PST 24 |
| Peak memory | 143024 kb |
| Host | smart-5debcdbc-0147-4d63-ae50-5a4cd52291ce |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1509017089 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.1509017089 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.2711624455 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 3315140000 ps |
| CPU time | 13.86 seconds |
| Started | Jan 14 12:16:05 PM PST 24 |
| Finished | Jan 14 12:16:32 PM PST 24 |
| Peak memory | 144532 kb |
| Host | smart-58da0b05-d150-4072-8ab8-7d245fd6741a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2711624455 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.2711624455 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.2443411206 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 6208060000 ps |
| CPU time | 24.22 seconds |
| Started | Jan 14 12:16:02 PM PST 24 |
| Finished | Jan 14 12:16:49 PM PST 24 |
| Peak memory | 142312 kb |
| Host | smart-15f4a45d-465f-498d-a263-50a218550fb8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2443411206 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.2443411206 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.43896602 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 5617820000 ps |
| CPU time | 22.32 seconds |
| Started | Jan 14 12:16:05 PM PST 24 |
| Finished | Jan 14 12:16:48 PM PST 24 |
| Peak memory | 144648 kb |
| Host | smart-533b4502-9d01-42aa-9a06-d75b7f8d18d1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=43896602 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.43896602 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.1105523777 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 8653340000 ps |
| CPU time | 36.95 seconds |
| Started | Jan 14 12:16:04 PM PST 24 |
| Finished | Jan 14 12:17:12 PM PST 24 |
| Peak memory | 144416 kb |
| Host | smart-4ebe8b30-57b5-4f1e-a9a3-9b0325cdf903 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1105523777 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.1105523777 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.3473433835 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 4738660000 ps |
| CPU time | 20.34 seconds |
| Started | Jan 14 12:16:03 PM PST 24 |
| Finished | Jan 14 12:16:44 PM PST 24 |
| Peak memory | 144200 kb |
| Host | smart-9810154a-7d3e-4d99-8c49-b0d92c7ce3ce |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3473433835 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.3473433835 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.3488463173 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 13191120000 ps |
| CPU time | 49.76 seconds |
| Started | Jan 14 12:16:06 PM PST 24 |
| Finished | Jan 14 12:17:38 PM PST 24 |
| Peak memory | 144756 kb |
| Host | smart-6129dbc4-9c20-40e9-8a66-31b43abb782f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3488463173 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.3488463173 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.3480054590 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 4720680000 ps |
| CPU time | 19.97 seconds |
| Started | Jan 14 12:16:04 PM PST 24 |
| Finished | Jan 14 12:16:43 PM PST 24 |
| Peak memory | 144656 kb |
| Host | smart-ca750703-f3d4-4ec4-9110-1b658bfaaaca |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3480054590 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.3480054590 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.3263981390 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 13599700000 ps |
| CPU time | 56.23 seconds |
| Started | Jan 14 12:15:57 PM PST 24 |
| Finished | Jan 14 12:17:46 PM PST 24 |
| Peak memory | 144656 kb |
| Host | smart-0ef6f0ee-7017-4084-8322-7c6a04cdf36f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3263981390 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.3263981390 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.4182215583 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 8618000000 ps |
| CPU time | 34.85 seconds |
| Started | Jan 14 12:16:04 PM PST 24 |
| Finished | Jan 14 12:17:11 PM PST 24 |
| Peak memory | 144668 kb |
| Host | smart-1b7d9dad-7764-47a5-a08e-ee04ce2971de |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4182215583 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.4182215583 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.3004125104 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 11948020000 ps |
| CPU time | 47.87 seconds |
| Started | Jan 14 12:16:04 PM PST 24 |
| Finished | Jan 14 12:17:34 PM PST 24 |
| Peak memory | 144656 kb |
| Host | smart-4b51e02f-6f4e-4a7f-8d53-f07186bec642 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3004125104 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.3004125104 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.2479516068 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 6577580000 ps |
| CPU time | 29.09 seconds |
| Started | Jan 14 12:16:02 PM PST 24 |
| Finished | Jan 14 12:16:57 PM PST 24 |
| Peak memory | 144200 kb |
| Host | smart-6dc06bf8-c74a-4727-bf15-edfc05f2350c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2479516068 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.2479516068 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.110419531 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 11268500000 ps |
| CPU time | 45.96 seconds |
| Started | Jan 14 12:16:04 PM PST 24 |
| Finished | Jan 14 12:17:31 PM PST 24 |
| Peak memory | 144656 kb |
| Host | smart-7a06587e-d851-4f2a-8ab0-fef01dd7ae29 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=110419531 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.110419531 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.2626376553 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 10424680000 ps |
| CPU time | 39.98 seconds |
| Started | Jan 14 12:16:06 PM PST 24 |
| Finished | Jan 14 12:17:20 PM PST 24 |
| Peak memory | 144756 kb |
| Host | smart-2cf0f8c8-2fb5-4e26-86e6-71109f538eb4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2626376553 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.2626376553 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.3655928292 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 7870280000 ps |
| CPU time | 29.91 seconds |
| Started | Jan 14 12:16:06 PM PST 24 |
| Finished | Jan 14 12:17:02 PM PST 24 |
| Peak memory | 144696 kb |
| Host | smart-63cccab2-239c-4bcb-9e19-419241b3c830 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3655928292 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.3655928292 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.2061722693 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 11082500000 ps |
| CPU time | 45.05 seconds |
| Started | Jan 14 12:16:05 PM PST 24 |
| Finished | Jan 14 12:17:30 PM PST 24 |
| Peak memory | 144668 kb |
| Host | smart-8c43c3f7-bdf3-496b-99aa-e3ba121bc8a6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2061722693 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.2061722693 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.1364508068 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 6715840000 ps |
| CPU time | 27.18 seconds |
| Started | Jan 14 12:16:04 PM PST 24 |
| Finished | Jan 14 12:16:57 PM PST 24 |
| Peak memory | 144668 kb |
| Host | smart-fdd02d49-5d1f-481e-a951-a6472a8326f0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1364508068 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.1364508068 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.1103498050 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 13312640000 ps |
| CPU time | 52.41 seconds |
| Started | Jan 14 12:16:02 PM PST 24 |
| Finished | Jan 14 12:17:42 PM PST 24 |
| Peak memory | 142664 kb |
| Host | smart-dc484516-f689-4799-8673-4f9bc84a0885 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1103498050 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.1103498050 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.1607718764 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 9889620000 ps |
| CPU time | 43.15 seconds |
| Started | Jan 14 12:16:02 PM PST 24 |
| Finished | Jan 14 12:17:26 PM PST 24 |
| Peak memory | 144200 kb |
| Host | smart-1a9895ef-ea76-4ad1-8a85-0a44ea4d0092 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1607718764 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.1607718764 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.1068383133 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 15342520000 ps |
| CPU time | 63.92 seconds |
| Started | Jan 14 12:15:57 PM PST 24 |
| Finished | Jan 14 12:17:58 PM PST 24 |
| Peak memory | 143884 kb |
| Host | smart-df1aff42-c3ec-45be-9a32-e615a1ecbf4d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1068383133 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.1068383133 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.1449340464 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 14935800000 ps |
| CPU time | 63.05 seconds |
| Started | Jan 14 12:16:01 PM PST 24 |
| Finished | Jan 14 12:18:02 PM PST 24 |
| Peak memory | 144200 kb |
| Host | smart-4afcbfed-0318-4a5b-93ad-10c597b8f3f9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1449340464 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.1449340464 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.2786277 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 12500440000 ps |
| CPU time | 47.93 seconds |
| Started | Jan 14 12:16:06 PM PST 24 |
| Finished | Jan 14 12:17:34 PM PST 24 |
| Peak memory | 144692 kb |
| Host | smart-c1d50e4f-0223-403e-aa15-f4f3e66321d4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2786277 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.2786277 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.405311363 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 12016840000 ps |
| CPU time | 45.75 seconds |
| Started | Jan 14 12:16:06 PM PST 24 |
| Finished | Jan 14 12:17:31 PM PST 24 |
| Peak memory | 144756 kb |
| Host | smart-30d848d1-0cb4-4ad1-a52a-dd2593a15a02 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=405311363 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.405311363 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.1889627936 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 4028760000 ps |
| CPU time | 15.7 seconds |
| Started | Jan 14 12:16:06 PM PST 24 |
| Finished | Jan 14 12:16:35 PM PST 24 |
| Peak memory | 144620 kb |
| Host | smart-c325e48f-814f-43ce-8789-034c553463fd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1889627936 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.1889627936 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.3925372160 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 3369700000 ps |
| CPU time | 13.74 seconds |
| Started | Jan 14 12:16:05 PM PST 24 |
| Finished | Jan 14 12:16:32 PM PST 24 |
| Peak memory | 144532 kb |
| Host | smart-9c3133a1-a1b7-4605-b41d-8260099af5b4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3925372160 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.3925372160 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.395120280 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 12320020000 ps |
| CPU time | 46.75 seconds |
| Started | Jan 14 12:16:06 PM PST 24 |
| Finished | Jan 14 12:17:33 PM PST 24 |
| Peak memory | 144756 kb |
| Host | smart-d42656f7-35b3-40e6-b827-7132a8a5c05c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=395120280 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.395120280 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.195020073 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 10185980000 ps |
| CPU time | 43.5 seconds |
| Started | Jan 14 12:16:01 PM PST 24 |
| Finished | Jan 14 12:17:26 PM PST 24 |
| Peak memory | 144200 kb |
| Host | smart-eed30ac6-02c7-4717-8db4-0beb100390b9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=195020073 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.195020073 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.166980292 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 12293980000 ps |
| CPU time | 53.91 seconds |
| Started | Jan 14 12:16:01 PM PST 24 |
| Finished | Jan 14 12:17:45 PM PST 24 |
| Peak memory | 144200 kb |
| Host | smart-bf010fea-07fb-4415-8e30-6a0979c6c01d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=166980292 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.166980292 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.990747867 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 10137620000 ps |
| CPU time | 42.63 seconds |
| Started | Jan 14 12:16:04 PM PST 24 |
| Finished | Jan 14 12:17:24 PM PST 24 |
| Peak memory | 144364 kb |
| Host | smart-8d309e72-a872-4be6-8659-d047ddf484da |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=990747867 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.990747867 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.3480032709 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 14718800000 ps |
| CPU time | 61.19 seconds |
| Started | Jan 14 12:16:02 PM PST 24 |
| Finished | Jan 14 12:18:00 PM PST 24 |
| Peak memory | 144200 kb |
| Host | smart-dd2f8658-901e-4d5e-8670-b6bbc68c80f8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3480032709 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.3480032709 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.927218511 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 8725880000 ps |
| CPU time | 34.41 seconds |
| Started | Jan 14 12:16:09 PM PST 24 |
| Finished | Jan 14 12:17:13 PM PST 24 |
| Peak memory | 144044 kb |
| Host | smart-4d01aa4c-c94a-478a-bd05-a8e0d0c742b7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=927218511 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.927218511 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.962062716 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 8738280000 ps |
| CPU time | 34.62 seconds |
| Started | Jan 14 12:16:09 PM PST 24 |
| Finished | Jan 14 12:17:13 PM PST 24 |
| Peak memory | 142712 kb |
| Host | smart-491db767-c040-4763-8ea9-79b9f52b7b22 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=962062716 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.962062716 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.3060809346 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 8528100000 ps |
| CPU time | 37.34 seconds |
| Started | Jan 14 12:15:56 PM PST 24 |
| Finished | Jan 14 12:17:08 PM PST 24 |
| Peak memory | 142876 kb |
| Host | smart-74180d33-5c90-4b73-8e7e-7eeac79b7b31 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3060809346 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.3060809346 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.4110115585 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 8397280000 ps |
| CPU time | 36.1 seconds |
| Started | Jan 14 12:15:56 PM PST 24 |
| Finished | Jan 14 12:17:06 PM PST 24 |
| Peak memory | 144660 kb |
| Host | smart-47256708-3414-4965-a0d4-7ad773a30d14 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4110115585 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.4110115585 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.54018320 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 13442220000 ps |
| CPU time | 41.22 seconds |
| Started | Jan 14 12:16:01 PM PST 24 |
| Finished | Jan 14 12:17:15 PM PST 24 |
| Peak memory | 143492 kb |
| Host | smart-fa572881-3f5d-4cba-93e2-5c8597894e13 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=54018320 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.54018320 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |