| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/11.prim_present_test.818839676 | ||
| Name |
|---|
| /workspace/coverage/default/0.prim_present_test.2659956940 |
| /workspace/coverage/default/1.prim_present_test.541618591 |
| /workspace/coverage/default/10.prim_present_test.1470990571 |
| /workspace/coverage/default/12.prim_present_test.3850736986 |
| /workspace/coverage/default/13.prim_present_test.626752608 |
| /workspace/coverage/default/14.prim_present_test.383019235 |
| /workspace/coverage/default/15.prim_present_test.1529360397 |
| /workspace/coverage/default/16.prim_present_test.540248947 |
| /workspace/coverage/default/17.prim_present_test.1071174785 |
| /workspace/coverage/default/18.prim_present_test.2708282457 |
| /workspace/coverage/default/19.prim_present_test.79689094 |
| /workspace/coverage/default/2.prim_present_test.730522635 |
| /workspace/coverage/default/20.prim_present_test.2777627338 |
| /workspace/coverage/default/21.prim_present_test.784222954 |
| /workspace/coverage/default/22.prim_present_test.1711373502 |
| /workspace/coverage/default/23.prim_present_test.751575570 |
| /workspace/coverage/default/24.prim_present_test.951228274 |
| /workspace/coverage/default/25.prim_present_test.1981527664 |
| /workspace/coverage/default/26.prim_present_test.3360321233 |
| /workspace/coverage/default/27.prim_present_test.912646126 |
| /workspace/coverage/default/28.prim_present_test.3453215725 |
| /workspace/coverage/default/29.prim_present_test.2459037850 |
| /workspace/coverage/default/3.prim_present_test.46639386 |
| /workspace/coverage/default/30.prim_present_test.2824089888 |
| /workspace/coverage/default/31.prim_present_test.402566742 |
| /workspace/coverage/default/32.prim_present_test.3866991150 |
| /workspace/coverage/default/33.prim_present_test.694242942 |
| /workspace/coverage/default/34.prim_present_test.3465844382 |
| /workspace/coverage/default/35.prim_present_test.1122890988 |
| /workspace/coverage/default/36.prim_present_test.4200712582 |
| /workspace/coverage/default/37.prim_present_test.2202992753 |
| /workspace/coverage/default/38.prim_present_test.2396465294 |
| /workspace/coverage/default/39.prim_present_test.2734464877 |
| /workspace/coverage/default/4.prim_present_test.543571139 |
| /workspace/coverage/default/40.prim_present_test.1377748244 |
| /workspace/coverage/default/41.prim_present_test.3616292809 |
| /workspace/coverage/default/42.prim_present_test.2785026669 |
| /workspace/coverage/default/43.prim_present_test.2940349454 |
| /workspace/coverage/default/44.prim_present_test.1296877743 |
| /workspace/coverage/default/45.prim_present_test.2296014645 |
| /workspace/coverage/default/46.prim_present_test.4132814084 |
| /workspace/coverage/default/47.prim_present_test.223194698 |
| /workspace/coverage/default/48.prim_present_test.44565214 |
| /workspace/coverage/default/49.prim_present_test.1948225533 |
| /workspace/coverage/default/5.prim_present_test.3683524706 |
| /workspace/coverage/default/6.prim_present_test.2227779577 |
| /workspace/coverage/default/7.prim_present_test.3892380501 |
| /workspace/coverage/default/8.prim_present_test.3706592976 |
| /workspace/coverage/default/9.prim_present_test.1032235515 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/25.prim_present_test.1981527664 | Jan 21 12:49:25 PM PST 24 | Jan 21 12:50:08 PM PST 24 | 7181460000 ps | ||
| T2 | /workspace/coverage/default/27.prim_present_test.912646126 | Jan 21 01:32:36 PM PST 24 | Jan 21 01:33:11 PM PST 24 | 4720060000 ps | ||
| T3 | /workspace/coverage/default/46.prim_present_test.4132814084 | Jan 21 12:18:39 PM PST 24 | Jan 21 12:19:10 PM PST 24 | 3971720000 ps | ||
| T4 | /workspace/coverage/default/33.prim_present_test.694242942 | Jan 21 12:18:39 PM PST 24 | Jan 21 12:20:16 PM PST 24 | 13432300000 ps | ||
| T5 | /workspace/coverage/default/11.prim_present_test.818839676 | Jan 21 12:57:29 PM PST 24 | Jan 21 12:57:54 PM PST 24 | 3956840000 ps | ||
| T6 | /workspace/coverage/default/14.prim_present_test.383019235 | Jan 21 01:54:27 PM PST 24 | Jan 21 01:55:38 PM PST 24 | 12092480000 ps | ||
| T7 | /workspace/coverage/default/35.prim_present_test.1122890988 | Jan 21 12:44:30 PM PST 24 | Jan 21 12:45:10 PM PST 24 | 6585640000 ps | ||
| T8 | /workspace/coverage/default/36.prim_present_test.4200712582 | Jan 21 12:18:39 PM PST 24 | Jan 21 12:20:21 PM PST 24 | 14276740000 ps | ||
| T9 | /workspace/coverage/default/31.prim_present_test.402566742 | Jan 21 12:18:39 PM PST 24 | Jan 21 12:19:32 PM PST 24 | 6846660000 ps | ||
| T10 | /workspace/coverage/default/41.prim_present_test.3616292809 | Jan 21 12:59:25 PM PST 24 | Jan 21 01:00:24 PM PST 24 | 9760660000 ps | ||
| T11 | /workspace/coverage/default/6.prim_present_test.2227779577 | Jan 21 12:18:38 PM PST 24 | Jan 21 12:19:22 PM PST 24 | 5985480000 ps | ||
| T12 | /workspace/coverage/default/22.prim_present_test.1711373502 | Jan 21 12:55:43 PM PST 24 | Jan 21 12:56:34 PM PST 24 | 8503300000 ps | ||
| T13 | /workspace/coverage/default/24.prim_present_test.951228274 | Jan 21 12:35:04 PM PST 24 | Jan 21 12:36:28 PM PST 24 | 14021920000 ps | ||
| T14 | /workspace/coverage/default/10.prim_present_test.1470990571 | Jan 21 12:28:50 PM PST 24 | Jan 21 12:29:14 PM PST 24 | 4133540000 ps | ||
| T15 | /workspace/coverage/default/19.prim_present_test.79689094 | Jan 21 12:24:37 PM PST 24 | Jan 21 12:25:59 PM PST 24 | 15367320000 ps | ||
| T16 | /workspace/coverage/default/29.prim_present_test.2459037850 | Jan 21 12:49:05 PM PST 24 | Jan 21 12:50:06 PM PST 24 | 10673300000 ps | ||
| T17 | /workspace/coverage/default/47.prim_present_test.223194698 | Jan 21 12:49:16 PM PST 24 | Jan 21 12:49:42 PM PST 24 | 4747960000 ps | ||
| T18 | /workspace/coverage/default/34.prim_present_test.3465844382 | Jan 21 12:41:34 PM PST 24 | Jan 21 12:43:08 PM PST 24 | 14867600000 ps | ||
| T19 | /workspace/coverage/default/13.prim_present_test.626752608 | Jan 21 12:18:39 PM PST 24 | Jan 21 12:19:35 PM PST 24 | 7297400000 ps | ||
| T20 | /workspace/coverage/default/37.prim_present_test.2202992753 | Jan 21 01:30:59 PM PST 24 | Jan 21 01:32:05 PM PST 24 | 11546880000 ps | ||
| T21 | /workspace/coverage/default/4.prim_present_test.543571139 | Jan 21 01:19:58 PM PST 24 | Jan 21 01:20:34 PM PST 24 | 5790180000 ps | ||
| T22 | /workspace/coverage/default/2.prim_present_test.730522635 | Jan 21 12:18:57 PM PST 24 | Jan 21 12:19:49 PM PST 24 | 8056280000 ps | ||
| T23 | /workspace/coverage/default/21.prim_present_test.784222954 | Jan 21 12:33:47 PM PST 24 | Jan 21 12:34:56 PM PST 24 | 13076420000 ps | ||
| T24 | /workspace/coverage/default/23.prim_present_test.751575570 | Jan 21 12:19:04 PM PST 24 | Jan 21 12:20:16 PM PST 24 | 10177300000 ps | ||
| T25 | /workspace/coverage/default/49.prim_present_test.1948225533 | Jan 21 12:38:20 PM PST 24 | Jan 21 12:39:29 PM PST 24 | 10687560000 ps | ||
| T26 | /workspace/coverage/default/1.prim_present_test.541618591 | Jan 21 12:18:38 PM PST 24 | Jan 21 12:19:04 PM PST 24 | 3947540000 ps | ||
| T27 | /workspace/coverage/default/39.prim_present_test.2734464877 | Jan 21 01:01:15 PM PST 24 | Jan 21 01:01:59 PM PST 24 | 8755020000 ps | ||
| T28 | /workspace/coverage/default/3.prim_present_test.46639386 | Jan 21 12:20:15 PM PST 24 | Jan 21 12:21:51 PM PST 24 | 15142260000 ps | ||
| T29 | /workspace/coverage/default/7.prim_present_test.3892380501 | Jan 21 12:18:57 PM PST 24 | Jan 21 12:19:25 PM PST 24 | 4168260000 ps | ||
| T30 | /workspace/coverage/default/44.prim_present_test.1296877743 | Jan 21 01:57:19 PM PST 24 | Jan 21 01:58:41 PM PST 24 | 13455860000 ps | ||
| T31 | /workspace/coverage/default/30.prim_present_test.2824089888 | Jan 21 12:25:00 PM PST 24 | Jan 21 12:25:56 PM PST 24 | 9846840000 ps | ||
| T32 | /workspace/coverage/default/42.prim_present_test.2785026669 | Jan 21 12:37:40 PM PST 24 | Jan 21 12:39:03 PM PST 24 | 14067800000 ps | ||
| T33 | /workspace/coverage/default/12.prim_present_test.3850736986 | Jan 21 12:18:55 PM PST 24 | Jan 21 12:20:29 PM PST 24 | 15173880000 ps | ||
| T34 | /workspace/coverage/default/17.prim_present_test.1071174785 | Jan 21 12:53:44 PM PST 24 | Jan 21 12:54:33 PM PST 24 | 7495800000 ps | ||
| T35 | /workspace/coverage/default/43.prim_present_test.2940349454 | Jan 21 12:41:38 PM PST 24 | Jan 21 12:42:10 PM PST 24 | 5461580000 ps | ||
| T36 | /workspace/coverage/default/16.prim_present_test.540248947 | Jan 21 12:18:39 PM PST 24 | Jan 21 12:20:30 PM PST 24 | 15261920000 ps | ||
| T37 | /workspace/coverage/default/32.prim_present_test.3866991150 | Jan 21 12:36:18 PM PST 24 | Jan 21 12:36:55 PM PST 24 | 5643240000 ps | ||
| T38 | /workspace/coverage/default/15.prim_present_test.1529360397 | Jan 21 12:54:51 PM PST 24 | Jan 21 12:55:17 PM PST 24 | 4176320000 ps | ||
| T39 | /workspace/coverage/default/28.prim_present_test.3453215725 | Jan 21 12:53:59 PM PST 24 | Jan 21 12:55:10 PM PST 24 | 12709380000 ps | ||
| T40 | /workspace/coverage/default/26.prim_present_test.3360321233 | Jan 21 01:25:56 PM PST 24 | Jan 21 01:27:09 PM PST 24 | 13220260000 ps | ||
| T41 | /workspace/coverage/default/48.prim_present_test.44565214 | Jan 21 12:37:56 PM PST 24 | Jan 21 12:38:46 PM PST 24 | 8055040000 ps | ||
| T42 | /workspace/coverage/default/5.prim_present_test.3683524706 | Jan 21 12:46:53 PM PST 24 | Jan 21 12:48:16 PM PST 24 | 13068980000 ps | ||
| T43 | /workspace/coverage/default/45.prim_present_test.2296014645 | Jan 21 12:46:38 PM PST 24 | Jan 21 12:47:33 PM PST 24 | 8849880000 ps | ||
| T44 | /workspace/coverage/default/9.prim_present_test.1032235515 | Jan 21 01:08:33 PM PST 24 | Jan 21 01:09:40 PM PST 24 | 12089380000 ps | ||
| T45 | /workspace/coverage/default/38.prim_present_test.2396465294 | Jan 21 12:53:29 PM PST 24 | Jan 21 12:54:34 PM PST 24 | 11194720000 ps | ||
| T46 | /workspace/coverage/default/8.prim_present_test.3706592976 | Jan 21 01:04:17 PM PST 24 | Jan 21 01:04:59 PM PST 24 | 6461020000 ps | ||
| T47 | /workspace/coverage/default/18.prim_present_test.2708282457 | Jan 21 01:05:37 PM PST 24 | Jan 21 01:07:02 PM PST 24 | 14756000000 ps | ||
| T48 | /workspace/coverage/default/20.prim_present_test.2777627338 | Jan 21 12:55:52 PM PST 24 | Jan 21 12:57:13 PM PST 24 | 13274820000 ps | ||
| T49 | /workspace/coverage/default/0.prim_present_test.2659956940 | Jan 21 12:40:29 PM PST 24 | Jan 21 12:41:55 PM PST 24 | 14251320000 ps | ||
| T50 | /workspace/coverage/default/40.prim_present_test.1377748244 | Jan 21 01:12:36 PM PST 24 | Jan 21 01:13:37 PM PST 24 | 10517680000 ps |
| Test location | /workspace/coverage/default/11.prim_present_test.818839676 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 3956840000 ps |
| CPU time | 12.83 seconds |
| Started | Jan 21 12:57:29 PM PST 24 |
| Finished | Jan 21 12:57:54 PM PST 24 |
| Peak memory | 144812 kb |
| Host | smart-8af60994-0f74-4559-beea-e089d57ab0f4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=818839676 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.818839676 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/0.prim_present_test.2659956940 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 14251320000 ps |
| CPU time | 46.08 seconds |
| Started | Jan 21 12:40:29 PM PST 24 |
| Finished | Jan 21 12:41:55 PM PST 24 |
| Peak memory | 144992 kb |
| Host | smart-ea094d6e-fcce-4060-b292-c02e25141653 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2659956940 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.2659956940 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/1.prim_present_test.541618591 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 3947540000 ps |
| CPU time | 13.36 seconds |
| Started | Jan 21 12:18:38 PM PST 24 |
| Finished | Jan 21 12:19:04 PM PST 24 |
| Peak memory | 145060 kb |
| Host | smart-00783ed5-4e0a-413c-b800-e54a91d7e239 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=541618591 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.541618591 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/10.prim_present_test.1470990571 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 4133540000 ps |
| CPU time | 12.59 seconds |
| Started | Jan 21 12:28:50 PM PST 24 |
| Finished | Jan 21 12:29:14 PM PST 24 |
| Peak memory | 144796 kb |
| Host | smart-04b7b24e-2877-467a-a01b-68d926e901bb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1470990571 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.1470990571 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.3850736986 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 15173880000 ps |
| CPU time | 50.84 seconds |
| Started | Jan 21 12:18:55 PM PST 24 |
| Finished | Jan 21 12:20:29 PM PST 24 |
| Peak memory | 145212 kb |
| Host | smart-f0911026-b242-4a83-a937-063211c04266 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3850736986 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.3850736986 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.626752608 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 7297400000 ps |
| CPU time | 29.52 seconds |
| Started | Jan 21 12:18:39 PM PST 24 |
| Finished | Jan 21 12:19:35 PM PST 24 |
| Peak memory | 144192 kb |
| Host | smart-d1e5f40c-bf44-4541-a34d-dfe7a869b533 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=626752608 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.626752608 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.383019235 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 12092480000 ps |
| CPU time | 37.9 seconds |
| Started | Jan 21 01:54:27 PM PST 24 |
| Finished | Jan 21 01:55:38 PM PST 24 |
| Peak memory | 144884 kb |
| Host | smart-10d2ad0b-4bdd-413e-8022-5fad6ea34de4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=383019235 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.383019235 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.1529360397 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 4176320000 ps |
| CPU time | 14 seconds |
| Started | Jan 21 12:54:51 PM PST 24 |
| Finished | Jan 21 12:55:17 PM PST 24 |
| Peak memory | 144688 kb |
| Host | smart-1ae7e943-6cbd-43e5-b8d8-21abb4284e0c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1529360397 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.1529360397 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.540248947 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 15261920000 ps |
| CPU time | 58.4 seconds |
| Started | Jan 21 12:18:39 PM PST 24 |
| Finished | Jan 21 12:20:30 PM PST 24 |
| Peak memory | 144920 kb |
| Host | smart-3c82132e-f1ee-49ce-995e-d6746da0c73a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=540248947 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.540248947 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.1071174785 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 7495800000 ps |
| CPU time | 24.32 seconds |
| Started | Jan 21 12:53:44 PM PST 24 |
| Finished | Jan 21 12:54:33 PM PST 24 |
| Peak memory | 145040 kb |
| Host | smart-c8627acf-f36b-4cdc-8e6c-d88d8b180de9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1071174785 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.1071174785 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.2708282457 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 14756000000 ps |
| CPU time | 45.29 seconds |
| Started | Jan 21 01:05:37 PM PST 24 |
| Finished | Jan 21 01:07:02 PM PST 24 |
| Peak memory | 144932 kb |
| Host | smart-e547e002-9d43-4710-b1bb-b98938d53fae |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2708282457 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.2708282457 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.79689094 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 15367320000 ps |
| CPU time | 44.38 seconds |
| Started | Jan 21 12:24:37 PM PST 24 |
| Finished | Jan 21 12:25:59 PM PST 24 |
| Peak memory | 144940 kb |
| Host | smart-f17d41bd-926f-45f6-a19b-3fb67e61aa95 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=79689094 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.79689094 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.730522635 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 8056280000 ps |
| CPU time | 28.01 seconds |
| Started | Jan 21 12:18:57 PM PST 24 |
| Finished | Jan 21 12:19:49 PM PST 24 |
| Peak memory | 145204 kb |
| Host | smart-b979ca42-322e-43a5-8e64-dbe45ed484f7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=730522635 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.730522635 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.2777627338 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 13274820000 ps |
| CPU time | 43.16 seconds |
| Started | Jan 21 12:55:52 PM PST 24 |
| Finished | Jan 21 12:57:13 PM PST 24 |
| Peak memory | 144996 kb |
| Host | smart-03b2cba1-b5c5-455a-ab59-4c17a30d6d03 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2777627338 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.2777627338 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.784222954 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 13076420000 ps |
| CPU time | 37.3 seconds |
| Started | Jan 21 12:33:47 PM PST 24 |
| Finished | Jan 21 12:34:56 PM PST 24 |
| Peak memory | 144952 kb |
| Host | smart-572c7b6a-1a82-495a-af25-95017c7d5f39 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=784222954 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.784222954 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.1711373502 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 8503300000 ps |
| CPU time | 27.01 seconds |
| Started | Jan 21 12:55:43 PM PST 24 |
| Finished | Jan 21 12:56:34 PM PST 24 |
| Peak memory | 144872 kb |
| Host | smart-2c8611d4-3d2a-4a20-9517-a39bedadafbd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1711373502 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.1711373502 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.751575570 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 10177300000 ps |
| CPU time | 37.99 seconds |
| Started | Jan 21 12:19:04 PM PST 24 |
| Finished | Jan 21 12:20:16 PM PST 24 |
| Peak memory | 144960 kb |
| Host | smart-df28316b-3a61-41a5-a359-faf26277d642 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=751575570 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.751575570 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.951228274 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 14021920000 ps |
| CPU time | 44.78 seconds |
| Started | Jan 21 12:35:04 PM PST 24 |
| Finished | Jan 21 12:36:28 PM PST 24 |
| Peak memory | 144992 kb |
| Host | smart-7ca764e4-d9a5-4aa0-8a41-5df4357fd90a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=951228274 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.951228274 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.1981527664 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 7181460000 ps |
| CPU time | 23.38 seconds |
| Started | Jan 21 12:49:25 PM PST 24 |
| Finished | Jan 21 12:50:08 PM PST 24 |
| Peak memory | 144824 kb |
| Host | smart-48e25134-757b-4fb5-92f4-27663a9bd3c9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1981527664 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.1981527664 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.3360321233 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 13220260000 ps |
| CPU time | 39.32 seconds |
| Started | Jan 21 01:25:56 PM PST 24 |
| Finished | Jan 21 01:27:09 PM PST 24 |
| Peak memory | 145064 kb |
| Host | smart-dfa7e501-ce6b-434c-b002-ecbdbc2c6de0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3360321233 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.3360321233 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.912646126 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 4720060000 ps |
| CPU time | 16.04 seconds |
| Started | Jan 21 01:32:36 PM PST 24 |
| Finished | Jan 21 01:33:11 PM PST 24 |
| Peak memory | 145024 kb |
| Host | smart-5e6862f3-14d4-4834-95aa-010ee958aa50 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=912646126 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.912646126 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.3453215725 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 12709380000 ps |
| CPU time | 38.04 seconds |
| Started | Jan 21 12:53:59 PM PST 24 |
| Finished | Jan 21 12:55:10 PM PST 24 |
| Peak memory | 144948 kb |
| Host | smart-28386bf9-7123-40eb-8781-761e505c76ec |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3453215725 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.3453215725 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.2459037850 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 10673300000 ps |
| CPU time | 32.26 seconds |
| Started | Jan 21 12:49:05 PM PST 24 |
| Finished | Jan 21 12:50:06 PM PST 24 |
| Peak memory | 144952 kb |
| Host | smart-0a98a92f-8ab3-4be0-9d88-62238b0b348b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2459037850 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.2459037850 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.46639386 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 15142260000 ps |
| CPU time | 51.85 seconds |
| Started | Jan 21 12:20:15 PM PST 24 |
| Finished | Jan 21 12:21:51 PM PST 24 |
| Peak memory | 145188 kb |
| Host | smart-35b55d43-4579-45e2-85c5-19499b82a8b4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=46639386 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.46639386 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.2824089888 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 9846840000 ps |
| CPU time | 29.73 seconds |
| Started | Jan 21 12:25:00 PM PST 24 |
| Finished | Jan 21 12:25:56 PM PST 24 |
| Peak memory | 144836 kb |
| Host | smart-808d30cf-aa2b-4ff4-8953-3236246a6c6e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2824089888 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.2824089888 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.402566742 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 6846660000 ps |
| CPU time | 27.51 seconds |
| Started | Jan 21 12:18:39 PM PST 24 |
| Finished | Jan 21 12:19:32 PM PST 24 |
| Peak memory | 144532 kb |
| Host | smart-fdbf8f8c-aa97-4deb-bfa1-280f975a2813 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=402566742 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.402566742 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.3866991150 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 5643240000 ps |
| CPU time | 18.69 seconds |
| Started | Jan 21 12:36:18 PM PST 24 |
| Finished | Jan 21 12:36:55 PM PST 24 |
| Peak memory | 144860 kb |
| Host | smart-94ceed68-4280-43c4-b44a-3174a442a7cf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3866991150 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.3866991150 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.694242942 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 13432300000 ps |
| CPU time | 51.53 seconds |
| Started | Jan 21 12:18:39 PM PST 24 |
| Finished | Jan 21 12:20:16 PM PST 24 |
| Peak memory | 144916 kb |
| Host | smart-4c56003f-e6c0-4210-9f69-4eeeeb444a78 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=694242942 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.694242942 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.3465844382 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 14867600000 ps |
| CPU time | 50.52 seconds |
| Started | Jan 21 12:41:34 PM PST 24 |
| Finished | Jan 21 12:43:08 PM PST 24 |
| Peak memory | 145040 kb |
| Host | smart-3feef767-6a89-4f54-8997-7d730dbb9481 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3465844382 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.3465844382 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.1122890988 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 6585640000 ps |
| CPU time | 21.36 seconds |
| Started | Jan 21 12:44:30 PM PST 24 |
| Finished | Jan 21 12:45:10 PM PST 24 |
| Peak memory | 144968 kb |
| Host | smart-ad93829f-dd95-43ec-8ff0-ea3c6b867927 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1122890988 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.1122890988 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.4200712582 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 14276740000 ps |
| CPU time | 54.3 seconds |
| Started | Jan 21 12:18:39 PM PST 24 |
| Finished | Jan 21 12:20:21 PM PST 24 |
| Peak memory | 144320 kb |
| Host | smart-0159453f-685f-491d-b1e6-76edf79513ca |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4200712582 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.4200712582 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.2202992753 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 11546880000 ps |
| CPU time | 35.7 seconds |
| Started | Jan 21 01:30:59 PM PST 24 |
| Finished | Jan 21 01:32:05 PM PST 24 |
| Peak memory | 145060 kb |
| Host | smart-84048211-9291-4fc6-b37f-2bd5bf358a4d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2202992753 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.2202992753 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.2396465294 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 11194720000 ps |
| CPU time | 34.04 seconds |
| Started | Jan 21 12:53:29 PM PST 24 |
| Finished | Jan 21 12:54:34 PM PST 24 |
| Peak memory | 144944 kb |
| Host | smart-fbfb05e2-6c27-4d64-a19b-e81fcaf10565 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2396465294 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.2396465294 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.2734464877 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 8755020000 ps |
| CPU time | 23.63 seconds |
| Started | Jan 21 01:01:15 PM PST 24 |
| Finished | Jan 21 01:01:59 PM PST 24 |
| Peak memory | 144956 kb |
| Host | smart-a59f72e0-4886-4149-a9ec-2de58f3cbd60 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2734464877 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.2734464877 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.543571139 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 5790180000 ps |
| CPU time | 18.8 seconds |
| Started | Jan 21 01:19:58 PM PST 24 |
| Finished | Jan 21 01:20:34 PM PST 24 |
| Peak memory | 145204 kb |
| Host | smart-3d149c9c-b805-44f8-ba2d-6cc41c87ba1b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=543571139 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.543571139 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.1377748244 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 10517680000 ps |
| CPU time | 33.13 seconds |
| Started | Jan 21 01:12:36 PM PST 24 |
| Finished | Jan 21 01:13:37 PM PST 24 |
| Peak memory | 144976 kb |
| Host | smart-2f205823-8dbf-485a-871c-8c28a3de181f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1377748244 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.1377748244 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.3616292809 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 9760660000 ps |
| CPU time | 30.03 seconds |
| Started | Jan 21 12:59:25 PM PST 24 |
| Finished | Jan 21 01:00:24 PM PST 24 |
| Peak memory | 144904 kb |
| Host | smart-115f481a-6569-4b79-a43a-9de8d2a77a2d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3616292809 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.3616292809 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.2785026669 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 14067800000 ps |
| CPU time | 44.51 seconds |
| Started | Jan 21 12:37:40 PM PST 24 |
| Finished | Jan 21 12:39:03 PM PST 24 |
| Peak memory | 144956 kb |
| Host | smart-68b9ae31-e5c0-4151-91a0-574ebf51cc1f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2785026669 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.2785026669 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.2940349454 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 5461580000 ps |
| CPU time | 17.3 seconds |
| Started | Jan 21 12:41:38 PM PST 24 |
| Finished | Jan 21 12:42:10 PM PST 24 |
| Peak memory | 144928 kb |
| Host | smart-77133d18-5225-40d9-90ba-88fadcfac393 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2940349454 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.2940349454 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.1296877743 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 13455860000 ps |
| CPU time | 43.83 seconds |
| Started | Jan 21 01:57:19 PM PST 24 |
| Finished | Jan 21 01:58:41 PM PST 24 |
| Peak memory | 145016 kb |
| Host | smart-4a2a5e60-5517-48d4-b6b1-ae9d10e2af07 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1296877743 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.1296877743 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.2296014645 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 8849880000 ps |
| CPU time | 29.42 seconds |
| Started | Jan 21 12:46:38 PM PST 24 |
| Finished | Jan 21 12:47:33 PM PST 24 |
| Peak memory | 145012 kb |
| Host | smart-5843c017-0772-4982-b7e8-0d3833f6f4cb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2296014645 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.2296014645 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.4132814084 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 3971720000 ps |
| CPU time | 15.5 seconds |
| Started | Jan 21 12:18:39 PM PST 24 |
| Finished | Jan 21 12:19:10 PM PST 24 |
| Peak memory | 144772 kb |
| Host | smart-70b6bffc-9d61-4c66-83d1-0c3b3ff63bf5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4132814084 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.4132814084 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.223194698 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 4747960000 ps |
| CPU time | 13.83 seconds |
| Started | Jan 21 12:49:16 PM PST 24 |
| Finished | Jan 21 12:49:42 PM PST 24 |
| Peak memory | 144936 kb |
| Host | smart-d195fe0b-0765-483c-b239-385076ec1883 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=223194698 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.223194698 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.44565214 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 8055040000 ps |
| CPU time | 26.51 seconds |
| Started | Jan 21 12:37:56 PM PST 24 |
| Finished | Jan 21 12:38:46 PM PST 24 |
| Peak memory | 144936 kb |
| Host | smart-3a39b760-5cfc-4dc2-9e02-fd0922725244 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=44565214 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.44565214 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.1948225533 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 10687560000 ps |
| CPU time | 36.28 seconds |
| Started | Jan 21 12:38:20 PM PST 24 |
| Finished | Jan 21 12:39:29 PM PST 24 |
| Peak memory | 144928 kb |
| Host | smart-3328ad2f-1866-4261-a84c-7184ce2279e3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1948225533 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.1948225533 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.3683524706 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 13068980000 ps |
| CPU time | 43.74 seconds |
| Started | Jan 21 12:46:53 PM PST 24 |
| Finished | Jan 21 12:48:16 PM PST 24 |
| Peak memory | 144948 kb |
| Host | smart-5741dc9d-a095-4349-977e-f7768c7586ca |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3683524706 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.3683524706 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.2227779577 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 5985480000 ps |
| CPU time | 23.45 seconds |
| Started | Jan 21 12:18:38 PM PST 24 |
| Finished | Jan 21 12:19:22 PM PST 24 |
| Peak memory | 144916 kb |
| Host | smart-5e778553-8fb5-423e-b93b-b669f49e491a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2227779577 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.2227779577 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.3892380501 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 4168260000 ps |
| CPU time | 15.06 seconds |
| Started | Jan 21 12:18:57 PM PST 24 |
| Finished | Jan 21 12:19:25 PM PST 24 |
| Peak memory | 145068 kb |
| Host | smart-946d0660-6de8-4327-9be6-d01b10be9b90 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3892380501 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.3892380501 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.3706592976 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 6461020000 ps |
| CPU time | 22.2 seconds |
| Started | Jan 21 01:04:17 PM PST 24 |
| Finished | Jan 21 01:04:59 PM PST 24 |
| Peak memory | 144932 kb |
| Host | smart-28fca771-6655-4cb2-a8bd-87f285b5e0fa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3706592976 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.3706592976 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.1032235515 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 12089380000 ps |
| CPU time | 36.02 seconds |
| Started | Jan 21 01:08:33 PM PST 24 |
| Finished | Jan 21 01:09:40 PM PST 24 |
| Peak memory | 144916 kb |
| Host | smart-651b0dde-a77b-4752-9074-ad4f0023705a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1032235515 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.1032235515 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |