| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/10.prim_present_test.426089781 | ||
| Name |
|---|
| /workspace/coverage/default/0.prim_present_test.1606542811 |
| /workspace/coverage/default/1.prim_present_test.4056845304 |
| /workspace/coverage/default/11.prim_present_test.2301568748 |
| /workspace/coverage/default/12.prim_present_test.2647280256 |
| /workspace/coverage/default/13.prim_present_test.2827397289 |
| /workspace/coverage/default/14.prim_present_test.2998211263 |
| /workspace/coverage/default/15.prim_present_test.3622799859 |
| /workspace/coverage/default/16.prim_present_test.867204892 |
| /workspace/coverage/default/17.prim_present_test.3883828180 |
| /workspace/coverage/default/18.prim_present_test.4110603233 |
| /workspace/coverage/default/19.prim_present_test.3101311954 |
| /workspace/coverage/default/2.prim_present_test.966943514 |
| /workspace/coverage/default/20.prim_present_test.1809636777 |
| /workspace/coverage/default/21.prim_present_test.1108996762 |
| /workspace/coverage/default/22.prim_present_test.693627437 |
| /workspace/coverage/default/23.prim_present_test.1237837738 |
| /workspace/coverage/default/24.prim_present_test.192601617 |
| /workspace/coverage/default/25.prim_present_test.207153305 |
| /workspace/coverage/default/26.prim_present_test.4236957400 |
| /workspace/coverage/default/27.prim_present_test.1995017351 |
| /workspace/coverage/default/28.prim_present_test.2927487555 |
| /workspace/coverage/default/29.prim_present_test.3982921550 |
| /workspace/coverage/default/3.prim_present_test.3619004231 |
| /workspace/coverage/default/30.prim_present_test.3397657216 |
| /workspace/coverage/default/31.prim_present_test.921105966 |
| /workspace/coverage/default/32.prim_present_test.3495275641 |
| /workspace/coverage/default/33.prim_present_test.3188248330 |
| /workspace/coverage/default/34.prim_present_test.2391757486 |
| /workspace/coverage/default/35.prim_present_test.3341080834 |
| /workspace/coverage/default/36.prim_present_test.2304552645 |
| /workspace/coverage/default/37.prim_present_test.717193443 |
| /workspace/coverage/default/38.prim_present_test.2848564922 |
| /workspace/coverage/default/39.prim_present_test.2381095555 |
| /workspace/coverage/default/4.prim_present_test.1645867113 |
| /workspace/coverage/default/40.prim_present_test.3527990845 |
| /workspace/coverage/default/41.prim_present_test.2987612817 |
| /workspace/coverage/default/42.prim_present_test.1615148204 |
| /workspace/coverage/default/43.prim_present_test.2120638718 |
| /workspace/coverage/default/44.prim_present_test.2445097003 |
| /workspace/coverage/default/45.prim_present_test.3591312580 |
| /workspace/coverage/default/46.prim_present_test.4145714881 |
| /workspace/coverage/default/47.prim_present_test.2600959893 |
| /workspace/coverage/default/48.prim_present_test.716951215 |
| /workspace/coverage/default/49.prim_present_test.1201446727 |
| /workspace/coverage/default/5.prim_present_test.2143137483 |
| /workspace/coverage/default/6.prim_present_test.1960172070 |
| /workspace/coverage/default/7.prim_present_test.444281676 |
| /workspace/coverage/default/8.prim_present_test.3735309298 |
| /workspace/coverage/default/9.prim_present_test.303292305 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/18.prim_present_test.4110603233 | Jan 24 12:43:11 PM PST 24 | Jan 24 12:44:45 PM PST 24 | 6473420000 ps | ||
| T2 | /workspace/coverage/default/30.prim_present_test.3397657216 | Jan 24 12:43:18 PM PST 24 | Jan 24 12:45:50 PM PST 24 | 15374760000 ps | ||
| T3 | /workspace/coverage/default/31.prim_present_test.921105966 | Jan 24 12:43:18 PM PST 24 | Jan 24 12:45:21 PM PST 24 | 10788000000 ps | ||
| T4 | /workspace/coverage/default/36.prim_present_test.2304552645 | Jan 24 12:43:25 PM PST 24 | Jan 24 12:45:21 PM PST 24 | 8578320000 ps | ||
| T5 | /workspace/coverage/default/10.prim_present_test.426089781 | Jan 24 12:43:05 PM PST 24 | Jan 24 12:45:27 PM PST 24 | 14391440000 ps | ||
| T6 | /workspace/coverage/default/19.prim_present_test.3101311954 | Jan 24 12:43:12 PM PST 24 | Jan 24 12:44:47 PM PST 24 | 7359400000 ps | ||
| T7 | /workspace/coverage/default/20.prim_present_test.1809636777 | Jan 24 12:43:10 PM PST 24 | Jan 24 12:44:27 PM PST 24 | 3908480000 ps | ||
| T8 | /workspace/coverage/default/9.prim_present_test.303292305 | Jan 24 12:43:11 PM PST 24 | Jan 24 12:45:18 PM PST 24 | 11989560000 ps | ||
| T9 | /workspace/coverage/default/26.prim_present_test.4236957400 | Jan 24 12:43:25 PM PST 24 | Jan 24 12:45:38 PM PST 24 | 11796120000 ps | ||
| T10 | /workspace/coverage/default/41.prim_present_test.2987612817 | Jan 24 12:43:25 PM PST 24 | Jan 24 12:45:10 PM PST 24 | 7293060000 ps | ||
| T11 | /workspace/coverage/default/13.prim_present_test.2827397289 | Jan 24 12:43:08 PM PST 24 | Jan 24 12:45:34 PM PST 24 | 13820420000 ps | ||
| T12 | /workspace/coverage/default/23.prim_present_test.1237837738 | Jan 24 12:43:21 PM PST 24 | Jan 24 12:44:31 PM PST 24 | 3532760000 ps | ||
| T13 | /workspace/coverage/default/35.prim_present_test.3341080834 | Jan 24 12:43:25 PM PST 24 | Jan 24 12:45:09 PM PST 24 | 7766120000 ps | ||
| T14 | /workspace/coverage/default/11.prim_present_test.2301568748 | Jan 24 12:43:14 PM PST 24 | Jan 24 12:44:21 PM PST 24 | 3396980000 ps | ||
| T15 | /workspace/coverage/default/25.prim_present_test.207153305 | Jan 24 12:43:21 PM PST 24 | Jan 24 12:45:26 PM PST 24 | 12636220000 ps | ||
| T16 | /workspace/coverage/default/29.prim_present_test.3982921550 | Jan 24 12:43:21 PM PST 24 | Jan 24 12:45:28 PM PST 24 | 11794880000 ps | ||
| T17 | /workspace/coverage/default/17.prim_present_test.3883828180 | Jan 24 12:43:04 PM PST 24 | Jan 24 12:45:15 PM PST 24 | 12745960000 ps | ||
| T18 | /workspace/coverage/default/12.prim_present_test.2647280256 | Jan 24 12:43:07 PM PST 24 | Jan 24 12:44:45 PM PST 24 | 9569700000 ps | ||
| T19 | /workspace/coverage/default/21.prim_present_test.1108996762 | Jan 24 12:43:20 PM PST 24 | Jan 24 12:45:16 PM PST 24 | 8851740000 ps | ||
| T20 | /workspace/coverage/default/8.prim_present_test.3735309298 | Jan 24 12:43:05 PM PST 24 | Jan 24 12:44:14 PM PST 24 | 4003340000 ps | ||
| T21 | /workspace/coverage/default/5.prim_present_test.2143137483 | Jan 24 12:43:12 PM PST 24 | Jan 24 12:44:42 PM PST 24 | 6337020000 ps | ||
| T22 | /workspace/coverage/default/47.prim_present_test.2600959893 | Jan 24 12:43:20 PM PST 24 | Jan 24 12:45:11 PM PST 24 | 8424560000 ps | ||
| T23 | /workspace/coverage/default/38.prim_present_test.2848564922 | Jan 24 12:43:26 PM PST 24 | Jan 24 12:45:51 PM PST 24 | 14668580000 ps | ||
| T24 | /workspace/coverage/default/7.prim_present_test.444281676 | Jan 24 12:43:13 PM PST 24 | Jan 24 12:44:21 PM PST 24 | 3586700000 ps | ||
| T25 | /workspace/coverage/default/22.prim_present_test.693627437 | Jan 24 12:43:21 PM PST 24 | Jan 24 12:45:21 PM PST 24 | 9998120000 ps | ||
| T26 | /workspace/coverage/default/27.prim_present_test.1995017351 | Jan 24 12:43:18 PM PST 24 | Jan 24 12:45:14 PM PST 24 | 9459960000 ps | ||
| T27 | /workspace/coverage/default/3.prim_present_test.3619004231 | Jan 24 12:43:03 PM PST 24 | Jan 24 12:44:48 PM PST 24 | 9988200000 ps | ||
| T28 | /workspace/coverage/default/49.prim_present_test.1201446727 | Jan 24 12:43:30 PM PST 24 | Jan 24 12:45:47 PM PST 24 | 12063960000 ps | ||
| T29 | /workspace/coverage/default/16.prim_present_test.867204892 | Jan 24 12:43:05 PM PST 24 | Jan 24 12:45:18 PM PST 24 | 13196080000 ps | ||
| T30 | /workspace/coverage/default/2.prim_present_test.966943514 | Jan 24 12:43:13 PM PST 24 | Jan 24 12:44:41 PM PST 24 | 5416320000 ps | ||
| T31 | /workspace/coverage/default/46.prim_present_test.4145714881 | Jan 24 12:43:30 PM PST 24 | Jan 24 12:45:16 PM PST 24 | 7428220000 ps | ||
| T32 | /workspace/coverage/default/6.prim_present_test.1960172070 | Jan 24 12:43:10 PM PST 24 | Jan 24 12:45:01 PM PST 24 | 9933020000 ps | ||
| T33 | /workspace/coverage/default/33.prim_present_test.3188248330 | Jan 24 12:43:19 PM PST 24 | Jan 24 12:45:26 PM PST 24 | 13631320000 ps | ||
| T34 | /workspace/coverage/default/4.prim_present_test.1645867113 | Jan 24 12:43:24 PM PST 24 | Jan 24 12:45:06 PM PST 24 | 7495800000 ps | ||
| T35 | /workspace/coverage/default/45.prim_present_test.3591312580 | Jan 24 12:43:30 PM PST 24 | Jan 24 12:45:08 PM PST 24 | 6250220000 ps | ||
| T36 | /workspace/coverage/default/14.prim_present_test.2998211263 | Jan 24 12:43:08 PM PST 24 | Jan 24 12:45:27 PM PST 24 | 13372780000 ps | ||
| T37 | /workspace/coverage/default/34.prim_present_test.2391757486 | Jan 24 12:43:25 PM PST 24 | Jan 24 12:45:53 PM PST 24 | 14310840000 ps | ||
| T38 | /workspace/coverage/default/44.prim_present_test.2445097003 | Jan 24 12:43:20 PM PST 24 | Jan 24 12:45:15 PM PST 24 | 9121440000 ps | ||
| T39 | /workspace/coverage/default/42.prim_present_test.1615148204 | Jan 24 12:43:18 PM PST 24 | Jan 24 12:44:41 PM PST 24 | 6125600000 ps | ||
| T40 | /workspace/coverage/default/28.prim_present_test.2927487555 | Jan 24 12:43:25 PM PST 24 | Jan 24 12:45:25 PM PST 24 | 9838160000 ps | ||
| T41 | /workspace/coverage/default/24.prim_present_test.192601617 | Jan 24 12:43:25 PM PST 24 | Jan 24 12:45:25 PM PST 24 | 9313640000 ps | ||
| T42 | /workspace/coverage/default/32.prim_present_test.3495275641 | Jan 24 12:43:18 PM PST 24 | Jan 24 12:44:39 PM PST 24 | 4802520000 ps | ||
| T43 | /workspace/coverage/default/15.prim_present_test.3622799859 | Jan 24 12:43:10 PM PST 24 | Jan 24 12:44:29 PM PST 24 | 4281100000 ps | ||
| T44 | /workspace/coverage/default/40.prim_present_test.3527990845 | Jan 24 12:43:19 PM PST 24 | Jan 24 12:45:46 PM PST 24 | 15361740000 ps | ||
| T45 | /workspace/coverage/default/37.prim_present_test.717193443 | Jan 24 12:43:18 PM PST 24 | Jan 24 12:44:53 PM PST 24 | 6748080000 ps | ||
| T46 | /workspace/coverage/default/39.prim_present_test.2381095555 | Jan 24 12:43:25 PM PST 24 | Jan 24 12:44:49 PM PST 24 | 4987900000 ps | ||
| T47 | /workspace/coverage/default/48.prim_present_test.716951215 | Jan 24 12:43:21 PM PST 24 | Jan 24 12:45:20 PM PST 24 | 10046480000 ps | ||
| T48 | /workspace/coverage/default/43.prim_present_test.2120638718 | Jan 24 12:43:20 PM PST 24 | Jan 24 12:45:40 PM PST 24 | 13082000000 ps | ||
| T49 | /workspace/coverage/default/0.prim_present_test.1606542811 | Jan 24 12:43:04 PM PST 24 | Jan 24 12:45:28 PM PST 24 | 14641300000 ps | ||
| T50 | /workspace/coverage/default/1.prim_present_test.4056845304 | Jan 24 12:43:12 PM PST 24 | Jan 24 12:44:51 PM PST 24 | 7962660000 ps |
| Test location | /workspace/coverage/default/10.prim_present_test.426089781 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 14391440000 ps |
| CPU time | 52.35 seconds |
| Started | Jan 24 12:43:05 PM PST 24 |
| Finished | Jan 24 12:45:27 PM PST 24 |
| Peak memory | 145024 kb |
| Host | smart-46760a54-eaa5-4881-ab52-7dec1de0c302 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=426089781 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.426089781 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/0.prim_present_test.1606542811 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 14641300000 ps |
| CPU time | 54.47 seconds |
| Started | Jan 24 12:43:04 PM PST 24 |
| Finished | Jan 24 12:45:28 PM PST 24 |
| Peak memory | 145020 kb |
| Host | smart-48669f45-f151-48e6-9ec2-556badd5fe7f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1606542811 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.1606542811 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/1.prim_present_test.4056845304 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 7962660000 ps |
| CPU time | 27.69 seconds |
| Started | Jan 24 12:43:12 PM PST 24 |
| Finished | Jan 24 12:44:51 PM PST 24 |
| Peak memory | 145040 kb |
| Host | smart-c9cf3fd7-8689-4102-98ee-7ecd968137d6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4056845304 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.4056845304 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/11.prim_present_test.2301568748 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 3396980000 ps |
| CPU time | 10.41 seconds |
| Started | Jan 24 12:43:14 PM PST 24 |
| Finished | Jan 24 12:44:21 PM PST 24 |
| Peak memory | 144884 kb |
| Host | smart-0aa38992-fc03-464b-aaa0-dbafc3b229c1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2301568748 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.2301568748 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.2647280256 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 9569700000 ps |
| CPU time | 28 seconds |
| Started | Jan 24 12:43:07 PM PST 24 |
| Finished | Jan 24 12:44:45 PM PST 24 |
| Peak memory | 144624 kb |
| Host | smart-1679a18c-731a-432d-8c1e-63915fe2de21 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2647280256 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.2647280256 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.2827397289 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 13820420000 ps |
| CPU time | 52.12 seconds |
| Started | Jan 24 12:43:08 PM PST 24 |
| Finished | Jan 24 12:45:34 PM PST 24 |
| Peak memory | 143480 kb |
| Host | smart-635e1ebb-d7d7-4b5a-9c17-16b8c53d1b5a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2827397289 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.2827397289 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.2998211263 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 13372780000 ps |
| CPU time | 48.71 seconds |
| Started | Jan 24 12:43:08 PM PST 24 |
| Finished | Jan 24 12:45:27 PM PST 24 |
| Peak memory | 143544 kb |
| Host | smart-7d75167a-7bfe-40a7-b11d-cd497c54c25f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2998211263 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.2998211263 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.3622799859 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 4281100000 ps |
| CPU time | 17.11 seconds |
| Started | Jan 24 12:43:10 PM PST 24 |
| Finished | Jan 24 12:44:29 PM PST 24 |
| Peak memory | 143280 kb |
| Host | smart-c1aa4e79-4f17-43df-b6de-6ec3c0d8cedc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3622799859 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.3622799859 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.867204892 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 13196080000 ps |
| CPU time | 47.71 seconds |
| Started | Jan 24 12:43:05 PM PST 24 |
| Finished | Jan 24 12:45:18 PM PST 24 |
| Peak memory | 145024 kb |
| Host | smart-29a0fc66-e497-41e8-9d75-4921f60d9a40 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=867204892 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.867204892 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.3883828180 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 12745960000 ps |
| CPU time | 47.06 seconds |
| Started | Jan 24 12:43:04 PM PST 24 |
| Finished | Jan 24 12:45:15 PM PST 24 |
| Peak memory | 145016 kb |
| Host | smart-dd30aabe-f6db-46bf-afce-cf14361b8186 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3883828180 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.3883828180 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.4110603233 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 6473420000 ps |
| CPU time | 24.66 seconds |
| Started | Jan 24 12:43:11 PM PST 24 |
| Finished | Jan 24 12:44:45 PM PST 24 |
| Peak memory | 144456 kb |
| Host | smart-92eb7779-cc02-4986-b735-df9951e7344b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4110603233 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.4110603233 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.3101311954 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 7359400000 ps |
| CPU time | 25.35 seconds |
| Started | Jan 24 12:43:12 PM PST 24 |
| Finished | Jan 24 12:44:47 PM PST 24 |
| Peak memory | 145040 kb |
| Host | smart-932429a3-4540-4973-a78f-bfa21736a345 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3101311954 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.3101311954 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.966943514 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 5416320000 ps |
| CPU time | 21.63 seconds |
| Started | Jan 24 12:43:13 PM PST 24 |
| Finished | Jan 24 12:44:41 PM PST 24 |
| Peak memory | 144616 kb |
| Host | smart-796f2214-2104-4942-bcdf-af7b0ea7965d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=966943514 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.966943514 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.1809636777 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 3908480000 ps |
| CPU time | 15.92 seconds |
| Started | Jan 24 12:43:10 PM PST 24 |
| Finished | Jan 24 12:44:27 PM PST 24 |
| Peak memory | 143636 kb |
| Host | smart-3b1eff06-df94-46ea-8ff4-77852aef56ec |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1809636777 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.1809636777 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.1108996762 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 8851740000 ps |
| CPU time | 35.32 seconds |
| Started | Jan 24 12:43:20 PM PST 24 |
| Finished | Jan 24 12:45:16 PM PST 24 |
| Peak memory | 144680 kb |
| Host | smart-28ca043a-1569-4235-a4d1-bd80d5592608 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1108996762 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.1108996762 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.693627437 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 9998120000 ps |
| CPU time | 37.86 seconds |
| Started | Jan 24 12:43:21 PM PST 24 |
| Finished | Jan 24 12:45:21 PM PST 24 |
| Peak memory | 144660 kb |
| Host | smart-16f5b7cf-0352-4a27-8058-ba00a48fd59b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=693627437 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.693627437 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.1237837738 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 3532760000 ps |
| CPU time | 11.6 seconds |
| Started | Jan 24 12:43:21 PM PST 24 |
| Finished | Jan 24 12:44:31 PM PST 24 |
| Peak memory | 144816 kb |
| Host | smart-ecbb3664-c1d4-48d1-ab08-5d640a0cd850 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1237837738 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.1237837738 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.192601617 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 9313640000 ps |
| CPU time | 37.65 seconds |
| Started | Jan 24 12:43:25 PM PST 24 |
| Finished | Jan 24 12:45:25 PM PST 24 |
| Peak memory | 144480 kb |
| Host | smart-03c2ca97-1e63-4361-91d4-7373d39553ca |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=192601617 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.192601617 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.207153305 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 12636220000 ps |
| CPU time | 41.76 seconds |
| Started | Jan 24 12:43:21 PM PST 24 |
| Finished | Jan 24 12:45:26 PM PST 24 |
| Peak memory | 144904 kb |
| Host | smart-4b30b698-929f-460e-9306-ce0dd592136c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=207153305 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.207153305 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.4236957400 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 11796120000 ps |
| CPU time | 44.95 seconds |
| Started | Jan 24 12:43:25 PM PST 24 |
| Finished | Jan 24 12:45:38 PM PST 24 |
| Peak memory | 144508 kb |
| Host | smart-8f35d3a3-3401-4625-8a38-f1308d7eca68 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4236957400 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.4236957400 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.1995017351 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 9459960000 ps |
| CPU time | 36.12 seconds |
| Started | Jan 24 12:43:18 PM PST 24 |
| Finished | Jan 24 12:45:14 PM PST 24 |
| Peak memory | 145016 kb |
| Host | smart-94c62f7b-a228-4aa5-8c4d-6feba3a3145f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1995017351 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.1995017351 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.2927487555 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 9838160000 ps |
| CPU time | 37.68 seconds |
| Started | Jan 24 12:43:25 PM PST 24 |
| Finished | Jan 24 12:45:25 PM PST 24 |
| Peak memory | 144508 kb |
| Host | smart-e96db55c-8678-49be-b19b-de0c28e9f1d1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2927487555 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.2927487555 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.3982921550 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 11794880000 ps |
| CPU time | 41.86 seconds |
| Started | Jan 24 12:43:21 PM PST 24 |
| Finished | Jan 24 12:45:28 PM PST 24 |
| Peak memory | 144680 kb |
| Host | smart-d5feca3f-fd03-47b3-823d-e680c6feeea1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3982921550 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.3982921550 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.3619004231 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 9988200000 ps |
| CPU time | 32.54 seconds |
| Started | Jan 24 12:43:03 PM PST 24 |
| Finished | Jan 24 12:44:48 PM PST 24 |
| Peak memory | 144600 kb |
| Host | smart-f69fdfd2-fb07-4f37-83d2-cc226810153c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3619004231 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.3619004231 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.3397657216 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 15374760000 ps |
| CPU time | 55.31 seconds |
| Started | Jan 24 12:43:18 PM PST 24 |
| Finished | Jan 24 12:45:50 PM PST 24 |
| Peak memory | 145008 kb |
| Host | smart-9d06244e-fd6f-4c6c-813c-6094696eb242 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3397657216 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.3397657216 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.921105966 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 10788000000 ps |
| CPU time | 40.29 seconds |
| Started | Jan 24 12:43:18 PM PST 24 |
| Finished | Jan 24 12:45:21 PM PST 24 |
| Peak memory | 145024 kb |
| Host | smart-3c96dab7-c34d-4a45-ada5-691d157eb050 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=921105966 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.921105966 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.3495275641 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 4802520000 ps |
| CPU time | 17.39 seconds |
| Started | Jan 24 12:43:18 PM PST 24 |
| Finished | Jan 24 12:44:39 PM PST 24 |
| Peak memory | 144704 kb |
| Host | smart-aa90b133-7cc6-4718-a5d5-2288792b7963 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3495275641 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.3495275641 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.3188248330 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 13631320000 ps |
| CPU time | 42.4 seconds |
| Started | Jan 24 12:43:19 PM PST 24 |
| Finished | Jan 24 12:45:26 PM PST 24 |
| Peak memory | 144684 kb |
| Host | smart-55052ec3-57c1-44f6-a02e-c8651804a499 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3188248330 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.3188248330 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.2391757486 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 14310840000 ps |
| CPU time | 52.47 seconds |
| Started | Jan 24 12:43:25 PM PST 24 |
| Finished | Jan 24 12:45:53 PM PST 24 |
| Peak memory | 144540 kb |
| Host | smart-ee59a45d-6146-4c13-9322-28fca0315590 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2391757486 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.2391757486 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.3341080834 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 7766120000 ps |
| CPU time | 28.92 seconds |
| Started | Jan 24 12:43:25 PM PST 24 |
| Finished | Jan 24 12:45:09 PM PST 24 |
| Peak memory | 144508 kb |
| Host | smart-4a3a0373-7469-4f7c-9865-6c3ba6363ace |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3341080834 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.3341080834 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.2304552645 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 8578320000 ps |
| CPU time | 34.78 seconds |
| Started | Jan 24 12:43:25 PM PST 24 |
| Finished | Jan 24 12:45:21 PM PST 24 |
| Peak memory | 144540 kb |
| Host | smart-48d84190-d460-4cfd-9032-46a98db0521f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2304552645 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.2304552645 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.717193443 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 6748080000 ps |
| CPU time | 25.24 seconds |
| Started | Jan 24 12:43:18 PM PST 24 |
| Finished | Jan 24 12:44:53 PM PST 24 |
| Peak memory | 144720 kb |
| Host | smart-ecb2a795-e919-4928-bf9b-290cc71e740b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=717193443 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.717193443 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.2848564922 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 14668580000 ps |
| CPU time | 51.15 seconds |
| Started | Jan 24 12:43:26 PM PST 24 |
| Finished | Jan 24 12:45:51 PM PST 24 |
| Peak memory | 144508 kb |
| Host | smart-6ec11dc0-7fb1-46d0-8ea5-2b74be29afbe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2848564922 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.2848564922 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.2381095555 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 4987900000 ps |
| CPU time | 18.31 seconds |
| Started | Jan 24 12:43:25 PM PST 24 |
| Finished | Jan 24 12:44:49 PM PST 24 |
| Peak memory | 144508 kb |
| Host | smart-b529c49e-0c99-4e78-a236-78c4bc2f8be2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2381095555 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.2381095555 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.1645867113 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 7495800000 ps |
| CPU time | 28.21 seconds |
| Started | Jan 24 12:43:24 PM PST 24 |
| Finished | Jan 24 12:45:06 PM PST 24 |
| Peak memory | 143972 kb |
| Host | smart-5a63f893-2258-49de-86f3-5a3b74dee09c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1645867113 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.1645867113 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.3527990845 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 15361740000 ps |
| CPU time | 53.16 seconds |
| Started | Jan 24 12:43:19 PM PST 24 |
| Finished | Jan 24 12:45:46 PM PST 24 |
| Peak memory | 144984 kb |
| Host | smart-0b24146b-ff0c-4437-bd30-e9efbe98f33f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3527990845 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.3527990845 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.2987612817 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 7293060000 ps |
| CPU time | 28.99 seconds |
| Started | Jan 24 12:43:25 PM PST 24 |
| Finished | Jan 24 12:45:10 PM PST 24 |
| Peak memory | 144504 kb |
| Host | smart-5d05a66d-8eb8-4517-9a88-d495a47682e7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2987612817 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.2987612817 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.1615148204 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 6125600000 ps |
| CPU time | 18.39 seconds |
| Started | Jan 24 12:43:18 PM PST 24 |
| Finished | Jan 24 12:44:41 PM PST 24 |
| Peak memory | 144996 kb |
| Host | smart-a159108e-39b1-450b-a7a4-2edff09b67cc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1615148204 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.1615148204 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.2120638718 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 13082000000 ps |
| CPU time | 49.21 seconds |
| Started | Jan 24 12:43:20 PM PST 24 |
| Finished | Jan 24 12:45:40 PM PST 24 |
| Peak memory | 144584 kb |
| Host | smart-2a8fc14d-549e-4fda-a426-1a638c2b5f4a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2120638718 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.2120638718 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.2445097003 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 9121440000 ps |
| CPU time | 34.72 seconds |
| Started | Jan 24 12:43:20 PM PST 24 |
| Finished | Jan 24 12:45:15 PM PST 24 |
| Peak memory | 144616 kb |
| Host | smart-8f51f65f-761b-477c-a81c-cfb1b47f8584 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2445097003 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.2445097003 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.3591312580 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 6250220000 ps |
| CPU time | 25.03 seconds |
| Started | Jan 24 12:43:30 PM PST 24 |
| Finished | Jan 24 12:45:08 PM PST 24 |
| Peak memory | 144512 kb |
| Host | smart-e4c1dc28-f73e-466f-b8a1-edd4e9cf6259 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3591312580 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.3591312580 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.4145714881 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 7428220000 ps |
| CPU time | 29.69 seconds |
| Started | Jan 24 12:43:30 PM PST 24 |
| Finished | Jan 24 12:45:16 PM PST 24 |
| Peak memory | 144536 kb |
| Host | smart-b8a7e5a7-3f21-4137-9945-3c57800232e4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4145714881 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.4145714881 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.2600959893 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 8424560000 ps |
| CPU time | 33.34 seconds |
| Started | Jan 24 12:43:20 PM PST 24 |
| Finished | Jan 24 12:45:11 PM PST 24 |
| Peak memory | 144616 kb |
| Host | smart-3c9dd360-64aa-4123-a181-f457bb1bca04 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2600959893 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.2600959893 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.716951215 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 10046480000 ps |
| CPU time | 38.17 seconds |
| Started | Jan 24 12:43:21 PM PST 24 |
| Finished | Jan 24 12:45:20 PM PST 24 |
| Peak memory | 144628 kb |
| Host | smart-04072ee9-900d-4720-a4f1-7d4a500a97c0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=716951215 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.716951215 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.1201446727 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 12063960000 ps |
| CPU time | 46.86 seconds |
| Started | Jan 24 12:43:30 PM PST 24 |
| Finished | Jan 24 12:45:47 PM PST 24 |
| Peak memory | 144416 kb |
| Host | smart-acd35999-f615-4f82-9eb5-85922778732f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1201446727 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.1201446727 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.2143137483 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 6337020000 ps |
| CPU time | 22.96 seconds |
| Started | Jan 24 12:43:12 PM PST 24 |
| Finished | Jan 24 12:44:42 PM PST 24 |
| Peak memory | 145040 kb |
| Host | smart-60ba8895-7853-4664-b5e5-78330137fdf7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2143137483 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.2143137483 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.1960172070 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 9933020000 ps |
| CPU time | 34.25 seconds |
| Started | Jan 24 12:43:10 PM PST 24 |
| Finished | Jan 24 12:45:01 PM PST 24 |
| Peak memory | 143792 kb |
| Host | smart-a45b0f3f-f062-4a4f-9822-f1ad569e7ee1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1960172070 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.1960172070 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.444281676 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 3586700000 ps |
| CPU time | 11.08 seconds |
| Started | Jan 24 12:43:13 PM PST 24 |
| Finished | Jan 24 12:44:21 PM PST 24 |
| Peak memory | 144888 kb |
| Host | smart-5ceb6db3-a70c-4c3e-9ded-ca4020ec2a85 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=444281676 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.444281676 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.3735309298 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 4003340000 ps |
| CPU time | 13.48 seconds |
| Started | Jan 24 12:43:05 PM PST 24 |
| Finished | Jan 24 12:44:14 PM PST 24 |
| Peak memory | 144720 kb |
| Host | smart-7733a451-8470-4105-a2eb-04885e452c02 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3735309298 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.3735309298 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.303292305 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 11989560000 ps |
| CPU time | 42.72 seconds |
| Started | Jan 24 12:43:11 PM PST 24 |
| Finished | Jan 24 12:45:18 PM PST 24 |
| Peak memory | 144552 kb |
| Host | smart-6b899aa0-37fc-4f31-82ba-091793437b6e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=303292305 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.303292305 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |