| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/1.prim_present_test.3596946711 | ||
| Name |
|---|
| /workspace/coverage/default/0.prim_present_test.1205413442 |
| /workspace/coverage/default/10.prim_present_test.1237208358 |
| /workspace/coverage/default/11.prim_present_test.1410004229 |
| /workspace/coverage/default/12.prim_present_test.1520695689 |
| /workspace/coverage/default/13.prim_present_test.926340816 |
| /workspace/coverage/default/14.prim_present_test.3745397042 |
| /workspace/coverage/default/15.prim_present_test.3731658354 |
| /workspace/coverage/default/16.prim_present_test.2145031036 |
| /workspace/coverage/default/17.prim_present_test.445590729 |
| /workspace/coverage/default/18.prim_present_test.4181830024 |
| /workspace/coverage/default/19.prim_present_test.2444184865 |
| /workspace/coverage/default/2.prim_present_test.1822749292 |
| /workspace/coverage/default/20.prim_present_test.2187752373 |
| /workspace/coverage/default/21.prim_present_test.4023704013 |
| /workspace/coverage/default/22.prim_present_test.4105876988 |
| /workspace/coverage/default/23.prim_present_test.2090850970 |
| /workspace/coverage/default/24.prim_present_test.3150027024 |
| /workspace/coverage/default/25.prim_present_test.1039958463 |
| /workspace/coverage/default/26.prim_present_test.706598407 |
| /workspace/coverage/default/27.prim_present_test.1680491197 |
| /workspace/coverage/default/28.prim_present_test.2793834648 |
| /workspace/coverage/default/29.prim_present_test.1385960756 |
| /workspace/coverage/default/3.prim_present_test.2722980794 |
| /workspace/coverage/default/30.prim_present_test.310668465 |
| /workspace/coverage/default/31.prim_present_test.3315534459 |
| /workspace/coverage/default/32.prim_present_test.4217759069 |
| /workspace/coverage/default/33.prim_present_test.2539145097 |
| /workspace/coverage/default/34.prim_present_test.1365029153 |
| /workspace/coverage/default/35.prim_present_test.194728167 |
| /workspace/coverage/default/36.prim_present_test.2217795607 |
| /workspace/coverage/default/37.prim_present_test.165833636 |
| /workspace/coverage/default/38.prim_present_test.2533378820 |
| /workspace/coverage/default/39.prim_present_test.1024686923 |
| /workspace/coverage/default/4.prim_present_test.1700667838 |
| /workspace/coverage/default/40.prim_present_test.857413565 |
| /workspace/coverage/default/41.prim_present_test.3995595387 |
| /workspace/coverage/default/42.prim_present_test.2572845421 |
| /workspace/coverage/default/43.prim_present_test.4222405159 |
| /workspace/coverage/default/44.prim_present_test.2223527011 |
| /workspace/coverage/default/45.prim_present_test.1701565656 |
| /workspace/coverage/default/46.prim_present_test.1886440006 |
| /workspace/coverage/default/47.prim_present_test.1396185560 |
| /workspace/coverage/default/48.prim_present_test.3220005268 |
| /workspace/coverage/default/49.prim_present_test.150218723 |
| /workspace/coverage/default/5.prim_present_test.1016537088 |
| /workspace/coverage/default/6.prim_present_test.1231278908 |
| /workspace/coverage/default/7.prim_present_test.3015504679 |
| /workspace/coverage/default/8.prim_present_test.3150497765 |
| /workspace/coverage/default/9.prim_present_test.2132570654 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/43.prim_present_test.4222405159 | Feb 04 12:20:43 PM PST 24 | Feb 04 12:21:54 PM PST 24 | 8683720000 ps | ||
| T2 | /workspace/coverage/default/31.prim_present_test.3315534459 | Feb 04 12:22:05 PM PST 24 | Feb 04 12:23:22 PM PST 24 | 10303160000 ps | ||
| T3 | /workspace/coverage/default/20.prim_present_test.2187752373 | Feb 04 12:20:50 PM PST 24 | Feb 04 12:22:50 PM PST 24 | 15153420000 ps | ||
| T4 | /workspace/coverage/default/30.prim_present_test.310668465 | Feb 04 12:22:23 PM PST 24 | Feb 04 12:23:47 PM PST 24 | 9337820000 ps | ||
| T5 | /workspace/coverage/default/16.prim_present_test.2145031036 | Feb 04 12:20:44 PM PST 24 | Feb 04 12:22:36 PM PST 24 | 14517920000 ps | ||
| T6 | /workspace/coverage/default/33.prim_present_test.2539145097 | Feb 04 12:20:37 PM PST 24 | Feb 04 12:21:24 PM PST 24 | 5772820000 ps | ||
| T7 | /workspace/coverage/default/35.prim_present_test.194728167 | Feb 04 12:22:20 PM PST 24 | Feb 04 12:23:30 PM PST 24 | 7146120000 ps | ||
| T8 | /workspace/coverage/default/1.prim_present_test.3596946711 | Feb 04 12:20:42 PM PST 24 | Feb 04 12:21:26 PM PST 24 | 5206760000 ps | ||
| T9 | /workspace/coverage/default/37.prim_present_test.165833636 | Feb 04 12:20:45 PM PST 24 | Feb 04 12:21:37 PM PST 24 | 6737540000 ps | ||
| T10 | /workspace/coverage/default/38.prim_present_test.2533378820 | Feb 04 12:22:21 PM PST 24 | Feb 04 12:23:51 PM PST 24 | 9851180000 ps | ||
| T11 | /workspace/coverage/default/9.prim_present_test.2132570654 | Feb 04 12:22:21 PM PST 24 | Feb 04 12:23:49 PM PST 24 | 9568460000 ps | ||
| T12 | /workspace/coverage/default/0.prim_present_test.1205413442 | Feb 04 12:20:44 PM PST 24 | Feb 04 12:22:29 PM PST 24 | 13350460000 ps | ||
| T13 | /workspace/coverage/default/34.prim_present_test.1365029153 | Feb 04 12:20:45 PM PST 24 | Feb 04 12:22:28 PM PST 24 | 15372280000 ps | ||
| T14 | /workspace/coverage/default/39.prim_present_test.1024686923 | Feb 04 12:20:43 PM PST 24 | Feb 04 12:21:50 PM PST 24 | 9135080000 ps | ||
| T15 | /workspace/coverage/default/36.prim_present_test.2217795607 | Feb 04 12:22:05 PM PST 24 | Feb 04 12:22:43 PM PST 24 | 5704000000 ps | ||
| T16 | /workspace/coverage/default/2.prim_present_test.1822749292 | Feb 04 12:20:45 PM PST 24 | Feb 04 12:21:54 PM PST 24 | 8255920000 ps | ||
| T17 | /workspace/coverage/default/12.prim_present_test.1520695689 | Feb 04 12:20:37 PM PST 24 | Feb 04 12:21:27 PM PST 24 | 6196900000 ps | ||
| T18 | /workspace/coverage/default/5.prim_present_test.1016537088 | Feb 04 12:20:37 PM PST 24 | Feb 04 12:21:25 PM PST 24 | 5927200000 ps | ||
| T19 | /workspace/coverage/default/28.prim_present_test.2793834648 | Feb 04 12:22:22 PM PST 24 | Feb 04 12:24:12 PM PST 24 | 13297140000 ps | ||
| T20 | /workspace/coverage/default/41.prim_present_test.3995595387 | Feb 04 12:20:43 PM PST 24 | Feb 04 12:21:34 PM PST 24 | 6418240000 ps | ||
| T21 | /workspace/coverage/default/29.prim_present_test.1385960756 | Feb 04 12:20:44 PM PST 24 | Feb 04 12:21:31 PM PST 24 | 5965020000 ps | ||
| T22 | /workspace/coverage/default/47.prim_present_test.1396185560 | Feb 04 12:20:43 PM PST 24 | Feb 04 12:22:03 PM PST 24 | 9504600000 ps | ||
| T23 | /workspace/coverage/default/11.prim_present_test.1410004229 | Feb 04 12:20:43 PM PST 24 | Feb 04 12:21:44 PM PST 24 | 7154180000 ps | ||
| T24 | /workspace/coverage/default/8.prim_present_test.3150497765 | Feb 04 12:20:41 PM PST 24 | Feb 04 12:22:16 PM PST 24 | 12449600000 ps | ||
| T25 | /workspace/coverage/default/48.prim_present_test.3220005268 | Feb 04 12:20:50 PM PST 24 | Feb 04 12:22:04 PM PST 24 | 8904440000 ps | ||
| T26 | /workspace/coverage/default/49.prim_present_test.150218723 | Feb 04 12:20:44 PM PST 24 | Feb 04 12:22:42 PM PST 24 | 15438000000 ps | ||
| T27 | /workspace/coverage/default/45.prim_present_test.1701565656 | Feb 04 12:20:50 PM PST 24 | Feb 04 12:22:48 PM PST 24 | 15096380000 ps | ||
| T28 | /workspace/coverage/default/44.prim_present_test.2223527011 | Feb 04 12:20:43 PM PST 24 | Feb 04 12:21:58 PM PST 24 | 9894580000 ps | ||
| T29 | /workspace/coverage/default/7.prim_present_test.3015504679 | Feb 04 12:20:50 PM PST 24 | Feb 04 12:21:41 PM PST 24 | 5982380000 ps | ||
| T30 | /workspace/coverage/default/18.prim_present_test.4181830024 | Feb 04 12:20:45 PM PST 24 | Feb 04 12:21:59 PM PST 24 | 9184060000 ps | ||
| T31 | /workspace/coverage/default/22.prim_present_test.4105876988 | Feb 04 12:20:42 PM PST 24 | Feb 04 12:21:53 PM PST 24 | 9077420000 ps | ||
| T32 | /workspace/coverage/default/19.prim_present_test.2444184865 | Feb 04 12:20:43 PM PST 24 | Feb 04 12:21:31 PM PST 24 | 5617200000 ps | ||
| T33 | /workspace/coverage/default/4.prim_present_test.1700667838 | Feb 04 12:20:46 PM PST 24 | Feb 04 12:22:01 PM PST 24 | 10391820000 ps | ||
| T34 | /workspace/coverage/default/17.prim_present_test.445590729 | Feb 04 12:20:44 PM PST 24 | Feb 04 12:21:44 PM PST 24 | 7976920000 ps | ||
| T35 | /workspace/coverage/default/27.prim_present_test.1680491197 | Feb 04 12:20:45 PM PST 24 | Feb 04 12:21:43 PM PST 24 | 7653280000 ps | ||
| T36 | /workspace/coverage/default/21.prim_present_test.4023704013 | Feb 04 12:20:50 PM PST 24 | Feb 04 12:22:02 PM PST 24 | 8499580000 ps | ||
| T37 | /workspace/coverage/default/3.prim_present_test.2722980794 | Feb 04 12:20:42 PM PST 24 | Feb 04 12:21:31 PM PST 24 | 5988580000 ps | ||
| T38 | /workspace/coverage/default/10.prim_present_test.1237208358 | Feb 04 12:20:42 PM PST 24 | Feb 04 12:22:14 PM PST 24 | 12137740000 ps | ||
| T39 | /workspace/coverage/default/40.prim_present_test.857413565 | Feb 04 12:20:45 PM PST 24 | Feb 04 12:22:08 PM PST 24 | 11672120000 ps | ||
| T40 | /workspace/coverage/default/23.prim_present_test.2090850970 | Feb 04 12:20:42 PM PST 24 | Feb 04 12:22:22 PM PST 24 | 13507940000 ps | ||
| T41 | /workspace/coverage/default/6.prim_present_test.1231278908 | Feb 04 12:20:50 PM PST 24 | Feb 04 12:21:36 PM PST 24 | 5425000000 ps | ||
| T42 | /workspace/coverage/default/15.prim_present_test.3731658354 | Feb 04 12:20:50 PM PST 24 | Feb 04 12:22:49 PM PST 24 | 15454740000 ps | ||
| T43 | /workspace/coverage/default/26.prim_present_test.706598407 | Feb 04 12:22:23 PM PST 24 | Feb 04 12:23:19 PM PST 24 | 5836680000 ps | ||
| T44 | /workspace/coverage/default/46.prim_present_test.1886440006 | Feb 04 12:20:44 PM PST 24 | Feb 04 12:22:33 PM PST 24 | 14764060000 ps | ||
| T45 | /workspace/coverage/default/32.prim_present_test.4217759069 | Feb 04 12:20:42 PM PST 24 | Feb 04 12:21:47 PM PST 24 | 8404100000 ps | ||
| T46 | /workspace/coverage/default/42.prim_present_test.2572845421 | Feb 04 12:22:21 PM PST 24 | Feb 04 12:23:16 PM PST 24 | 5261320000 ps | ||
| T47 | /workspace/coverage/default/14.prim_present_test.3745397042 | Feb 04 12:20:37 PM PST 24 | Feb 04 12:21:23 PM PST 24 | 5586200000 ps | ||
| T48 | /workspace/coverage/default/25.prim_present_test.1039958463 | Feb 04 12:20:46 PM PST 24 | Feb 04 12:21:48 PM PST 24 | 8537400000 ps | ||
| T49 | /workspace/coverage/default/13.prim_present_test.926340816 | Feb 04 12:20:43 PM PST 24 | Feb 04 12:22:18 PM PST 24 | 12687680000 ps | ||
| T50 | /workspace/coverage/default/24.prim_present_test.3150027024 | Feb 04 12:20:50 PM PST 24 | Feb 04 12:22:46 PM PST 24 | 14720660000 ps |
| Test location | /workspace/coverage/default/1.prim_present_test.3596946711 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 5206760000 ps |
| CPU time | 20.84 seconds |
| Started | Feb 04 12:20:42 PM PST 24 |
| Finished | Feb 04 12:21:26 PM PST 24 |
| Peak memory | 144268 kb |
| Host | smart-3b76277e-0ff8-4a47-8b86-a60ebedb36c5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3596946711 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.3596946711 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/0.prim_present_test.1205413442 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 13350460000 ps |
| CPU time | 53.11 seconds |
| Started | Feb 04 12:20:44 PM PST 24 |
| Finished | Feb 04 12:22:29 PM PST 24 |
| Peak memory | 145100 kb |
| Host | smart-a8214038-65f6-4a8e-a847-95cbcd21f35b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1205413442 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.1205413442 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/10.prim_present_test.1237208358 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 12137740000 ps |
| CPU time | 45.43 seconds |
| Started | Feb 04 12:20:42 PM PST 24 |
| Finished | Feb 04 12:22:14 PM PST 24 |
| Peak memory | 142988 kb |
| Host | smart-8fbdc925-48e0-47fe-be1d-6da3785a0aaf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1237208358 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.1237208358 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/11.prim_present_test.1410004229 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 7154180000 ps |
| CPU time | 30.31 seconds |
| Started | Feb 04 12:20:43 PM PST 24 |
| Finished | Feb 04 12:21:44 PM PST 24 |
| Peak memory | 143256 kb |
| Host | smart-53588993-f3f0-4f43-a816-e7800bd686b9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1410004229 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.1410004229 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.1520695689 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 6196900000 ps |
| CPU time | 25.61 seconds |
| Started | Feb 04 12:20:37 PM PST 24 |
| Finished | Feb 04 12:21:27 PM PST 24 |
| Peak memory | 143632 kb |
| Host | smart-7628b6b2-5cf4-4ff2-aeeb-b6575af98b42 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1520695689 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.1520695689 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.926340816 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 12687680000 ps |
| CPU time | 48.09 seconds |
| Started | Feb 04 12:20:43 PM PST 24 |
| Finished | Feb 04 12:22:18 PM PST 24 |
| Peak memory | 143836 kb |
| Host | smart-cbdb5950-d9d2-4bed-85d0-7318e1c3fe3e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=926340816 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.926340816 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.3745397042 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 5586200000 ps |
| CPU time | 23.34 seconds |
| Started | Feb 04 12:20:37 PM PST 24 |
| Finished | Feb 04 12:21:23 PM PST 24 |
| Peak memory | 143092 kb |
| Host | smart-da096415-67ed-4dbf-aab2-ec4c3b1b05dc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3745397042 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.3745397042 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.3731658354 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 15454740000 ps |
| CPU time | 60.41 seconds |
| Started | Feb 04 12:20:50 PM PST 24 |
| Finished | Feb 04 12:22:49 PM PST 24 |
| Peak memory | 144784 kb |
| Host | smart-62bb4758-63db-4859-9580-d860f85d0fa7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3731658354 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.3731658354 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.2145031036 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 14517920000 ps |
| CPU time | 56.71 seconds |
| Started | Feb 04 12:20:44 PM PST 24 |
| Finished | Feb 04 12:22:36 PM PST 24 |
| Peak memory | 145096 kb |
| Host | smart-e4ea2bb5-429b-4600-9633-4cc83bc64b40 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2145031036 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.2145031036 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.445590729 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 7976920000 ps |
| CPU time | 29.58 seconds |
| Started | Feb 04 12:20:44 PM PST 24 |
| Finished | Feb 04 12:21:44 PM PST 24 |
| Peak memory | 145020 kb |
| Host | smart-83652b8b-6d19-4dcf-b341-ca58e566b095 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=445590729 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.445590729 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.4181830024 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 9184060000 ps |
| CPU time | 36.92 seconds |
| Started | Feb 04 12:20:45 PM PST 24 |
| Finished | Feb 04 12:21:59 PM PST 24 |
| Peak memory | 145100 kb |
| Host | smart-10b92859-efb7-48ba-9bcc-7c1e3d923d00 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4181830024 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.4181830024 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.2444184865 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 5617200000 ps |
| CPU time | 23.79 seconds |
| Started | Feb 04 12:20:43 PM PST 24 |
| Finished | Feb 04 12:21:31 PM PST 24 |
| Peak memory | 144776 kb |
| Host | smart-0764fbf4-fcc1-4ec7-ae57-7563cfa0bb94 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2444184865 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.2444184865 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.1822749292 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 8255920000 ps |
| CPU time | 34.92 seconds |
| Started | Feb 04 12:20:45 PM PST 24 |
| Finished | Feb 04 12:21:54 PM PST 24 |
| Peak memory | 145100 kb |
| Host | smart-889e1aeb-8e6a-4233-8186-42c4ff19b1bb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1822749292 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.1822749292 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.2187752373 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 15153420000 ps |
| CPU time | 61.25 seconds |
| Started | Feb 04 12:20:50 PM PST 24 |
| Finished | Feb 04 12:22:50 PM PST 24 |
| Peak memory | 144448 kb |
| Host | smart-cb160dbc-7201-4bc7-9548-f3731d314cd3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2187752373 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.2187752373 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.4023704013 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 8499580000 ps |
| CPU time | 35.83 seconds |
| Started | Feb 04 12:20:50 PM PST 24 |
| Finished | Feb 04 12:22:02 PM PST 24 |
| Peak memory | 144768 kb |
| Host | smart-8614c04a-7a3a-48c8-a5f6-239b58d54d3d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4023704013 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.4023704013 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.4105876988 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 9077420000 ps |
| CPU time | 34.91 seconds |
| Started | Feb 04 12:20:42 PM PST 24 |
| Finished | Feb 04 12:21:53 PM PST 24 |
| Peak memory | 142832 kb |
| Host | smart-8c6b9add-feaa-4cf7-83ba-48cc76062a2e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4105876988 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.4105876988 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.2090850970 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 13507940000 ps |
| CPU time | 50.17 seconds |
| Started | Feb 04 12:20:42 PM PST 24 |
| Finished | Feb 04 12:22:22 PM PST 24 |
| Peak memory | 143092 kb |
| Host | smart-2131191c-003a-4552-aad6-64a0ba13a540 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2090850970 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.2090850970 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.3150027024 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 14720660000 ps |
| CPU time | 58.91 seconds |
| Started | Feb 04 12:20:50 PM PST 24 |
| Finished | Feb 04 12:22:46 PM PST 24 |
| Peak memory | 144512 kb |
| Host | smart-3860a17f-c107-4afc-ac5f-34650b977d94 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3150027024 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.3150027024 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.1039958463 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 8537400000 ps |
| CPU time | 31.84 seconds |
| Started | Feb 04 12:20:46 PM PST 24 |
| Finished | Feb 04 12:21:48 PM PST 24 |
| Peak memory | 145016 kb |
| Host | smart-999f9ac6-fe26-434e-bb90-adc3c910bc93 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1039958463 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.1039958463 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.706598407 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 5836680000 ps |
| CPU time | 24.68 seconds |
| Started | Feb 04 12:22:23 PM PST 24 |
| Finished | Feb 04 12:23:19 PM PST 24 |
| Peak memory | 144624 kb |
| Host | smart-3fd2f244-e8c5-458d-9d1b-eed4bd3f5cf8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=706598407 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.706598407 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.1680491197 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 7653280000 ps |
| CPU time | 28.85 seconds |
| Started | Feb 04 12:20:45 PM PST 24 |
| Finished | Feb 04 12:21:43 PM PST 24 |
| Peak memory | 145016 kb |
| Host | smart-31465db2-a58b-422d-add0-f02f3b159626 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1680491197 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.1680491197 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.2793834648 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 13297140000 ps |
| CPU time | 51.86 seconds |
| Started | Feb 04 12:22:22 PM PST 24 |
| Finished | Feb 04 12:24:12 PM PST 24 |
| Peak memory | 144792 kb |
| Host | smart-1b1c9757-4244-4ec9-9f7d-06b49b478401 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2793834648 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.2793834648 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.1385960756 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 5965020000 ps |
| CPU time | 23.56 seconds |
| Started | Feb 04 12:20:44 PM PST 24 |
| Finished | Feb 04 12:21:31 PM PST 24 |
| Peak memory | 145024 kb |
| Host | smart-5255784b-1c90-4628-a157-94d429b952e8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1385960756 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.1385960756 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.2722980794 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 5988580000 ps |
| CPU time | 23.13 seconds |
| Started | Feb 04 12:20:42 PM PST 24 |
| Finished | Feb 04 12:21:31 PM PST 24 |
| Peak memory | 143000 kb |
| Host | smart-09469a1d-dee4-4e98-bf87-d1a385770bfe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2722980794 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.2722980794 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.310668465 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 9337820000 ps |
| CPU time | 38.61 seconds |
| Started | Feb 04 12:22:23 PM PST 24 |
| Finished | Feb 04 12:23:47 PM PST 24 |
| Peak memory | 144772 kb |
| Host | smart-717e736a-abe2-47d1-98c1-bfe60219f8b9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=310668465 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.310668465 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.3315534459 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 10303160000 ps |
| CPU time | 39.39 seconds |
| Started | Feb 04 12:22:05 PM PST 24 |
| Finished | Feb 04 12:23:22 PM PST 24 |
| Peak memory | 143760 kb |
| Host | smart-0f749e8a-fe1b-444b-a82e-253574c3abc6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3315534459 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.3315534459 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.4217759069 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 8404100000 ps |
| CPU time | 32.12 seconds |
| Started | Feb 04 12:20:42 PM PST 24 |
| Finished | Feb 04 12:21:47 PM PST 24 |
| Peak memory | 144320 kb |
| Host | smart-bf329c3e-5128-447e-a90e-a9423a6836d1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4217759069 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.4217759069 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.2539145097 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 5772820000 ps |
| CPU time | 23.54 seconds |
| Started | Feb 04 12:20:37 PM PST 24 |
| Finished | Feb 04 12:21:24 PM PST 24 |
| Peak memory | 142692 kb |
| Host | smart-5fcfdd19-e7a0-43e2-8503-d86beb8b2363 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2539145097 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.2539145097 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.1365029153 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 15372280000 ps |
| CPU time | 53.83 seconds |
| Started | Feb 04 12:20:45 PM PST 24 |
| Finished | Feb 04 12:22:28 PM PST 24 |
| Peak memory | 145016 kb |
| Host | smart-4ea79c4b-580f-47a2-bf8c-a0a30602f795 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1365029153 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.1365029153 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.194728167 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 7146120000 ps |
| CPU time | 30.03 seconds |
| Started | Feb 04 12:22:20 PM PST 24 |
| Finished | Feb 04 12:23:30 PM PST 24 |
| Peak memory | 144804 kb |
| Host | smart-6c4f22c4-2911-4adf-95ca-cf25fb816c26 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=194728167 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.194728167 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.2217795607 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 5704000000 ps |
| CPU time | 19.28 seconds |
| Started | Feb 04 12:22:05 PM PST 24 |
| Finished | Feb 04 12:22:43 PM PST 24 |
| Peak memory | 143664 kb |
| Host | smart-f804bc31-004b-4baa-a5c7-d743ef53d092 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2217795607 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.2217795607 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.165833636 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 6737540000 ps |
| CPU time | 26.4 seconds |
| Started | Feb 04 12:20:45 PM PST 24 |
| Finished | Feb 04 12:21:37 PM PST 24 |
| Peak memory | 145020 kb |
| Host | smart-a1620a27-fb38-473f-b7b9-751f18532109 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=165833636 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.165833636 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.2533378820 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 9851180000 ps |
| CPU time | 40.43 seconds |
| Started | Feb 04 12:22:21 PM PST 24 |
| Finished | Feb 04 12:23:51 PM PST 24 |
| Peak memory | 144536 kb |
| Host | smart-69d1d393-abbf-4c4f-93b1-e57e3502a17c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2533378820 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.2533378820 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.1024686923 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 9135080000 ps |
| CPU time | 33.24 seconds |
| Started | Feb 04 12:20:43 PM PST 24 |
| Finished | Feb 04 12:21:50 PM PST 24 |
| Peak memory | 144588 kb |
| Host | smart-816db8be-47eb-4371-8709-f20c542e7cb5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1024686923 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.1024686923 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.1700667838 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 10391820000 ps |
| CPU time | 38.42 seconds |
| Started | Feb 04 12:20:46 PM PST 24 |
| Finished | Feb 04 12:22:01 PM PST 24 |
| Peak memory | 145020 kb |
| Host | smart-685fcd34-13db-45de-9732-3bd62cd654fd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1700667838 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.1700667838 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.857413565 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 11672120000 ps |
| CPU time | 42.61 seconds |
| Started | Feb 04 12:20:45 PM PST 24 |
| Finished | Feb 04 12:22:08 PM PST 24 |
| Peak memory | 145020 kb |
| Host | smart-72e8cd27-a051-419a-bb8c-7e8b4da15174 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=857413565 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.857413565 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.3995595387 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 6418240000 ps |
| CPU time | 24.98 seconds |
| Started | Feb 04 12:20:43 PM PST 24 |
| Finished | Feb 04 12:21:34 PM PST 24 |
| Peak memory | 143908 kb |
| Host | smart-65786472-078e-4747-8cdb-2fc4370197f7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3995595387 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.3995595387 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.2572845421 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 5261320000 ps |
| CPU time | 22.69 seconds |
| Started | Feb 04 12:22:21 PM PST 24 |
| Finished | Feb 04 12:23:16 PM PST 24 |
| Peak memory | 144880 kb |
| Host | smart-682d437b-959d-43f6-a05e-08d946e177a9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2572845421 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.2572845421 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.4222405159 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 8683720000 ps |
| CPU time | 35.14 seconds |
| Started | Feb 04 12:20:43 PM PST 24 |
| Finished | Feb 04 12:21:54 PM PST 24 |
| Peak memory | 143788 kb |
| Host | smart-3569a79c-2859-4a8a-acbd-bfae6fb896f7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4222405159 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.4222405159 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.2223527011 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 9894580000 ps |
| CPU time | 37.24 seconds |
| Started | Feb 04 12:20:43 PM PST 24 |
| Finished | Feb 04 12:21:58 PM PST 24 |
| Peak memory | 143524 kb |
| Host | smart-692afda6-5eb8-4761-99f5-3db646082543 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2223527011 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.2223527011 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.1701565656 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 15096380000 ps |
| CPU time | 59.11 seconds |
| Started | Feb 04 12:20:50 PM PST 24 |
| Finished | Feb 04 12:22:48 PM PST 24 |
| Peak memory | 144964 kb |
| Host | smart-89c62ec5-2d7d-4c01-8796-f08e062513b9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1701565656 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.1701565656 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.1886440006 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 14764060000 ps |
| CPU time | 55.57 seconds |
| Started | Feb 04 12:20:44 PM PST 24 |
| Finished | Feb 04 12:22:33 PM PST 24 |
| Peak memory | 145088 kb |
| Host | smart-059984cf-9221-4976-a4b2-7704a9e4f175 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1886440006 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.1886440006 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.1396185560 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 9504600000 ps |
| CPU time | 39.99 seconds |
| Started | Feb 04 12:20:43 PM PST 24 |
| Finished | Feb 04 12:22:03 PM PST 24 |
| Peak memory | 143080 kb |
| Host | smart-14e79746-3f2b-46c8-b414-14efa56164f7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1396185560 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.1396185560 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.3220005268 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 8904440000 ps |
| CPU time | 36.6 seconds |
| Started | Feb 04 12:20:50 PM PST 24 |
| Finished | Feb 04 12:22:04 PM PST 24 |
| Peak memory | 144824 kb |
| Host | smart-7180069c-d132-4ce9-aaa6-24e3db58f8a5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3220005268 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.3220005268 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.150218723 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 15438000000 ps |
| CPU time | 60.17 seconds |
| Started | Feb 04 12:20:44 PM PST 24 |
| Finished | Feb 04 12:22:42 PM PST 24 |
| Peak memory | 145080 kb |
| Host | smart-494822b1-ddfc-4b86-9c92-06d316e5669c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=150218723 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.150218723 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.1016537088 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 5927200000 ps |
| CPU time | 24.51 seconds |
| Started | Feb 04 12:20:37 PM PST 24 |
| Finished | Feb 04 12:21:25 PM PST 24 |
| Peak memory | 143132 kb |
| Host | smart-f1894417-9992-4597-820a-56bfcc2f5963 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1016537088 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.1016537088 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.1231278908 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 5425000000 ps |
| CPU time | 22.99 seconds |
| Started | Feb 04 12:20:50 PM PST 24 |
| Finished | Feb 04 12:21:36 PM PST 24 |
| Peak memory | 144724 kb |
| Host | smart-069dfe97-c83a-4cb7-b80a-c2b92010ec08 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1231278908 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.1231278908 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.3015504679 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 5982380000 ps |
| CPU time | 24.88 seconds |
| Started | Feb 04 12:20:50 PM PST 24 |
| Finished | Feb 04 12:21:41 PM PST 24 |
| Peak memory | 144880 kb |
| Host | smart-c145777c-1f75-461f-b8df-4918f8a251a0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3015504679 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.3015504679 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.3150497765 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 12449600000 ps |
| CPU time | 46.71 seconds |
| Started | Feb 04 12:20:41 PM PST 24 |
| Finished | Feb 04 12:22:16 PM PST 24 |
| Peak memory | 143032 kb |
| Host | smart-6ce7d628-be81-4085-a137-676afdf5d7f2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3150497765 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.3150497765 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.2132570654 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 9568460000 ps |
| CPU time | 39.48 seconds |
| Started | Feb 04 12:22:21 PM PST 24 |
| Finished | Feb 04 12:23:49 PM PST 24 |
| Peak memory | 145000 kb |
| Host | smart-e3963174-11ae-41d3-8785-3f1c91079699 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2132570654 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.2132570654 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |