| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/0.prim_present_test.481434860 | ||
| Name |
|---|
| /workspace/coverage/default/1.prim_present_test.1190191050 |
| /workspace/coverage/default/10.prim_present_test.3169260988 |
| /workspace/coverage/default/11.prim_present_test.2178734453 |
| /workspace/coverage/default/12.prim_present_test.874410420 |
| /workspace/coverage/default/13.prim_present_test.2282174434 |
| /workspace/coverage/default/14.prim_present_test.383567626 |
| /workspace/coverage/default/15.prim_present_test.2752468191 |
| /workspace/coverage/default/16.prim_present_test.820889567 |
| /workspace/coverage/default/17.prim_present_test.3736190518 |
| /workspace/coverage/default/18.prim_present_test.2723251085 |
| /workspace/coverage/default/19.prim_present_test.253295001 |
| /workspace/coverage/default/2.prim_present_test.2961294152 |
| /workspace/coverage/default/20.prim_present_test.4250920459 |
| /workspace/coverage/default/21.prim_present_test.719526263 |
| /workspace/coverage/default/22.prim_present_test.3239170057 |
| /workspace/coverage/default/23.prim_present_test.113951920 |
| /workspace/coverage/default/24.prim_present_test.3119205793 |
| /workspace/coverage/default/25.prim_present_test.2993260861 |
| /workspace/coverage/default/26.prim_present_test.1936892848 |
| /workspace/coverage/default/27.prim_present_test.698973310 |
| /workspace/coverage/default/28.prim_present_test.3515485217 |
| /workspace/coverage/default/29.prim_present_test.1212002530 |
| /workspace/coverage/default/3.prim_present_test.1283032489 |
| /workspace/coverage/default/30.prim_present_test.1681800898 |
| /workspace/coverage/default/31.prim_present_test.295615391 |
| /workspace/coverage/default/32.prim_present_test.779475855 |
| /workspace/coverage/default/33.prim_present_test.3520419966 |
| /workspace/coverage/default/34.prim_present_test.1013018580 |
| /workspace/coverage/default/35.prim_present_test.2070874190 |
| /workspace/coverage/default/36.prim_present_test.923037269 |
| /workspace/coverage/default/37.prim_present_test.14239162 |
| /workspace/coverage/default/38.prim_present_test.650414534 |
| /workspace/coverage/default/39.prim_present_test.1521368963 |
| /workspace/coverage/default/4.prim_present_test.4144075642 |
| /workspace/coverage/default/40.prim_present_test.408496806 |
| /workspace/coverage/default/41.prim_present_test.386544510 |
| /workspace/coverage/default/42.prim_present_test.313016781 |
| /workspace/coverage/default/43.prim_present_test.4046373786 |
| /workspace/coverage/default/44.prim_present_test.2434729248 |
| /workspace/coverage/default/45.prim_present_test.2159834636 |
| /workspace/coverage/default/46.prim_present_test.2354654672 |
| /workspace/coverage/default/47.prim_present_test.2239505370 |
| /workspace/coverage/default/48.prim_present_test.3708607978 |
| /workspace/coverage/default/49.prim_present_test.1591583785 |
| /workspace/coverage/default/5.prim_present_test.1679823449 |
| /workspace/coverage/default/6.prim_present_test.2114919089 |
| /workspace/coverage/default/7.prim_present_test.2719568473 |
| /workspace/coverage/default/8.prim_present_test.1389543419 |
| /workspace/coverage/default/9.prim_present_test.1498568765 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/28.prim_present_test.3515485217 | Feb 07 01:18:43 PM PST 24 | Feb 07 01:19:42 PM PST 24 | 6426300000 ps | ||
| T2 | /workspace/coverage/default/15.prim_present_test.2752468191 | Feb 07 01:18:40 PM PST 24 | Feb 07 01:19:55 PM PST 24 | 9174760000 ps | ||
| T3 | /workspace/coverage/default/18.prim_present_test.2723251085 | Feb 07 01:18:41 PM PST 24 | Feb 07 01:19:31 PM PST 24 | 5696560000 ps | ||
| T4 | /workspace/coverage/default/8.prim_present_test.1389543419 | Feb 07 01:18:38 PM PST 24 | Feb 07 01:20:04 PM PST 24 | 9726560000 ps | ||
| T5 | /workspace/coverage/default/25.prim_present_test.2993260861 | Feb 07 01:18:41 PM PST 24 | Feb 07 01:20:13 PM PST 24 | 11482400000 ps | ||
| T6 | /workspace/coverage/default/29.prim_present_test.1212002530 | Feb 07 01:18:43 PM PST 24 | Feb 07 01:19:46 PM PST 24 | 7173400000 ps | ||
| T7 | /workspace/coverage/default/23.prim_present_test.113951920 | Feb 07 01:18:41 PM PST 24 | Feb 07 01:20:17 PM PST 24 | 12263600000 ps | ||
| T8 | /workspace/coverage/default/20.prim_present_test.4250920459 | Feb 07 01:18:42 PM PST 24 | Feb 07 01:20:40 PM PST 24 | 15224100000 ps | ||
| T9 | /workspace/coverage/default/0.prim_present_test.481434860 | Feb 07 01:17:49 PM PST 24 | Feb 07 01:18:38 PM PST 24 | 8381780000 ps | ||
| T10 | /workspace/coverage/default/6.prim_present_test.2114919089 | Feb 07 01:18:40 PM PST 24 | Feb 07 01:19:33 PM PST 24 | 6751800000 ps | ||
| T11 | /workspace/coverage/default/36.prim_present_test.923037269 | Feb 07 01:18:51 PM PST 24 | Feb 07 01:20:31 PM PST 24 | 12101160000 ps | ||
| T12 | /workspace/coverage/default/26.prim_present_test.1936892848 | Feb 07 01:18:40 PM PST 24 | Feb 07 01:19:27 PM PST 24 | 6046240000 ps | ||
| T13 | /workspace/coverage/default/40.prim_present_test.408496806 | Feb 07 01:18:51 PM PST 24 | Feb 07 01:20:11 PM PST 24 | 9582100000 ps | ||
| T14 | /workspace/coverage/default/31.prim_present_test.295615391 | Feb 07 01:18:42 PM PST 24 | Feb 07 01:19:58 PM PST 24 | 10672680000 ps | ||
| T15 | /workspace/coverage/default/42.prim_present_test.313016781 | Feb 07 01:18:58 PM PST 24 | Feb 07 01:19:59 PM PST 24 | 7297400000 ps | ||
| T16 | /workspace/coverage/default/37.prim_present_test.14239162 | Feb 07 01:18:54 PM PST 24 | Feb 07 01:19:13 PM PST 24 | 3488120000 ps | ||
| T17 | /workspace/coverage/default/39.prim_present_test.1521368963 | Feb 07 01:18:52 PM PST 24 | Feb 07 01:20:30 PM PST 24 | 13328140000 ps | ||
| T18 | /workspace/coverage/default/13.prim_present_test.2282174434 | Feb 07 01:18:39 PM PST 24 | Feb 07 01:19:59 PM PST 24 | 9584580000 ps | ||
| T19 | /workspace/coverage/default/3.prim_present_test.1283032489 | Feb 07 01:18:40 PM PST 24 | Feb 07 01:19:18 PM PST 24 | 5400200000 ps | ||
| T20 | /workspace/coverage/default/14.prim_present_test.383567626 | Feb 07 01:18:39 PM PST 24 | Feb 07 01:20:30 PM PST 24 | 11487360000 ps | ||
| T21 | /workspace/coverage/default/41.prim_present_test.386544510 | Feb 07 01:18:52 PM PST 24 | Feb 07 01:20:09 PM PST 24 | 9148100000 ps | ||
| T22 | /workspace/coverage/default/9.prim_present_test.1498568765 | Feb 07 01:18:39 PM PST 24 | Feb 07 01:19:49 PM PST 24 | 9812740000 ps | ||
| T23 | /workspace/coverage/default/30.prim_present_test.1681800898 | Feb 07 01:18:43 PM PST 24 | Feb 07 01:19:41 PM PST 24 | 6410800000 ps | ||
| T24 | /workspace/coverage/default/7.prim_present_test.2719568473 | Feb 07 01:18:38 PM PST 24 | Feb 07 01:20:05 PM PST 24 | 13917140000 ps | ||
| T25 | /workspace/coverage/default/4.prim_present_test.4144075642 | Feb 07 01:18:38 PM PST 24 | Feb 07 01:19:38 PM PST 24 | 9942940000 ps | ||
| T26 | /workspace/coverage/default/33.prim_present_test.3520419966 | Feb 07 01:18:51 PM PST 24 | Feb 07 01:19:19 PM PST 24 | 5418800000 ps | ||
| T27 | /workspace/coverage/default/35.prim_present_test.2070874190 | Feb 07 01:18:50 PM PST 24 | Feb 07 01:20:12 PM PST 24 | 9557920000 ps | ||
| T28 | /workspace/coverage/default/47.prim_present_test.2239505370 | Feb 07 01:19:04 PM PST 24 | Feb 07 01:20:45 PM PST 24 | 14966800000 ps | ||
| T29 | /workspace/coverage/default/2.prim_present_test.2961294152 | Feb 07 01:17:45 PM PST 24 | Feb 07 01:19:27 PM PST 24 | 13943180000 ps | ||
| T30 | /workspace/coverage/default/12.prim_present_test.874410420 | Feb 07 01:18:39 PM PST 24 | Feb 07 01:20:04 PM PST 24 | 10178540000 ps | ||
| T31 | /workspace/coverage/default/11.prim_present_test.2178734453 | Feb 07 01:18:39 PM PST 24 | Feb 07 01:20:02 PM PST 24 | 9869160000 ps | ||
| T32 | /workspace/coverage/default/5.prim_present_test.1679823449 | Feb 07 01:18:38 PM PST 24 | Feb 07 01:20:03 PM PST 24 | 14571240000 ps | ||
| T33 | /workspace/coverage/default/44.prim_present_test.2434729248 | Feb 07 01:18:55 PM PST 24 | Feb 07 01:19:42 PM PST 24 | 5488860000 ps | ||
| T34 | /workspace/coverage/default/21.prim_present_test.719526263 | Feb 07 01:18:41 PM PST 24 | Feb 07 01:20:13 PM PST 24 | 12444640000 ps | ||
| T35 | /workspace/coverage/default/17.prim_present_test.3736190518 | Feb 07 01:18:42 PM PST 24 | Feb 07 01:20:33 PM PST 24 | 14365400000 ps | ||
| T36 | /workspace/coverage/default/10.prim_present_test.3169260988 | Feb 07 01:18:40 PM PST 24 | Feb 07 01:19:52 PM PST 24 | 8321640000 ps | ||
| T37 | /workspace/coverage/default/49.prim_present_test.1591583785 | Feb 07 01:19:05 PM PST 24 | Feb 07 01:19:46 PM PST 24 | 5775300000 ps | ||
| T38 | /workspace/coverage/default/24.prim_present_test.3119205793 | Feb 07 01:18:41 PM PST 24 | Feb 07 01:19:10 PM PST 24 | 4216620000 ps | ||
| T39 | /workspace/coverage/default/46.prim_present_test.2354654672 | Feb 07 01:18:50 PM PST 24 | Feb 07 01:19:58 PM PST 24 | 8743860000 ps | ||
| T40 | /workspace/coverage/default/34.prim_present_test.1013018580 | Feb 07 01:18:52 PM PST 24 | Feb 07 01:19:32 PM PST 24 | 4873820000 ps | ||
| T41 | /workspace/coverage/default/16.prim_present_test.820889567 | Feb 07 01:18:40 PM PST 24 | Feb 07 01:19:16 PM PST 24 | 4532200000 ps | ||
| T42 | /workspace/coverage/default/19.prim_present_test.253295001 | Feb 07 01:18:41 PM PST 24 | Feb 07 01:20:28 PM PST 24 | 12954900000 ps | ||
| T43 | /workspace/coverage/default/45.prim_present_test.2159834636 | Feb 07 01:18:56 PM PST 24 | Feb 07 01:19:59 PM PST 24 | 9342160000 ps | ||
| T44 | /workspace/coverage/default/48.prim_present_test.3708607978 | Feb 07 01:19:05 PM PST 24 | Feb 07 01:19:53 PM PST 24 | 5462820000 ps | ||
| T45 | /workspace/coverage/default/27.prim_present_test.698973310 | Feb 07 01:18:40 PM PST 24 | Feb 07 01:20:41 PM PST 24 | 14583640000 ps | ||
| T46 | /workspace/coverage/default/1.prim_present_test.1190191050 | Feb 07 01:17:46 PM PST 24 | Feb 07 01:18:47 PM PST 24 | 7521840000 ps | ||
| T47 | /workspace/coverage/default/22.prim_present_test.3239170057 | Feb 07 01:18:40 PM PST 24 | Feb 07 01:19:10 PM PST 24 | 4271800000 ps | ||
| T48 | /workspace/coverage/default/38.prim_present_test.650414534 | Feb 07 01:18:58 PM PST 24 | Feb 07 01:20:20 PM PST 24 | 10449480000 ps | ||
| T49 | /workspace/coverage/default/43.prim_present_test.4046373786 | Feb 07 01:18:51 PM PST 24 | Feb 07 01:20:35 PM PST 24 | 14111200000 ps | ||
| T50 | /workspace/coverage/default/32.prim_present_test.779475855 | Feb 07 01:18:44 PM PST 24 | Feb 07 01:19:51 PM PST 24 | 10194040000 ps |
| Test location | /workspace/coverage/default/0.prim_present_test.481434860 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 8381780000 ps |
| CPU time | 24.68 seconds |
| Started | Feb 07 01:17:49 PM PST 24 |
| Finished | Feb 07 01:18:38 PM PST 24 |
| Peak memory | 145708 kb |
| Host | smart-d0b87a18-3be9-4d96-8e06-5e0269b86d56 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=481434860 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.481434860 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/1.prim_present_test.1190191050 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 7521840000 ps |
| CPU time | 29.25 seconds |
| Started | Feb 07 01:17:46 PM PST 24 |
| Finished | Feb 07 01:18:47 PM PST 24 |
| Peak memory | 145672 kb |
| Host | smart-58702a80-23bc-49f4-9784-4af1ac3e6f14 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1190191050 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.1190191050 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/10.prim_present_test.3169260988 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 8321640000 ps |
| CPU time | 36.57 seconds |
| Started | Feb 07 01:18:40 PM PST 24 |
| Finished | Feb 07 01:19:52 PM PST 24 |
| Peak memory | 145640 kb |
| Host | smart-994ab36a-29f0-43af-b376-2c5fc7092f6b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3169260988 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.3169260988 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/11.prim_present_test.2178734453 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 9869160000 ps |
| CPU time | 42.21 seconds |
| Started | Feb 07 01:18:39 PM PST 24 |
| Finished | Feb 07 01:20:02 PM PST 24 |
| Peak memory | 145640 kb |
| Host | smart-bfe5ef63-9da9-4ac0-872f-8254ebb3d36b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2178734453 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.2178734453 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.874410420 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 10178540000 ps |
| CPU time | 40.91 seconds |
| Started | Feb 07 01:18:39 PM PST 24 |
| Finished | Feb 07 01:20:04 PM PST 24 |
| Peak memory | 145620 kb |
| Host | smart-072e11cc-69bb-48a2-9839-60626bdc6c8d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=874410420 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.874410420 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.2282174434 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 9584580000 ps |
| CPU time | 39.09 seconds |
| Started | Feb 07 01:18:39 PM PST 24 |
| Finished | Feb 07 01:19:59 PM PST 24 |
| Peak memory | 145620 kb |
| Host | smart-b38afb94-570d-4818-83d5-7aa5f8afc93c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2282174434 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.2282174434 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.383567626 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 11487360000 ps |
| CPU time | 54.33 seconds |
| Started | Feb 07 01:18:39 PM PST 24 |
| Finished | Feb 07 01:20:30 PM PST 24 |
| Peak memory | 145708 kb |
| Host | smart-95171274-9465-4f56-b184-e1a419f8ac57 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=383567626 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.383567626 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.2752468191 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 9174760000 ps |
| CPU time | 39.03 seconds |
| Started | Feb 07 01:18:40 PM PST 24 |
| Finished | Feb 07 01:19:55 PM PST 24 |
| Peak memory | 145680 kb |
| Host | smart-e31d996f-5d5f-4fee-9879-cb2e120faad8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2752468191 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.2752468191 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.820889567 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 4532200000 ps |
| CPU time | 18.72 seconds |
| Started | Feb 07 01:18:40 PM PST 24 |
| Finished | Feb 07 01:19:16 PM PST 24 |
| Peak memory | 145636 kb |
| Host | smart-7220f807-b22e-4b72-b492-3a7707bdce6c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=820889567 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.820889567 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.3736190518 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 14365400000 ps |
| CPU time | 57.76 seconds |
| Started | Feb 07 01:18:42 PM PST 24 |
| Finished | Feb 07 01:20:33 PM PST 24 |
| Peak memory | 145652 kb |
| Host | smart-eb46bb2a-8ab0-4477-8c06-e900b3f6fbb1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3736190518 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.3736190518 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.2723251085 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 5696560000 ps |
| CPU time | 25.22 seconds |
| Started | Feb 07 01:18:41 PM PST 24 |
| Finished | Feb 07 01:19:31 PM PST 24 |
| Peak memory | 145632 kb |
| Host | smart-51576407-f137-42ef-a5cd-5012279a6343 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2723251085 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.2723251085 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.253295001 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 12954900000 ps |
| CPU time | 53.55 seconds |
| Started | Feb 07 01:18:41 PM PST 24 |
| Finished | Feb 07 01:20:28 PM PST 24 |
| Peak memory | 145624 kb |
| Host | smart-3162ed94-3a95-4bfe-89f9-8ff10343b53a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=253295001 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.253295001 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.2961294152 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 13943180000 ps |
| CPU time | 50.92 seconds |
| Started | Feb 07 01:17:45 PM PST 24 |
| Finished | Feb 07 01:19:27 PM PST 24 |
| Peak memory | 145636 kb |
| Host | smart-5d07119c-e2d6-48e2-80c9-813baff02680 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2961294152 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.2961294152 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.4250920459 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 15224100000 ps |
| CPU time | 59.91 seconds |
| Started | Feb 07 01:18:42 PM PST 24 |
| Finished | Feb 07 01:20:40 PM PST 24 |
| Peak memory | 145632 kb |
| Host | smart-c9eebc64-0aac-4377-9d71-5750ef99d31b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4250920459 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.4250920459 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.719526263 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 12444640000 ps |
| CPU time | 46.88 seconds |
| Started | Feb 07 01:18:41 PM PST 24 |
| Finished | Feb 07 01:20:13 PM PST 24 |
| Peak memory | 145664 kb |
| Host | smart-910f76a0-9550-4e00-a576-d9c1e1dde338 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=719526263 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.719526263 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.3239170057 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 4271800000 ps |
| CPU time | 15.68 seconds |
| Started | Feb 07 01:18:40 PM PST 24 |
| Finished | Feb 07 01:19:10 PM PST 24 |
| Peak memory | 145484 kb |
| Host | smart-f3885981-12cb-49e7-b06d-4d26536f6c1e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3239170057 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.3239170057 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.113951920 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 12263600000 ps |
| CPU time | 49.31 seconds |
| Started | Feb 07 01:18:41 PM PST 24 |
| Finished | Feb 07 01:20:17 PM PST 24 |
| Peak memory | 145652 kb |
| Host | smart-06a46822-3c61-43d4-aec3-e443a2eeae5f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=113951920 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.113951920 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.3119205793 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 4216620000 ps |
| CPU time | 14.96 seconds |
| Started | Feb 07 01:18:41 PM PST 24 |
| Finished | Feb 07 01:19:10 PM PST 24 |
| Peak memory | 145496 kb |
| Host | smart-855bcbd6-6aac-4a48-bf1e-915b786f1b24 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3119205793 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.3119205793 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.2993260861 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 11482400000 ps |
| CPU time | 45.26 seconds |
| Started | Feb 07 01:18:41 PM PST 24 |
| Finished | Feb 07 01:20:13 PM PST 24 |
| Peak memory | 145668 kb |
| Host | smart-2fc459d6-44c2-4410-999e-120033681f9d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2993260861 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.2993260861 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.1936892848 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 6046240000 ps |
| CPU time | 23.01 seconds |
| Started | Feb 07 01:18:40 PM PST 24 |
| Finished | Feb 07 01:19:27 PM PST 24 |
| Peak memory | 145664 kb |
| Host | smart-0d9e824c-5f96-448f-b8a5-c127e1e3485e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1936892848 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.1936892848 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.698973310 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 14583640000 ps |
| CPU time | 61.4 seconds |
| Started | Feb 07 01:18:40 PM PST 24 |
| Finished | Feb 07 01:20:41 PM PST 24 |
| Peak memory | 145660 kb |
| Host | smart-95d80812-e4bd-4721-b79e-4479f2c15f1d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=698973310 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.698973310 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.3515485217 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 6426300000 ps |
| CPU time | 27.49 seconds |
| Started | Feb 07 01:18:43 PM PST 24 |
| Finished | Feb 07 01:19:42 PM PST 24 |
| Peak memory | 145700 kb |
| Host | smart-ad152bac-7279-4a87-af32-e43e1c6ddc0e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3515485217 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.3515485217 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.1212002530 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 7173400000 ps |
| CPU time | 29.85 seconds |
| Started | Feb 07 01:18:43 PM PST 24 |
| Finished | Feb 07 01:19:46 PM PST 24 |
| Peak memory | 145724 kb |
| Host | smart-1240403c-56da-49fc-a317-2972e77fb3e4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1212002530 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.1212002530 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.1283032489 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 5400200000 ps |
| CPU time | 20.07 seconds |
| Started | Feb 07 01:18:40 PM PST 24 |
| Finished | Feb 07 01:19:18 PM PST 24 |
| Peak memory | 145692 kb |
| Host | smart-c926cf5a-9d83-48df-84be-338721afe8bd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1283032489 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.1283032489 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.1681800898 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 6410800000 ps |
| CPU time | 27.47 seconds |
| Started | Feb 07 01:18:43 PM PST 24 |
| Finished | Feb 07 01:19:41 PM PST 24 |
| Peak memory | 145724 kb |
| Host | smart-337ed856-a8fc-4ec1-bde3-1435eb300c66 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1681800898 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.1681800898 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.295615391 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 10672680000 ps |
| CPU time | 40.84 seconds |
| Started | Feb 07 01:18:42 PM PST 24 |
| Finished | Feb 07 01:19:58 PM PST 24 |
| Peak memory | 145700 kb |
| Host | smart-f8faa815-e3fd-4338-8ce1-2b9043f31e4f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=295615391 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.295615391 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.779475855 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 10194040000 ps |
| CPU time | 34.99 seconds |
| Started | Feb 07 01:18:44 PM PST 24 |
| Finished | Feb 07 01:19:51 PM PST 24 |
| Peak memory | 145672 kb |
| Host | smart-7ef70ca0-107d-4a53-8993-3b55346c185f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=779475855 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.779475855 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.3520419966 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 5418800000 ps |
| CPU time | 15.26 seconds |
| Started | Feb 07 01:18:51 PM PST 24 |
| Finished | Feb 07 01:19:19 PM PST 24 |
| Peak memory | 145660 kb |
| Host | smart-69fb56bb-a5cc-448e-a0e8-9b7e2f2f8c93 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3520419966 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.3520419966 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.1013018580 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 4873820000 ps |
| CPU time | 20.16 seconds |
| Started | Feb 07 01:18:52 PM PST 24 |
| Finished | Feb 07 01:19:32 PM PST 24 |
| Peak memory | 145652 kb |
| Host | smart-526bc282-5b84-41af-8783-70a7b8f37f64 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1013018580 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.1013018580 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.2070874190 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 9557920000 ps |
| CPU time | 42.44 seconds |
| Started | Feb 07 01:18:50 PM PST 24 |
| Finished | Feb 07 01:20:12 PM PST 24 |
| Peak memory | 145640 kb |
| Host | smart-2e417985-5fee-4726-aa7e-2483743860e4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2070874190 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.2070874190 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.923037269 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 12101160000 ps |
| CPU time | 50.17 seconds |
| Started | Feb 07 01:18:51 PM PST 24 |
| Finished | Feb 07 01:20:31 PM PST 24 |
| Peak memory | 145672 kb |
| Host | smart-b278c9b5-c970-4b7a-863a-7e05321d8955 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=923037269 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.923037269 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.14239162 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 3488120000 ps |
| CPU time | 10.14 seconds |
| Started | Feb 07 01:18:54 PM PST 24 |
| Finished | Feb 07 01:19:13 PM PST 24 |
| Peak memory | 145536 kb |
| Host | smart-0f8ce8ab-b9be-4dc0-9534-af955502e340 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=14239162 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.14239162 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.650414534 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 10449480000 ps |
| CPU time | 41.53 seconds |
| Started | Feb 07 01:18:58 PM PST 24 |
| Finished | Feb 07 01:20:20 PM PST 24 |
| Peak memory | 145676 kb |
| Host | smart-a1e64623-6691-4944-997d-8b60c5657f9b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=650414534 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.650414534 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.1521368963 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 13328140000 ps |
| CPU time | 48.04 seconds |
| Started | Feb 07 01:18:52 PM PST 24 |
| Finished | Feb 07 01:20:30 PM PST 24 |
| Peak memory | 145644 kb |
| Host | smart-96d26e67-725b-45f5-b042-e9a7c4cd0a0e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1521368963 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.1521368963 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.4144075642 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 9942940000 ps |
| CPU time | 31.39 seconds |
| Started | Feb 07 01:18:38 PM PST 24 |
| Finished | Feb 07 01:19:38 PM PST 24 |
| Peak memory | 145664 kb |
| Host | smart-71872ea2-1193-4556-a501-fbb5acb689a5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4144075642 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.4144075642 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.408496806 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 9582100000 ps |
| CPU time | 38.63 seconds |
| Started | Feb 07 01:18:51 PM PST 24 |
| Finished | Feb 07 01:20:11 PM PST 24 |
| Peak memory | 145672 kb |
| Host | smart-c6601548-21a2-4642-aa77-a1a3bbdb5b7d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=408496806 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.408496806 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.386544510 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 9148100000 ps |
| CPU time | 37.19 seconds |
| Started | Feb 07 01:18:52 PM PST 24 |
| Finished | Feb 07 01:20:09 PM PST 24 |
| Peak memory | 145672 kb |
| Host | smart-a0d3a64e-1a51-481e-ab18-388a5b81f533 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=386544510 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.386544510 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.313016781 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 7297400000 ps |
| CPU time | 30.6 seconds |
| Started | Feb 07 01:18:58 PM PST 24 |
| Finished | Feb 07 01:19:59 PM PST 24 |
| Peak memory | 145672 kb |
| Host | smart-a3452f0d-8ebb-4102-bcf8-c6146adbcdf8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=313016781 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.313016781 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.4046373786 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 14111200000 ps |
| CPU time | 51.54 seconds |
| Started | Feb 07 01:18:51 PM PST 24 |
| Finished | Feb 07 01:20:35 PM PST 24 |
| Peak memory | 145644 kb |
| Host | smart-18346f4e-8501-46ed-90bf-30e78fdec590 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4046373786 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.4046373786 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.2434729248 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 5488860000 ps |
| CPU time | 23.15 seconds |
| Started | Feb 07 01:18:55 PM PST 24 |
| Finished | Feb 07 01:19:42 PM PST 24 |
| Peak memory | 145668 kb |
| Host | smart-da81d5ac-6ab5-4916-9e45-756d51a453e8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2434729248 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.2434729248 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.2159834636 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 9342160000 ps |
| CPU time | 32.96 seconds |
| Started | Feb 07 01:18:56 PM PST 24 |
| Finished | Feb 07 01:19:59 PM PST 24 |
| Peak memory | 145628 kb |
| Host | smart-569a4ded-12ff-4a0e-aa20-fb8e18e27348 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2159834636 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.2159834636 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.2354654672 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 8743860000 ps |
| CPU time | 32.44 seconds |
| Started | Feb 07 01:18:50 PM PST 24 |
| Finished | Feb 07 01:19:58 PM PST 24 |
| Peak memory | 145644 kb |
| Host | smart-60fce8bc-3829-4c24-b259-16751aa7a6f1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2354654672 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.2354654672 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.2239505370 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 14966800000 ps |
| CPU time | 53.58 seconds |
| Started | Feb 07 01:19:04 PM PST 24 |
| Finished | Feb 07 01:20:45 PM PST 24 |
| Peak memory | 145672 kb |
| Host | smart-a30da6dc-6db3-4329-a2d1-f6de8f214392 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2239505370 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.2239505370 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.3708607978 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 5462820000 ps |
| CPU time | 25.79 seconds |
| Started | Feb 07 01:19:05 PM PST 24 |
| Finished | Feb 07 01:19:53 PM PST 24 |
| Peak memory | 145716 kb |
| Host | smart-676c8e10-b918-4816-a7da-1a5a5ab472e6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3708607978 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.3708607978 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.1591583785 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 5775300000 ps |
| CPU time | 21.08 seconds |
| Started | Feb 07 01:19:05 PM PST 24 |
| Finished | Feb 07 01:19:46 PM PST 24 |
| Peak memory | 145716 kb |
| Host | smart-3e858d4b-b9e9-4792-83bf-682daa2bda9d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1591583785 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.1591583785 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.1679823449 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 14571240000 ps |
| CPU time | 44.69 seconds |
| Started | Feb 07 01:18:38 PM PST 24 |
| Finished | Feb 07 01:20:03 PM PST 24 |
| Peak memory | 145660 kb |
| Host | smart-28074939-a14f-425a-9c34-ef626f0068dd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1679823449 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.1679823449 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.2114919089 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 6751800000 ps |
| CPU time | 27.04 seconds |
| Started | Feb 07 01:18:40 PM PST 24 |
| Finished | Feb 07 01:19:33 PM PST 24 |
| Peak memory | 145652 kb |
| Host | smart-a1c8bdee-f38b-48c2-ab2f-04ab6a27246f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2114919089 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.2114919089 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.2719568473 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 13917140000 ps |
| CPU time | 45.91 seconds |
| Started | Feb 07 01:18:38 PM PST 24 |
| Finished | Feb 07 01:20:05 PM PST 24 |
| Peak memory | 145656 kb |
| Host | smart-69bf8c6a-c274-4bab-a0b8-64c3b007d46d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2719568473 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.2719568473 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.1389543419 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 9726560000 ps |
| CPU time | 44.54 seconds |
| Started | Feb 07 01:18:38 PM PST 24 |
| Finished | Feb 07 01:20:04 PM PST 24 |
| Peak memory | 145636 kb |
| Host | smart-7e6bfbbc-0149-46cc-9d26-5c5161897d63 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1389543419 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.1389543419 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.1498568765 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 9812740000 ps |
| CPU time | 35.83 seconds |
| Started | Feb 07 01:18:39 PM PST 24 |
| Finished | Feb 07 01:19:49 PM PST 24 |
| Peak memory | 145652 kb |
| Host | smart-7f6084e4-2087-4e4e-ae96-45f879837ddd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1498568765 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.1498568765 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |