| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/11.prim_present_test.3223014903 | ||
| Name |
|---|
| /workspace/coverage/default/0.prim_present_test.90861074 |
| /workspace/coverage/default/1.prim_present_test.2825649533 |
| /workspace/coverage/default/10.prim_present_test.2258358610 |
| /workspace/coverage/default/12.prim_present_test.2915670683 |
| /workspace/coverage/default/13.prim_present_test.423044749 |
| /workspace/coverage/default/14.prim_present_test.123868154 |
| /workspace/coverage/default/15.prim_present_test.1393472418 |
| /workspace/coverage/default/16.prim_present_test.2607407902 |
| /workspace/coverage/default/17.prim_present_test.1528436734 |
| /workspace/coverage/default/18.prim_present_test.2198417165 |
| /workspace/coverage/default/19.prim_present_test.1565733509 |
| /workspace/coverage/default/2.prim_present_test.1817046318 |
| /workspace/coverage/default/20.prim_present_test.179892734 |
| /workspace/coverage/default/21.prim_present_test.2800262981 |
| /workspace/coverage/default/22.prim_present_test.2954770996 |
| /workspace/coverage/default/23.prim_present_test.3697104255 |
| /workspace/coverage/default/24.prim_present_test.776443714 |
| /workspace/coverage/default/25.prim_present_test.3779667658 |
| /workspace/coverage/default/26.prim_present_test.3134283418 |
| /workspace/coverage/default/27.prim_present_test.3638719741 |
| /workspace/coverage/default/28.prim_present_test.1763963998 |
| /workspace/coverage/default/29.prim_present_test.1867965379 |
| /workspace/coverage/default/3.prim_present_test.3103436217 |
| /workspace/coverage/default/30.prim_present_test.1521733808 |
| /workspace/coverage/default/31.prim_present_test.1342049051 |
| /workspace/coverage/default/32.prim_present_test.117619238 |
| /workspace/coverage/default/33.prim_present_test.1264650306 |
| /workspace/coverage/default/34.prim_present_test.1472317740 |
| /workspace/coverage/default/35.prim_present_test.3247399296 |
| /workspace/coverage/default/36.prim_present_test.164228151 |
| /workspace/coverage/default/37.prim_present_test.3165960672 |
| /workspace/coverage/default/38.prim_present_test.270090372 |
| /workspace/coverage/default/39.prim_present_test.82599164 |
| /workspace/coverage/default/4.prim_present_test.1160727917 |
| /workspace/coverage/default/40.prim_present_test.472241417 |
| /workspace/coverage/default/41.prim_present_test.3465502609 |
| /workspace/coverage/default/42.prim_present_test.2501186143 |
| /workspace/coverage/default/43.prim_present_test.1293356037 |
| /workspace/coverage/default/44.prim_present_test.1443318348 |
| /workspace/coverage/default/45.prim_present_test.2837470168 |
| /workspace/coverage/default/46.prim_present_test.2213110526 |
| /workspace/coverage/default/47.prim_present_test.1516747000 |
| /workspace/coverage/default/48.prim_present_test.363271242 |
| /workspace/coverage/default/49.prim_present_test.1465998203 |
| /workspace/coverage/default/5.prim_present_test.545329117 |
| /workspace/coverage/default/6.prim_present_test.1961928061 |
| /workspace/coverage/default/7.prim_present_test.3746214635 |
| /workspace/coverage/default/8.prim_present_test.2021797321 |
| /workspace/coverage/default/9.prim_present_test.2223065882 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/13.prim_present_test.423044749 | Feb 18 12:29:26 PM PST 24 | Feb 18 12:30:35 PM PST 24 | 9971460000 ps | ||
| T2 | /workspace/coverage/default/25.prim_present_test.3779667658 | Feb 18 12:29:41 PM PST 24 | Feb 18 12:30:10 PM PST 24 | 4357360000 ps | ||
| T3 | /workspace/coverage/default/33.prim_present_test.1264650306 | Feb 18 12:29:22 PM PST 24 | Feb 18 12:30:20 PM PST 24 | 7719620000 ps | ||
| T4 | /workspace/coverage/default/31.prim_present_test.1342049051 | Feb 18 12:29:36 PM PST 24 | Feb 18 12:31:12 PM PST 24 | 14025640000 ps | ||
| T5 | /workspace/coverage/default/16.prim_present_test.2607407902 | Feb 18 12:29:27 PM PST 24 | Feb 18 12:30:43 PM PST 24 | 9511420000 ps | ||
| T6 | /workspace/coverage/default/11.prim_present_test.3223014903 | Feb 18 12:29:32 PM PST 24 | Feb 18 12:31:32 PM PST 24 | 15276800000 ps | ||
| T7 | /workspace/coverage/default/20.prim_present_test.179892734 | Feb 18 12:29:35 PM PST 24 | Feb 18 12:30:58 PM PST 24 | 13199180000 ps | ||
| T8 | /workspace/coverage/default/5.prim_present_test.545329117 | Feb 18 12:29:31 PM PST 24 | Feb 18 12:30:49 PM PST 24 | 11618180000 ps | ||
| T9 | /workspace/coverage/default/6.prim_present_test.1961928061 | Feb 18 12:29:34 PM PST 24 | Feb 18 12:30:19 PM PST 24 | 5446700000 ps | ||
| T10 | /workspace/coverage/default/24.prim_present_test.776443714 | Feb 18 12:29:17 PM PST 24 | Feb 18 12:30:11 PM PST 24 | 7865320000 ps | ||
| T11 | /workspace/coverage/default/40.prim_present_test.472241417 | Feb 18 12:29:27 PM PST 24 | Feb 18 12:30:49 PM PST 24 | 11144500000 ps | ||
| T12 | /workspace/coverage/default/9.prim_present_test.2223065882 | Feb 18 12:29:23 PM PST 24 | Feb 18 12:30:53 PM PST 24 | 11221380000 ps | ||
| T13 | /workspace/coverage/default/44.prim_present_test.1443318348 | Feb 18 12:29:40 PM PST 24 | Feb 18 12:30:04 PM PST 24 | 3688380000 ps | ||
| T14 | /workspace/coverage/default/28.prim_present_test.1763963998 | Feb 18 12:29:35 PM PST 24 | Feb 18 12:30:04 PM PST 24 | 3310180000 ps | ||
| T15 | /workspace/coverage/default/10.prim_present_test.2258358610 | Feb 18 12:29:31 PM PST 24 | Feb 18 12:30:12 PM PST 24 | 7329640000 ps | ||
| T16 | /workspace/coverage/default/17.prim_present_test.1528436734 | Feb 18 12:29:27 PM PST 24 | Feb 18 12:29:54 PM PST 24 | 4720060000 ps | ||
| T17 | /workspace/coverage/default/2.prim_present_test.1817046318 | Feb 18 12:29:46 PM PST 24 | Feb 18 12:30:17 PM PST 24 | 4351160000 ps | ||
| T18 | /workspace/coverage/default/35.prim_present_test.3247399296 | Feb 18 12:29:28 PM PST 24 | Feb 18 12:30:23 PM PST 24 | 7678080000 ps | ||
| T19 | /workspace/coverage/default/47.prim_present_test.1516747000 | Feb 18 12:29:39 PM PST 24 | Feb 18 12:30:44 PM PST 24 | 11573540000 ps | ||
| T20 | /workspace/coverage/default/29.prim_present_test.1867965379 | Feb 18 12:29:39 PM PST 24 | Feb 18 12:30:25 PM PST 24 | 7298020000 ps | ||
| T21 | /workspace/coverage/default/30.prim_present_test.1521733808 | Feb 18 12:29:32 PM PST 24 | Feb 18 12:30:55 PM PST 24 | 13190500000 ps | ||
| T22 | /workspace/coverage/default/27.prim_present_test.3638719741 | Feb 18 12:29:33 PM PST 24 | Feb 18 12:30:09 PM PST 24 | 5388420000 ps | ||
| T23 | /workspace/coverage/default/26.prim_present_test.3134283418 | Feb 18 12:29:35 PM PST 24 | Feb 18 12:30:16 PM PST 24 | 6544100000 ps | ||
| T24 | /workspace/coverage/default/15.prim_present_test.1393472418 | Feb 18 12:29:38 PM PST 24 | Feb 18 12:30:24 PM PST 24 | 6260140000 ps | ||
| T25 | /workspace/coverage/default/3.prim_present_test.3103436217 | Feb 18 12:29:34 PM PST 24 | Feb 18 12:30:41 PM PST 24 | 8163540000 ps | ||
| T26 | /workspace/coverage/default/14.prim_present_test.123868154 | Feb 18 12:29:34 PM PST 24 | Feb 18 12:31:18 PM PST 24 | 13320700000 ps | ||
| T27 | /workspace/coverage/default/41.prim_present_test.3465502609 | Feb 18 12:29:39 PM PST 24 | Feb 18 12:31:07 PM PST 24 | 14405080000 ps | ||
| T28 | /workspace/coverage/default/12.prim_present_test.2915670683 | Feb 18 12:29:36 PM PST 24 | Feb 18 12:31:25 PM PST 24 | 14620220000 ps | ||
| T29 | /workspace/coverage/default/34.prim_present_test.1472317740 | Feb 18 12:29:36 PM PST 24 | Feb 18 12:31:07 PM PST 24 | 12966680000 ps | ||
| T30 | /workspace/coverage/default/36.prim_present_test.164228151 | Feb 18 12:29:32 PM PST 24 | Feb 18 12:31:16 PM PST 24 | 12919560000 ps | ||
| T31 | /workspace/coverage/default/42.prim_present_test.2501186143 | Feb 18 12:29:46 PM PST 24 | Feb 18 12:30:08 PM PST 24 | 3474480000 ps | ||
| T32 | /workspace/coverage/default/21.prim_present_test.2800262981 | Feb 18 12:29:22 PM PST 24 | Feb 18 12:31:11 PM PST 24 | 14694000000 ps | ||
| T33 | /workspace/coverage/default/22.prim_present_test.2954770996 | Feb 18 12:29:35 PM PST 24 | Feb 18 12:30:52 PM PST 24 | 13139040000 ps | ||
| T34 | /workspace/coverage/default/37.prim_present_test.3165960672 | Feb 18 12:29:36 PM PST 24 | Feb 18 12:30:21 PM PST 24 | 7335840000 ps | ||
| T35 | /workspace/coverage/default/8.prim_present_test.2021797321 | Feb 18 12:29:30 PM PST 24 | Feb 18 12:30:23 PM PST 24 | 6790860000 ps | ||
| T36 | /workspace/coverage/default/23.prim_present_test.3697104255 | Feb 18 12:29:36 PM PST 24 | Feb 18 12:31:13 PM PST 24 | 14308360000 ps | ||
| T37 | /workspace/coverage/default/19.prim_present_test.1565733509 | Feb 18 12:29:26 PM PST 24 | Feb 18 12:30:24 PM PST 24 | 8029620000 ps | ||
| T38 | /workspace/coverage/default/38.prim_present_test.270090372 | Feb 18 12:29:36 PM PST 24 | Feb 18 12:31:17 PM PST 24 | 13254360000 ps | ||
| T39 | /workspace/coverage/default/32.prim_present_test.117619238 | Feb 18 12:29:19 PM PST 24 | Feb 18 12:30:12 PM PST 24 | 9117720000 ps | ||
| T40 | /workspace/coverage/default/4.prim_present_test.1160727917 | Feb 18 12:29:38 PM PST 24 | Feb 18 12:31:11 PM PST 24 | 14612780000 ps | ||
| T41 | /workspace/coverage/default/7.prim_present_test.3746214635 | Feb 18 12:29:25 PM PST 24 | Feb 18 12:30:38 PM PST 24 | 10664000000 ps | ||
| T42 | /workspace/coverage/default/46.prim_present_test.2213110526 | Feb 18 12:29:34 PM PST 24 | Feb 18 12:30:08 PM PST 24 | 5160260000 ps | ||
| T43 | /workspace/coverage/default/39.prim_present_test.82599164 | Feb 18 12:29:47 PM PST 24 | Feb 18 12:31:15 PM PST 24 | 12569260000 ps | ||
| T44 | /workspace/coverage/default/48.prim_present_test.363271242 | Feb 18 12:31:21 PM PST 24 | Feb 18 12:31:56 PM PST 24 | 6865260000 ps | ||
| T45 | /workspace/coverage/default/43.prim_present_test.1293356037 | Feb 18 12:29:36 PM PST 24 | Feb 18 12:30:55 PM PST 24 | 13368440000 ps | ||
| T46 | /workspace/coverage/default/18.prim_present_test.2198417165 | Feb 18 12:29:32 PM PST 24 | Feb 18 12:31:12 PM PST 24 | 12349160000 ps | ||
| T47 | /workspace/coverage/default/45.prim_present_test.2837470168 | Feb 18 12:29:40 PM PST 24 | Feb 18 12:31:09 PM PST 24 | 13988440000 ps | ||
| T48 | /workspace/coverage/default/49.prim_present_test.1465998203 | Feb 18 12:29:35 PM PST 24 | Feb 18 12:30:22 PM PST 24 | 6447380000 ps | ||
| T49 | /workspace/coverage/default/1.prim_present_test.2825649533 | Feb 18 12:29:21 PM PST 24 | Feb 18 12:29:46 PM PST 24 | 3779520000 ps | ||
| T50 | /workspace/coverage/default/0.prim_present_test.90861074 | Feb 18 12:29:24 PM PST 24 | Feb 18 12:30:31 PM PST 24 | 9092300000 ps |
| Test location | /workspace/coverage/default/11.prim_present_test.3223014903 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 15276800000 ps |
| CPU time | 60.37 seconds |
| Started | Feb 18 12:29:32 PM PST 24 |
| Finished | Feb 18 12:31:32 PM PST 24 |
| Peak memory | 145560 kb |
| Host | smart-1604a8db-f5ab-4f5f-905f-e0d57778f589 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3223014903 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.3223014903 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/0.prim_present_test.90861074 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 9092300000 ps |
| CPU time | 34.74 seconds |
| Started | Feb 18 12:29:24 PM PST 24 |
| Finished | Feb 18 12:30:31 PM PST 24 |
| Peak memory | 145584 kb |
| Host | smart-bc2052ba-b7d2-4bbb-9773-c400bd08511e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=90861074 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.90861074 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/1.prim_present_test.2825649533 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 3779520000 ps |
| CPU time | 12.74 seconds |
| Started | Feb 18 12:29:21 PM PST 24 |
| Finished | Feb 18 12:29:46 PM PST 24 |
| Peak memory | 145344 kb |
| Host | smart-4d3b4ce3-e079-4231-a795-1e36fd106116 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2825649533 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.2825649533 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/10.prim_present_test.2258358610 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 7329640000 ps |
| CPU time | 21.32 seconds |
| Started | Feb 18 12:29:31 PM PST 24 |
| Finished | Feb 18 12:30:12 PM PST 24 |
| Peak memory | 145484 kb |
| Host | smart-4f894987-fde1-4ca8-ba23-c5353f6604f9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2258358610 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.2258358610 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.2915670683 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 14620220000 ps |
| CPU time | 54.81 seconds |
| Started | Feb 18 12:29:36 PM PST 24 |
| Finished | Feb 18 12:31:25 PM PST 24 |
| Peak memory | 145488 kb |
| Host | smart-4f9b4188-89f3-44e3-bf62-7a57d8235264 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2915670683 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.2915670683 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.423044749 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 9971460000 ps |
| CPU time | 36.42 seconds |
| Started | Feb 18 12:29:26 PM PST 24 |
| Finished | Feb 18 12:30:35 PM PST 24 |
| Peak memory | 144544 kb |
| Host | smart-d07d8bd5-b71f-405f-a53f-0e199c31777d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=423044749 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.423044749 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.123868154 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 13320700000 ps |
| CPU time | 52.13 seconds |
| Started | Feb 18 12:29:34 PM PST 24 |
| Finished | Feb 18 12:31:18 PM PST 24 |
| Peak memory | 144556 kb |
| Host | smart-541cd1be-dcfd-4d69-9b92-6839793021c7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=123868154 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.123868154 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.1393472418 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 6260140000 ps |
| CPU time | 23.42 seconds |
| Started | Feb 18 12:29:38 PM PST 24 |
| Finished | Feb 18 12:30:24 PM PST 24 |
| Peak memory | 145484 kb |
| Host | smart-3c2d68b4-42e6-41af-8dfe-60a56cc84b78 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1393472418 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.1393472418 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.2607407902 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 9511420000 ps |
| CPU time | 37.95 seconds |
| Started | Feb 18 12:29:27 PM PST 24 |
| Finished | Feb 18 12:30:43 PM PST 24 |
| Peak memory | 145560 kb |
| Host | smart-2fb10cdd-3409-4bab-9953-453332b9858a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2607407902 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.2607407902 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.1528436734 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 4720060000 ps |
| CPU time | 14 seconds |
| Started | Feb 18 12:29:27 PM PST 24 |
| Finished | Feb 18 12:29:54 PM PST 24 |
| Peak memory | 145520 kb |
| Host | smart-a1187d2a-ed40-4d50-a6c1-cb8963e94c74 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1528436734 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.1528436734 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.2198417165 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 12349160000 ps |
| CPU time | 51.13 seconds |
| Started | Feb 18 12:29:32 PM PST 24 |
| Finished | Feb 18 12:31:12 PM PST 24 |
| Peak memory | 145560 kb |
| Host | smart-1938136f-61d7-4722-a7c9-7cfe0c3e4f8e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2198417165 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.2198417165 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.1565733509 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 8029620000 ps |
| CPU time | 30.01 seconds |
| Started | Feb 18 12:29:26 PM PST 24 |
| Finished | Feb 18 12:30:24 PM PST 24 |
| Peak memory | 144760 kb |
| Host | smart-83e9b7df-293b-4c19-a06b-e97c33c98c61 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1565733509 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.1565733509 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.1817046318 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 4351160000 ps |
| CPU time | 15.65 seconds |
| Started | Feb 18 12:29:46 PM PST 24 |
| Finished | Feb 18 12:30:17 PM PST 24 |
| Peak memory | 145488 kb |
| Host | smart-f896c106-7703-4db0-8407-eb74d0488cf2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1817046318 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.1817046318 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.179892734 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 13199180000 ps |
| CPU time | 43.3 seconds |
| Started | Feb 18 12:29:35 PM PST 24 |
| Finished | Feb 18 12:30:58 PM PST 24 |
| Peak memory | 145528 kb |
| Host | smart-a33b1d75-1137-4e3d-8360-46f69d7e231c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=179892734 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.179892734 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.2800262981 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 14694000000 ps |
| CPU time | 56.76 seconds |
| Started | Feb 18 12:29:22 PM PST 24 |
| Finished | Feb 18 12:31:11 PM PST 24 |
| Peak memory | 145560 kb |
| Host | smart-410d2d83-1093-44c1-9c84-ef0faeccf0b8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2800262981 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.2800262981 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.2954770996 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 13139040000 ps |
| CPU time | 40.49 seconds |
| Started | Feb 18 12:29:35 PM PST 24 |
| Finished | Feb 18 12:30:52 PM PST 24 |
| Peak memory | 145488 kb |
| Host | smart-499dde2b-c398-4fb4-b8f6-e735efe99a2c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2954770996 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.2954770996 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.3697104255 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 14308360000 ps |
| CPU time | 49.65 seconds |
| Started | Feb 18 12:29:36 PM PST 24 |
| Finished | Feb 18 12:31:13 PM PST 24 |
| Peak memory | 145488 kb |
| Host | smart-d52d6d9b-9abd-4c29-9741-31af0c2ad249 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3697104255 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.3697104255 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.776443714 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 7865320000 ps |
| CPU time | 26.66 seconds |
| Started | Feb 18 12:29:17 PM PST 24 |
| Finished | Feb 18 12:30:11 PM PST 24 |
| Peak memory | 145488 kb |
| Host | smart-afe7de48-a3b9-4878-a695-270bb0f6335a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=776443714 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.776443714 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.3779667658 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 4357360000 ps |
| CPU time | 15.36 seconds |
| Started | Feb 18 12:29:41 PM PST 24 |
| Finished | Feb 18 12:30:10 PM PST 24 |
| Peak memory | 145520 kb |
| Host | smart-f7ef6e1a-844b-4808-bc2a-9e466d83f0fe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3779667658 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.3779667658 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.3134283418 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 6544100000 ps |
| CPU time | 20.95 seconds |
| Started | Feb 18 12:29:35 PM PST 24 |
| Finished | Feb 18 12:30:16 PM PST 24 |
| Peak memory | 145488 kb |
| Host | smart-43dad0d6-1be3-41d7-b406-8e18bc74f599 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3134283418 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.3134283418 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.3638719741 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 5388420000 ps |
| CPU time | 18.5 seconds |
| Started | Feb 18 12:29:33 PM PST 24 |
| Finished | Feb 18 12:30:09 PM PST 24 |
| Peak memory | 145484 kb |
| Host | smart-2925dc75-555e-48ee-addc-cb92bd12149b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3638719741 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.3638719741 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.1763963998 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 3310180000 ps |
| CPU time | 13.9 seconds |
| Started | Feb 18 12:29:35 PM PST 24 |
| Finished | Feb 18 12:30:04 PM PST 24 |
| Peak memory | 145408 kb |
| Host | smart-aa80e20d-2d5b-49ad-a44f-d4735d9cd32c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1763963998 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.1763963998 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.1867965379 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 7298020000 ps |
| CPU time | 23.69 seconds |
| Started | Feb 18 12:29:39 PM PST 24 |
| Finished | Feb 18 12:30:25 PM PST 24 |
| Peak memory | 145520 kb |
| Host | smart-d9ea7962-f5db-4ce2-854e-5618378bf362 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1867965379 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.1867965379 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.3103436217 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 8163540000 ps |
| CPU time | 32.92 seconds |
| Started | Feb 18 12:29:34 PM PST 24 |
| Finished | Feb 18 12:30:41 PM PST 24 |
| Peak memory | 144520 kb |
| Host | smart-686613e0-ae51-4188-82fb-1a86e754b15c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3103436217 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.3103436217 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.1521733808 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 13190500000 ps |
| CPU time | 43.88 seconds |
| Started | Feb 18 12:29:32 PM PST 24 |
| Finished | Feb 18 12:30:55 PM PST 24 |
| Peak memory | 145524 kb |
| Host | smart-189f1fd8-ee27-4b7d-a7a8-202ef40a67a3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1521733808 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.1521733808 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.1342049051 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 14025640000 ps |
| CPU time | 49.72 seconds |
| Started | Feb 18 12:29:36 PM PST 24 |
| Finished | Feb 18 12:31:12 PM PST 24 |
| Peak memory | 145484 kb |
| Host | smart-1728fe3f-d64d-4b69-b1c7-6a669b027e74 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1342049051 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.1342049051 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.117619238 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 9117720000 ps |
| CPU time | 27.12 seconds |
| Started | Feb 18 12:29:19 PM PST 24 |
| Finished | Feb 18 12:30:12 PM PST 24 |
| Peak memory | 145488 kb |
| Host | smart-467c275d-99e1-44f1-9753-f8b650be92b7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=117619238 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.117619238 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.1264650306 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 7719620000 ps |
| CPU time | 30.14 seconds |
| Started | Feb 18 12:29:22 PM PST 24 |
| Finished | Feb 18 12:30:20 PM PST 24 |
| Peak memory | 145580 kb |
| Host | smart-7de3631e-6f84-41c6-bb37-16f45de32688 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1264650306 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.1264650306 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.1472317740 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 12966680000 ps |
| CPU time | 46.61 seconds |
| Started | Feb 18 12:29:36 PM PST 24 |
| Finished | Feb 18 12:31:07 PM PST 24 |
| Peak memory | 145484 kb |
| Host | smart-4a9935a3-7544-4e56-9f51-29b6560f08b0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1472317740 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.1472317740 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.3247399296 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 7678080000 ps |
| CPU time | 27.79 seconds |
| Started | Feb 18 12:29:28 PM PST 24 |
| Finished | Feb 18 12:30:23 PM PST 24 |
| Peak memory | 145520 kb |
| Host | smart-1121d33f-7480-44d4-801a-f5a1cb424747 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3247399296 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.3247399296 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.164228151 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 12919560000 ps |
| CPU time | 52.14 seconds |
| Started | Feb 18 12:29:32 PM PST 24 |
| Finished | Feb 18 12:31:16 PM PST 24 |
| Peak memory | 145560 kb |
| Host | smart-9e2d823f-0926-491b-bc05-d63fb35e0155 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=164228151 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.164228151 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.3165960672 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 7335840000 ps |
| CPU time | 23.68 seconds |
| Started | Feb 18 12:29:36 PM PST 24 |
| Finished | Feb 18 12:30:21 PM PST 24 |
| Peak memory | 145488 kb |
| Host | smart-2a18d48f-38e3-4658-93c0-446a5d213b9e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3165960672 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.3165960672 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.270090372 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 13254360000 ps |
| CPU time | 50.71 seconds |
| Started | Feb 18 12:29:36 PM PST 24 |
| Finished | Feb 18 12:31:17 PM PST 24 |
| Peak memory | 145436 kb |
| Host | smart-cd7dad9c-12a4-4c7f-a2a4-1717652815d3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=270090372 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.270090372 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.82599164 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 12569260000 ps |
| CPU time | 44.84 seconds |
| Started | Feb 18 12:29:47 PM PST 24 |
| Finished | Feb 18 12:31:15 PM PST 24 |
| Peak memory | 145528 kb |
| Host | smart-34e8329d-2076-4453-9603-1ee57aa96e4e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=82599164 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.82599164 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.1160727917 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 14612780000 ps |
| CPU time | 48.16 seconds |
| Started | Feb 18 12:29:38 PM PST 24 |
| Finished | Feb 18 12:31:11 PM PST 24 |
| Peak memory | 145528 kb |
| Host | smart-1632becb-4bf7-40da-bcce-62b8391f9b1b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1160727917 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.1160727917 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.472241417 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 11144500000 ps |
| CPU time | 43.28 seconds |
| Started | Feb 18 12:29:27 PM PST 24 |
| Finished | Feb 18 12:30:49 PM PST 24 |
| Peak memory | 145564 kb |
| Host | smart-f71f9814-7431-4a35-9bde-16d21e55f6bd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=472241417 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.472241417 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.3465502609 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 14405080000 ps |
| CPU time | 45.83 seconds |
| Started | Feb 18 12:29:39 PM PST 24 |
| Finished | Feb 18 12:31:07 PM PST 24 |
| Peak memory | 145484 kb |
| Host | smart-efdcd547-ead9-4c4b-a94e-08653d91c6bb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3465502609 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.3465502609 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.2501186143 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 3474480000 ps |
| CPU time | 10.91 seconds |
| Started | Feb 18 12:29:46 PM PST 24 |
| Finished | Feb 18 12:30:08 PM PST 24 |
| Peak memory | 145376 kb |
| Host | smart-2c6622c9-6ccd-4c9e-b91c-668f31172c46 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2501186143 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.2501186143 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.1293356037 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 13368440000 ps |
| CPU time | 40.96 seconds |
| Started | Feb 18 12:29:36 PM PST 24 |
| Finished | Feb 18 12:30:55 PM PST 24 |
| Peak memory | 145484 kb |
| Host | smart-226b944a-702e-4478-a576-deee881954a7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1293356037 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.1293356037 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.1443318348 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 3688380000 ps |
| CPU time | 12.01 seconds |
| Started | Feb 18 12:29:40 PM PST 24 |
| Finished | Feb 18 12:30:04 PM PST 24 |
| Peak memory | 145372 kb |
| Host | smart-2f04a790-c289-4f00-9d4e-ed9a583a06ee |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1443318348 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.1443318348 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.2837470168 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 13988440000 ps |
| CPU time | 46.16 seconds |
| Started | Feb 18 12:29:40 PM PST 24 |
| Finished | Feb 18 12:31:09 PM PST 24 |
| Peak memory | 145528 kb |
| Host | smart-3ee7fec4-8868-497e-bda1-a06ddd0d74e0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2837470168 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.2837470168 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.2213110526 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 5160260000 ps |
| CPU time | 17.61 seconds |
| Started | Feb 18 12:29:34 PM PST 24 |
| Finished | Feb 18 12:30:08 PM PST 24 |
| Peak memory | 145484 kb |
| Host | smart-1eb70f56-c2ed-411d-a887-ffc9a0bb21a5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2213110526 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.2213110526 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.1516747000 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 11573540000 ps |
| CPU time | 34.7 seconds |
| Started | Feb 18 12:29:39 PM PST 24 |
| Finished | Feb 18 12:30:44 PM PST 24 |
| Peak memory | 145520 kb |
| Host | smart-87cb4d45-d0b8-41f4-b428-7cc8c122509a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1516747000 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.1516747000 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.363271242 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 6865260000 ps |
| CPU time | 18.17 seconds |
| Started | Feb 18 12:31:21 PM PST 24 |
| Finished | Feb 18 12:31:56 PM PST 24 |
| Peak memory | 145488 kb |
| Host | smart-9c8c0ad4-1681-4cb3-a1a3-7f32e36e6dd8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=363271242 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.363271242 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.1465998203 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 6447380000 ps |
| CPU time | 23.63 seconds |
| Started | Feb 18 12:29:35 PM PST 24 |
| Finished | Feb 18 12:30:22 PM PST 24 |
| Peak memory | 145524 kb |
| Host | smart-edfdd920-65be-42a1-bfbc-a87aa5395b4c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1465998203 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.1465998203 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.545329117 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 11618180000 ps |
| CPU time | 40.72 seconds |
| Started | Feb 18 12:29:31 PM PST 24 |
| Finished | Feb 18 12:30:49 PM PST 24 |
| Peak memory | 145452 kb |
| Host | smart-1651adbb-723e-44bb-a4a8-67b4918e3bf9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=545329117 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.545329117 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.1961928061 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 5446700000 ps |
| CPU time | 22.16 seconds |
| Started | Feb 18 12:29:34 PM PST 24 |
| Finished | Feb 18 12:30:19 PM PST 24 |
| Peak memory | 145452 kb |
| Host | smart-c6a35ad7-f2e1-46ed-9fcf-7685eecb62b7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1961928061 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.1961928061 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.3746214635 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 10664000000 ps |
| CPU time | 38.48 seconds |
| Started | Feb 18 12:29:25 PM PST 24 |
| Finished | Feb 18 12:30:38 PM PST 24 |
| Peak memory | 145456 kb |
| Host | smart-290a4285-339d-4960-80a9-6e32c5a7b870 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3746214635 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.3746214635 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.2021797321 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 6790860000 ps |
| CPU time | 26.4 seconds |
| Started | Feb 18 12:29:30 PM PST 24 |
| Finished | Feb 18 12:30:23 PM PST 24 |
| Peak memory | 145452 kb |
| Host | smart-de6e5c5d-1ac0-49f0-b864-c0432b2b0e24 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2021797321 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.2021797321 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.2223065882 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 11221380000 ps |
| CPU time | 46.12 seconds |
| Started | Feb 18 12:29:23 PM PST 24 |
| Finished | Feb 18 12:30:53 PM PST 24 |
| Peak memory | 145560 kb |
| Host | smart-7132f87b-9359-4586-a9ac-e4b38df8af0b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2223065882 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.2223065882 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |