| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/0.prim_present_test.2001746389 | ||
| Name |
|---|
| /workspace/coverage/default/1.prim_present_test.108218746 |
| /workspace/coverage/default/10.prim_present_test.2259962461 |
| /workspace/coverage/default/11.prim_present_test.684421817 |
| /workspace/coverage/default/12.prim_present_test.36636898 |
| /workspace/coverage/default/13.prim_present_test.2992539024 |
| /workspace/coverage/default/14.prim_present_test.819418346 |
| /workspace/coverage/default/15.prim_present_test.298564289 |
| /workspace/coverage/default/16.prim_present_test.907854778 |
| /workspace/coverage/default/17.prim_present_test.1177118011 |
| /workspace/coverage/default/18.prim_present_test.1580672428 |
| /workspace/coverage/default/19.prim_present_test.3428548238 |
| /workspace/coverage/default/2.prim_present_test.3411809402 |
| /workspace/coverage/default/20.prim_present_test.3002945141 |
| /workspace/coverage/default/21.prim_present_test.4102572742 |
| /workspace/coverage/default/22.prim_present_test.3929655158 |
| /workspace/coverage/default/23.prim_present_test.1964115945 |
| /workspace/coverage/default/24.prim_present_test.2597248112 |
| /workspace/coverage/default/25.prim_present_test.1403128850 |
| /workspace/coverage/default/26.prim_present_test.2233116488 |
| /workspace/coverage/default/27.prim_present_test.3932343093 |
| /workspace/coverage/default/28.prim_present_test.2428118439 |
| /workspace/coverage/default/29.prim_present_test.4274233603 |
| /workspace/coverage/default/3.prim_present_test.198869188 |
| /workspace/coverage/default/30.prim_present_test.1598511830 |
| /workspace/coverage/default/31.prim_present_test.2061981972 |
| /workspace/coverage/default/32.prim_present_test.2554437993 |
| /workspace/coverage/default/33.prim_present_test.2215370346 |
| /workspace/coverage/default/34.prim_present_test.401464036 |
| /workspace/coverage/default/35.prim_present_test.3640937924 |
| /workspace/coverage/default/36.prim_present_test.2442519321 |
| /workspace/coverage/default/37.prim_present_test.3429709293 |
| /workspace/coverage/default/38.prim_present_test.2419244737 |
| /workspace/coverage/default/39.prim_present_test.4066983124 |
| /workspace/coverage/default/4.prim_present_test.3422012055 |
| /workspace/coverage/default/40.prim_present_test.1738173860 |
| /workspace/coverage/default/41.prim_present_test.1673441136 |
| /workspace/coverage/default/42.prim_present_test.628168294 |
| /workspace/coverage/default/43.prim_present_test.2386698194 |
| /workspace/coverage/default/44.prim_present_test.3625666283 |
| /workspace/coverage/default/45.prim_present_test.3660847682 |
| /workspace/coverage/default/46.prim_present_test.2920348561 |
| /workspace/coverage/default/47.prim_present_test.2703671444 |
| /workspace/coverage/default/48.prim_present_test.2092709571 |
| /workspace/coverage/default/49.prim_present_test.3337372888 |
| /workspace/coverage/default/5.prim_present_test.3959645534 |
| /workspace/coverage/default/6.prim_present_test.3988048231 |
| /workspace/coverage/default/7.prim_present_test.1607092246 |
| /workspace/coverage/default/8.prim_present_test.2528743733 |
| /workspace/coverage/default/9.prim_present_test.2088069913 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/10.prim_present_test.2259962461 | Feb 21 12:24:13 PM PST 24 | Feb 21 12:25:24 PM PST 24 | 9775540000 ps | ||
| T2 | /workspace/coverage/default/48.prim_present_test.2092709571 | Feb 21 12:26:11 PM PST 24 | Feb 21 12:27:36 PM PST 24 | 14951920000 ps | ||
| T3 | /workspace/coverage/default/15.prim_present_test.298564289 | Feb 21 12:27:19 PM PST 24 | Feb 21 12:27:44 PM PST 24 | 5351840000 ps | ||
| T4 | /workspace/coverage/default/0.prim_present_test.2001746389 | Feb 21 12:29:52 PM PST 24 | Feb 21 12:31:13 PM PST 24 | 12866240000 ps | ||
| T5 | /workspace/coverage/default/25.prim_present_test.1403128850 | Feb 21 12:25:49 PM PST 24 | Feb 21 12:26:59 PM PST 24 | 12319400000 ps | ||
| T6 | /workspace/coverage/default/12.prim_present_test.36636898 | Feb 21 12:31:46 PM PST 24 | Feb 21 12:33:18 PM PST 24 | 15054840000 ps | ||
| T7 | /workspace/coverage/default/23.prim_present_test.1964115945 | Feb 21 12:24:13 PM PST 24 | Feb 21 12:25:13 PM PST 24 | 8130680000 ps | ||
| T8 | /workspace/coverage/default/14.prim_present_test.819418346 | Feb 21 12:26:14 PM PST 24 | Feb 21 12:26:43 PM PST 24 | 4354880000 ps | ||
| T9 | /workspace/coverage/default/16.prim_present_test.907854778 | Feb 21 12:30:01 PM PST 24 | Feb 21 12:30:49 PM PST 24 | 7207500000 ps | ||
| T10 | /workspace/coverage/default/8.prim_present_test.2528743733 | Feb 21 12:24:12 PM PST 24 | Feb 21 12:25:16 PM PST 24 | 8631640000 ps | ||
| T11 | /workspace/coverage/default/1.prim_present_test.108218746 | Feb 21 12:31:46 PM PST 24 | Feb 21 12:32:29 PM PST 24 | 6458540000 ps | ||
| T12 | /workspace/coverage/default/2.prim_present_test.3411809402 | Feb 21 12:26:51 PM PST 24 | Feb 21 12:27:42 PM PST 24 | 8658300000 ps | ||
| T13 | /workspace/coverage/default/36.prim_present_test.2442519321 | Feb 21 12:30:01 PM PST 24 | Feb 21 12:30:48 PM PST 24 | 7043820000 ps | ||
| T14 | /workspace/coverage/default/42.prim_present_test.628168294 | Feb 21 12:23:51 PM PST 24 | Feb 21 12:25:32 PM PST 24 | 13722460000 ps | ||
| T15 | /workspace/coverage/default/6.prim_present_test.3988048231 | Feb 21 12:24:04 PM PST 24 | Feb 21 12:25:29 PM PST 24 | 12047840000 ps | ||
| T16 | /workspace/coverage/default/21.prim_present_test.4102572742 | Feb 21 12:27:27 PM PST 24 | Feb 21 12:28:33 PM PST 24 | 10562940000 ps | ||
| T17 | /workspace/coverage/default/5.prim_present_test.3959645534 | Feb 21 12:22:03 PM PST 24 | Feb 21 12:22:39 PM PST 24 | 4669220000 ps | ||
| T18 | /workspace/coverage/default/7.prim_present_test.1607092246 | Feb 21 12:24:14 PM PST 24 | Feb 21 12:25:05 PM PST 24 | 6827440000 ps | ||
| T19 | /workspace/coverage/default/38.prim_present_test.2419244737 | Feb 21 12:24:13 PM PST 24 | Feb 21 12:25:11 PM PST 24 | 7010960000 ps | ||
| T20 | /workspace/coverage/default/37.prim_present_test.3429709293 | Feb 21 12:24:14 PM PST 24 | Feb 21 12:25:26 PM PST 24 | 9758180000 ps | ||
| T21 | /workspace/coverage/default/4.prim_present_test.3422012055 | Feb 21 12:26:06 PM PST 24 | Feb 21 12:27:45 PM PST 24 | 13388900000 ps | ||
| T22 | /workspace/coverage/default/18.prim_present_test.1580672428 | Feb 21 12:25:59 PM PST 24 | Feb 21 12:26:40 PM PST 24 | 6656940000 ps | ||
| T23 | /workspace/coverage/default/35.prim_present_test.3640937924 | Feb 21 12:29:19 PM PST 24 | Feb 21 12:29:40 PM PST 24 | 3458360000 ps | ||
| T24 | /workspace/coverage/default/32.prim_present_test.2554437993 | Feb 21 12:25:59 PM PST 24 | Feb 21 12:27:31 PM PST 24 | 15441720000 ps | ||
| T25 | /workspace/coverage/default/26.prim_present_test.2233116488 | Feb 21 12:29:37 PM PST 24 | Feb 21 12:30:42 PM PST 24 | 9660220000 ps | ||
| T26 | /workspace/coverage/default/9.prim_present_test.2088069913 | Feb 21 12:26:10 PM PST 24 | Feb 21 12:26:41 PM PST 24 | 4925280000 ps | ||
| T27 | /workspace/coverage/default/27.prim_present_test.3932343093 | Feb 21 12:24:13 PM PST 24 | Feb 21 12:25:46 PM PST 24 | 12828420000 ps | ||
| T28 | /workspace/coverage/default/39.prim_present_test.4066983124 | Feb 21 12:24:13 PM PST 24 | Feb 21 12:25:22 PM PST 24 | 9298140000 ps | ||
| T29 | /workspace/coverage/default/11.prim_present_test.684421817 | Feb 21 12:24:14 PM PST 24 | Feb 21 12:25:50 PM PST 24 | 13600320000 ps | ||
| T30 | /workspace/coverage/default/46.prim_present_test.2920348561 | Feb 21 12:27:26 PM PST 24 | Feb 21 12:27:56 PM PST 24 | 4986660000 ps | ||
| T31 | /workspace/coverage/default/41.prim_present_test.1673441136 | Feb 21 12:30:01 PM PST 24 | Feb 21 12:30:37 PM PST 24 | 5413220000 ps | ||
| T32 | /workspace/coverage/default/49.prim_present_test.3337372888 | Feb 21 12:22:18 PM PST 24 | Feb 21 12:23:46 PM PST 24 | 11752100000 ps | ||
| T33 | /workspace/coverage/default/34.prim_present_test.401464036 | Feb 21 12:26:40 PM PST 24 | Feb 21 12:27:03 PM PST 24 | 3111780000 ps | ||
| T34 | /workspace/coverage/default/13.prim_present_test.2992539024 | Feb 21 12:22:18 PM PST 24 | Feb 21 12:22:48 PM PST 24 | 3855780000 ps | ||
| T35 | /workspace/coverage/default/33.prim_present_test.2215370346 | Feb 21 12:24:30 PM PST 24 | Feb 21 12:25:05 PM PST 24 | 4343100000 ps | ||
| T36 | /workspace/coverage/default/19.prim_present_test.3428548238 | Feb 21 12:26:40 PM PST 24 | Feb 21 12:27:16 PM PST 24 | 5411980000 ps | ||
| T37 | /workspace/coverage/default/40.prim_present_test.1738173860 | Feb 21 12:22:13 PM PST 24 | Feb 21 12:22:50 PM PST 24 | 5183200000 ps | ||
| T38 | /workspace/coverage/default/24.prim_present_test.2597248112 | Feb 21 12:26:13 PM PST 24 | Feb 21 12:26:42 PM PST 24 | 4371620000 ps | ||
| T39 | /workspace/coverage/default/28.prim_present_test.2428118439 | Feb 21 12:29:19 PM PST 24 | Feb 21 12:30:23 PM PST 24 | 10150020000 ps | ||
| T40 | /workspace/coverage/default/45.prim_present_test.3660847682 | Feb 21 12:24:14 PM PST 24 | Feb 21 12:25:30 PM PST 24 | 10514580000 ps | ||
| T41 | /workspace/coverage/default/30.prim_present_test.1598511830 | Feb 21 12:26:13 PM PST 24 | Feb 21 12:26:39 PM PST 24 | 3909100000 ps | ||
| T42 | /workspace/coverage/default/3.prim_present_test.198869188 | Feb 21 12:25:07 PM PST 24 | Feb 21 12:26:50 PM PST 24 | 14760340000 ps | ||
| T43 | /workspace/coverage/default/43.prim_present_test.2386698194 | Feb 21 12:29:52 PM PST 24 | Feb 21 12:30:53 PM PST 24 | 9461200000 ps | ||
| T44 | /workspace/coverage/default/29.prim_present_test.4274233603 | Feb 21 12:22:05 PM PST 24 | Feb 21 12:22:52 PM PST 24 | 6831160000 ps | ||
| T45 | /workspace/coverage/default/31.prim_present_test.2061981972 | Feb 21 12:29:37 PM PST 24 | Feb 21 12:30:11 PM PST 24 | 4987900000 ps | ||
| T46 | /workspace/coverage/default/47.prim_present_test.2703671444 | Feb 21 12:22:18 PM PST 24 | Feb 21 12:23:28 PM PST 24 | 9432680000 ps | ||
| T47 | /workspace/coverage/default/20.prim_present_test.3002945141 | Feb 21 12:26:10 PM PST 24 | Feb 21 12:27:18 PM PST 24 | 11230680000 ps | ||
| T48 | /workspace/coverage/default/22.prim_present_test.3929655158 | Feb 21 12:30:01 PM PST 24 | Feb 21 12:30:23 PM PST 24 | 3222760000 ps | ||
| T49 | /workspace/coverage/default/44.prim_present_test.3625666283 | Feb 21 12:30:22 PM PST 24 | Feb 21 12:31:17 PM PST 24 | 8460520000 ps | ||
| T50 | /workspace/coverage/default/17.prim_present_test.1177118011 | Feb 21 12:24:12 PM PST 24 | Feb 21 12:25:50 PM PST 24 | 13538940000 ps |
| Test location | /workspace/coverage/default/0.prim_present_test.2001746389 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 12866240000 ps |
| CPU time | 43.78 seconds |
| Started | Feb 21 12:29:52 PM PST 24 |
| Finished | Feb 21 12:31:13 PM PST 24 |
| Peak memory | 144116 kb |
| Host | smart-c6c1ea2c-bbca-48f4-aaa5-228a1a3f54a9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2001746389 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.2001746389 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/1.prim_present_test.108218746 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 6458540000 ps |
| CPU time | 22.94 seconds |
| Started | Feb 21 12:31:46 PM PST 24 |
| Finished | Feb 21 12:32:29 PM PST 24 |
| Peak memory | 143736 kb |
| Host | smart-a169038c-f4a9-4e4f-8bd3-743eab1e981d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=108218746 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.108218746 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/10.prim_present_test.2259962461 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 9775540000 ps |
| CPU time | 37.35 seconds |
| Started | Feb 21 12:24:13 PM PST 24 |
| Finished | Feb 21 12:25:24 PM PST 24 |
| Peak memory | 145060 kb |
| Host | smart-03d74694-f156-4797-a179-91a650697a5e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2259962461 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.2259962461 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/11.prim_present_test.684421817 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 13600320000 ps |
| CPU time | 50.94 seconds |
| Started | Feb 21 12:24:14 PM PST 24 |
| Finished | Feb 21 12:25:50 PM PST 24 |
| Peak memory | 145060 kb |
| Host | smart-1bef7277-e369-47f7-a049-2c45f305c09a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=684421817 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.684421817 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.36636898 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 15054840000 ps |
| CPU time | 49.22 seconds |
| Started | Feb 21 12:31:46 PM PST 24 |
| Finished | Feb 21 12:33:18 PM PST 24 |
| Peak memory | 143380 kb |
| Host | smart-064ffa15-0f6b-4dfa-8f15-69b03d5f2974 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=36636898 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.36636898 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.2992539024 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 3855780000 ps |
| CPU time | 15.46 seconds |
| Started | Feb 21 12:22:18 PM PST 24 |
| Finished | Feb 21 12:22:48 PM PST 24 |
| Peak memory | 145324 kb |
| Host | smart-e01b37b2-368f-4be2-aa67-0af9e2f6c09e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2992539024 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.2992539024 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.819418346 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 4354880000 ps |
| CPU time | 15.81 seconds |
| Started | Feb 21 12:26:14 PM PST 24 |
| Finished | Feb 21 12:26:43 PM PST 24 |
| Peak memory | 145032 kb |
| Host | smart-feb655bd-ec77-49ae-a88e-248bfbbd9659 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=819418346 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.819418346 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.298564289 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 5351840000 ps |
| CPU time | 13.73 seconds |
| Started | Feb 21 12:27:19 PM PST 24 |
| Finished | Feb 21 12:27:44 PM PST 24 |
| Peak memory | 145752 kb |
| Host | smart-b6ea0560-7b38-440c-8c01-b08670de82a3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=298564289 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.298564289 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.907854778 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 7207500000 ps |
| CPU time | 25.33 seconds |
| Started | Feb 21 12:30:01 PM PST 24 |
| Finished | Feb 21 12:30:49 PM PST 24 |
| Peak memory | 145020 kb |
| Host | smart-17a206d1-971a-4091-ab4e-49a6620ddff7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=907854778 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.907854778 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.1177118011 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 13538940000 ps |
| CPU time | 51.63 seconds |
| Started | Feb 21 12:24:12 PM PST 24 |
| Finished | Feb 21 12:25:50 PM PST 24 |
| Peak memory | 145060 kb |
| Host | smart-e12b468e-5772-4dfd-b435-cfadf97b15b5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1177118011 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.1177118011 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.1580672428 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 6656940000 ps |
| CPU time | 21.76 seconds |
| Started | Feb 21 12:25:59 PM PST 24 |
| Finished | Feb 21 12:26:40 PM PST 24 |
| Peak memory | 144460 kb |
| Host | smart-df84211a-a27f-4ed0-9ac1-5c1bb922dd77 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1580672428 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.1580672428 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.3428548238 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 5411980000 ps |
| CPU time | 18.99 seconds |
| Started | Feb 21 12:26:40 PM PST 24 |
| Finished | Feb 21 12:27:16 PM PST 24 |
| Peak memory | 144448 kb |
| Host | smart-7d7fc70b-271e-4164-9bf5-bd8ddbb9f454 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3428548238 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.3428548238 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.3411809402 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 8658300000 ps |
| CPU time | 27.16 seconds |
| Started | Feb 21 12:26:51 PM PST 24 |
| Finished | Feb 21 12:27:42 PM PST 24 |
| Peak memory | 144384 kb |
| Host | smart-b765311f-631f-4ccc-8947-b3caef0d1397 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3411809402 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.3411809402 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.3002945141 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 11230680000 ps |
| CPU time | 36.96 seconds |
| Started | Feb 21 12:26:10 PM PST 24 |
| Finished | Feb 21 12:27:18 PM PST 24 |
| Peak memory | 145012 kb |
| Host | smart-3f49aeb5-2967-4ec4-bad9-9a042e6592f7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3002945141 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.3002945141 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.4102572742 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 10562940000 ps |
| CPU time | 35.87 seconds |
| Started | Feb 21 12:27:27 PM PST 24 |
| Finished | Feb 21 12:28:33 PM PST 24 |
| Peak memory | 144984 kb |
| Host | smart-164dd86a-f500-4947-810f-5bc5c27fe7f0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4102572742 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.4102572742 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.3929655158 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 3222760000 ps |
| CPU time | 11.59 seconds |
| Started | Feb 21 12:30:01 PM PST 24 |
| Finished | Feb 21 12:30:23 PM PST 24 |
| Peak memory | 146136 kb |
| Host | smart-6352d1ad-86e6-4d08-8dff-0d693acf481c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3929655158 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.3929655158 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.1964115945 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 8130680000 ps |
| CPU time | 31.17 seconds |
| Started | Feb 21 12:24:13 PM PST 24 |
| Finished | Feb 21 12:25:13 PM PST 24 |
| Peak memory | 145060 kb |
| Host | smart-6ab6d4eb-ed12-47b8-ae26-2cd3f0b1ef5f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1964115945 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.1964115945 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.2597248112 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 4371620000 ps |
| CPU time | 15.5 seconds |
| Started | Feb 21 12:26:13 PM PST 24 |
| Finished | Feb 21 12:26:42 PM PST 24 |
| Peak memory | 144968 kb |
| Host | smart-3fd197b0-ee34-4929-99b2-5c212d5c25ce |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2597248112 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.2597248112 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.1403128850 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 12319400000 ps |
| CPU time | 38.29 seconds |
| Started | Feb 21 12:25:49 PM PST 24 |
| Finished | Feb 21 12:26:59 PM PST 24 |
| Peak memory | 144448 kb |
| Host | smart-27d28534-5326-47f7-b9a3-85979929beec |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1403128850 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.1403128850 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.2233116488 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 9660220000 ps |
| CPU time | 34.63 seconds |
| Started | Feb 21 12:29:37 PM PST 24 |
| Finished | Feb 21 12:30:42 PM PST 24 |
| Peak memory | 145012 kb |
| Host | smart-1428b4b6-be92-4f75-b49e-c6aa9149bfa8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2233116488 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.2233116488 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.3932343093 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 12828420000 ps |
| CPU time | 49.35 seconds |
| Started | Feb 21 12:24:13 PM PST 24 |
| Finished | Feb 21 12:25:46 PM PST 24 |
| Peak memory | 145060 kb |
| Host | smart-578180a9-f5d5-409f-84c5-49d81afc32cf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3932343093 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.3932343093 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.2428118439 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 10150020000 ps |
| CPU time | 33.3 seconds |
| Started | Feb 21 12:29:19 PM PST 24 |
| Finished | Feb 21 12:30:23 PM PST 24 |
| Peak memory | 143960 kb |
| Host | smart-f519b8c4-7527-4039-bc31-eb98425277ca |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2428118439 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.2428118439 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.4274233603 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 6831160000 ps |
| CPU time | 24.85 seconds |
| Started | Feb 21 12:22:05 PM PST 24 |
| Finished | Feb 21 12:22:52 PM PST 24 |
| Peak memory | 145796 kb |
| Host | smart-488e337d-1009-4f52-9b12-21b846b40dd5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4274233603 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.4274233603 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.198869188 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 14760340000 ps |
| CPU time | 53.72 seconds |
| Started | Feb 21 12:25:07 PM PST 24 |
| Finished | Feb 21 12:26:50 PM PST 24 |
| Peak memory | 145540 kb |
| Host | smart-91e101b1-6345-4110-911a-e37335162974 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=198869188 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.198869188 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.1598511830 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 3909100000 ps |
| CPU time | 13.9 seconds |
| Started | Feb 21 12:26:13 PM PST 24 |
| Finished | Feb 21 12:26:39 PM PST 24 |
| Peak memory | 146156 kb |
| Host | smart-bf804de5-7e59-4a66-89c7-93a99457c47d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1598511830 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.1598511830 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.2061981972 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 4987900000 ps |
| CPU time | 18.44 seconds |
| Started | Feb 21 12:29:37 PM PST 24 |
| Finished | Feb 21 12:30:11 PM PST 24 |
| Peak memory | 145012 kb |
| Host | smart-70815687-f805-48d3-82bb-b764e82a725c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2061981972 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.2061981972 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.2554437993 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 15441720000 ps |
| CPU time | 50.53 seconds |
| Started | Feb 21 12:25:59 PM PST 24 |
| Finished | Feb 21 12:27:31 PM PST 24 |
| Peak memory | 143192 kb |
| Host | smart-3f77bffb-c969-4602-a38f-24d652c911f2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2554437993 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.2554437993 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.2215370346 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 4343100000 ps |
| CPU time | 17.72 seconds |
| Started | Feb 21 12:24:30 PM PST 24 |
| Finished | Feb 21 12:25:05 PM PST 24 |
| Peak memory | 145244 kb |
| Host | smart-6332898c-e849-4ae9-97ef-ddfbedda08d9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2215370346 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.2215370346 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.401464036 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 3111780000 ps |
| CPU time | 11.59 seconds |
| Started | Feb 21 12:26:40 PM PST 24 |
| Finished | Feb 21 12:27:03 PM PST 24 |
| Peak memory | 146112 kb |
| Host | smart-7cd91cbb-367d-44d3-98d9-8ab60ec8b29c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=401464036 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.401464036 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.3640937924 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 3458360000 ps |
| CPU time | 10.64 seconds |
| Started | Feb 21 12:29:19 PM PST 24 |
| Finished | Feb 21 12:29:40 PM PST 24 |
| Peak memory | 145100 kb |
| Host | smart-ad44ebb9-de5d-4a49-99c6-02fe51e8ee2d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3640937924 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.3640937924 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.2442519321 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 7043820000 ps |
| CPU time | 24.88 seconds |
| Started | Feb 21 12:30:01 PM PST 24 |
| Finished | Feb 21 12:30:48 PM PST 24 |
| Peak memory | 145024 kb |
| Host | smart-a230a18d-5bad-41d3-a021-5e91a73b08c9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2442519321 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.2442519321 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.3429709293 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 9758180000 ps |
| CPU time | 37.59 seconds |
| Started | Feb 21 12:24:14 PM PST 24 |
| Finished | Feb 21 12:25:26 PM PST 24 |
| Peak memory | 145060 kb |
| Host | smart-62bb0b09-7ef5-4c9a-a198-94eff476006f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3429709293 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.3429709293 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.2419244737 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 7010960000 ps |
| CPU time | 30.1 seconds |
| Started | Feb 21 12:24:13 PM PST 24 |
| Finished | Feb 21 12:25:11 PM PST 24 |
| Peak memory | 145796 kb |
| Host | smart-6d64d5db-8d45-4a4b-afed-81c4945a56bf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2419244737 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.2419244737 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.4066983124 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 9298140000 ps |
| CPU time | 37.01 seconds |
| Started | Feb 21 12:24:13 PM PST 24 |
| Finished | Feb 21 12:25:22 PM PST 24 |
| Peak memory | 145060 kb |
| Host | smart-3be27435-ce8d-4401-96c9-27fa3cdb44b8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4066983124 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.4066983124 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.3422012055 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 13388900000 ps |
| CPU time | 51 seconds |
| Started | Feb 21 12:26:06 PM PST 24 |
| Finished | Feb 21 12:27:45 PM PST 24 |
| Peak memory | 144412 kb |
| Host | smart-9c4b1c67-5a8f-492f-8f72-8687bcb66ea8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3422012055 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.3422012055 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.1738173860 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 5183200000 ps |
| CPU time | 19.29 seconds |
| Started | Feb 21 12:22:13 PM PST 24 |
| Finished | Feb 21 12:22:50 PM PST 24 |
| Peak memory | 145800 kb |
| Host | smart-ff242652-47c3-45dd-8455-38b2506abc36 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1738173860 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.1738173860 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.1673441136 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 5413220000 ps |
| CPU time | 18.78 seconds |
| Started | Feb 21 12:30:01 PM PST 24 |
| Finished | Feb 21 12:30:37 PM PST 24 |
| Peak memory | 145024 kb |
| Host | smart-51831e0c-4409-4d8d-aa9b-38814369d13e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1673441136 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.1673441136 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.628168294 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 13722460000 ps |
| CPU time | 53.11 seconds |
| Started | Feb 21 12:23:51 PM PST 24 |
| Finished | Feb 21 12:25:32 PM PST 24 |
| Peak memory | 145228 kb |
| Host | smart-71b06735-8b74-4215-96e6-676bec15bded |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=628168294 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.628168294 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.2386698194 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 9461200000 ps |
| CPU time | 32.6 seconds |
| Started | Feb 21 12:29:52 PM PST 24 |
| Finished | Feb 21 12:30:53 PM PST 24 |
| Peak memory | 144080 kb |
| Host | smart-264ba149-1dd9-419e-84b1-737dd7ebc5ac |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2386698194 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.2386698194 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.3625666283 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 8460520000 ps |
| CPU time | 29.27 seconds |
| Started | Feb 21 12:30:22 PM PST 24 |
| Finished | Feb 21 12:31:17 PM PST 24 |
| Peak memory | 145020 kb |
| Host | smart-0ad6f0aa-edb4-42a4-9998-0ede4ebae5de |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3625666283 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.3625666283 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.3660847682 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 10514580000 ps |
| CPU time | 40.22 seconds |
| Started | Feb 21 12:24:14 PM PST 24 |
| Finished | Feb 21 12:25:30 PM PST 24 |
| Peak memory | 145060 kb |
| Host | smart-5298e827-e05b-412e-bae2-15fd1db8818b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3660847682 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.3660847682 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.2920348561 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 4986660000 ps |
| CPU time | 15.71 seconds |
| Started | Feb 21 12:27:26 PM PST 24 |
| Finished | Feb 21 12:27:56 PM PST 24 |
| Peak memory | 145724 kb |
| Host | smart-7279822f-5bce-4e46-9585-a62ec6a7d088 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2920348561 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.2920348561 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.2703671444 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 9432680000 ps |
| CPU time | 36.1 seconds |
| Started | Feb 21 12:22:18 PM PST 24 |
| Finished | Feb 21 12:23:28 PM PST 24 |
| Peak memory | 144196 kb |
| Host | smart-a80b64c4-f775-4ee3-a23a-6f362648c15a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2703671444 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.2703671444 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.2092709571 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 14951920000 ps |
| CPU time | 46.15 seconds |
| Started | Feb 21 12:26:11 PM PST 24 |
| Finished | Feb 21 12:27:36 PM PST 24 |
| Peak memory | 145032 kb |
| Host | smart-54701b93-d1d1-4d65-bdf3-4c4de340d73d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2092709571 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.2092709571 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.3337372888 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 11752100000 ps |
| CPU time | 46.34 seconds |
| Started | Feb 21 12:22:18 PM PST 24 |
| Finished | Feb 21 12:23:46 PM PST 24 |
| Peak memory | 145564 kb |
| Host | smart-3561311c-b72d-40f5-a531-02423f12048f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3337372888 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.3337372888 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.3959645534 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 4669220000 ps |
| CPU time | 18.63 seconds |
| Started | Feb 21 12:22:03 PM PST 24 |
| Finished | Feb 21 12:22:39 PM PST 24 |
| Peak memory | 145528 kb |
| Host | smart-59412698-fcfd-4904-a55a-a6e6fc4ae9c1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3959645534 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.3959645534 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.3988048231 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 12047840000 ps |
| CPU time | 44.69 seconds |
| Started | Feb 21 12:24:04 PM PST 24 |
| Finished | Feb 21 12:25:29 PM PST 24 |
| Peak memory | 144468 kb |
| Host | smart-bbfcd8fa-c506-4a2a-bd40-37fe88f5b383 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3988048231 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.3988048231 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.1607092246 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 6827440000 ps |
| CPU time | 27.28 seconds |
| Started | Feb 21 12:24:14 PM PST 24 |
| Finished | Feb 21 12:25:05 PM PST 24 |
| Peak memory | 146324 kb |
| Host | smart-dfd06e43-f9a4-4291-8b29-69e83da417c6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1607092246 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.1607092246 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.2528743733 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 8631640000 ps |
| CPU time | 33.33 seconds |
| Started | Feb 21 12:24:12 PM PST 24 |
| Finished | Feb 21 12:25:16 PM PST 24 |
| Peak memory | 145060 kb |
| Host | smart-c58ad105-d083-4632-b570-8d78deb5ab53 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2528743733 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.2528743733 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.2088069913 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 4925280000 ps |
| CPU time | 16.84 seconds |
| Started | Feb 21 12:26:10 PM PST 24 |
| Finished | Feb 21 12:26:41 PM PST 24 |
| Peak memory | 145012 kb |
| Host | smart-9757484d-4f28-44ad-8f84-9b458fc4736a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2088069913 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.2088069913 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |