| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/14.prim_present_test.769761513 | ||
| Name |
|---|
| /workspace/coverage/default/0.prim_present_test.3417410157 |
| /workspace/coverage/default/1.prim_present_test.1898469059 |
| /workspace/coverage/default/10.prim_present_test.1129117045 |
| /workspace/coverage/default/11.prim_present_test.4219036802 |
| /workspace/coverage/default/12.prim_present_test.1333076579 |
| /workspace/coverage/default/13.prim_present_test.3086247947 |
| /workspace/coverage/default/15.prim_present_test.742473849 |
| /workspace/coverage/default/16.prim_present_test.3906007562 |
| /workspace/coverage/default/17.prim_present_test.3172032456 |
| /workspace/coverage/default/18.prim_present_test.3057981449 |
| /workspace/coverage/default/19.prim_present_test.844307857 |
| /workspace/coverage/default/2.prim_present_test.4036302041 |
| /workspace/coverage/default/20.prim_present_test.2819784816 |
| /workspace/coverage/default/21.prim_present_test.4056790208 |
| /workspace/coverage/default/22.prim_present_test.2062823750 |
| /workspace/coverage/default/23.prim_present_test.1006738832 |
| /workspace/coverage/default/24.prim_present_test.1850861019 |
| /workspace/coverage/default/25.prim_present_test.1174640606 |
| /workspace/coverage/default/26.prim_present_test.1783332721 |
| /workspace/coverage/default/27.prim_present_test.1310617395 |
| /workspace/coverage/default/28.prim_present_test.4139182273 |
| /workspace/coverage/default/29.prim_present_test.4291246737 |
| /workspace/coverage/default/3.prim_present_test.3128088209 |
| /workspace/coverage/default/30.prim_present_test.3974128448 |
| /workspace/coverage/default/31.prim_present_test.2374693070 |
| /workspace/coverage/default/32.prim_present_test.1719542008 |
| /workspace/coverage/default/33.prim_present_test.3180814350 |
| /workspace/coverage/default/34.prim_present_test.1657139438 |
| /workspace/coverage/default/35.prim_present_test.4294764438 |
| /workspace/coverage/default/36.prim_present_test.330638280 |
| /workspace/coverage/default/37.prim_present_test.192003372 |
| /workspace/coverage/default/38.prim_present_test.3226326405 |
| /workspace/coverage/default/39.prim_present_test.2226388438 |
| /workspace/coverage/default/4.prim_present_test.1190378991 |
| /workspace/coverage/default/40.prim_present_test.2756244437 |
| /workspace/coverage/default/41.prim_present_test.2043208046 |
| /workspace/coverage/default/42.prim_present_test.3548762984 |
| /workspace/coverage/default/43.prim_present_test.2635121284 |
| /workspace/coverage/default/44.prim_present_test.1808431832 |
| /workspace/coverage/default/45.prim_present_test.1398565585 |
| /workspace/coverage/default/46.prim_present_test.3523668129 |
| /workspace/coverage/default/47.prim_present_test.2157601871 |
| /workspace/coverage/default/48.prim_present_test.3700143317 |
| /workspace/coverage/default/49.prim_present_test.3781270955 |
| /workspace/coverage/default/5.prim_present_test.1250902147 |
| /workspace/coverage/default/6.prim_present_test.2759086841 |
| /workspace/coverage/default/7.prim_present_test.2635952964 |
| /workspace/coverage/default/8.prim_present_test.1540237307 |
| /workspace/coverage/default/9.prim_present_test.376909545 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/35.prim_present_test.4294764438 | Feb 25 12:16:58 PM PST 24 | Feb 25 12:17:49 PM PST 24 | 6466600000 ps | ||
| T2 | /workspace/coverage/default/28.prim_present_test.4139182273 | Feb 25 12:16:58 PM PST 24 | Feb 25 12:17:22 PM PST 24 | 3114880000 ps | ||
| T3 | /workspace/coverage/default/46.prim_present_test.3523668129 | Feb 25 12:16:58 PM PST 24 | Feb 25 12:18:25 PM PST 24 | 9549240000 ps | ||
| T4 | /workspace/coverage/default/2.prim_present_test.4036302041 | Feb 25 12:16:59 PM PST 24 | Feb 25 12:17:55 PM PST 24 | 7482780000 ps | ||
| T5 | /workspace/coverage/default/18.prim_present_test.3057981449 | Feb 25 12:16:58 PM PST 24 | Feb 25 12:17:53 PM PST 24 | 7037000000 ps | ||
| T6 | /workspace/coverage/default/14.prim_present_test.769761513 | Feb 25 12:17:07 PM PST 24 | Feb 25 12:17:36 PM PST 24 | 3134720000 ps | ||
| T7 | /workspace/coverage/default/30.prim_present_test.3974128448 | Feb 25 12:17:07 PM PST 24 | Feb 25 12:18:05 PM PST 24 | 6276880000 ps | ||
| T8 | /workspace/coverage/default/29.prim_present_test.4291246737 | Feb 25 12:17:07 PM PST 24 | Feb 25 12:18:44 PM PST 24 | 12959240000 ps | ||
| T9 | /workspace/coverage/default/32.prim_present_test.1719542008 | Feb 25 12:16:58 PM PST 24 | Feb 25 12:18:48 PM PST 24 | 14353000000 ps | ||
| T10 | /workspace/coverage/default/39.prim_present_test.2226388438 | Feb 25 12:17:07 PM PST 24 | Feb 25 12:17:57 PM PST 24 | 5493820000 ps | ||
| T11 | /workspace/coverage/default/36.prim_present_test.330638280 | Feb 25 12:17:08 PM PST 24 | Feb 25 12:18:41 PM PST 24 | 12404960000 ps | ||
| T12 | /workspace/coverage/default/49.prim_present_test.3781270955 | Feb 25 12:24:26 PM PST 24 | Feb 25 12:24:52 PM PST 24 | 3966140000 ps | ||
| T13 | /workspace/coverage/default/13.prim_present_test.3086247947 | Feb 25 12:17:07 PM PST 24 | Feb 25 12:18:13 PM PST 24 | 7268880000 ps | ||
| T14 | /workspace/coverage/default/15.prim_present_test.742473849 | Feb 25 12:16:58 PM PST 24 | Feb 25 12:17:53 PM PST 24 | 5773440000 ps | ||
| T15 | /workspace/coverage/default/6.prim_present_test.2759086841 | Feb 25 12:16:59 PM PST 24 | Feb 25 12:17:51 PM PST 24 | 5501260000 ps | ||
| T16 | /workspace/coverage/default/42.prim_present_test.3548762984 | Feb 25 12:17:07 PM PST 24 | Feb 25 12:18:29 PM PST 24 | 9048280000 ps | ||
| T17 | /workspace/coverage/default/19.prim_present_test.844307857 | Feb 25 12:17:09 PM PST 24 | Feb 25 12:17:49 PM PST 24 | 4808720000 ps | ||
| T18 | /workspace/coverage/default/47.prim_present_test.2157601871 | Feb 25 12:17:20 PM PST 24 | Feb 25 12:19:01 PM PST 24 | 15288580000 ps | ||
| T19 | /workspace/coverage/default/41.prim_present_test.2043208046 | Feb 25 12:16:58 PM PST 24 | Feb 25 12:18:26 PM PST 24 | 9672620000 ps | ||
| T20 | /workspace/coverage/default/0.prim_present_test.3417410157 | Feb 25 12:17:30 PM PST 24 | Feb 25 12:17:52 PM PST 24 | 3403180000 ps | ||
| T21 | /workspace/coverage/default/5.prim_present_test.1250902147 | Feb 25 12:16:58 PM PST 24 | Feb 25 12:17:23 PM PST 24 | 3162620000 ps | ||
| T22 | /workspace/coverage/default/8.prim_present_test.1540237307 | Feb 25 12:16:58 PM PST 24 | Feb 25 12:18:19 PM PST 24 | 11513400000 ps | ||
| T23 | /workspace/coverage/default/43.prim_present_test.2635121284 | Feb 25 12:17:09 PM PST 24 | Feb 25 12:18:50 PM PST 24 | 13852660000 ps | ||
| T24 | /workspace/coverage/default/26.prim_present_test.1783332721 | Feb 25 12:17:09 PM PST 24 | Feb 25 12:17:47 PM PST 24 | 4605360000 ps | ||
| T25 | /workspace/coverage/default/21.prim_present_test.4056790208 | Feb 25 12:16:58 PM PST 24 | Feb 25 12:17:52 PM PST 24 | 7100240000 ps | ||
| T26 | /workspace/coverage/default/31.prim_present_test.2374693070 | Feb 25 12:17:09 PM PST 24 | Feb 25 12:17:47 PM PST 24 | 4556380000 ps | ||
| T27 | /workspace/coverage/default/33.prim_present_test.3180814350 | Feb 25 12:16:58 PM PST 24 | Feb 25 12:18:21 PM PST 24 | 10752040000 ps | ||
| T28 | /workspace/coverage/default/20.prim_present_test.2819784816 | Feb 25 12:17:07 PM PST 24 | Feb 25 12:19:14 PM PST 24 | 14571240000 ps | ||
| T29 | /workspace/coverage/default/23.prim_present_test.1006738832 | Feb 25 12:16:59 PM PST 24 | Feb 25 12:17:52 PM PST 24 | 5619060000 ps | ||
| T30 | /workspace/coverage/default/9.prim_present_test.376909545 | Feb 25 12:16:58 PM PST 24 | Feb 25 12:18:03 PM PST 24 | 8136880000 ps | ||
| T31 | /workspace/coverage/default/12.prim_present_test.1333076579 | Feb 25 12:17:22 PM PST 24 | Feb 25 12:19:17 PM PST 24 | 15480160000 ps | ||
| T32 | /workspace/coverage/default/48.prim_present_test.3700143317 | Feb 25 12:24:27 PM PST 24 | Feb 25 12:24:49 PM PST 24 | 3364120000 ps | ||
| T33 | /workspace/coverage/default/24.prim_present_test.1850861019 | Feb 25 12:16:58 PM PST 24 | Feb 25 12:18:09 PM PST 24 | 9422140000 ps | ||
| T34 | /workspace/coverage/default/11.prim_present_test.4219036802 | Feb 25 12:17:07 PM PST 24 | Feb 25 12:19:11 PM PST 24 | 14390820000 ps | ||
| T35 | /workspace/coverage/default/10.prim_present_test.1129117045 | Feb 25 12:16:59 PM PST 24 | Feb 25 12:17:29 PM PST 24 | 3189900000 ps | ||
| T36 | /workspace/coverage/default/34.prim_present_test.1657139438 | Feb 25 12:17:07 PM PST 24 | Feb 25 12:18:20 PM PST 24 | 8190820000 ps | ||
| T37 | /workspace/coverage/default/16.prim_present_test.3906007562 | Feb 25 12:16:58 PM PST 24 | Feb 25 12:17:43 PM PST 24 | 4805620000 ps | ||
| T38 | /workspace/coverage/default/40.prim_present_test.2756244437 | Feb 25 12:18:12 PM PST 24 | Feb 25 12:19:49 PM PST 24 | 14537760000 ps | ||
| T39 | /workspace/coverage/default/22.prim_present_test.2062823750 | Feb 25 12:16:59 PM PST 24 | Feb 25 12:17:27 PM PST 24 | 3506720000 ps | ||
| T40 | /workspace/coverage/default/37.prim_present_test.192003372 | Feb 25 12:16:59 PM PST 24 | Feb 25 12:18:13 PM PST 24 | 9559780000 ps | ||
| T41 | /workspace/coverage/default/1.prim_present_test.1898469059 | Feb 25 12:17:09 PM PST 24 | Feb 25 12:18:00 PM PST 24 | 6374840000 ps | ||
| T42 | /workspace/coverage/default/45.prim_present_test.1398565585 | Feb 25 12:16:59 PM PST 24 | Feb 25 12:17:56 PM PST 24 | 6108240000 ps | ||
| T43 | /workspace/coverage/default/25.prim_present_test.1174640606 | Feb 25 12:16:58 PM PST 24 | Feb 25 12:18:15 PM PST 24 | 8297460000 ps | ||
| T44 | /workspace/coverage/default/44.prim_present_test.1808431832 | Feb 25 12:16:59 PM PST 24 | Feb 25 12:18:01 PM PST 24 | 6620980000 ps | ||
| T45 | /workspace/coverage/default/27.prim_present_test.1310617395 | Feb 25 12:16:58 PM PST 24 | Feb 25 12:18:32 PM PST 24 | 10534420000 ps | ||
| T46 | /workspace/coverage/default/4.prim_present_test.1190378991 | Feb 25 12:17:07 PM PST 24 | Feb 25 12:19:18 PM PST 24 | 15193100000 ps | ||
| T47 | /workspace/coverage/default/7.prim_present_test.2635952964 | Feb 25 12:17:07 PM PST 24 | Feb 25 12:17:37 PM PST 24 | 3164480000 ps | ||
| T48 | /workspace/coverage/default/38.prim_present_test.3226326405 | Feb 25 12:16:58 PM PST 24 | Feb 25 12:18:02 PM PST 24 | 8113320000 ps | ||
| T49 | /workspace/coverage/default/17.prim_present_test.3172032456 | Feb 25 12:17:09 PM PST 24 | Feb 25 12:17:59 PM PST 24 | 6298580000 ps | ||
| T50 | /workspace/coverage/default/3.prim_present_test.3128088209 | Feb 25 12:16:59 PM PST 24 | Feb 25 12:17:26 PM PST 24 | 3494940000 ps |
| Test location | /workspace/coverage/default/14.prim_present_test.769761513 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 3134720000 ps |
| CPU time | 14.81 seconds |
| Started | Feb 25 12:17:07 PM PST 24 |
| Finished | Feb 25 12:17:36 PM PST 24 |
| Peak memory | 144516 kb |
| Host | smart-79c737c9-7ca5-4a73-bce8-f2107bd1695d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=769761513 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.769761513 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/0.prim_present_test.3417410157 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 3403180000 ps |
| CPU time | 11.43 seconds |
| Started | Feb 25 12:17:30 PM PST 24 |
| Finished | Feb 25 12:17:52 PM PST 24 |
| Peak memory | 145588 kb |
| Host | smart-8316e9df-2a4e-41e1-9554-26c527a31191 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3417410157 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.3417410157 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/1.prim_present_test.1898469059 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 6374840000 ps |
| CPU time | 25.28 seconds |
| Started | Feb 25 12:17:09 PM PST 24 |
| Finished | Feb 25 12:18:00 PM PST 24 |
| Peak memory | 144952 kb |
| Host | smart-9a3bb14c-63d4-4e28-b617-e3f2cbc7e9f4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1898469059 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.1898469059 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/10.prim_present_test.1129117045 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 3189900000 ps |
| CPU time | 14.83 seconds |
| Started | Feb 25 12:16:59 PM PST 24 |
| Finished | Feb 25 12:17:29 PM PST 24 |
| Peak memory | 145660 kb |
| Host | smart-b92ab9b9-fa6f-4d91-9166-126e69715c31 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1129117045 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.1129117045 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/11.prim_present_test.4219036802 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 14390820000 ps |
| CPU time | 61.65 seconds |
| Started | Feb 25 12:17:07 PM PST 24 |
| Finished | Feb 25 12:19:11 PM PST 24 |
| Peak memory | 145036 kb |
| Host | smart-42e18c38-837d-4951-97ad-1aa456373e83 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4219036802 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.4219036802 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.1333076579 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 15480160000 ps |
| CPU time | 59.76 seconds |
| Started | Feb 25 12:17:22 PM PST 24 |
| Finished | Feb 25 12:19:17 PM PST 24 |
| Peak memory | 145032 kb |
| Host | smart-96b1922a-9b48-4ff8-aebc-a0cd072d0d73 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1333076579 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.1333076579 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.3086247947 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 7268880000 ps |
| CPU time | 32.78 seconds |
| Started | Feb 25 12:17:07 PM PST 24 |
| Finished | Feb 25 12:18:13 PM PST 24 |
| Peak memory | 145024 kb |
| Host | smart-59f24832-cad1-429f-ba01-0e436c56cd38 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3086247947 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.3086247947 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.742473849 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 5773440000 ps |
| CPU time | 26.68 seconds |
| Started | Feb 25 12:16:58 PM PST 24 |
| Finished | Feb 25 12:17:53 PM PST 24 |
| Peak memory | 145808 kb |
| Host | smart-d412c74f-f115-4be3-add0-255a0bcba5ae |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=742473849 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.742473849 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.3906007562 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 4805620000 ps |
| CPU time | 21.94 seconds |
| Started | Feb 25 12:16:58 PM PST 24 |
| Finished | Feb 25 12:17:43 PM PST 24 |
| Peak memory | 145812 kb |
| Host | smart-c7d5aa22-6ef8-4fab-bef4-18d5f53419fc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3906007562 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.3906007562 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.3172032456 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 6298580000 ps |
| CPU time | 25.03 seconds |
| Started | Feb 25 12:17:09 PM PST 24 |
| Finished | Feb 25 12:17:59 PM PST 24 |
| Peak memory | 144952 kb |
| Host | smart-33d75915-7649-4436-95bb-f2611113f373 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3172032456 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.3172032456 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.3057981449 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 7037000000 ps |
| CPU time | 28.12 seconds |
| Started | Feb 25 12:16:58 PM PST 24 |
| Finished | Feb 25 12:17:53 PM PST 24 |
| Peak memory | 144404 kb |
| Host | smart-b96b7444-bf49-451c-a48d-e0c2705f6d5a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3057981449 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.3057981449 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.844307857 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 4808720000 ps |
| CPU time | 19.96 seconds |
| Started | Feb 25 12:17:09 PM PST 24 |
| Finished | Feb 25 12:17:49 PM PST 24 |
| Peak memory | 145016 kb |
| Host | smart-927a4e40-d365-4959-874c-ba90b5188472 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=844307857 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.844307857 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.4036302041 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 7482780000 ps |
| CPU time | 29.68 seconds |
| Started | Feb 25 12:16:59 PM PST 24 |
| Finished | Feb 25 12:17:55 PM PST 24 |
| Peak memory | 145040 kb |
| Host | smart-ffd43509-24c4-416c-8f33-719d65dc46e9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4036302041 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.4036302041 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.2819784816 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 14571240000 ps |
| CPU time | 63.1 seconds |
| Started | Feb 25 12:17:07 PM PST 24 |
| Finished | Feb 25 12:19:14 PM PST 24 |
| Peak memory | 145028 kb |
| Host | smart-92c1b32c-4cdd-4acc-9479-d34e4a27572e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2819784816 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.2819784816 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.4056790208 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 7100240000 ps |
| CPU time | 28.55 seconds |
| Started | Feb 25 12:16:58 PM PST 24 |
| Finished | Feb 25 12:17:52 PM PST 24 |
| Peak memory | 142636 kb |
| Host | smart-d91888da-ccd8-4f8f-86ad-5a2c19324f8e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4056790208 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.4056790208 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.2062823750 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 3506720000 ps |
| CPU time | 14.27 seconds |
| Started | Feb 25 12:16:59 PM PST 24 |
| Finished | Feb 25 12:17:27 PM PST 24 |
| Peak memory | 144908 kb |
| Host | smart-060d0cc6-7524-4d02-a7ff-e00e1a96e03f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2062823750 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.2062823750 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.1006738832 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 5619060000 ps |
| CPU time | 25.7 seconds |
| Started | Feb 25 12:16:59 PM PST 24 |
| Finished | Feb 25 12:17:52 PM PST 24 |
| Peak memory | 145812 kb |
| Host | smart-5793c9af-3d10-4d6c-8889-9cc40f7e07a4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1006738832 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.1006738832 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.1850861019 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 9422140000 ps |
| CPU time | 37.53 seconds |
| Started | Feb 25 12:16:58 PM PST 24 |
| Finished | Feb 25 12:18:09 PM PST 24 |
| Peak memory | 142692 kb |
| Host | smart-fa84158a-69e7-4c6b-a398-f44664f85cb4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1850861019 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.1850861019 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.1174640606 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 8297460000 ps |
| CPU time | 37.91 seconds |
| Started | Feb 25 12:16:58 PM PST 24 |
| Finished | Feb 25 12:18:15 PM PST 24 |
| Peak memory | 145812 kb |
| Host | smart-fea7b7e0-f782-490b-86ad-023d976bfd9b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1174640606 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.1174640606 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.1783332721 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 4605360000 ps |
| CPU time | 18.49 seconds |
| Started | Feb 25 12:17:09 PM PST 24 |
| Finished | Feb 25 12:17:47 PM PST 24 |
| Peak memory | 145016 kb |
| Host | smart-b68a691a-ca0b-46b6-ab43-720bc23ba8c2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1783332721 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.1783332721 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.1310617395 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 10534420000 ps |
| CPU time | 46.87 seconds |
| Started | Feb 25 12:16:58 PM PST 24 |
| Finished | Feb 25 12:18:32 PM PST 24 |
| Peak memory | 145812 kb |
| Host | smart-a3646d46-e316-462c-8f2d-87390caf1d5d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1310617395 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.1310617395 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.4139182273 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 3114880000 ps |
| CPU time | 12.33 seconds |
| Started | Feb 25 12:16:58 PM PST 24 |
| Finished | Feb 25 12:17:22 PM PST 24 |
| Peak memory | 145536 kb |
| Host | smart-2e476cc7-ecd1-4d4c-a97b-cb0bc36abb70 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4139182273 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.4139182273 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.4291246737 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 12959240000 ps |
| CPU time | 50.29 seconds |
| Started | Feb 25 12:17:07 PM PST 24 |
| Finished | Feb 25 12:18:44 PM PST 24 |
| Peak memory | 144460 kb |
| Host | smart-b3f037a7-408b-4e35-813e-642d79682941 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4291246737 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.4291246737 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.3128088209 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 3494940000 ps |
| CPU time | 14.34 seconds |
| Started | Feb 25 12:16:59 PM PST 24 |
| Finished | Feb 25 12:17:26 PM PST 24 |
| Peak memory | 144900 kb |
| Host | smart-d1de4e5a-9f3d-4090-b352-cf5c539ebb04 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3128088209 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.3128088209 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.3974128448 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 6276880000 ps |
| CPU time | 28.4 seconds |
| Started | Feb 25 12:17:07 PM PST 24 |
| Finished | Feb 25 12:18:05 PM PST 24 |
| Peak memory | 145028 kb |
| Host | smart-6624d3e3-75b8-49fa-b7bd-a1309a9c9d4d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3974128448 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.3974128448 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.2374693070 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 4556380000 ps |
| CPU time | 19.04 seconds |
| Started | Feb 25 12:17:09 PM PST 24 |
| Finished | Feb 25 12:17:47 PM PST 24 |
| Peak memory | 146296 kb |
| Host | smart-ed1bf09d-518f-46dc-bbc9-247dca679a05 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2374693070 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.2374693070 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.1719542008 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 14353000000 ps |
| CPU time | 56.9 seconds |
| Started | Feb 25 12:16:58 PM PST 24 |
| Finished | Feb 25 12:18:48 PM PST 24 |
| Peak memory | 143464 kb |
| Host | smart-36f22381-f9a6-41d3-b757-78546a428c16 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1719542008 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.1719542008 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.3180814350 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 10752040000 ps |
| CPU time | 42.99 seconds |
| Started | Feb 25 12:16:58 PM PST 24 |
| Finished | Feb 25 12:18:21 PM PST 24 |
| Peak memory | 142700 kb |
| Host | smart-80514a1f-1fab-4fd2-9520-f191f4390c93 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3180814350 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.3180814350 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.1657139438 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 8190820000 ps |
| CPU time | 36.84 seconds |
| Started | Feb 25 12:17:07 PM PST 24 |
| Finished | Feb 25 12:18:20 PM PST 24 |
| Peak memory | 145032 kb |
| Host | smart-fb72d139-7525-4ae2-aeb0-b79c2947dfb2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1657139438 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.1657139438 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.4294764438 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 6466600000 ps |
| CPU time | 26.46 seconds |
| Started | Feb 25 12:16:58 PM PST 24 |
| Finished | Feb 25 12:17:49 PM PST 24 |
| Peak memory | 142320 kb |
| Host | smart-b38076e8-b3a9-487d-a5c3-0b15a4ed5838 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4294764438 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.4294764438 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.330638280 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 12404960000 ps |
| CPU time | 47.87 seconds |
| Started | Feb 25 12:17:08 PM PST 24 |
| Finished | Feb 25 12:18:41 PM PST 24 |
| Peak memory | 145016 kb |
| Host | smart-b72006bd-9cc0-4dc4-9ebe-76737e6d9559 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=330638280 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.330638280 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.192003372 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 9559780000 ps |
| CPU time | 38.9 seconds |
| Started | Feb 25 12:16:59 PM PST 24 |
| Finished | Feb 25 12:18:13 PM PST 24 |
| Peak memory | 145048 kb |
| Host | smart-b047d20e-b7c5-4181-90d4-ed0bf9e6f018 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=192003372 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.192003372 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.3226326405 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 8113320000 ps |
| CPU time | 33.55 seconds |
| Started | Feb 25 12:16:58 PM PST 24 |
| Finished | Feb 25 12:18:02 PM PST 24 |
| Peak memory | 143508 kb |
| Host | smart-48bbff14-7aee-497f-871e-5bc30a5e66d2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3226326405 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.3226326405 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.2226388438 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 5493820000 ps |
| CPU time | 25.1 seconds |
| Started | Feb 25 12:17:07 PM PST 24 |
| Finished | Feb 25 12:17:57 PM PST 24 |
| Peak memory | 143396 kb |
| Host | smart-140238a4-a9f8-40c3-9c24-2301e52d6390 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2226388438 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.2226388438 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.1190378991 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 15193100000 ps |
| CPU time | 66.22 seconds |
| Started | Feb 25 12:17:07 PM PST 24 |
| Finished | Feb 25 12:19:18 PM PST 24 |
| Peak memory | 143524 kb |
| Host | smart-9f5b2470-23c1-4658-9411-1d40c22fd83c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1190378991 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.1190378991 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.2756244437 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 14537760000 ps |
| CPU time | 51.3 seconds |
| Started | Feb 25 12:18:12 PM PST 24 |
| Finished | Feb 25 12:19:49 PM PST 24 |
| Peak memory | 145720 kb |
| Host | smart-f9d9e5e5-daf2-4cbc-8c83-5697a590d5aa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2756244437 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.2756244437 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.2043208046 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 9672620000 ps |
| CPU time | 43.63 seconds |
| Started | Feb 25 12:16:58 PM PST 24 |
| Finished | Feb 25 12:18:26 PM PST 24 |
| Peak memory | 145808 kb |
| Host | smart-36c2d14e-a1a0-4282-9932-a630d5d85b34 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2043208046 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.2043208046 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.3548762984 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 9048280000 ps |
| CPU time | 40.54 seconds |
| Started | Feb 25 12:17:07 PM PST 24 |
| Finished | Feb 25 12:18:29 PM PST 24 |
| Peak memory | 145028 kb |
| Host | smart-2a02a91f-7981-487f-a399-2272443b5c88 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3548762984 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.3548762984 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.2635121284 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 13852660000 ps |
| CPU time | 52.08 seconds |
| Started | Feb 25 12:17:09 PM PST 24 |
| Finished | Feb 25 12:18:50 PM PST 24 |
| Peak memory | 145016 kb |
| Host | smart-c76a6e15-750f-4a23-b41c-839d7c83a3e7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2635121284 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.2635121284 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.1808431832 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 6620980000 ps |
| CPU time | 30.42 seconds |
| Started | Feb 25 12:16:59 PM PST 24 |
| Finished | Feb 25 12:18:01 PM PST 24 |
| Peak memory | 145812 kb |
| Host | smart-461e5fac-1754-4833-9a3d-d1a7a498a62a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1808431832 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.1808431832 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.1398565585 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 6108240000 ps |
| CPU time | 27.79 seconds |
| Started | Feb 25 12:16:59 PM PST 24 |
| Finished | Feb 25 12:17:56 PM PST 24 |
| Peak memory | 145812 kb |
| Host | smart-afe83934-d029-46ca-8696-9694e4c8ca0f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1398565585 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.1398565585 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.3523668129 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 9549240000 ps |
| CPU time | 43.2 seconds |
| Started | Feb 25 12:16:58 PM PST 24 |
| Finished | Feb 25 12:18:25 PM PST 24 |
| Peak memory | 145812 kb |
| Host | smart-127c9aa2-7dea-4f52-b858-0a1b8f7a3dec |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3523668129 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.3523668129 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.2157601871 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 15288580000 ps |
| CPU time | 53.03 seconds |
| Started | Feb 25 12:17:20 PM PST 24 |
| Finished | Feb 25 12:19:01 PM PST 24 |
| Peak memory | 145732 kb |
| Host | smart-dd0e865a-d719-42b5-9699-d1c26c89c521 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2157601871 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.2157601871 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.3700143317 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 3364120000 ps |
| CPU time | 11.67 seconds |
| Started | Feb 25 12:24:27 PM PST 24 |
| Finished | Feb 25 12:24:49 PM PST 24 |
| Peak memory | 145608 kb |
| Host | smart-65a100a2-c4dd-422b-9671-d4c6dcaa4a3e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3700143317 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.3700143317 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.3781270955 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 3966140000 ps |
| CPU time | 13.56 seconds |
| Started | Feb 25 12:24:26 PM PST 24 |
| Finished | Feb 25 12:24:52 PM PST 24 |
| Peak memory | 144152 kb |
| Host | smart-397b9b38-a68c-4673-987b-6d80fae72eed |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3781270955 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.3781270955 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.1250902147 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 3162620000 ps |
| CPU time | 13.23 seconds |
| Started | Feb 25 12:16:58 PM PST 24 |
| Finished | Feb 25 12:17:23 PM PST 24 |
| Peak memory | 142244 kb |
| Host | smart-1e28ca46-f668-4f97-a35b-1be95fdc90ee |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1250902147 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.1250902147 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.2759086841 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 5501260000 ps |
| CPU time | 25.93 seconds |
| Started | Feb 25 12:16:59 PM PST 24 |
| Finished | Feb 25 12:17:51 PM PST 24 |
| Peak memory | 145812 kb |
| Host | smart-efde1059-f600-4c13-9fdd-a96647dd6855 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2759086841 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.2759086841 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.2635952964 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 3164480000 ps |
| CPU time | 14.39 seconds |
| Started | Feb 25 12:17:07 PM PST 24 |
| Finished | Feb 25 12:17:37 PM PST 24 |
| Peak memory | 144876 kb |
| Host | smart-9d8d5678-276a-4abf-a05b-cbf174a78171 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2635952964 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.2635952964 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.1540237307 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 11513400000 ps |
| CPU time | 43.03 seconds |
| Started | Feb 25 12:16:58 PM PST 24 |
| Finished | Feb 25 12:18:19 PM PST 24 |
| Peak memory | 144748 kb |
| Host | smart-dca959e8-975b-4787-bbbd-ba054e8f6113 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1540237307 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.1540237307 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.376909545 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 8136880000 ps |
| CPU time | 33.04 seconds |
| Started | Feb 25 12:16:58 PM PST 24 |
| Finished | Feb 25 12:18:03 PM PST 24 |
| Peak memory | 142720 kb |
| Host | smart-1c894edc-4569-46b5-af12-99b1b76a5b12 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=376909545 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.376909545 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |