| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/13.prim_present_test.1594657393 | ||
| Name |
|---|
| /workspace/coverage/default/0.prim_present_test.1403212205 |
| /workspace/coverage/default/1.prim_present_test.4073468107 |
| /workspace/coverage/default/10.prim_present_test.1082475073 |
| /workspace/coverage/default/11.prim_present_test.2773484219 |
| /workspace/coverage/default/12.prim_present_test.1494739036 |
| /workspace/coverage/default/14.prim_present_test.3587225240 |
| /workspace/coverage/default/15.prim_present_test.3584883280 |
| /workspace/coverage/default/16.prim_present_test.2333308589 |
| /workspace/coverage/default/17.prim_present_test.2983767730 |
| /workspace/coverage/default/18.prim_present_test.4234546836 |
| /workspace/coverage/default/19.prim_present_test.3210853339 |
| /workspace/coverage/default/2.prim_present_test.1430270080 |
| /workspace/coverage/default/20.prim_present_test.1428002566 |
| /workspace/coverage/default/21.prim_present_test.296910271 |
| /workspace/coverage/default/22.prim_present_test.3805524150 |
| /workspace/coverage/default/23.prim_present_test.1835716838 |
| /workspace/coverage/default/24.prim_present_test.2175899636 |
| /workspace/coverage/default/25.prim_present_test.917919170 |
| /workspace/coverage/default/26.prim_present_test.1717129229 |
| /workspace/coverage/default/27.prim_present_test.3152226500 |
| /workspace/coverage/default/28.prim_present_test.1394557202 |
| /workspace/coverage/default/29.prim_present_test.439368421 |
| /workspace/coverage/default/3.prim_present_test.1348775856 |
| /workspace/coverage/default/30.prim_present_test.3483320492 |
| /workspace/coverage/default/31.prim_present_test.1316968810 |
| /workspace/coverage/default/32.prim_present_test.2211581103 |
| /workspace/coverage/default/33.prim_present_test.2616533873 |
| /workspace/coverage/default/34.prim_present_test.723502165 |
| /workspace/coverage/default/35.prim_present_test.3646572467 |
| /workspace/coverage/default/36.prim_present_test.1152289753 |
| /workspace/coverage/default/37.prim_present_test.266201656 |
| /workspace/coverage/default/38.prim_present_test.2035278294 |
| /workspace/coverage/default/39.prim_present_test.379759802 |
| /workspace/coverage/default/4.prim_present_test.1283303445 |
| /workspace/coverage/default/40.prim_present_test.3661740612 |
| /workspace/coverage/default/41.prim_present_test.3183903177 |
| /workspace/coverage/default/42.prim_present_test.1246552959 |
| /workspace/coverage/default/43.prim_present_test.696147422 |
| /workspace/coverage/default/44.prim_present_test.2789866859 |
| /workspace/coverage/default/45.prim_present_test.1168373494 |
| /workspace/coverage/default/46.prim_present_test.2587920250 |
| /workspace/coverage/default/47.prim_present_test.1403823341 |
| /workspace/coverage/default/48.prim_present_test.683572193 |
| /workspace/coverage/default/49.prim_present_test.3154876162 |
| /workspace/coverage/default/5.prim_present_test.1262550365 |
| /workspace/coverage/default/6.prim_present_test.755431225 |
| /workspace/coverage/default/7.prim_present_test.3881854842 |
| /workspace/coverage/default/8.prim_present_test.674407373 |
| /workspace/coverage/default/9.prim_present_test.1213939246 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/16.prim_present_test.2333308589 | Feb 29 12:23:22 PM PST 24 | Feb 29 12:23:45 PM PST 24 | 3780760000 ps | ||
| T2 | /workspace/coverage/default/23.prim_present_test.1835716838 | Feb 29 12:23:22 PM PST 24 | Feb 29 12:24:41 PM PST 24 | 13841500000 ps | ||
| T3 | /workspace/coverage/default/13.prim_present_test.1594657393 | Feb 29 12:20:31 PM PST 24 | Feb 29 12:21:03 PM PST 24 | 4916600000 ps | ||
| T4 | /workspace/coverage/default/35.prim_present_test.3646572467 | Feb 29 12:20:28 PM PST 24 | Feb 29 12:20:52 PM PST 24 | 3465800000 ps | ||
| T5 | /workspace/coverage/default/17.prim_present_test.2983767730 | Feb 29 12:19:55 PM PST 24 | Feb 29 12:20:19 PM PST 24 | 3884920000 ps | ||
| T6 | /workspace/coverage/default/4.prim_present_test.1283303445 | Feb 29 12:16:51 PM PST 24 | Feb 29 12:18:14 PM PST 24 | 14096940000 ps | ||
| T7 | /workspace/coverage/default/24.prim_present_test.2175899636 | Feb 29 12:23:22 PM PST 24 | Feb 29 12:24:51 PM PST 24 | 15225960000 ps | ||
| T8 | /workspace/coverage/default/6.prim_present_test.755431225 | Feb 29 12:16:52 PM PST 24 | Feb 29 12:17:32 PM PST 24 | 7198820000 ps | ||
| T9 | /workspace/coverage/default/15.prim_present_test.3584883280 | Feb 29 12:19:53 PM PST 24 | Feb 29 12:20:15 PM PST 24 | 3627000000 ps | ||
| T10 | /workspace/coverage/default/47.prim_present_test.1403823341 | Feb 29 12:19:52 PM PST 24 | Feb 29 12:20:48 PM PST 24 | 9286980000 ps | ||
| T11 | /workspace/coverage/default/44.prim_present_test.2789866859 | Feb 29 12:20:17 PM PST 24 | Feb 29 12:21:07 PM PST 24 | 7007240000 ps | ||
| T12 | /workspace/coverage/default/33.prim_present_test.2616533873 | Feb 29 12:22:46 PM PST 24 | Feb 29 12:23:24 PM PST 24 | 7543540000 ps | ||
| T13 | /workspace/coverage/default/12.prim_present_test.1494739036 | Feb 29 12:20:03 PM PST 24 | Feb 29 12:20:28 PM PST 24 | 3419300000 ps | ||
| T14 | /workspace/coverage/default/28.prim_present_test.1394557202 | Feb 29 12:19:55 PM PST 24 | Feb 29 12:20:45 PM PST 24 | 8080460000 ps | ||
| T15 | /workspace/coverage/default/25.prim_present_test.917919170 | Feb 29 12:19:55 PM PST 24 | Feb 29 12:21:26 PM PST 24 | 14385860000 ps | ||
| T16 | /workspace/coverage/default/41.prim_present_test.3183903177 | Feb 29 12:20:17 PM PST 24 | Feb 29 12:21:42 PM PST 24 | 12596540000 ps | ||
| T17 | /workspace/coverage/default/29.prim_present_test.439368421 | Feb 29 12:20:20 PM PST 24 | Feb 29 12:21:37 PM PST 24 | 10757620000 ps | ||
| T18 | /workspace/coverage/default/36.prim_present_test.1152289753 | Feb 29 12:19:57 PM PST 24 | Feb 29 12:21:14 PM PST 24 | 12109840000 ps | ||
| T19 | /workspace/coverage/default/3.prim_present_test.1348775856 | Feb 29 12:16:55 PM PST 24 | Feb 29 12:18:20 PM PST 24 | 15065380000 ps | ||
| T20 | /workspace/coverage/default/48.prim_present_test.683572193 | Feb 29 12:19:55 PM PST 24 | Feb 29 12:21:33 PM PST 24 | 14785760000 ps | ||
| T21 | /workspace/coverage/default/11.prim_present_test.2773484219 | Feb 29 12:19:55 PM PST 24 | Feb 29 12:21:03 PM PST 24 | 10491020000 ps | ||
| T22 | /workspace/coverage/default/0.prim_present_test.1403212205 | Feb 29 12:16:51 PM PST 24 | Feb 29 12:17:40 PM PST 24 | 7696060000 ps | ||
| T23 | /workspace/coverage/default/45.prim_present_test.1168373494 | Feb 29 12:20:01 PM PST 24 | Feb 29 12:20:39 PM PST 24 | 5652540000 ps | ||
| T24 | /workspace/coverage/default/14.prim_present_test.3587225240 | Feb 29 12:23:13 PM PST 24 | Feb 29 12:23:47 PM PST 24 | 5931540000 ps | ||
| T25 | /workspace/coverage/default/30.prim_present_test.3483320492 | Feb 29 12:22:53 PM PST 24 | Feb 29 12:23:58 PM PST 24 | 13767720000 ps | ||
| T26 | /workspace/coverage/default/42.prim_present_test.1246552959 | Feb 29 12:19:57 PM PST 24 | Feb 29 12:21:04 PM PST 24 | 10074380000 ps | ||
| T27 | /workspace/coverage/default/8.prim_present_test.674407373 | Feb 29 12:16:54 PM PST 24 | Feb 29 12:17:45 PM PST 24 | 8784160000 ps | ||
| T28 | /workspace/coverage/default/22.prim_present_test.3805524150 | Feb 29 12:23:21 PM PST 24 | Feb 29 12:24:24 PM PST 24 | 11290200000 ps | ||
| T29 | /workspace/coverage/default/1.prim_present_test.4073468107 | Feb 29 12:16:59 PM PST 24 | Feb 29 12:18:02 PM PST 24 | 8755640000 ps | ||
| T30 | /workspace/coverage/default/7.prim_present_test.3881854842 | Feb 29 12:16:54 PM PST 24 | Feb 29 12:17:21 PM PST 24 | 4365420000 ps | ||
| T31 | /workspace/coverage/default/2.prim_present_test.1430270080 | Feb 29 12:16:50 PM PST 24 | Feb 29 12:17:52 PM PST 24 | 9768720000 ps | ||
| T32 | /workspace/coverage/default/34.prim_present_test.723502165 | Feb 29 12:25:35 PM PST 24 | Feb 29 12:25:55 PM PST 24 | 3462080000 ps | ||
| T33 | /workspace/coverage/default/39.prim_present_test.379759802 | Feb 29 12:20:15 PM PST 24 | Feb 29 12:21:50 PM PST 24 | 13954340000 ps | ||
| T34 | /workspace/coverage/default/38.prim_present_test.2035278294 | Feb 29 12:20:19 PM PST 24 | Feb 29 12:21:17 PM PST 24 | 8634740000 ps | ||
| T35 | /workspace/coverage/default/49.prim_present_test.3154876162 | Feb 29 12:22:21 PM PST 24 | Feb 29 12:23:03 PM PST 24 | 7106440000 ps | ||
| T36 | /workspace/coverage/default/31.prim_present_test.1316968810 | Feb 29 12:20:28 PM PST 24 | Feb 29 12:22:08 PM PST 24 | 14483820000 ps | ||
| T37 | /workspace/coverage/default/18.prim_present_test.4234546836 | Feb 29 12:20:12 PM PST 24 | Feb 29 12:21:28 PM PST 24 | 12749680000 ps | ||
| T38 | /workspace/coverage/default/26.prim_present_test.1717129229 | Feb 29 12:19:52 PM PST 24 | Feb 29 12:20:24 PM PST 24 | 5376640000 ps | ||
| T39 | /workspace/coverage/default/9.prim_present_test.1213939246 | Feb 29 12:16:53 PM PST 24 | Feb 29 12:18:10 PM PST 24 | 13365340000 ps | ||
| T40 | /workspace/coverage/default/46.prim_present_test.2587920250 | Feb 29 12:20:17 PM PST 24 | Feb 29 12:21:27 PM PST 24 | 10345940000 ps | ||
| T41 | /workspace/coverage/default/19.prim_present_test.3210853339 | Feb 29 12:19:52 PM PST 24 | Feb 29 12:20:30 PM PST 24 | 5951380000 ps | ||
| T42 | /workspace/coverage/default/27.prim_present_test.3152226500 | Feb 29 12:20:01 PM PST 24 | Feb 29 12:20:59 PM PST 24 | 8055040000 ps | ||
| T43 | /workspace/coverage/default/21.prim_present_test.296910271 | Feb 29 12:20:36 PM PST 24 | Feb 29 12:21:33 PM PST 24 | 8514460000 ps | ||
| T44 | /workspace/coverage/default/10.prim_present_test.1082475073 | Feb 29 12:19:57 PM PST 24 | Feb 29 12:20:34 PM PST 24 | 6341980000 ps | ||
| T45 | /workspace/coverage/default/5.prim_present_test.1262550365 | Feb 29 12:16:50 PM PST 24 | Feb 29 12:17:44 PM PST 24 | 8596920000 ps | ||
| T46 | /workspace/coverage/default/40.prim_present_test.3661740612 | Feb 29 12:20:25 PM PST 24 | Feb 29 12:21:37 PM PST 24 | 10589600000 ps | ||
| T47 | /workspace/coverage/default/20.prim_present_test.1428002566 | Feb 29 12:23:22 PM PST 24 | Feb 29 12:24:45 PM PST 24 | 14144060000 ps | ||
| T48 | /workspace/coverage/default/37.prim_present_test.266201656 | Feb 29 12:19:57 PM PST 24 | Feb 29 12:21:37 PM PST 24 | 14874420000 ps | ||
| T49 | /workspace/coverage/default/32.prim_present_test.2211581103 | Feb 29 12:25:45 PM PST 24 | Feb 29 12:26:04 PM PST 24 | 3445960000 ps | ||
| T50 | /workspace/coverage/default/43.prim_present_test.696147422 | Feb 29 12:19:54 PM PST 24 | Feb 29 12:20:48 PM PST 24 | 7453640000 ps |
| Test location | /workspace/coverage/default/13.prim_present_test.1594657393 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 4916600000 ps |
| CPU time | 17.21 seconds |
| Started | Feb 29 12:20:31 PM PST 24 |
| Finished | Feb 29 12:21:03 PM PST 24 |
| Peak memory | 145632 kb |
| Host | smart-9048fdb8-1dfe-4115-9d59-db02017a4478 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1594657393 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.1594657393 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/0.prim_present_test.1403212205 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 7696060000 ps |
| CPU time | 26.39 seconds |
| Started | Feb 29 12:16:51 PM PST 24 |
| Finished | Feb 29 12:17:40 PM PST 24 |
| Peak memory | 145600 kb |
| Host | smart-8811c3b9-b182-4577-9dbe-270f5d257852 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1403212205 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.1403212205 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/1.prim_present_test.4073468107 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 8755640000 ps |
| CPU time | 31.86 seconds |
| Started | Feb 29 12:16:59 PM PST 24 |
| Finished | Feb 29 12:18:02 PM PST 24 |
| Peak memory | 145604 kb |
| Host | smart-025f3403-8146-42c8-8178-57f950bab07c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4073468107 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.4073468107 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/10.prim_present_test.1082475073 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 6341980000 ps |
| CPU time | 19.98 seconds |
| Started | Feb 29 12:19:57 PM PST 24 |
| Finished | Feb 29 12:20:34 PM PST 24 |
| Peak memory | 145560 kb |
| Host | smart-f0ee79b0-5a95-4070-b950-a68c0905d3fb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1082475073 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.1082475073 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/11.prim_present_test.2773484219 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 10491020000 ps |
| CPU time | 36.99 seconds |
| Started | Feb 29 12:19:55 PM PST 24 |
| Finished | Feb 29 12:21:03 PM PST 24 |
| Peak memory | 145560 kb |
| Host | smart-b3f27d85-3e6d-4402-9a06-47e191b5652f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2773484219 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.2773484219 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.1494739036 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 3419300000 ps |
| CPU time | 13.34 seconds |
| Started | Feb 29 12:20:03 PM PST 24 |
| Finished | Feb 29 12:20:28 PM PST 24 |
| Peak memory | 145392 kb |
| Host | smart-281962dd-c43a-4858-be59-8fa6c77a881c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1494739036 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.1494739036 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.3587225240 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 5931540000 ps |
| CPU time | 18.27 seconds |
| Started | Feb 29 12:23:13 PM PST 24 |
| Finished | Feb 29 12:23:47 PM PST 24 |
| Peak memory | 144448 kb |
| Host | smart-8c8c75cd-7468-4cdd-b87f-d82dc25cb82f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3587225240 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.3587225240 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.3584883280 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 3627000000 ps |
| CPU time | 12.12 seconds |
| Started | Feb 29 12:19:53 PM PST 24 |
| Finished | Feb 29 12:20:15 PM PST 24 |
| Peak memory | 145340 kb |
| Host | smart-e9fbe408-bf69-404e-a5a0-a21292ae1b39 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3584883280 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.3584883280 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.2333308589 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 3780760000 ps |
| CPU time | 12.39 seconds |
| Started | Feb 29 12:23:22 PM PST 24 |
| Finished | Feb 29 12:23:45 PM PST 24 |
| Peak memory | 146156 kb |
| Host | smart-9cf8dce6-cb86-43db-9d9e-be4eabaf2e0b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2333308589 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.2333308589 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.2983767730 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 3884920000 ps |
| CPU time | 13.25 seconds |
| Started | Feb 29 12:19:55 PM PST 24 |
| Finished | Feb 29 12:20:19 PM PST 24 |
| Peak memory | 145408 kb |
| Host | smart-464cde10-004a-4f3c-9702-3efa5f342f6e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2983767730 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.2983767730 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.4234546836 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 12749680000 ps |
| CPU time | 41.36 seconds |
| Started | Feb 29 12:20:12 PM PST 24 |
| Finished | Feb 29 12:21:28 PM PST 24 |
| Peak memory | 145560 kb |
| Host | smart-b29e1ea7-02d2-417c-946c-751418965cd5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4234546836 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.4234546836 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.3210853339 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 5951380000 ps |
| CPU time | 20.31 seconds |
| Started | Feb 29 12:19:52 PM PST 24 |
| Finished | Feb 29 12:20:30 PM PST 24 |
| Peak memory | 145624 kb |
| Host | smart-79f980ec-2d0f-43c3-8378-fa56a1c2e921 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3210853339 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.3210853339 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.1430270080 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 9768720000 ps |
| CPU time | 32.84 seconds |
| Started | Feb 29 12:16:50 PM PST 24 |
| Finished | Feb 29 12:17:52 PM PST 24 |
| Peak memory | 145632 kb |
| Host | smart-ca6b4590-0e24-4c4e-a056-617c454ff2de |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1430270080 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.1430270080 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.1428002566 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 14144060000 ps |
| CPU time | 45.02 seconds |
| Started | Feb 29 12:23:22 PM PST 24 |
| Finished | Feb 29 12:24:45 PM PST 24 |
| Peak memory | 145032 kb |
| Host | smart-cc506c9f-bcb6-4968-9f8d-fca516e2eefb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1428002566 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.1428002566 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.296910271 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 8514460000 ps |
| CPU time | 30.4 seconds |
| Started | Feb 29 12:20:36 PM PST 24 |
| Finished | Feb 29 12:21:33 PM PST 24 |
| Peak memory | 145768 kb |
| Host | smart-045c1843-cd71-440a-a658-b432e3021519 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=296910271 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.296910271 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.3805524150 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 11290200000 ps |
| CPU time | 34.06 seconds |
| Started | Feb 29 12:23:21 PM PST 24 |
| Finished | Feb 29 12:24:24 PM PST 24 |
| Peak memory | 145036 kb |
| Host | smart-7e920285-edc1-4a23-9c1f-11cfa3f9b7e4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3805524150 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.3805524150 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.1835716838 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 13841500000 ps |
| CPU time | 43.09 seconds |
| Started | Feb 29 12:23:22 PM PST 24 |
| Finished | Feb 29 12:24:41 PM PST 24 |
| Peak memory | 145036 kb |
| Host | smart-ed904c0f-78f9-4c83-9614-fdea28cf5760 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1835716838 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.1835716838 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.2175899636 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 15225960000 ps |
| CPU time | 48.56 seconds |
| Started | Feb 29 12:23:22 PM PST 24 |
| Finished | Feb 29 12:24:51 PM PST 24 |
| Peak memory | 145032 kb |
| Host | smart-d6aacb41-a295-4d8f-a69e-0a911dcd3a02 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2175899636 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.2175899636 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.917919170 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 14385860000 ps |
| CPU time | 48.51 seconds |
| Started | Feb 29 12:19:55 PM PST 24 |
| Finished | Feb 29 12:21:26 PM PST 24 |
| Peak memory | 145504 kb |
| Host | smart-ef632c0c-2483-4d2c-a57a-bbf2d2776374 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=917919170 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.917919170 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.1717129229 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 5376640000 ps |
| CPU time | 16.69 seconds |
| Started | Feb 29 12:19:52 PM PST 24 |
| Finished | Feb 29 12:20:24 PM PST 24 |
| Peak memory | 145520 kb |
| Host | smart-e5e64195-b4ef-45be-912f-463a22e87f2d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1717129229 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.1717129229 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.3152226500 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 8055040000 ps |
| CPU time | 30.72 seconds |
| Started | Feb 29 12:20:01 PM PST 24 |
| Finished | Feb 29 12:20:59 PM PST 24 |
| Peak memory | 145540 kb |
| Host | smart-be561401-1392-4da4-9539-bbaa31a8ebba |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3152226500 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.3152226500 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.1394557202 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 8080460000 ps |
| CPU time | 26.64 seconds |
| Started | Feb 29 12:19:55 PM PST 24 |
| Finished | Feb 29 12:20:45 PM PST 24 |
| Peak memory | 145504 kb |
| Host | smart-f7a72fab-a5c2-476a-9a5a-d74f8d9630d5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1394557202 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.1394557202 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.439368421 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 10757620000 ps |
| CPU time | 40.84 seconds |
| Started | Feb 29 12:20:20 PM PST 24 |
| Finished | Feb 29 12:21:37 PM PST 24 |
| Peak memory | 145536 kb |
| Host | smart-1dc672a6-96c6-4e92-aee6-35d953757638 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=439368421 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.439368421 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.1348775856 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 15065380000 ps |
| CPU time | 46.93 seconds |
| Started | Feb 29 12:16:55 PM PST 24 |
| Finished | Feb 29 12:18:20 PM PST 24 |
| Peak memory | 145604 kb |
| Host | smart-7f81f1bd-91b9-4f03-ab1a-0cdac2d6bba0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1348775856 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.1348775856 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.3483320492 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 13767720000 ps |
| CPU time | 36.07 seconds |
| Started | Feb 29 12:22:53 PM PST 24 |
| Finished | Feb 29 12:23:58 PM PST 24 |
| Peak memory | 145052 kb |
| Host | smart-0b7414e7-b7b7-442d-9acb-73732bad90cb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3483320492 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.3483320492 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.1316968810 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 14483820000 ps |
| CPU time | 53.6 seconds |
| Started | Feb 29 12:20:28 PM PST 24 |
| Finished | Feb 29 12:22:08 PM PST 24 |
| Peak memory | 145500 kb |
| Host | smart-1707370f-0705-436c-8748-ab326aea5eee |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1316968810 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.1316968810 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.2211581103 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 3445960000 ps |
| CPU time | 10.29 seconds |
| Started | Feb 29 12:25:45 PM PST 24 |
| Finished | Feb 29 12:26:04 PM PST 24 |
| Peak memory | 144884 kb |
| Host | smart-417a9b10-4eed-420e-9c90-dece91b4f93e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2211581103 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.2211581103 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.2616533873 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 7543540000 ps |
| CPU time | 21.11 seconds |
| Started | Feb 29 12:22:46 PM PST 24 |
| Finished | Feb 29 12:23:24 PM PST 24 |
| Peak memory | 145740 kb |
| Host | smart-02820ad1-b987-4d24-a02a-007abd16bcbb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2616533873 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.2616533873 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.723502165 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 3462080000 ps |
| CPU time | 10.64 seconds |
| Started | Feb 29 12:25:35 PM PST 24 |
| Finished | Feb 29 12:25:55 PM PST 24 |
| Peak memory | 144300 kb |
| Host | smart-19369d8e-27f6-4852-919d-3cbcddc60a08 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=723502165 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.723502165 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.3646572467 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 3465800000 ps |
| CPU time | 12.93 seconds |
| Started | Feb 29 12:20:28 PM PST 24 |
| Finished | Feb 29 12:20:52 PM PST 24 |
| Peak memory | 145460 kb |
| Host | smart-ad1ba7da-b78e-4e88-9786-ecea8d8b6953 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3646572467 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.3646572467 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.1152289753 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 12109840000 ps |
| CPU time | 41.45 seconds |
| Started | Feb 29 12:19:57 PM PST 24 |
| Finished | Feb 29 12:21:14 PM PST 24 |
| Peak memory | 145560 kb |
| Host | smart-0e4cc39a-e490-4e2c-b4eb-d3d6292998c5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1152289753 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.1152289753 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.266201656 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 14874420000 ps |
| CPU time | 53.82 seconds |
| Started | Feb 29 12:19:57 PM PST 24 |
| Finished | Feb 29 12:21:37 PM PST 24 |
| Peak memory | 145620 kb |
| Host | smart-5231fb50-8a99-424c-a72b-22fc54ae37e0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=266201656 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.266201656 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.2035278294 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 8634740000 ps |
| CPU time | 30.65 seconds |
| Started | Feb 29 12:20:19 PM PST 24 |
| Finished | Feb 29 12:21:17 PM PST 24 |
| Peak memory | 145768 kb |
| Host | smart-482f9e96-2912-4a98-96aa-041758c29def |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2035278294 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.2035278294 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.379759802 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 13954340000 ps |
| CPU time | 50.77 seconds |
| Started | Feb 29 12:20:15 PM PST 24 |
| Finished | Feb 29 12:21:50 PM PST 24 |
| Peak memory | 145576 kb |
| Host | smart-389323a9-2bad-4a5c-9c40-b79ad4983e47 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=379759802 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.379759802 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.1283303445 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 14096940000 ps |
| CPU time | 45.11 seconds |
| Started | Feb 29 12:16:51 PM PST 24 |
| Finished | Feb 29 12:18:14 PM PST 24 |
| Peak memory | 145484 kb |
| Host | smart-984e440d-56c2-405f-ae52-305b5bac6a01 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1283303445 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.1283303445 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.3661740612 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 10589600000 ps |
| CPU time | 38.24 seconds |
| Started | Feb 29 12:20:25 PM PST 24 |
| Finished | Feb 29 12:21:37 PM PST 24 |
| Peak memory | 145640 kb |
| Host | smart-3ad7d7fa-073d-4b1d-bd49-62cddea08708 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3661740612 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.3661740612 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.3183903177 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 12596540000 ps |
| CPU time | 44.86 seconds |
| Started | Feb 29 12:20:17 PM PST 24 |
| Finished | Feb 29 12:21:42 PM PST 24 |
| Peak memory | 145548 kb |
| Host | smart-0fbfb12a-b3da-4b15-b587-5cb8ec7f4f8a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3183903177 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.3183903177 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.1246552959 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 10074380000 ps |
| CPU time | 35.77 seconds |
| Started | Feb 29 12:19:57 PM PST 24 |
| Finished | Feb 29 12:21:04 PM PST 24 |
| Peak memory | 145548 kb |
| Host | smart-70f575b7-10f2-4f9c-982b-b001e52b4db8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1246552959 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.1246552959 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.696147422 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 7453640000 ps |
| CPU time | 28.43 seconds |
| Started | Feb 29 12:19:54 PM PST 24 |
| Finished | Feb 29 12:20:48 PM PST 24 |
| Peak memory | 145628 kb |
| Host | smart-5ec42253-57e2-472a-9a4d-76e81dca8ca6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=696147422 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.696147422 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.2789866859 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 7007240000 ps |
| CPU time | 26.3 seconds |
| Started | Feb 29 12:20:17 PM PST 24 |
| Finished | Feb 29 12:21:07 PM PST 24 |
| Peak memory | 145552 kb |
| Host | smart-a9312c38-6fa4-42b1-b1b8-8c3e02540401 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2789866859 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.2789866859 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.1168373494 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 5652540000 ps |
| CPU time | 21.03 seconds |
| Started | Feb 29 12:20:01 PM PST 24 |
| Finished | Feb 29 12:20:39 PM PST 24 |
| Peak memory | 145560 kb |
| Host | smart-bd116e4e-fbfe-4f2d-9815-0d5e872f9b66 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1168373494 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.1168373494 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.2587920250 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 10345940000 ps |
| CPU time | 36.69 seconds |
| Started | Feb 29 12:20:17 PM PST 24 |
| Finished | Feb 29 12:21:27 PM PST 24 |
| Peak memory | 145548 kb |
| Host | smart-9bb8646f-4609-4a49-a684-bd9d032c4252 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2587920250 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.2587920250 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.1403823341 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 9286980000 ps |
| CPU time | 30.36 seconds |
| Started | Feb 29 12:19:52 PM PST 24 |
| Finished | Feb 29 12:20:48 PM PST 24 |
| Peak memory | 145648 kb |
| Host | smart-3a854fdf-453a-4de6-8d4b-d55ba67ad9db |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1403823341 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.1403823341 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.683572193 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 14785760000 ps |
| CPU time | 52.82 seconds |
| Started | Feb 29 12:19:55 PM PST 24 |
| Finished | Feb 29 12:21:33 PM PST 24 |
| Peak memory | 145560 kb |
| Host | smart-fd2cdfb7-00a0-4a6a-9dd1-94379c0f0783 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=683572193 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.683572193 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.3154876162 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 7106440000 ps |
| CPU time | 21.77 seconds |
| Started | Feb 29 12:22:21 PM PST 24 |
| Finished | Feb 29 12:23:03 PM PST 24 |
| Peak memory | 145724 kb |
| Host | smart-de027da7-4bc3-4399-b3a2-3e5b9457643a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3154876162 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.3154876162 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.1262550365 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 8596920000 ps |
| CPU time | 29.12 seconds |
| Started | Feb 29 12:16:50 PM PST 24 |
| Finished | Feb 29 12:17:44 PM PST 24 |
| Peak memory | 145632 kb |
| Host | smart-eb01a649-890a-4326-afd2-aebfa439a2b6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1262550365 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.1262550365 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.755431225 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 7198820000 ps |
| CPU time | 21.76 seconds |
| Started | Feb 29 12:16:52 PM PST 24 |
| Finished | Feb 29 12:17:32 PM PST 24 |
| Peak memory | 145580 kb |
| Host | smart-fb868b82-b7e5-453f-8d5b-6f8c0e25adc5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=755431225 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.755431225 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.3881854842 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 4365420000 ps |
| CPU time | 14.62 seconds |
| Started | Feb 29 12:16:54 PM PST 24 |
| Finished | Feb 29 12:17:21 PM PST 24 |
| Peak memory | 145568 kb |
| Host | smart-b302b438-34b6-4f01-a3e6-c67b804be65b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3881854842 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.3881854842 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.674407373 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 8784160000 ps |
| CPU time | 28.04 seconds |
| Started | Feb 29 12:16:54 PM PST 24 |
| Finished | Feb 29 12:17:45 PM PST 24 |
| Peak memory | 145568 kb |
| Host | smart-7f8c48ea-d2ba-494b-acce-4b3fee9f64ed |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=674407373 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.674407373 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.1213939246 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 13365340000 ps |
| CPU time | 41.89 seconds |
| Started | Feb 29 12:16:53 PM PST 24 |
| Finished | Feb 29 12:18:10 PM PST 24 |
| Peak memory | 145560 kb |
| Host | smart-b6f0fcb7-7006-495f-b30b-f51af486e301 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1213939246 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.1213939246 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |