| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/10.prim_present_test.3008010177 | ||
| Name |
|---|
| /workspace/coverage/default/0.prim_present_test.3205363012 |
| /workspace/coverage/default/1.prim_present_test.2239314302 |
| /workspace/coverage/default/11.prim_present_test.2388353820 |
| /workspace/coverage/default/12.prim_present_test.4046577405 |
| /workspace/coverage/default/13.prim_present_test.2111195164 |
| /workspace/coverage/default/14.prim_present_test.1876541586 |
| /workspace/coverage/default/15.prim_present_test.401051395 |
| /workspace/coverage/default/16.prim_present_test.2877681060 |
| /workspace/coverage/default/17.prim_present_test.1717545300 |
| /workspace/coverage/default/18.prim_present_test.874040577 |
| /workspace/coverage/default/19.prim_present_test.1448817905 |
| /workspace/coverage/default/2.prim_present_test.968240110 |
| /workspace/coverage/default/20.prim_present_test.989243486 |
| /workspace/coverage/default/21.prim_present_test.1584229754 |
| /workspace/coverage/default/22.prim_present_test.891896 |
| /workspace/coverage/default/23.prim_present_test.72332662 |
| /workspace/coverage/default/24.prim_present_test.3465198291 |
| /workspace/coverage/default/25.prim_present_test.2609130081 |
| /workspace/coverage/default/26.prim_present_test.658995771 |
| /workspace/coverage/default/27.prim_present_test.521956475 |
| /workspace/coverage/default/28.prim_present_test.2041207519 |
| /workspace/coverage/default/29.prim_present_test.1715395570 |
| /workspace/coverage/default/3.prim_present_test.2917712572 |
| /workspace/coverage/default/30.prim_present_test.796848004 |
| /workspace/coverage/default/31.prim_present_test.1052955374 |
| /workspace/coverage/default/32.prim_present_test.220186900 |
| /workspace/coverage/default/33.prim_present_test.1932539212 |
| /workspace/coverage/default/34.prim_present_test.2359158622 |
| /workspace/coverage/default/35.prim_present_test.3676237468 |
| /workspace/coverage/default/36.prim_present_test.2197376892 |
| /workspace/coverage/default/37.prim_present_test.4091298344 |
| /workspace/coverage/default/38.prim_present_test.3042966821 |
| /workspace/coverage/default/39.prim_present_test.3497677646 |
| /workspace/coverage/default/4.prim_present_test.1226178245 |
| /workspace/coverage/default/40.prim_present_test.1540687233 |
| /workspace/coverage/default/41.prim_present_test.1597372930 |
| /workspace/coverage/default/42.prim_present_test.3931182842 |
| /workspace/coverage/default/43.prim_present_test.2105886215 |
| /workspace/coverage/default/44.prim_present_test.3339081446 |
| /workspace/coverage/default/45.prim_present_test.1682293517 |
| /workspace/coverage/default/46.prim_present_test.151706283 |
| /workspace/coverage/default/47.prim_present_test.1052456703 |
| /workspace/coverage/default/48.prim_present_test.1081921668 |
| /workspace/coverage/default/49.prim_present_test.3488726361 |
| /workspace/coverage/default/5.prim_present_test.1425380521 |
| /workspace/coverage/default/6.prim_present_test.2867217466 |
| /workspace/coverage/default/7.prim_present_test.4252950414 |
| /workspace/coverage/default/8.prim_present_test.1181740077 |
| /workspace/coverage/default/9.prim_present_test.2734707714 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/36.prim_present_test.2197376892 | Mar 03 01:04:57 PM PST 24 | Mar 03 01:06:48 PM PST 24 | 15340040000 ps | ||
| T2 | /workspace/coverage/default/35.prim_present_test.3676237468 | Mar 03 01:04:54 PM PST 24 | Mar 03 01:06:18 PM PST 24 | 14650600000 ps | ||
| T3 | /workspace/coverage/default/19.prim_present_test.1448817905 | Mar 03 01:04:18 PM PST 24 | Mar 03 01:05:25 PM PST 24 | 8990620000 ps | ||
| T4 | /workspace/coverage/default/16.prim_present_test.2877681060 | Mar 03 01:04:17 PM PST 24 | Mar 03 01:06:01 PM PST 24 | 15294780000 ps | ||
| T5 | /workspace/coverage/default/25.prim_present_test.2609130081 | Mar 03 01:04:33 PM PST 24 | Mar 03 01:05:10 PM PST 24 | 4408200000 ps | ||
| T6 | /workspace/coverage/default/9.prim_present_test.2734707714 | Mar 03 01:04:11 PM PST 24 | Mar 03 01:05:28 PM PST 24 | 10299440000 ps | ||
| T7 | /workspace/coverage/default/10.prim_present_test.3008010177 | Mar 03 01:04:12 PM PST 24 | Mar 03 01:06:04 PM PST 24 | 13245060000 ps | ||
| T8 | /workspace/coverage/default/48.prim_present_test.1081921668 | Mar 03 01:05:24 PM PST 24 | Mar 03 01:06:33 PM PST 24 | 8298080000 ps | ||
| T9 | /workspace/coverage/default/24.prim_present_test.3465198291 | Mar 03 01:04:33 PM PST 24 | Mar 03 01:05:36 PM PST 24 | 10546200000 ps | ||
| T10 | /workspace/coverage/default/27.prim_present_test.521956475 | Mar 03 01:04:34 PM PST 24 | Mar 03 01:05:03 PM PST 24 | 3297780000 ps | ||
| T11 | /workspace/coverage/default/8.prim_present_test.1181740077 | Mar 03 01:04:10 PM PST 24 | Mar 03 01:05:42 PM PST 24 | 10420960000 ps | ||
| T12 | /workspace/coverage/default/7.prim_present_test.4252950414 | Mar 03 01:04:11 PM PST 24 | Mar 03 01:05:48 PM PST 24 | 14240780000 ps | ||
| T13 | /workspace/coverage/default/33.prim_present_test.1932539212 | Mar 03 01:04:42 PM PST 24 | Mar 03 01:06:33 PM PST 24 | 14490640000 ps | ||
| T14 | /workspace/coverage/default/39.prim_present_test.3497677646 | Mar 03 01:05:01 PM PST 24 | Mar 03 01:06:16 PM PST 24 | 10336640000 ps | ||
| T15 | /workspace/coverage/default/11.prim_present_test.2388353820 | Mar 03 01:04:11 PM PST 24 | Mar 03 01:05:35 PM PST 24 | 9989440000 ps | ||
| T16 | /workspace/coverage/default/20.prim_present_test.989243486 | Mar 03 01:04:27 PM PST 24 | Mar 03 01:05:45 PM PST 24 | 12013740000 ps | ||
| T17 | /workspace/coverage/default/15.prim_present_test.401051395 | Mar 03 01:04:20 PM PST 24 | Mar 03 01:05:49 PM PST 24 | 11328020000 ps | ||
| T18 | /workspace/coverage/default/0.prim_present_test.3205363012 | Mar 03 01:03:53 PM PST 24 | Mar 03 01:06:03 PM PST 24 | 14627040000 ps | ||
| T19 | /workspace/coverage/default/12.prim_present_test.4046577405 | Mar 03 01:04:10 PM PST 24 | Mar 03 01:04:51 PM PST 24 | 5241480000 ps | ||
| T20 | /workspace/coverage/default/42.prim_present_test.3931182842 | Mar 03 01:05:10 PM PST 24 | Mar 03 01:05:44 PM PST 24 | 4553280000 ps | ||
| T21 | /workspace/coverage/default/1.prim_present_test.2239314302 | Mar 03 01:03:53 PM PST 24 | Mar 03 01:05:41 PM PST 24 | 13649300000 ps | ||
| T22 | /workspace/coverage/default/37.prim_present_test.4091298344 | Mar 03 01:04:55 PM PST 24 | Mar 03 01:06:36 PM PST 24 | 13103700000 ps | ||
| T23 | /workspace/coverage/default/40.prim_present_test.1540687233 | Mar 03 01:05:10 PM PST 24 | Mar 03 01:06:40 PM PST 24 | 12394420000 ps | ||
| T24 | /workspace/coverage/default/31.prim_present_test.1052955374 | Mar 03 01:04:42 PM PST 24 | Mar 03 01:05:38 PM PST 24 | 6496360000 ps | ||
| T25 | /workspace/coverage/default/23.prim_present_test.72332662 | Mar 03 01:04:34 PM PST 24 | Mar 03 01:05:33 PM PST 24 | 7842380000 ps | ||
| T26 | /workspace/coverage/default/32.prim_present_test.220186900 | Mar 03 01:04:41 PM PST 24 | Mar 03 01:05:35 PM PST 24 | 6077860000 ps | ||
| T27 | /workspace/coverage/default/34.prim_present_test.2359158622 | Mar 03 01:04:41 PM PST 24 | Mar 03 01:05:05 PM PST 24 | 3266780000 ps | ||
| T28 | /workspace/coverage/default/49.prim_present_test.3488726361 | Mar 03 01:05:24 PM PST 24 | Mar 03 01:06:43 PM PST 24 | 9508320000 ps | ||
| T29 | /workspace/coverage/default/47.prim_present_test.1052456703 | Mar 03 01:05:18 PM PST 24 | Mar 03 01:06:09 PM PST 24 | 7839280000 ps | ||
| T30 | /workspace/coverage/default/22.prim_present_test.891896 | Mar 03 01:04:33 PM PST 24 | Mar 03 01:05:03 PM PST 24 | 3909100000 ps | ||
| T31 | /workspace/coverage/default/21.prim_present_test.1584229754 | Mar 03 01:04:26 PM PST 24 | Mar 03 01:04:53 PM PST 24 | 3414960000 ps | ||
| T32 | /workspace/coverage/default/28.prim_present_test.2041207519 | Mar 03 01:04:32 PM PST 24 | Mar 03 01:06:25 PM PST 24 | 12553140000 ps | ||
| T33 | /workspace/coverage/default/18.prim_present_test.874040577 | Mar 03 01:04:18 PM PST 24 | Mar 03 01:06:05 PM PST 24 | 14672300000 ps | ||
| T34 | /workspace/coverage/default/38.prim_present_test.3042966821 | Mar 03 01:05:08 PM PST 24 | Mar 03 01:05:43 PM PST 24 | 5315880000 ps | ||
| T35 | /workspace/coverage/default/45.prim_present_test.1682293517 | Mar 03 01:05:16 PM PST 24 | Mar 03 01:06:13 PM PST 24 | 7007860000 ps | ||
| T36 | /workspace/coverage/default/17.prim_present_test.1717545300 | Mar 03 01:04:18 PM PST 24 | Mar 03 01:05:56 PM PST 24 | 12121000000 ps | ||
| T37 | /workspace/coverage/default/26.prim_present_test.658995771 | Mar 03 01:04:33 PM PST 24 | Mar 03 01:05:14 PM PST 24 | 5772200000 ps | ||
| T38 | /workspace/coverage/default/29.prim_present_test.1715395570 | Mar 03 01:04:33 PM PST 24 | Mar 03 01:06:01 PM PST 24 | 12050320000 ps | ||
| T39 | /workspace/coverage/default/30.prim_present_test.796848004 | Mar 03 01:04:41 PM PST 24 | Mar 03 01:05:36 PM PST 24 | 6376700000 ps | ||
| T40 | /workspace/coverage/default/5.prim_present_test.1425380521 | Mar 03 01:04:02 PM PST 24 | Mar 03 01:04:53 PM PST 24 | 7745040000 ps | ||
| T41 | /workspace/coverage/default/6.prim_present_test.2867217466 | Mar 03 01:04:01 PM PST 24 | Mar 03 01:05:48 PM PST 24 | 14545200000 ps | ||
| T42 | /workspace/coverage/default/14.prim_present_test.1876541586 | Mar 03 01:04:17 PM PST 24 | Mar 03 01:06:01 PM PST 24 | 12623820000 ps | ||
| T43 | /workspace/coverage/default/13.prim_present_test.2111195164 | Mar 03 01:04:11 PM PST 24 | Mar 03 01:05:56 PM PST 24 | 12479360000 ps | ||
| T44 | /workspace/coverage/default/2.prim_present_test.968240110 | Mar 03 01:03:54 PM PST 24 | Mar 03 01:04:38 PM PST 24 | 6870220000 ps | ||
| T45 | /workspace/coverage/default/46.prim_present_test.151706283 | Mar 03 01:05:16 PM PST 24 | Mar 03 01:06:58 PM PST 24 | 12348540000 ps | ||
| T46 | /workspace/coverage/default/3.prim_present_test.2917712572 | Mar 03 01:04:00 PM PST 24 | Mar 03 01:06:02 PM PST 24 | 15243320000 ps | ||
| T47 | /workspace/coverage/default/4.prim_present_test.1226178245 | Mar 03 01:04:01 PM PST 24 | Mar 03 01:04:51 PM PST 24 | 6539760000 ps | ||
| T48 | /workspace/coverage/default/43.prim_present_test.2105886215 | Mar 03 01:05:17 PM PST 24 | Mar 03 01:06:53 PM PST 24 | 12161920000 ps | ||
| T49 | /workspace/coverage/default/41.prim_present_test.1597372930 | Mar 03 01:05:10 PM PST 24 | Mar 03 01:06:31 PM PST 24 | 9515760000 ps | ||
| T50 | /workspace/coverage/default/44.prim_present_test.3339081446 | Mar 03 01:05:17 PM PST 24 | Mar 03 01:06:18 PM PST 24 | 7572060000 ps |
| Test location | /workspace/coverage/default/10.prim_present_test.3008010177 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 13245060000 ps |
| CPU time | 57.52 seconds |
| Started | Mar 03 01:04:12 PM PST 24 |
| Finished | Mar 03 01:06:04 PM PST 24 |
| Peak memory | 145608 kb |
| Host | smart-0cfbf29d-cf19-4b2b-99d6-72d047807340 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3008010177 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.3008010177 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/0.prim_present_test.3205363012 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 14627040000 ps |
| CPU time | 62.71 seconds |
| Started | Mar 03 01:03:53 PM PST 24 |
| Finished | Mar 03 01:06:03 PM PST 24 |
| Peak memory | 145576 kb |
| Host | smart-6d5a5c48-684c-4a1b-a117-154eea5287c7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3205363012 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.3205363012 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/1.prim_present_test.2239314302 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 13649300000 ps |
| CPU time | 54.54 seconds |
| Started | Mar 03 01:03:53 PM PST 24 |
| Finished | Mar 03 01:05:41 PM PST 24 |
| Peak memory | 145688 kb |
| Host | smart-647dae02-49b0-4b61-8a56-3c5e4149fd16 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2239314302 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.2239314302 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/11.prim_present_test.2388353820 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 9989440000 ps |
| CPU time | 41.53 seconds |
| Started | Mar 03 01:04:11 PM PST 24 |
| Finished | Mar 03 01:05:35 PM PST 24 |
| Peak memory | 145596 kb |
| Host | smart-0c8e1312-8369-48e3-b3ff-48a49582c804 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2388353820 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.2388353820 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.4046577405 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 5241480000 ps |
| CPU time | 20.44 seconds |
| Started | Mar 03 01:04:10 PM PST 24 |
| Finished | Mar 03 01:04:51 PM PST 24 |
| Peak memory | 145528 kb |
| Host | smart-6f442a29-1345-4b35-9eb4-6f728cecfe50 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4046577405 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.4046577405 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.2111195164 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 12479360000 ps |
| CPU time | 51.84 seconds |
| Started | Mar 03 01:04:11 PM PST 24 |
| Finished | Mar 03 01:05:56 PM PST 24 |
| Peak memory | 145676 kb |
| Host | smart-b2a6e1ee-d00b-4fc0-bf71-f57936c19d67 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2111195164 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.2111195164 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.1876541586 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 12623820000 ps |
| CPU time | 52.13 seconds |
| Started | Mar 03 01:04:17 PM PST 24 |
| Finished | Mar 03 01:06:01 PM PST 24 |
| Peak memory | 145680 kb |
| Host | smart-9dd8e26e-5af4-46ed-9cfe-9c7d66bb5918 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1876541586 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.1876541586 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.401051395 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 11328020000 ps |
| CPU time | 43.23 seconds |
| Started | Mar 03 01:04:20 PM PST 24 |
| Finished | Mar 03 01:05:49 PM PST 24 |
| Peak memory | 145676 kb |
| Host | smart-987ff327-81bc-4709-a882-84984617b03b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=401051395 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.401051395 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.2877681060 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 15294780000 ps |
| CPU time | 56.25 seconds |
| Started | Mar 03 01:04:17 PM PST 24 |
| Finished | Mar 03 01:06:01 PM PST 24 |
| Peak memory | 145680 kb |
| Host | smart-289490b3-d458-4b15-92e7-8ab9fb96427b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2877681060 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.2877681060 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.1717545300 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 12121000000 ps |
| CPU time | 48.59 seconds |
| Started | Mar 03 01:04:18 PM PST 24 |
| Finished | Mar 03 01:05:56 PM PST 24 |
| Peak memory | 145664 kb |
| Host | smart-fd4bc95f-a841-479d-a506-fa4541beb98e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1717545300 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.1717545300 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.874040577 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 14672300000 ps |
| CPU time | 53.79 seconds |
| Started | Mar 03 01:04:18 PM PST 24 |
| Finished | Mar 03 01:06:05 PM PST 24 |
| Peak memory | 145680 kb |
| Host | smart-22845634-1150-42d9-a84f-0b647caf19c4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=874040577 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.874040577 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.1448817905 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 8990620000 ps |
| CPU time | 34.94 seconds |
| Started | Mar 03 01:04:18 PM PST 24 |
| Finished | Mar 03 01:05:25 PM PST 24 |
| Peak memory | 145792 kb |
| Host | smart-5543f14f-7e0b-4fc7-b1d9-c00ff94b652b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1448817905 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.1448817905 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.968240110 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 6870220000 ps |
| CPU time | 24.15 seconds |
| Started | Mar 03 01:03:54 PM PST 24 |
| Finished | Mar 03 01:04:38 PM PST 24 |
| Peak memory | 145608 kb |
| Host | smart-e3bc8a87-9108-4b28-8219-2a57adcb1b3b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=968240110 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.968240110 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.989243486 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 12013740000 ps |
| CPU time | 41.42 seconds |
| Started | Mar 03 01:04:27 PM PST 24 |
| Finished | Mar 03 01:05:45 PM PST 24 |
| Peak memory | 145684 kb |
| Host | smart-3821ac65-9c44-4281-ba92-5fc233edaf25 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=989243486 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.989243486 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.1584229754 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 3414960000 ps |
| CPU time | 14.03 seconds |
| Started | Mar 03 01:04:26 PM PST 24 |
| Finished | Mar 03 01:04:53 PM PST 24 |
| Peak memory | 145424 kb |
| Host | smart-1f45fe99-1d89-4e48-9a89-cc4cfd61f0a3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1584229754 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.1584229754 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.891896 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 3909100000 ps |
| CPU time | 14.76 seconds |
| Started | Mar 03 01:04:33 PM PST 24 |
| Finished | Mar 03 01:05:03 PM PST 24 |
| Peak memory | 145392 kb |
| Host | smart-a4ef8efc-a932-4f1f-b50a-731b7ec56340 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=891896 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace /coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.891896 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.72332662 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 7842380000 ps |
| CPU time | 31.21 seconds |
| Started | Mar 03 01:04:34 PM PST 24 |
| Finished | Mar 03 01:05:33 PM PST 24 |
| Peak memory | 145680 kb |
| Host | smart-4589b189-3bb7-4a3f-abb9-c65a98e7b140 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=72332662 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.72332662 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.3465198291 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 10546200000 ps |
| CPU time | 33.86 seconds |
| Started | Mar 03 01:04:33 PM PST 24 |
| Finished | Mar 03 01:05:36 PM PST 24 |
| Peak memory | 145676 kb |
| Host | smart-0d053f1a-98d1-4c0e-bc35-4072c639514b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3465198291 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.3465198291 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.2609130081 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 4408200000 ps |
| CPU time | 18.34 seconds |
| Started | Mar 03 01:04:33 PM PST 24 |
| Finished | Mar 03 01:05:10 PM PST 24 |
| Peak memory | 145692 kb |
| Host | smart-eaf93fb3-a317-4e54-b741-db581e54b373 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2609130081 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.2609130081 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.658995771 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 5772200000 ps |
| CPU time | 21.76 seconds |
| Started | Mar 03 01:04:33 PM PST 24 |
| Finished | Mar 03 01:05:14 PM PST 24 |
| Peak memory | 145684 kb |
| Host | smart-86404bc5-5d77-4dd3-90aa-5db9d779bda9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=658995771 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.658995771 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.521956475 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 3297780000 ps |
| CPU time | 14.66 seconds |
| Started | Mar 03 01:04:34 PM PST 24 |
| Finished | Mar 03 01:05:03 PM PST 24 |
| Peak memory | 145512 kb |
| Host | smart-8f1e4316-5490-4387-b688-9699f72bcb4b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=521956475 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.521956475 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.2041207519 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 12553140000 ps |
| CPU time | 54.58 seconds |
| Started | Mar 03 01:04:32 PM PST 24 |
| Finished | Mar 03 01:06:25 PM PST 24 |
| Peak memory | 145688 kb |
| Host | smart-1048b35d-b60d-48dc-ace6-aaad34409542 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2041207519 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.2041207519 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.1715395570 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 12050320000 ps |
| CPU time | 44.43 seconds |
| Started | Mar 03 01:04:33 PM PST 24 |
| Finished | Mar 03 01:06:01 PM PST 24 |
| Peak memory | 145660 kb |
| Host | smart-92fbc3ab-11a8-4664-9919-481c1032170f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1715395570 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.1715395570 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.2917712572 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 15243320000 ps |
| CPU time | 62.42 seconds |
| Started | Mar 03 01:04:00 PM PST 24 |
| Finished | Mar 03 01:06:02 PM PST 24 |
| Peak memory | 145680 kb |
| Host | smart-b00e5756-d0f6-416a-a632-36e4e46a3dc2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2917712572 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.2917712572 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.796848004 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 6376700000 ps |
| CPU time | 26.98 seconds |
| Started | Mar 03 01:04:41 PM PST 24 |
| Finished | Mar 03 01:05:36 PM PST 24 |
| Peak memory | 145672 kb |
| Host | smart-e660198b-86ae-41ea-bf12-d74b603da1eb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=796848004 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.796848004 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.1052955374 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 6496360000 ps |
| CPU time | 28.31 seconds |
| Started | Mar 03 01:04:42 PM PST 24 |
| Finished | Mar 03 01:05:38 PM PST 24 |
| Peak memory | 145664 kb |
| Host | smart-d54a5ec3-0962-48f2-a546-10aa17b223bf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1052955374 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.1052955374 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.220186900 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 6077860000 ps |
| CPU time | 26.02 seconds |
| Started | Mar 03 01:04:41 PM PST 24 |
| Finished | Mar 03 01:05:35 PM PST 24 |
| Peak memory | 145672 kb |
| Host | smart-7cf1ca75-dd89-4d3b-8b87-728138bd91b5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=220186900 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.220186900 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.1932539212 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 14490640000 ps |
| CPU time | 55.8 seconds |
| Started | Mar 03 01:04:42 PM PST 24 |
| Finished | Mar 03 01:06:33 PM PST 24 |
| Peak memory | 145672 kb |
| Host | smart-f4c845bb-7949-4e67-8d0f-6e004826c651 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1932539212 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.1932539212 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.2359158622 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 3266780000 ps |
| CPU time | 12.73 seconds |
| Started | Mar 03 01:04:41 PM PST 24 |
| Finished | Mar 03 01:05:05 PM PST 24 |
| Peak memory | 145536 kb |
| Host | smart-8443036f-d82e-49ac-be75-13417c2bf440 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2359158622 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.2359158622 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.3676237468 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 14650600000 ps |
| CPU time | 45.7 seconds |
| Started | Mar 03 01:04:54 PM PST 24 |
| Finished | Mar 03 01:06:18 PM PST 24 |
| Peak memory | 145676 kb |
| Host | smart-5268ff30-dfaf-43cc-a5f1-29265e205d24 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3676237468 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.3676237468 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.2197376892 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 15340040000 ps |
| CPU time | 56.76 seconds |
| Started | Mar 03 01:04:57 PM PST 24 |
| Finished | Mar 03 01:06:48 PM PST 24 |
| Peak memory | 145672 kb |
| Host | smart-4970dea5-9d65-4742-bdc2-6444b64e9fda |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2197376892 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.2197376892 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.4091298344 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 13103700000 ps |
| CPU time | 50.23 seconds |
| Started | Mar 03 01:04:55 PM PST 24 |
| Finished | Mar 03 01:06:36 PM PST 24 |
| Peak memory | 145716 kb |
| Host | smart-bdc6eaf4-557f-40b3-bb85-5d426d5ea849 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4091298344 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.4091298344 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.3042966821 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 5315880000 ps |
| CPU time | 18.78 seconds |
| Started | Mar 03 01:05:08 PM PST 24 |
| Finished | Mar 03 01:05:43 PM PST 24 |
| Peak memory | 145664 kb |
| Host | smart-6b413d1d-e18c-4260-882b-78534e7d3241 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3042966821 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.3042966821 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.3497677646 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 10336640000 ps |
| CPU time | 39.09 seconds |
| Started | Mar 03 01:05:01 PM PST 24 |
| Finished | Mar 03 01:06:16 PM PST 24 |
| Peak memory | 145684 kb |
| Host | smart-4a924851-c77e-456e-b433-548eb50e63ff |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3497677646 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.3497677646 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.1226178245 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 6539760000 ps |
| CPU time | 24.85 seconds |
| Started | Mar 03 01:04:01 PM PST 24 |
| Finished | Mar 03 01:04:51 PM PST 24 |
| Peak memory | 145688 kb |
| Host | smart-2f850e4a-81d4-4618-a741-f996c0bee762 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1226178245 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.1226178245 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.1540687233 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 12394420000 ps |
| CPU time | 47.01 seconds |
| Started | Mar 03 01:05:10 PM PST 24 |
| Finished | Mar 03 01:06:40 PM PST 24 |
| Peak memory | 145676 kb |
| Host | smart-2742155d-6e30-4d5b-aec1-176a7c7c4513 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1540687233 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.1540687233 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.1597372930 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 9515760000 ps |
| CPU time | 41.71 seconds |
| Started | Mar 03 01:05:10 PM PST 24 |
| Finished | Mar 03 01:06:31 PM PST 24 |
| Peak memory | 145676 kb |
| Host | smart-b5bdb48b-a14e-4a18-94bc-a6746d1afd11 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1597372930 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.1597372930 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.3931182842 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 4553280000 ps |
| CPU time | 17.88 seconds |
| Started | Mar 03 01:05:10 PM PST 24 |
| Finished | Mar 03 01:05:44 PM PST 24 |
| Peak memory | 145700 kb |
| Host | smart-b28f39f1-02ba-49fb-a148-8b2f5b86bf02 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3931182842 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.3931182842 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.2105886215 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 12161920000 ps |
| CPU time | 47.37 seconds |
| Started | Mar 03 01:05:17 PM PST 24 |
| Finished | Mar 03 01:06:53 PM PST 24 |
| Peak memory | 145672 kb |
| Host | smart-8198833b-f0a4-48bc-adc0-4cd668d8239d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2105886215 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.2105886215 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.3339081446 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 7572060000 ps |
| CPU time | 30.89 seconds |
| Started | Mar 03 01:05:17 PM PST 24 |
| Finished | Mar 03 01:06:18 PM PST 24 |
| Peak memory | 145560 kb |
| Host | smart-b97790df-f8fc-46ef-8935-ec12bd10376a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3339081446 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.3339081446 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.1682293517 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 7007860000 ps |
| CPU time | 28.82 seconds |
| Started | Mar 03 01:05:16 PM PST 24 |
| Finished | Mar 03 01:06:13 PM PST 24 |
| Peak memory | 145668 kb |
| Host | smart-146ea342-f42b-4740-959b-2ee887e561d8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1682293517 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.1682293517 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.151706283 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 12348540000 ps |
| CPU time | 54.67 seconds |
| Started | Mar 03 01:05:16 PM PST 24 |
| Finished | Mar 03 01:06:58 PM PST 24 |
| Peak memory | 145692 kb |
| Host | smart-002128c5-d2b3-491f-a7be-92db04909e43 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=151706283 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.151706283 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.1052456703 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 7839280000 ps |
| CPU time | 27.15 seconds |
| Started | Mar 03 01:05:18 PM PST 24 |
| Finished | Mar 03 01:06:09 PM PST 24 |
| Peak memory | 145676 kb |
| Host | smart-0f1dad4c-667e-4286-903b-67fada7ecec2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1052456703 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.1052456703 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.1081921668 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 8298080000 ps |
| CPU time | 33.74 seconds |
| Started | Mar 03 01:05:24 PM PST 24 |
| Finished | Mar 03 01:06:33 PM PST 24 |
| Peak memory | 145604 kb |
| Host | smart-21404f84-0020-40d7-bdbc-fa6601a35d00 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1081921668 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.1081921668 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.3488726361 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 9508320000 ps |
| CPU time | 39.12 seconds |
| Started | Mar 03 01:05:24 PM PST 24 |
| Finished | Mar 03 01:06:43 PM PST 24 |
| Peak memory | 145680 kb |
| Host | smart-39e14ec1-5022-40ec-95c3-af4186386c41 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3488726361 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.3488726361 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.1425380521 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 7745040000 ps |
| CPU time | 27.41 seconds |
| Started | Mar 03 01:04:02 PM PST 24 |
| Finished | Mar 03 01:04:53 PM PST 24 |
| Peak memory | 145688 kb |
| Host | smart-b8596f86-21df-4e9b-82e7-4c7c7cd0fd90 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1425380521 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.1425380521 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.2867217466 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 14545200000 ps |
| CPU time | 55.08 seconds |
| Started | Mar 03 01:04:01 PM PST 24 |
| Finished | Mar 03 01:05:48 PM PST 24 |
| Peak memory | 145664 kb |
| Host | smart-1a958995-b9f9-40fb-a5f2-611279bcc52b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2867217466 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.2867217466 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.4252950414 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 14240780000 ps |
| CPU time | 49.65 seconds |
| Started | Mar 03 01:04:11 PM PST 24 |
| Finished | Mar 03 01:05:48 PM PST 24 |
| Peak memory | 145692 kb |
| Host | smart-03f02810-c592-4ec9-bb4c-58e3cb1a7113 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4252950414 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.4252950414 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.1181740077 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 10420960000 ps |
| CPU time | 46.99 seconds |
| Started | Mar 03 01:04:10 PM PST 24 |
| Finished | Mar 03 01:05:42 PM PST 24 |
| Peak memory | 145704 kb |
| Host | smart-155ca05a-e45c-403d-9535-b042c25679d0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1181740077 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.1181740077 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.2734707714 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 10299440000 ps |
| CPU time | 39.92 seconds |
| Started | Mar 03 01:04:11 PM PST 24 |
| Finished | Mar 03 01:05:28 PM PST 24 |
| Peak memory | 145800 kb |
| Host | smart-65b97add-9b04-4bac-a6b3-bd4fd4cc0824 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2734707714 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.2734707714 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |