| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/15.prim_present_test.3060790380 | ||
| Name |
|---|
| /workspace/coverage/default/0.prim_present_test.1556306567 |
| /workspace/coverage/default/1.prim_present_test.1057474621 |
| /workspace/coverage/default/10.prim_present_test.1659828475 |
| /workspace/coverage/default/11.prim_present_test.2416741930 |
| /workspace/coverage/default/12.prim_present_test.1871856959 |
| /workspace/coverage/default/13.prim_present_test.1026627205 |
| /workspace/coverage/default/14.prim_present_test.2507271988 |
| /workspace/coverage/default/16.prim_present_test.3146208461 |
| /workspace/coverage/default/17.prim_present_test.1867339458 |
| /workspace/coverage/default/18.prim_present_test.517732678 |
| /workspace/coverage/default/19.prim_present_test.1460836164 |
| /workspace/coverage/default/2.prim_present_test.1335707903 |
| /workspace/coverage/default/20.prim_present_test.3328910448 |
| /workspace/coverage/default/21.prim_present_test.2407920339 |
| /workspace/coverage/default/22.prim_present_test.1639291620 |
| /workspace/coverage/default/23.prim_present_test.2790334227 |
| /workspace/coverage/default/24.prim_present_test.4123679731 |
| /workspace/coverage/default/25.prim_present_test.1765901864 |
| /workspace/coverage/default/26.prim_present_test.1101617764 |
| /workspace/coverage/default/27.prim_present_test.2654943261 |
| /workspace/coverage/default/28.prim_present_test.3009249209 |
| /workspace/coverage/default/29.prim_present_test.2790196624 |
| /workspace/coverage/default/3.prim_present_test.710329520 |
| /workspace/coverage/default/30.prim_present_test.877202870 |
| /workspace/coverage/default/31.prim_present_test.3229895040 |
| /workspace/coverage/default/32.prim_present_test.3770974974 |
| /workspace/coverage/default/33.prim_present_test.2643205400 |
| /workspace/coverage/default/34.prim_present_test.1253151706 |
| /workspace/coverage/default/35.prim_present_test.707399139 |
| /workspace/coverage/default/36.prim_present_test.2814369341 |
| /workspace/coverage/default/37.prim_present_test.3255090382 |
| /workspace/coverage/default/38.prim_present_test.3954811106 |
| /workspace/coverage/default/39.prim_present_test.184288968 |
| /workspace/coverage/default/4.prim_present_test.3324634074 |
| /workspace/coverage/default/40.prim_present_test.3787219444 |
| /workspace/coverage/default/41.prim_present_test.2794334655 |
| /workspace/coverage/default/42.prim_present_test.2946205896 |
| /workspace/coverage/default/43.prim_present_test.2320491953 |
| /workspace/coverage/default/44.prim_present_test.458409527 |
| /workspace/coverage/default/45.prim_present_test.2978214683 |
| /workspace/coverage/default/46.prim_present_test.1561907038 |
| /workspace/coverage/default/47.prim_present_test.4066717146 |
| /workspace/coverage/default/48.prim_present_test.1472894102 |
| /workspace/coverage/default/49.prim_present_test.217821216 |
| /workspace/coverage/default/5.prim_present_test.1353937127 |
| /workspace/coverage/default/6.prim_present_test.4180820509 |
| /workspace/coverage/default/7.prim_present_test.530743185 |
| /workspace/coverage/default/8.prim_present_test.1362160195 |
| /workspace/coverage/default/9.prim_present_test.893194115 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/34.prim_present_test.1253151706 | Mar 05 12:25:25 PM PST 24 | Mar 05 12:26:51 PM PST 24 | 12100540000 ps | ||
| T2 | /workspace/coverage/default/45.prim_present_test.2978214683 | Mar 05 12:21:20 PM PST 24 | Mar 05 12:22:52 PM PST 24 | 12865000000 ps | ||
| T3 | /workspace/coverage/default/38.prim_present_test.3954811106 | Mar 05 12:28:14 PM PST 24 | Mar 05 12:29:29 PM PST 24 | 8255920000 ps | ||
| T4 | /workspace/coverage/default/21.prim_present_test.2407920339 | Mar 05 12:24:57 PM PST 24 | Mar 05 12:26:25 PM PST 24 | 13920860000 ps | ||
| T5 | /workspace/coverage/default/47.prim_present_test.4066717146 | Mar 05 12:20:01 PM PST 24 | Mar 05 12:20:56 PM PST 24 | 8369380000 ps | ||
| T6 | /workspace/coverage/default/49.prim_present_test.217821216 | Mar 05 12:24:36 PM PST 24 | Mar 05 12:25:29 PM PST 24 | 7804560000 ps | ||
| T7 | /workspace/coverage/default/40.prim_present_test.3787219444 | Mar 05 12:19:17 PM PST 24 | Mar 05 12:20:05 PM PST 24 | 7939720000 ps | ||
| T8 | /workspace/coverage/default/42.prim_present_test.2946205896 | Mar 05 12:24:35 PM PST 24 | Mar 05 12:26:13 PM PST 24 | 15342520000 ps | ||
| T9 | /workspace/coverage/default/15.prim_present_test.3060790380 | Mar 05 12:20:27 PM PST 24 | Mar 05 12:21:33 PM PST 24 | 9829480000 ps | ||
| T10 | /workspace/coverage/default/28.prim_present_test.3009249209 | Mar 05 12:24:57 PM PST 24 | Mar 05 12:26:15 PM PST 24 | 12046600000 ps | ||
| T11 | /workspace/coverage/default/6.prim_present_test.4180820509 | Mar 05 12:24:33 PM PST 24 | Mar 05 12:25:00 PM PST 24 | 3957460000 ps | ||
| T12 | /workspace/coverage/default/0.prim_present_test.1556306567 | Mar 05 12:25:33 PM PST 24 | Mar 05 12:26:35 PM PST 24 | 11066380000 ps | ||
| T13 | /workspace/coverage/default/9.prim_present_test.893194115 | Mar 05 12:20:40 PM PST 24 | Mar 05 12:22:05 PM PST 24 | 11638020000 ps | ||
| T14 | /workspace/coverage/default/5.prim_present_test.1353937127 | Mar 05 12:20:40 PM PST 24 | Mar 05 12:21:04 PM PST 24 | 3263060000 ps | ||
| T15 | /workspace/coverage/default/30.prim_present_test.877202870 | Mar 05 12:24:34 PM PST 24 | Mar 05 12:25:59 PM PST 24 | 13548240000 ps | ||
| T16 | /workspace/coverage/default/22.prim_present_test.1639291620 | Mar 05 12:28:12 PM PST 24 | Mar 05 12:29:26 PM PST 24 | 9678200000 ps | ||
| T17 | /workspace/coverage/default/16.prim_present_test.3146208461 | Mar 05 12:25:24 PM PST 24 | Mar 05 12:26:47 PM PST 24 | 13891100000 ps | ||
| T18 | /workspace/coverage/default/39.prim_present_test.184288968 | Mar 05 12:28:11 PM PST 24 | Mar 05 12:29:48 PM PST 24 | 12995200000 ps | ||
| T19 | /workspace/coverage/default/37.prim_present_test.3255090382 | Mar 05 12:21:07 PM PST 24 | Mar 05 12:21:52 PM PST 24 | 6548440000 ps | ||
| T20 | /workspace/coverage/default/4.prim_present_test.3324634074 | Mar 05 12:26:50 PM PST 24 | Mar 05 12:27:31 PM PST 24 | 7786580000 ps | ||
| T21 | /workspace/coverage/default/2.prim_present_test.1335707903 | Mar 05 12:20:40 PM PST 24 | Mar 05 12:21:48 PM PST 24 | 9095400000 ps | ||
| T22 | /workspace/coverage/default/36.prim_present_test.2814369341 | Mar 05 12:25:15 PM PST 24 | Mar 05 12:26:31 PM PST 24 | 13808020000 ps | ||
| T23 | /workspace/coverage/default/7.prim_present_test.530743185 | Mar 05 12:18:08 PM PST 24 | Mar 05 12:18:29 PM PST 24 | 3151460000 ps | ||
| T24 | /workspace/coverage/default/46.prim_present_test.1561907038 | Mar 05 12:24:24 PM PST 24 | Mar 05 12:25:29 PM PST 24 | 9961540000 ps | ||
| T25 | /workspace/coverage/default/13.prim_present_test.1026627205 | Mar 05 12:25:10 PM PST 24 | Mar 05 12:26:39 PM PST 24 | 15490700000 ps | ||
| T26 | /workspace/coverage/default/1.prim_present_test.1057474621 | Mar 05 12:18:41 PM PST 24 | Mar 05 12:19:13 PM PST 24 | 4799420000 ps | ||
| T27 | /workspace/coverage/default/24.prim_present_test.4123679731 | Mar 05 12:25:24 PM PST 24 | Mar 05 12:25:57 PM PST 24 | 5712060000 ps | ||
| T28 | /workspace/coverage/default/25.prim_present_test.1765901864 | Mar 05 12:28:11 PM PST 24 | Mar 05 12:29:44 PM PST 24 | 12640560000 ps | ||
| T29 | /workspace/coverage/default/29.prim_present_test.2790196624 | Mar 05 12:21:05 PM PST 24 | Mar 05 12:22:47 PM PST 24 | 14478240000 ps | ||
| T30 | /workspace/coverage/default/12.prim_present_test.1871856959 | Mar 05 12:28:16 PM PST 24 | Mar 05 12:29:25 PM PST 24 | 12629400000 ps | ||
| T31 | /workspace/coverage/default/20.prim_present_test.3328910448 | Mar 05 12:24:27 PM PST 24 | Mar 05 12:26:00 PM PST 24 | 14209160000 ps | ||
| T32 | /workspace/coverage/default/17.prim_present_test.1867339458 | Mar 05 12:18:24 PM PST 24 | Mar 05 12:19:59 PM PST 24 | 14171340000 ps | ||
| T33 | /workspace/coverage/default/43.prim_present_test.2320491953 | Mar 05 12:18:52 PM PST 24 | Mar 05 12:19:51 PM PST 24 | 10225040000 ps | ||
| T34 | /workspace/coverage/default/31.prim_present_test.3229895040 | Mar 05 12:24:57 PM PST 24 | Mar 05 12:25:23 PM PST 24 | 3287860000 ps | ||
| T35 | /workspace/coverage/default/8.prim_present_test.1362160195 | Mar 05 12:24:33 PM PST 24 | Mar 05 12:24:56 PM PST 24 | 3396360000 ps | ||
| T36 | /workspace/coverage/default/3.prim_present_test.710329520 | Mar 05 12:18:21 PM PST 24 | Mar 05 12:19:08 PM PST 24 | 7343280000 ps | ||
| T37 | /workspace/coverage/default/23.prim_present_test.2790334227 | Mar 05 12:18:34 PM PST 24 | Mar 05 12:19:35 PM PST 24 | 9352080000 ps | ||
| T38 | /workspace/coverage/default/27.prim_present_test.2654943261 | Mar 05 12:21:08 PM PST 24 | Mar 05 12:22:40 PM PST 24 | 12631880000 ps | ||
| T39 | /workspace/coverage/default/35.prim_present_test.707399139 | Mar 05 12:19:00 PM PST 24 | Mar 05 12:19:28 PM PST 24 | 4288540000 ps | ||
| T40 | /workspace/coverage/default/26.prim_present_test.1101617764 | Mar 05 12:24:36 PM PST 24 | Mar 05 12:25:41 PM PST 24 | 9658980000 ps | ||
| T41 | /workspace/coverage/default/48.prim_present_test.1472894102 | Mar 05 12:21:08 PM PST 24 | Mar 05 12:22:10 PM PST 24 | 8565920000 ps | ||
| T42 | /workspace/coverage/default/33.prim_present_test.2643205400 | Mar 05 12:24:56 PM PST 24 | Mar 05 12:26:17 PM PST 24 | 12198500000 ps | ||
| T43 | /workspace/coverage/default/32.prim_present_test.3770974974 | Mar 05 12:24:25 PM PST 24 | Mar 05 12:25:08 PM PST 24 | 6418860000 ps | ||
| T44 | /workspace/coverage/default/41.prim_present_test.2794334655 | Mar 05 12:24:36 PM PST 24 | Mar 05 12:26:06 PM PST 24 | 13785080000 ps | ||
| T45 | /workspace/coverage/default/44.prim_present_test.458409527 | Mar 05 12:23:53 PM PST 24 | Mar 05 12:24:40 PM PST 24 | 9114620000 ps | ||
| T46 | /workspace/coverage/default/18.prim_present_test.517732678 | Mar 05 12:25:14 PM PST 24 | Mar 05 12:26:35 PM PST 24 | 13537700000 ps | ||
| T47 | /workspace/coverage/default/19.prim_present_test.1460836164 | Mar 05 12:17:52 PM PST 24 | Mar 05 12:19:09 PM PST 24 | 12010640000 ps | ||
| T48 | /workspace/coverage/default/11.prim_present_test.2416741930 | Mar 05 12:20:41 PM PST 24 | Mar 05 12:21:50 PM PST 24 | 9494060000 ps | ||
| T49 | /workspace/coverage/default/14.prim_present_test.2507271988 | Mar 05 12:28:35 PM PST 24 | Mar 05 12:29:58 PM PST 24 | 15108780000 ps | ||
| T50 | /workspace/coverage/default/10.prim_present_test.1659828475 | Mar 05 12:18:18 PM PST 24 | Mar 05 12:19:53 PM PST 24 | 13804920000 ps |
| Test location | /workspace/coverage/default/15.prim_present_test.3060790380 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 9829480000 ps |
| CPU time | 34.98 seconds |
| Started | Mar 05 12:20:27 PM PST 24 |
| Finished | Mar 05 12:21:33 PM PST 24 |
| Peak memory | 145676 kb |
| Host | smart-9a74fa39-861b-4a48-9446-02844f6c4c4d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3060790380 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.3060790380 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/0.prim_present_test.1556306567 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 11066380000 ps |
| CPU time | 32.97 seconds |
| Started | Mar 05 12:25:33 PM PST 24 |
| Finished | Mar 05 12:26:35 PM PST 24 |
| Peak memory | 145716 kb |
| Host | smart-5c5b510c-f762-42d9-be14-7fa026cefb8a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1556306567 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.1556306567 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/1.prim_present_test.1057474621 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 4799420000 ps |
| CPU time | 17.21 seconds |
| Started | Mar 05 12:18:41 PM PST 24 |
| Finished | Mar 05 12:19:13 PM PST 24 |
| Peak memory | 145732 kb |
| Host | smart-d226d7be-92d4-4765-9a39-eb02c4c69d0c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1057474621 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.1057474621 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/10.prim_present_test.1659828475 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 13804920000 ps |
| CPU time | 50.6 seconds |
| Started | Mar 05 12:18:18 PM PST 24 |
| Finished | Mar 05 12:19:53 PM PST 24 |
| Peak memory | 145616 kb |
| Host | smart-0a2c80db-ccfa-434e-9a7c-def065dd8cee |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1659828475 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.1659828475 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/11.prim_present_test.2416741930 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 9494060000 ps |
| CPU time | 36.53 seconds |
| Started | Mar 05 12:20:41 PM PST 24 |
| Finished | Mar 05 12:21:50 PM PST 24 |
| Peak memory | 145612 kb |
| Host | smart-0f9869cb-5483-4422-b164-7c5a75ea95b6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2416741930 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.2416741930 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.1871856959 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 12629400000 ps |
| CPU time | 35.62 seconds |
| Started | Mar 05 12:28:16 PM PST 24 |
| Finished | Mar 05 12:29:25 PM PST 24 |
| Peak memory | 145728 kb |
| Host | smart-2815393b-2072-4a3c-8f08-1887ffeef744 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1871856959 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.1871856959 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.1026627205 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 15490700000 ps |
| CPU time | 48.47 seconds |
| Started | Mar 05 12:25:10 PM PST 24 |
| Finished | Mar 05 12:26:39 PM PST 24 |
| Peak memory | 145752 kb |
| Host | smart-592c271b-7449-487b-b163-b1c4f41f31b5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1026627205 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.1026627205 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.2507271988 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 15108780000 ps |
| CPU time | 44.32 seconds |
| Started | Mar 05 12:28:35 PM PST 24 |
| Finished | Mar 05 12:29:58 PM PST 24 |
| Peak memory | 145032 kb |
| Host | smart-55d64191-b242-4a1b-8515-a91c159670eb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2507271988 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.2507271988 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.3146208461 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 13891100000 ps |
| CPU time | 45.33 seconds |
| Started | Mar 05 12:25:24 PM PST 24 |
| Finished | Mar 05 12:26:47 PM PST 24 |
| Peak memory | 145052 kb |
| Host | smart-babf10aa-62a8-4882-bd61-1971ad31e5e9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3146208461 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.3146208461 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.1867339458 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 14171340000 ps |
| CPU time | 51.37 seconds |
| Started | Mar 05 12:18:24 PM PST 24 |
| Finished | Mar 05 12:19:59 PM PST 24 |
| Peak memory | 145676 kb |
| Host | smart-cddcbd59-5087-43c9-83fc-d758daa37ece |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1867339458 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.1867339458 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.517732678 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 13537700000 ps |
| CPU time | 43.51 seconds |
| Started | Mar 05 12:25:14 PM PST 24 |
| Finished | Mar 05 12:26:35 PM PST 24 |
| Peak memory | 145732 kb |
| Host | smart-ca66cc85-768a-48d2-ba91-a3b71b87587d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=517732678 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.517732678 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.1460836164 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 12010640000 ps |
| CPU time | 41.01 seconds |
| Started | Mar 05 12:17:52 PM PST 24 |
| Finished | Mar 05 12:19:09 PM PST 24 |
| Peak memory | 145732 kb |
| Host | smart-7f138ef6-a32b-4ab3-a66e-52ebc7c5527c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1460836164 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.1460836164 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.1335707903 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 9095400000 ps |
| CPU time | 35.27 seconds |
| Started | Mar 05 12:20:40 PM PST 24 |
| Finished | Mar 05 12:21:48 PM PST 24 |
| Peak memory | 145608 kb |
| Host | smart-5b48c339-2951-4d4f-80c6-458b35c51051 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1335707903 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.1335707903 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.3328910448 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 14209160000 ps |
| CPU time | 49.83 seconds |
| Started | Mar 05 12:24:27 PM PST 24 |
| Finished | Mar 05 12:26:00 PM PST 24 |
| Peak memory | 144448 kb |
| Host | smart-119834f8-ba4e-47d2-957d-0ec2b87f95b7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3328910448 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.3328910448 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.2407920339 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 13920860000 ps |
| CPU time | 46.57 seconds |
| Started | Mar 05 12:24:57 PM PST 24 |
| Finished | Mar 05 12:26:25 PM PST 24 |
| Peak memory | 144948 kb |
| Host | smart-bd408d78-39dc-4789-8790-865e055f127f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2407920339 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.2407920339 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.1639291620 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 9678200000 ps |
| CPU time | 36.58 seconds |
| Started | Mar 05 12:28:12 PM PST 24 |
| Finished | Mar 05 12:29:26 PM PST 24 |
| Peak memory | 146240 kb |
| Host | smart-8507e2c6-4f88-4b73-a3ba-26f6b8e78217 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1639291620 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.1639291620 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.2790334227 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 9352080000 ps |
| CPU time | 32.49 seconds |
| Started | Mar 05 12:18:34 PM PST 24 |
| Finished | Mar 05 12:19:35 PM PST 24 |
| Peak memory | 145372 kb |
| Host | smart-85f25ed8-6ffc-4819-af54-01af64eec511 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2790334227 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.2790334227 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.4123679731 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 5712060000 ps |
| CPU time | 17.51 seconds |
| Started | Mar 05 12:25:24 PM PST 24 |
| Finished | Mar 05 12:25:57 PM PST 24 |
| Peak memory | 146248 kb |
| Host | smart-42b7d947-86eb-4005-a814-85255ae783b6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4123679731 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.4123679731 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.1765901864 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 12640560000 ps |
| CPU time | 46.52 seconds |
| Started | Mar 05 12:28:11 PM PST 24 |
| Finished | Mar 05 12:29:44 PM PST 24 |
| Peak memory | 144136 kb |
| Host | smart-163aa524-7d1a-42d0-85ed-8d6c1a5c4603 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1765901864 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.1765901864 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.1101617764 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 9658980000 ps |
| CPU time | 34.72 seconds |
| Started | Mar 05 12:24:36 PM PST 24 |
| Finished | Mar 05 12:25:41 PM PST 24 |
| Peak memory | 145128 kb |
| Host | smart-9e0b078f-e11a-46ce-8413-09a48f8a09c8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1101617764 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.1101617764 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.2654943261 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 12631880000 ps |
| CPU time | 48.68 seconds |
| Started | Mar 05 12:21:08 PM PST 24 |
| Finished | Mar 05 12:22:40 PM PST 24 |
| Peak memory | 145460 kb |
| Host | smart-724214ee-fcfc-4a3f-af72-e2b8c347b58d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2654943261 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.2654943261 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.3009249209 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 12046600000 ps |
| CPU time | 41.39 seconds |
| Started | Mar 05 12:24:57 PM PST 24 |
| Finished | Mar 05 12:26:15 PM PST 24 |
| Peak memory | 144312 kb |
| Host | smart-1f281a74-3a97-4cd8-a26a-8956ab5d069f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3009249209 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.3009249209 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.2790196624 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 14478240000 ps |
| CPU time | 53.69 seconds |
| Started | Mar 05 12:21:05 PM PST 24 |
| Finished | Mar 05 12:22:47 PM PST 24 |
| Peak memory | 145616 kb |
| Host | smart-5f0283b5-cbc7-4227-ab77-aa8163e79aa8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2790196624 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.2790196624 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.710329520 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 7343280000 ps |
| CPU time | 24.64 seconds |
| Started | Mar 05 12:18:21 PM PST 24 |
| Finished | Mar 05 12:19:08 PM PST 24 |
| Peak memory | 145628 kb |
| Host | smart-bf7c3fc9-5bd5-43eb-aa1f-754781484b6c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=710329520 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.710329520 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.877202870 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 13548240000 ps |
| CPU time | 45.8 seconds |
| Started | Mar 05 12:24:34 PM PST 24 |
| Finished | Mar 05 12:25:59 PM PST 24 |
| Peak memory | 145032 kb |
| Host | smart-b8de1a9a-a7b6-4191-86dd-d00e1dd12040 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=877202870 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.877202870 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.3229895040 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 3287860000 ps |
| CPU time | 13.53 seconds |
| Started | Mar 05 12:24:57 PM PST 24 |
| Finished | Mar 05 12:25:23 PM PST 24 |
| Peak memory | 146008 kb |
| Host | smart-001c8018-e802-424c-b6f9-51757b3b8963 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3229895040 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.3229895040 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.3770974974 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 6418860000 ps |
| CPU time | 22.98 seconds |
| Started | Mar 05 12:24:25 PM PST 24 |
| Finished | Mar 05 12:25:08 PM PST 24 |
| Peak memory | 146336 kb |
| Host | smart-36272e56-aed2-49e1-afbb-d51d66ffee84 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3770974974 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.3770974974 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.2643205400 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 12198500000 ps |
| CPU time | 42.9 seconds |
| Started | Mar 05 12:24:56 PM PST 24 |
| Finished | Mar 05 12:26:17 PM PST 24 |
| Peak memory | 144148 kb |
| Host | smart-74388620-8fdd-43de-b321-60c04acfb6af |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2643205400 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.2643205400 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.1253151706 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 12100540000 ps |
| CPU time | 45.55 seconds |
| Started | Mar 05 12:25:25 PM PST 24 |
| Finished | Mar 05 12:26:51 PM PST 24 |
| Peak memory | 146348 kb |
| Host | smart-35538e80-164f-4b88-9d18-3f47c0553237 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1253151706 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.1253151706 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.707399139 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 4288540000 ps |
| CPU time | 14.87 seconds |
| Started | Mar 05 12:19:00 PM PST 24 |
| Finished | Mar 05 12:19:28 PM PST 24 |
| Peak memory | 145392 kb |
| Host | smart-0971aaf6-1a34-4f92-abf3-47db12472985 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=707399139 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.707399139 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.2814369341 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 13808020000 ps |
| CPU time | 41.4 seconds |
| Started | Mar 05 12:25:15 PM PST 24 |
| Finished | Mar 05 12:26:31 PM PST 24 |
| Peak memory | 144448 kb |
| Host | smart-149139df-a481-4eb2-8a1c-3999c015df01 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2814369341 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.2814369341 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.3255090382 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 6548440000 ps |
| CPU time | 24 seconds |
| Started | Mar 05 12:21:07 PM PST 24 |
| Finished | Mar 05 12:21:52 PM PST 24 |
| Peak memory | 145388 kb |
| Host | smart-a85bbd7a-ce9e-44fb-acc5-fe460ea88e6c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3255090382 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.3255090382 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.3954811106 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 8255920000 ps |
| CPU time | 33.37 seconds |
| Started | Mar 05 12:28:14 PM PST 24 |
| Finished | Mar 05 12:29:29 PM PST 24 |
| Peak memory | 144976 kb |
| Host | smart-e6553ab4-31e5-4c06-bf22-5115ebaf9041 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3954811106 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.3954811106 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.184288968 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 12995200000 ps |
| CPU time | 47.9 seconds |
| Started | Mar 05 12:28:11 PM PST 24 |
| Finished | Mar 05 12:29:48 PM PST 24 |
| Peak memory | 144592 kb |
| Host | smart-d76b3307-b46d-43ae-a4be-cae807e7de05 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=184288968 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.184288968 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.3324634074 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 7786580000 ps |
| CPU time | 22.09 seconds |
| Started | Mar 05 12:26:50 PM PST 24 |
| Finished | Mar 05 12:27:31 PM PST 24 |
| Peak memory | 145732 kb |
| Host | smart-7dfa6d04-077f-40ca-9053-d67a35b23e14 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3324634074 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.3324634074 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.3787219444 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 7939720000 ps |
| CPU time | 26.12 seconds |
| Started | Mar 05 12:19:17 PM PST 24 |
| Finished | Mar 05 12:20:05 PM PST 24 |
| Peak memory | 145632 kb |
| Host | smart-edcd23c5-4798-436d-9de0-153725d7c075 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3787219444 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.3787219444 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.2794334655 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 13785080000 ps |
| CPU time | 48.83 seconds |
| Started | Mar 05 12:24:36 PM PST 24 |
| Finished | Mar 05 12:26:06 PM PST 24 |
| Peak memory | 145064 kb |
| Host | smart-a33be04a-62f0-43c3-84f5-a3b4fe609b65 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2794334655 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.2794334655 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.2946205896 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 15342520000 ps |
| CPU time | 52.42 seconds |
| Started | Mar 05 12:24:35 PM PST 24 |
| Finished | Mar 05 12:26:13 PM PST 24 |
| Peak memory | 145032 kb |
| Host | smart-1da86d17-0713-4bc6-9ec1-05588c464f24 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2946205896 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.2946205896 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.2320491953 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 10225040000 ps |
| CPU time | 32.21 seconds |
| Started | Mar 05 12:18:52 PM PST 24 |
| Finished | Mar 05 12:19:51 PM PST 24 |
| Peak memory | 145624 kb |
| Host | smart-fddf74a5-716a-4c97-a40a-d35777392216 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2320491953 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.2320491953 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.458409527 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 9114620000 ps |
| CPU time | 25.43 seconds |
| Started | Mar 05 12:23:53 PM PST 24 |
| Finished | Mar 05 12:24:40 PM PST 24 |
| Peak memory | 145732 kb |
| Host | smart-1f4d12d2-1514-494f-bd55-1972b80d4f88 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=458409527 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.458409527 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.2978214683 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 12865000000 ps |
| CPU time | 48.85 seconds |
| Started | Mar 05 12:21:20 PM PST 24 |
| Finished | Mar 05 12:22:52 PM PST 24 |
| Peak memory | 145680 kb |
| Host | smart-4aa3e2b3-ef0c-48ad-b45d-e6a8947dae66 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2978214683 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.2978214683 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.1561907038 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 9961540000 ps |
| CPU time | 34.65 seconds |
| Started | Mar 05 12:24:24 PM PST 24 |
| Finished | Mar 05 12:25:29 PM PST 24 |
| Peak memory | 145072 kb |
| Host | smart-6565ab10-ef22-4387-a540-575ccd6490b3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1561907038 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.1561907038 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.4066717146 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 8369380000 ps |
| CPU time | 29.17 seconds |
| Started | Mar 05 12:20:01 PM PST 24 |
| Finished | Mar 05 12:20:56 PM PST 24 |
| Peak memory | 145524 kb |
| Host | smart-fbae5ede-f866-4798-96f2-cba8dfcd7508 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4066717146 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.4066717146 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.1472894102 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 8565920000 ps |
| CPU time | 33.11 seconds |
| Started | Mar 05 12:21:08 PM PST 24 |
| Finished | Mar 05 12:22:10 PM PST 24 |
| Peak memory | 145456 kb |
| Host | smart-2fa9ca8b-b03b-408c-8e2e-285816d3b98f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1472894102 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.1472894102 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.217821216 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 7804560000 ps |
| CPU time | 28.27 seconds |
| Started | Mar 05 12:24:36 PM PST 24 |
| Finished | Mar 05 12:25:29 PM PST 24 |
| Peak memory | 146408 kb |
| Host | smart-e1373700-383a-4069-b54a-e4e20fbc4030 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=217821216 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.217821216 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.1353937127 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 3263060000 ps |
| CPU time | 12.55 seconds |
| Started | Mar 05 12:20:40 PM PST 24 |
| Finished | Mar 05 12:21:04 PM PST 24 |
| Peak memory | 145456 kb |
| Host | smart-2d9bf2fb-4c3c-4a08-be2f-39e4a4420efb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1353937127 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.1353937127 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.4180820509 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 3957460000 ps |
| CPU time | 13.99 seconds |
| Started | Mar 05 12:24:33 PM PST 24 |
| Finished | Mar 05 12:25:00 PM PST 24 |
| Peak memory | 143208 kb |
| Host | smart-d733bec0-0fbc-46c5-9052-022f9d91743f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4180820509 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.4180820509 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.530743185 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 3151460000 ps |
| CPU time | 11.53 seconds |
| Started | Mar 05 12:18:08 PM PST 24 |
| Finished | Mar 05 12:18:29 PM PST 24 |
| Peak memory | 145512 kb |
| Host | smart-152e770c-4957-4921-964b-965b5a61115c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=530743185 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.530743185 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.1362160195 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 3396360000 ps |
| CPU time | 12.09 seconds |
| Started | Mar 05 12:24:33 PM PST 24 |
| Finished | Mar 05 12:24:56 PM PST 24 |
| Peak memory | 144436 kb |
| Host | smart-ce58be2b-b3be-4b88-bb06-3a4f05351b47 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1362160195 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.1362160195 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.893194115 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 11638020000 ps |
| CPU time | 44.37 seconds |
| Started | Mar 05 12:20:40 PM PST 24 |
| Finished | Mar 05 12:22:05 PM PST 24 |
| Peak memory | 145612 kb |
| Host | smart-c662c204-6fcd-4bd9-84e1-1c8f14db55d7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=893194115 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.893194115 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |