| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/1.prim_present_test.1435948323 | ||
| Name |
|---|
| /workspace/coverage/default/0.prim_present_test.3177330157 |
| /workspace/coverage/default/10.prim_present_test.3624084285 |
| /workspace/coverage/default/11.prim_present_test.3811315265 |
| /workspace/coverage/default/12.prim_present_test.1051387056 |
| /workspace/coverage/default/13.prim_present_test.3205252654 |
| /workspace/coverage/default/14.prim_present_test.1994669601 |
| /workspace/coverage/default/15.prim_present_test.3439077404 |
| /workspace/coverage/default/16.prim_present_test.1031603122 |
| /workspace/coverage/default/17.prim_present_test.2604043771 |
| /workspace/coverage/default/18.prim_present_test.3208824737 |
| /workspace/coverage/default/19.prim_present_test.4081273839 |
| /workspace/coverage/default/2.prim_present_test.2094250153 |
| /workspace/coverage/default/20.prim_present_test.3969299773 |
| /workspace/coverage/default/21.prim_present_test.3490428540 |
| /workspace/coverage/default/22.prim_present_test.3867496832 |
| /workspace/coverage/default/23.prim_present_test.2126976292 |
| /workspace/coverage/default/24.prim_present_test.2680919093 |
| /workspace/coverage/default/25.prim_present_test.837844919 |
| /workspace/coverage/default/26.prim_present_test.1311473191 |
| /workspace/coverage/default/27.prim_present_test.2738773514 |
| /workspace/coverage/default/28.prim_present_test.1704368304 |
| /workspace/coverage/default/29.prim_present_test.2715577518 |
| /workspace/coverage/default/3.prim_present_test.443217576 |
| /workspace/coverage/default/30.prim_present_test.3665869552 |
| /workspace/coverage/default/31.prim_present_test.2997987922 |
| /workspace/coverage/default/32.prim_present_test.939243880 |
| /workspace/coverage/default/33.prim_present_test.2841144218 |
| /workspace/coverage/default/34.prim_present_test.3509021577 |
| /workspace/coverage/default/35.prim_present_test.3978143935 |
| /workspace/coverage/default/36.prim_present_test.3260977005 |
| /workspace/coverage/default/37.prim_present_test.1771471172 |
| /workspace/coverage/default/38.prim_present_test.2034004258 |
| /workspace/coverage/default/39.prim_present_test.1775056803 |
| /workspace/coverage/default/4.prim_present_test.418385146 |
| /workspace/coverage/default/40.prim_present_test.1063340781 |
| /workspace/coverage/default/41.prim_present_test.2578847463 |
| /workspace/coverage/default/42.prim_present_test.3941410503 |
| /workspace/coverage/default/43.prim_present_test.631260053 |
| /workspace/coverage/default/44.prim_present_test.2348934786 |
| /workspace/coverage/default/45.prim_present_test.267705849 |
| /workspace/coverage/default/46.prim_present_test.3424438748 |
| /workspace/coverage/default/47.prim_present_test.257865254 |
| /workspace/coverage/default/48.prim_present_test.3109944973 |
| /workspace/coverage/default/49.prim_present_test.134030111 |
| /workspace/coverage/default/5.prim_present_test.2480180643 |
| /workspace/coverage/default/6.prim_present_test.2984774197 |
| /workspace/coverage/default/7.prim_present_test.2654929905 |
| /workspace/coverage/default/8.prim_present_test.542457405 |
| /workspace/coverage/default/9.prim_present_test.1828042890 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/49.prim_present_test.134030111 | Mar 07 12:27:23 PM PST 24 | Mar 07 12:28:55 PM PST 24 | 14401980000 ps | ||
| T2 | /workspace/coverage/default/47.prim_present_test.257865254 | Mar 07 12:19:51 PM PST 24 | Mar 07 12:21:01 PM PST 24 | 10778700000 ps | ||
| T3 | /workspace/coverage/default/29.prim_present_test.2715577518 | Mar 07 12:19:10 PM PST 24 | Mar 07 12:20:35 PM PST 24 | 12646760000 ps | ||
| T4 | /workspace/coverage/default/2.prim_present_test.2094250153 | Mar 07 12:19:10 PM PST 24 | Mar 07 12:20:15 PM PST 24 | 9316740000 ps | ||
| T5 | /workspace/coverage/default/42.prim_present_test.3941410503 | Mar 07 12:19:11 PM PST 24 | Mar 07 12:20:06 PM PST 24 | 7883300000 ps | ||
| T6 | /workspace/coverage/default/12.prim_present_test.1051387056 | Mar 07 12:19:12 PM PST 24 | Mar 07 12:20:42 PM PST 24 | 13948140000 ps | ||
| T7 | /workspace/coverage/default/1.prim_present_test.1435948323 | Mar 07 12:19:09 PM PST 24 | Mar 07 12:19:44 PM PST 24 | 5241480000 ps | ||
| T8 | /workspace/coverage/default/40.prim_present_test.1063340781 | Mar 07 12:19:12 PM PST 24 | Mar 07 12:20:21 PM PST 24 | 10040900000 ps | ||
| T9 | /workspace/coverage/default/13.prim_present_test.3205252654 | Mar 07 12:19:12 PM PST 24 | Mar 07 12:19:57 PM PST 24 | 7037000000 ps | ||
| T10 | /workspace/coverage/default/38.prim_present_test.2034004258 | Mar 07 12:19:12 PM PST 24 | Mar 07 12:19:55 PM PST 24 | 6353140000 ps | ||
| T11 | /workspace/coverage/default/7.prim_present_test.2654929905 | Mar 07 12:19:11 PM PST 24 | Mar 07 12:20:36 PM PST 24 | 13075800000 ps | ||
| T12 | /workspace/coverage/default/39.prim_present_test.1775056803 | Mar 07 12:21:20 PM PST 24 | Mar 07 12:22:32 PM PST 24 | 11489840000 ps | ||
| T13 | /workspace/coverage/default/14.prim_present_test.1994669601 | Mar 07 12:19:12 PM PST 24 | Mar 07 12:20:40 PM PST 24 | 11904000000 ps | ||
| T14 | /workspace/coverage/default/44.prim_present_test.2348934786 | Mar 07 12:27:23 PM PST 24 | Mar 07 12:27:59 PM PST 24 | 4844060000 ps | ||
| T15 | /workspace/coverage/default/9.prim_present_test.1828042890 | Mar 07 12:19:11 PM PST 24 | Mar 07 12:19:54 PM PST 24 | 6436220000 ps | ||
| T16 | /workspace/coverage/default/33.prim_present_test.2841144218 | Mar 07 12:19:12 PM PST 24 | Mar 07 12:20:02 PM PST 24 | 7482160000 ps | ||
| T17 | /workspace/coverage/default/8.prim_present_test.542457405 | Mar 07 12:19:11 PM PST 24 | Mar 07 12:20:18 PM PST 24 | 10695000000 ps | ||
| T18 | /workspace/coverage/default/41.prim_present_test.2578847463 | Mar 07 12:21:19 PM PST 24 | Mar 07 12:22:03 PM PST 24 | 6677400000 ps | ||
| T19 | /workspace/coverage/default/11.prim_present_test.3811315265 | Mar 07 12:19:10 PM PST 24 | Mar 07 12:19:48 PM PST 24 | 5121820000 ps | ||
| T20 | /workspace/coverage/default/18.prim_present_test.3208824737 | Mar 07 12:19:10 PM PST 24 | Mar 07 12:20:44 PM PST 24 | 13502360000 ps | ||
| T21 | /workspace/coverage/default/5.prim_present_test.2480180643 | Mar 07 12:19:12 PM PST 24 | Mar 07 12:20:07 PM PST 24 | 8604980000 ps | ||
| T22 | /workspace/coverage/default/48.prim_present_test.3109944973 | Mar 07 12:19:29 PM PST 24 | Mar 07 12:19:51 PM PST 24 | 3475720000 ps | ||
| T23 | /workspace/coverage/default/24.prim_present_test.2680919093 | Mar 07 12:19:19 PM PST 24 | Mar 07 12:19:56 PM PST 24 | 4677280000 ps | ||
| T24 | /workspace/coverage/default/0.prim_present_test.3177330157 | Mar 07 12:19:22 PM PST 24 | Mar 07 12:20:05 PM PST 24 | 6305400000 ps | ||
| T25 | /workspace/coverage/default/43.prim_present_test.631260053 | Mar 07 12:27:23 PM PST 24 | Mar 07 12:28:53 PM PST 24 | 13386420000 ps | ||
| T26 | /workspace/coverage/default/19.prim_present_test.4081273839 | Mar 07 12:19:20 PM PST 24 | Mar 07 12:20:51 PM PST 24 | 12154480000 ps | ||
| T27 | /workspace/coverage/default/25.prim_present_test.837844919 | Mar 07 12:19:12 PM PST 24 | Mar 07 12:20:12 PM PST 24 | 8578320000 ps | ||
| T28 | /workspace/coverage/default/35.prim_present_test.3978143935 | Mar 07 12:19:12 PM PST 24 | Mar 07 12:20:13 PM PST 24 | 10079340000 ps | ||
| T29 | /workspace/coverage/default/3.prim_present_test.443217576 | Mar 07 12:19:12 PM PST 24 | Mar 07 12:19:49 PM PST 24 | 5661220000 ps | ||
| T30 | /workspace/coverage/default/34.prim_present_test.3509021577 | Mar 07 12:19:11 PM PST 24 | Mar 07 12:19:41 PM PST 24 | 4609080000 ps | ||
| T31 | /workspace/coverage/default/45.prim_present_test.267705849 | Mar 07 12:19:29 PM PST 24 | Mar 07 12:20:17 PM PST 24 | 7355680000 ps | ||
| T32 | /workspace/coverage/default/28.prim_present_test.1704368304 | Mar 07 12:19:11 PM PST 24 | Mar 07 12:20:37 PM PST 24 | 12613900000 ps | ||
| T33 | /workspace/coverage/default/20.prim_present_test.3969299773 | Mar 07 12:19:12 PM PST 24 | Mar 07 12:20:41 PM PST 24 | 13971700000 ps | ||
| T34 | /workspace/coverage/default/31.prim_present_test.2997987922 | Mar 07 12:19:11 PM PST 24 | Mar 07 12:19:49 PM PST 24 | 5442980000 ps | ||
| T35 | /workspace/coverage/default/4.prim_present_test.418385146 | Mar 07 12:19:12 PM PST 24 | Mar 07 12:20:01 PM PST 24 | 7749380000 ps | ||
| T36 | /workspace/coverage/default/15.prim_present_test.3439077404 | Mar 07 12:19:10 PM PST 24 | Mar 07 12:20:28 PM PST 24 | 11325540000 ps | ||
| T37 | /workspace/coverage/default/27.prim_present_test.2738773514 | Mar 07 12:19:11 PM PST 24 | Mar 07 12:20:18 PM PST 24 | 8940400000 ps | ||
| T38 | /workspace/coverage/default/16.prim_present_test.1031603122 | Mar 07 12:19:11 PM PST 24 | Mar 07 12:20:01 PM PST 24 | 6901220000 ps | ||
| T39 | /workspace/coverage/default/10.prim_present_test.3624084285 | Mar 07 12:19:12 PM PST 24 | Mar 07 12:19:56 PM PST 24 | 7167200000 ps | ||
| T40 | /workspace/coverage/default/26.prim_present_test.1311473191 | Mar 07 12:21:20 PM PST 24 | Mar 07 12:22:28 PM PST 24 | 11012440000 ps | ||
| T41 | /workspace/coverage/default/23.prim_present_test.2126976292 | Mar 07 12:19:12 PM PST 24 | Mar 07 12:20:47 PM PST 24 | 12660400000 ps | ||
| T42 | /workspace/coverage/default/37.prim_present_test.1771471172 | Mar 07 12:21:11 PM PST 24 | Mar 07 12:22:09 PM PST 24 | 9465540000 ps | ||
| T43 | /workspace/coverage/default/32.prim_present_test.939243880 | Mar 07 12:19:11 PM PST 24 | Mar 07 12:20:48 PM PST 24 | 15032520000 ps | ||
| T44 | /workspace/coverage/default/30.prim_present_test.3665869552 | Mar 07 12:19:10 PM PST 24 | Mar 07 12:20:09 PM PST 24 | 8228020000 ps | ||
| T45 | /workspace/coverage/default/21.prim_present_test.3490428540 | Mar 07 12:19:10 PM PST 24 | Mar 07 12:20:08 PM PST 24 | 8459280000 ps | ||
| T46 | /workspace/coverage/default/36.prim_present_test.3260977005 | Mar 07 12:19:13 PM PST 24 | Mar 07 12:20:45 PM PST 24 | 13745400000 ps | ||
| T47 | /workspace/coverage/default/6.prim_present_test.2984774197 | Mar 07 12:19:10 PM PST 24 | Mar 07 12:20:13 PM PST 24 | 9018520000 ps | ||
| T48 | /workspace/coverage/default/46.prim_present_test.3424438748 | Mar 07 12:19:23 PM PST 24 | Mar 07 12:20:06 PM PST 24 | 7484020000 ps | ||
| T49 | /workspace/coverage/default/22.prim_present_test.3867496832 | Mar 07 12:19:12 PM PST 24 | Mar 07 12:20:16 PM PST 24 | 9210100000 ps | ||
| T50 | /workspace/coverage/default/17.prim_present_test.2604043771 | Mar 07 12:19:20 PM PST 24 | Mar 07 12:20:08 PM PST 24 | 6022060000 ps |
| Test location | /workspace/coverage/default/1.prim_present_test.1435948323 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 5241480000 ps |
| CPU time | 18.77 seconds |
| Started | Mar 07 12:19:09 PM PST 24 |
| Finished | Mar 07 12:19:44 PM PST 24 |
| Peak memory | 144956 kb |
| Host | smart-25ffe059-a818-44d8-af6d-4b3bdae7d287 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1435948323 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.1435948323 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/0.prim_present_test.3177330157 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 6305400000 ps |
| CPU time | 22.77 seconds |
| Started | Mar 07 12:19:22 PM PST 24 |
| Finished | Mar 07 12:20:05 PM PST 24 |
| Peak memory | 144960 kb |
| Host | smart-bafe3341-eabe-4d2e-9305-427069424b21 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3177330157 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.3177330157 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/10.prim_present_test.3624084285 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 7167200000 ps |
| CPU time | 23.89 seconds |
| Started | Mar 07 12:19:12 PM PST 24 |
| Finished | Mar 07 12:19:56 PM PST 24 |
| Peak memory | 145060 kb |
| Host | smart-3085a40c-51ae-4d34-aca3-2b46c39d90ee |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3624084285 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.3624084285 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/11.prim_present_test.3811315265 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 5121820000 ps |
| CPU time | 19.99 seconds |
| Started | Mar 07 12:19:10 PM PST 24 |
| Finished | Mar 07 12:19:48 PM PST 24 |
| Peak memory | 144960 kb |
| Host | smart-562e6210-a690-499f-bca1-0efd7c6b8a4a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3811315265 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.3811315265 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.1051387056 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 13948140000 ps |
| CPU time | 49.06 seconds |
| Started | Mar 07 12:19:12 PM PST 24 |
| Finished | Mar 07 12:20:42 PM PST 24 |
| Peak memory | 144924 kb |
| Host | smart-1f847eb6-7c1a-45c8-9b07-cf69070688ba |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1051387056 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.1051387056 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.3205252654 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 7037000000 ps |
| CPU time | 24.72 seconds |
| Started | Mar 07 12:19:12 PM PST 24 |
| Finished | Mar 07 12:19:57 PM PST 24 |
| Peak memory | 144880 kb |
| Host | smart-3bc2e03f-7e4b-4bdc-91e1-3a816f118b97 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3205252654 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.3205252654 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.1994669601 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 11904000000 ps |
| CPU time | 45.86 seconds |
| Started | Mar 07 12:19:12 PM PST 24 |
| Finished | Mar 07 12:20:40 PM PST 24 |
| Peak memory | 144696 kb |
| Host | smart-220f31da-30c4-4ee9-b7b2-dd200168e9a7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1994669601 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.1994669601 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.3439077404 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 11325540000 ps |
| CPU time | 41.37 seconds |
| Started | Mar 07 12:19:10 PM PST 24 |
| Finished | Mar 07 12:20:28 PM PST 24 |
| Peak memory | 145004 kb |
| Host | smart-af607154-791a-49e9-8dfd-d4cc5779dfbc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3439077404 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.3439077404 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.1031603122 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 6901220000 ps |
| CPU time | 26.03 seconds |
| Started | Mar 07 12:19:11 PM PST 24 |
| Finished | Mar 07 12:20:01 PM PST 24 |
| Peak memory | 144896 kb |
| Host | smart-037729c6-3d0a-48c0-a772-c4b0b1b56b35 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1031603122 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.1031603122 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.2604043771 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 6022060000 ps |
| CPU time | 24.85 seconds |
| Started | Mar 07 12:19:20 PM PST 24 |
| Finished | Mar 07 12:20:08 PM PST 24 |
| Peak memory | 145004 kb |
| Host | smart-d8411abc-d43c-4b37-b6e0-a17e8d192d04 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2604043771 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.2604043771 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.3208824737 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 13502360000 ps |
| CPU time | 49.83 seconds |
| Started | Mar 07 12:19:10 PM PST 24 |
| Finished | Mar 07 12:20:44 PM PST 24 |
| Peak memory | 144960 kb |
| Host | smart-86e017ee-015e-454d-a69e-658a723fc201 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3208824737 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.3208824737 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.4081273839 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 12154480000 ps |
| CPU time | 47.35 seconds |
| Started | Mar 07 12:19:20 PM PST 24 |
| Finished | Mar 07 12:20:51 PM PST 24 |
| Peak memory | 145068 kb |
| Host | smart-3b614e43-a3ae-4782-9780-3344a1719267 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4081273839 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.4081273839 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.2094250153 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 9316740000 ps |
| CPU time | 35.05 seconds |
| Started | Mar 07 12:19:10 PM PST 24 |
| Finished | Mar 07 12:20:15 PM PST 24 |
| Peak memory | 144928 kb |
| Host | smart-d2d88c0c-ab6a-40d1-bcbd-9734423b6d71 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2094250153 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.2094250153 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.3969299773 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 13971700000 ps |
| CPU time | 47.77 seconds |
| Started | Mar 07 12:19:12 PM PST 24 |
| Finished | Mar 07 12:20:41 PM PST 24 |
| Peak memory | 144880 kb |
| Host | smart-f950bf7a-ce92-43da-a05b-4c950e80324b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3969299773 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.3969299773 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.3490428540 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 8459280000 ps |
| CPU time | 30.86 seconds |
| Started | Mar 07 12:19:10 PM PST 24 |
| Finished | Mar 07 12:20:08 PM PST 24 |
| Peak memory | 145004 kb |
| Host | smart-491763fd-9c58-4bc2-969e-89494184c002 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3490428540 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.3490428540 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.3867496832 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 9210100000 ps |
| CPU time | 34.01 seconds |
| Started | Mar 07 12:19:12 PM PST 24 |
| Finished | Mar 07 12:20:16 PM PST 24 |
| Peak memory | 144944 kb |
| Host | smart-434b1011-9317-450b-9892-13e639ee0629 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3867496832 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.3867496832 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.2126976292 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 12660400000 ps |
| CPU time | 49.6 seconds |
| Started | Mar 07 12:19:12 PM PST 24 |
| Finished | Mar 07 12:20:47 PM PST 24 |
| Peak memory | 145064 kb |
| Host | smart-734bc59f-a03b-4d7b-a6ef-dd288eb58c26 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2126976292 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.2126976292 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.2680919093 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 4677280000 ps |
| CPU time | 19.25 seconds |
| Started | Mar 07 12:19:19 PM PST 24 |
| Finished | Mar 07 12:19:56 PM PST 24 |
| Peak memory | 145004 kb |
| Host | smart-643fb339-762b-4305-bc4b-9ea25f5f90fb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2680919093 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.2680919093 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.837844919 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 8578320000 ps |
| CPU time | 31.91 seconds |
| Started | Mar 07 12:19:12 PM PST 24 |
| Finished | Mar 07 12:20:12 PM PST 24 |
| Peak memory | 144920 kb |
| Host | smart-98178ece-50d8-4204-b766-8c102a14a773 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=837844919 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.837844919 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.1311473191 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 11012440000 ps |
| CPU time | 37.79 seconds |
| Started | Mar 07 12:21:20 PM PST 24 |
| Finished | Mar 07 12:22:28 PM PST 24 |
| Peak memory | 144788 kb |
| Host | smart-f1d75429-ae1e-4494-80d2-5bee41501d8b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1311473191 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.1311473191 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.2738773514 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 8940400000 ps |
| CPU time | 34.92 seconds |
| Started | Mar 07 12:19:11 PM PST 24 |
| Finished | Mar 07 12:20:18 PM PST 24 |
| Peak memory | 145004 kb |
| Host | smart-d5339e01-ea01-4c3d-9dce-9354a293b7ea |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2738773514 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.2738773514 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.1704368304 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 12613900000 ps |
| CPU time | 45.59 seconds |
| Started | Mar 07 12:19:11 PM PST 24 |
| Finished | Mar 07 12:20:37 PM PST 24 |
| Peak memory | 144960 kb |
| Host | smart-586f2fde-fab9-4cd1-b654-aeb4e630c120 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1704368304 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.1704368304 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.2715577518 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 12646760000 ps |
| CPU time | 45.38 seconds |
| Started | Mar 07 12:19:10 PM PST 24 |
| Finished | Mar 07 12:20:35 PM PST 24 |
| Peak memory | 144956 kb |
| Host | smart-b190230a-548c-416e-b42a-1b8fa30a0cbe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2715577518 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.2715577518 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.443217576 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 5661220000 ps |
| CPU time | 19.92 seconds |
| Started | Mar 07 12:19:12 PM PST 24 |
| Finished | Mar 07 12:19:49 PM PST 24 |
| Peak memory | 144980 kb |
| Host | smart-fda843e3-5246-4eb3-a6c6-e8ab26095ca5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=443217576 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.443217576 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.3665869552 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 8228020000 ps |
| CPU time | 31.2 seconds |
| Started | Mar 07 12:19:10 PM PST 24 |
| Finished | Mar 07 12:20:09 PM PST 24 |
| Peak memory | 145004 kb |
| Host | smart-6b731448-4dec-43c7-9abd-5ac29ea22524 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3665869552 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.3665869552 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.2997987922 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 5442980000 ps |
| CPU time | 20.03 seconds |
| Started | Mar 07 12:19:11 PM PST 24 |
| Finished | Mar 07 12:19:49 PM PST 24 |
| Peak memory | 144920 kb |
| Host | smart-70248f88-a0b6-4774-8693-1cca950ade08 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2997987922 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.2997987922 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.939243880 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 15032520000 ps |
| CPU time | 51.79 seconds |
| Started | Mar 07 12:19:11 PM PST 24 |
| Finished | Mar 07 12:20:48 PM PST 24 |
| Peak memory | 144964 kb |
| Host | smart-ab38b8b1-ebe0-4d5b-b32a-d8a2654de80b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=939243880 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.939243880 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.2841144218 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 7482160000 ps |
| CPU time | 27.12 seconds |
| Started | Mar 07 12:19:12 PM PST 24 |
| Finished | Mar 07 12:20:02 PM PST 24 |
| Peak memory | 144928 kb |
| Host | smart-a11207d3-063e-4190-bef6-525fafadb994 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2841144218 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.2841144218 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.3509021577 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 4609080000 ps |
| CPU time | 15.83 seconds |
| Started | Mar 07 12:19:11 PM PST 24 |
| Finished | Mar 07 12:19:41 PM PST 24 |
| Peak memory | 144860 kb |
| Host | smart-9abf5c95-fe7a-4d08-be96-8292881c9d80 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3509021577 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.3509021577 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.3978143935 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 10079340000 ps |
| CPU time | 33.1 seconds |
| Started | Mar 07 12:19:12 PM PST 24 |
| Finished | Mar 07 12:20:13 PM PST 24 |
| Peak memory | 144996 kb |
| Host | smart-a5a8b83b-1ad7-4ce5-bf0f-d020cf528668 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3978143935 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.3978143935 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.3260977005 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 13745400000 ps |
| CPU time | 48.94 seconds |
| Started | Mar 07 12:19:13 PM PST 24 |
| Finished | Mar 07 12:20:45 PM PST 24 |
| Peak memory | 144860 kb |
| Host | smart-3352df06-de53-4c86-a4ba-77516045838b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3260977005 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.3260977005 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.1771471172 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 9465540000 ps |
| CPU time | 32.29 seconds |
| Started | Mar 07 12:21:11 PM PST 24 |
| Finished | Mar 07 12:22:09 PM PST 24 |
| Peak memory | 143800 kb |
| Host | smart-ffdbd236-dabc-4800-b391-7b2d284a3440 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1771471172 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.1771471172 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.2034004258 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 6353140000 ps |
| CPU time | 22.92 seconds |
| Started | Mar 07 12:19:12 PM PST 24 |
| Finished | Mar 07 12:19:55 PM PST 24 |
| Peak memory | 144928 kb |
| Host | smart-addf0e13-895a-43c1-a9a9-7f401fda6b57 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2034004258 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.2034004258 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.1775056803 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 11489840000 ps |
| CPU time | 39.77 seconds |
| Started | Mar 07 12:21:20 PM PST 24 |
| Finished | Mar 07 12:22:32 PM PST 24 |
| Peak memory | 144584 kb |
| Host | smart-cffdbe1a-b8c7-4bea-a5c8-cf8bd1f75cce |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1775056803 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.1775056803 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.418385146 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 7749380000 ps |
| CPU time | 26.25 seconds |
| Started | Mar 07 12:19:12 PM PST 24 |
| Finished | Mar 07 12:20:01 PM PST 24 |
| Peak memory | 144996 kb |
| Host | smart-8b0a6d01-410a-4306-9f0f-c937f8fafb7d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=418385146 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.418385146 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.1063340781 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 10040900000 ps |
| CPU time | 36.27 seconds |
| Started | Mar 07 12:19:12 PM PST 24 |
| Finished | Mar 07 12:20:21 PM PST 24 |
| Peak memory | 144928 kb |
| Host | smart-7d61c44e-9ccd-493e-adbf-71f28383ffef |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1063340781 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.1063340781 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.2578847463 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 6677400000 ps |
| CPU time | 24.18 seconds |
| Started | Mar 07 12:21:19 PM PST 24 |
| Finished | Mar 07 12:22:03 PM PST 24 |
| Peak memory | 144036 kb |
| Host | smart-01069730-3541-42b6-b182-7ed82e9a538e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2578847463 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.2578847463 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.3941410503 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 7883300000 ps |
| CPU time | 29.3 seconds |
| Started | Mar 07 12:19:11 PM PST 24 |
| Finished | Mar 07 12:20:06 PM PST 24 |
| Peak memory | 144864 kb |
| Host | smart-baaf0d36-c1dd-4f11-9658-4185de230008 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3941410503 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.3941410503 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.631260053 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 13386420000 ps |
| CPU time | 47.83 seconds |
| Started | Mar 07 12:27:23 PM PST 24 |
| Finished | Mar 07 12:28:53 PM PST 24 |
| Peak memory | 144568 kb |
| Host | smart-f143272c-3bbc-4535-a27c-1c14c2057dbf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=631260053 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.631260053 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.2348934786 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 4844060000 ps |
| CPU time | 19.24 seconds |
| Started | Mar 07 12:27:23 PM PST 24 |
| Finished | Mar 07 12:27:59 PM PST 24 |
| Peak memory | 143712 kb |
| Host | smart-15eece1a-86f6-49a6-8963-8570458d615c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2348934786 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.2348934786 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.267705849 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 7355680000 ps |
| CPU time | 25.83 seconds |
| Started | Mar 07 12:19:29 PM PST 24 |
| Finished | Mar 07 12:20:17 PM PST 24 |
| Peak memory | 145004 kb |
| Host | smart-eb1f0c02-1e2b-4fb0-94f8-fa53efe6956a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=267705849 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.267705849 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.3424438748 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 7484020000 ps |
| CPU time | 23.27 seconds |
| Started | Mar 07 12:19:23 PM PST 24 |
| Finished | Mar 07 12:20:06 PM PST 24 |
| Peak memory | 145032 kb |
| Host | smart-77b37795-0ba7-40c2-a791-a4c93d32be8a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3424438748 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.3424438748 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.257865254 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 10778700000 ps |
| CPU time | 37.13 seconds |
| Started | Mar 07 12:19:51 PM PST 24 |
| Finished | Mar 07 12:21:01 PM PST 24 |
| Peak memory | 144996 kb |
| Host | smart-a6eb7540-62a7-4846-b6f0-73cea7f6db72 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=257865254 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.257865254 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.3109944973 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 3475720000 ps |
| CPU time | 11.92 seconds |
| Started | Mar 07 12:19:29 PM PST 24 |
| Finished | Mar 07 12:19:51 PM PST 24 |
| Peak memory | 144752 kb |
| Host | smart-06859189-1f63-4097-8b57-152c13089bc5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3109944973 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.3109944973 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.134030111 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 14401980000 ps |
| CPU time | 49.1 seconds |
| Started | Mar 07 12:27:23 PM PST 24 |
| Finished | Mar 07 12:28:55 PM PST 24 |
| Peak memory | 144528 kb |
| Host | smart-1f348eae-2703-49a2-8901-5753caa866b2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=134030111 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.134030111 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.2480180643 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 8604980000 ps |
| CPU time | 29.65 seconds |
| Started | Mar 07 12:19:12 PM PST 24 |
| Finished | Mar 07 12:20:07 PM PST 24 |
| Peak memory | 144944 kb |
| Host | smart-a8234fe5-3826-4463-9353-953f3d74fc9c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2480180643 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.2480180643 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.2984774197 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 9018520000 ps |
| CPU time | 33.46 seconds |
| Started | Mar 07 12:19:10 PM PST 24 |
| Finished | Mar 07 12:20:13 PM PST 24 |
| Peak memory | 144892 kb |
| Host | smart-ab19575d-6a1a-4c57-8d09-bc15b657086b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2984774197 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.2984774197 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.2654929905 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 13075800000 ps |
| CPU time | 45.75 seconds |
| Started | Mar 07 12:19:11 PM PST 24 |
| Finished | Mar 07 12:20:36 PM PST 24 |
| Peak memory | 144944 kb |
| Host | smart-74606094-d15d-4474-9a8e-072443e770ec |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2654929905 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.2654929905 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.542457405 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 10695000000 ps |
| CPU time | 36.29 seconds |
| Started | Mar 07 12:19:11 PM PST 24 |
| Finished | Mar 07 12:20:18 PM PST 24 |
| Peak memory | 144980 kb |
| Host | smart-c6c26848-afd2-4e93-b615-d15027706b2f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=542457405 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.542457405 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.1828042890 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 6436220000 ps |
| CPU time | 23.18 seconds |
| Started | Mar 07 12:19:11 PM PST 24 |
| Finished | Mar 07 12:19:54 PM PST 24 |
| Peak memory | 144944 kb |
| Host | smart-a0c30b44-7f8f-44cb-9860-fc87ec6c4d3a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1828042890 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.1828042890 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |