| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/11.prim_present_test.976160155 | ||
| Name |
|---|
| /workspace/coverage/default/0.prim_present_test.492969802 |
| /workspace/coverage/default/1.prim_present_test.1198947162 |
| /workspace/coverage/default/10.prim_present_test.2582170585 |
| /workspace/coverage/default/12.prim_present_test.682506001 |
| /workspace/coverage/default/13.prim_present_test.236263451 |
| /workspace/coverage/default/14.prim_present_test.2478298937 |
| /workspace/coverage/default/15.prim_present_test.2059047351 |
| /workspace/coverage/default/16.prim_present_test.4007450748 |
| /workspace/coverage/default/17.prim_present_test.4261737175 |
| /workspace/coverage/default/18.prim_present_test.3413945570 |
| /workspace/coverage/default/19.prim_present_test.3739382522 |
| /workspace/coverage/default/2.prim_present_test.1166502883 |
| /workspace/coverage/default/20.prim_present_test.160552827 |
| /workspace/coverage/default/21.prim_present_test.3508413977 |
| /workspace/coverage/default/22.prim_present_test.541790425 |
| /workspace/coverage/default/23.prim_present_test.3782647310 |
| /workspace/coverage/default/24.prim_present_test.1966075524 |
| /workspace/coverage/default/25.prim_present_test.537957779 |
| /workspace/coverage/default/26.prim_present_test.1319157087 |
| /workspace/coverage/default/27.prim_present_test.3602103733 |
| /workspace/coverage/default/28.prim_present_test.1863542134 |
| /workspace/coverage/default/29.prim_present_test.3798284090 |
| /workspace/coverage/default/3.prim_present_test.62351830 |
| /workspace/coverage/default/30.prim_present_test.3696520841 |
| /workspace/coverage/default/31.prim_present_test.3177921582 |
| /workspace/coverage/default/32.prim_present_test.721024155 |
| /workspace/coverage/default/33.prim_present_test.3560805736 |
| /workspace/coverage/default/34.prim_present_test.3317159556 |
| /workspace/coverage/default/35.prim_present_test.4006782602 |
| /workspace/coverage/default/36.prim_present_test.1266901596 |
| /workspace/coverage/default/37.prim_present_test.666851090 |
| /workspace/coverage/default/38.prim_present_test.4228094670 |
| /workspace/coverage/default/39.prim_present_test.2123279276 |
| /workspace/coverage/default/4.prim_present_test.3489624867 |
| /workspace/coverage/default/40.prim_present_test.3811152445 |
| /workspace/coverage/default/41.prim_present_test.1787332382 |
| /workspace/coverage/default/42.prim_present_test.3536585521 |
| /workspace/coverage/default/43.prim_present_test.500452397 |
| /workspace/coverage/default/44.prim_present_test.2703206502 |
| /workspace/coverage/default/45.prim_present_test.254495220 |
| /workspace/coverage/default/46.prim_present_test.2117262158 |
| /workspace/coverage/default/47.prim_present_test.3867151704 |
| /workspace/coverage/default/48.prim_present_test.3309698373 |
| /workspace/coverage/default/49.prim_present_test.3526911013 |
| /workspace/coverage/default/5.prim_present_test.3451245341 |
| /workspace/coverage/default/6.prim_present_test.2131015766 |
| /workspace/coverage/default/7.prim_present_test.294818102 |
| /workspace/coverage/default/8.prim_present_test.3618140288 |
| /workspace/coverage/default/9.prim_present_test.2230346606 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/12.prim_present_test.682506001 | Mar 10 12:16:55 PM PDT 24 | Mar 10 12:18:13 PM PDT 24 | 13240720000 ps | ||
| T2 | /workspace/coverage/default/9.prim_present_test.2230346606 | Mar 10 12:16:55 PM PDT 24 | Mar 10 12:18:09 PM PDT 24 | 12639320000 ps | ||
| T3 | /workspace/coverage/default/11.prim_present_test.976160155 | Mar 10 12:21:02 PM PDT 24 | Mar 10 12:22:01 PM PDT 24 | 9014800000 ps | ||
| T4 | /workspace/coverage/default/17.prim_present_test.4261737175 | Mar 10 12:21:20 PM PDT 24 | Mar 10 12:22:22 PM PDT 24 | 9523200000 ps | ||
| T5 | /workspace/coverage/default/40.prim_present_test.3811152445 | Mar 10 12:23:59 PM PDT 24 | Mar 10 12:24:25 PM PDT 24 | 3474480000 ps | ||
| T6 | /workspace/coverage/default/8.prim_present_test.3618140288 | Mar 10 12:16:55 PM PDT 24 | Mar 10 12:18:14 PM PDT 24 | 13206620000 ps | ||
| T7 | /workspace/coverage/default/26.prim_present_test.1319157087 | Mar 10 12:17:21 PM PDT 24 | Mar 10 12:18:13 PM PDT 24 | 7027080000 ps | ||
| T8 | /workspace/coverage/default/31.prim_present_test.3177921582 | Mar 10 12:21:23 PM PDT 24 | Mar 10 12:21:56 PM PDT 24 | 5367340000 ps | ||
| T9 | /workspace/coverage/default/49.prim_present_test.3526911013 | Mar 10 12:17:05 PM PDT 24 | Mar 10 12:18:32 PM PDT 24 | 10011140000 ps | ||
| T10 | /workspace/coverage/default/25.prim_present_test.537957779 | Mar 10 12:17:05 PM PDT 24 | Mar 10 12:18:13 PM PDT 24 | 7574540000 ps | ||
| T11 | /workspace/coverage/default/37.prim_present_test.666851090 | Mar 10 12:23:59 PM PDT 24 | Mar 10 12:25:23 PM PDT 24 | 12918320000 ps | ||
| T12 | /workspace/coverage/default/28.prim_present_test.1863542134 | Mar 10 12:17:07 PM PDT 24 | Mar 10 12:17:37 PM PDT 24 | 3286000000 ps | ||
| T13 | /workspace/coverage/default/2.prim_present_test.1166502883 | Mar 10 12:23:02 PM PDT 24 | Mar 10 12:24:40 PM PDT 24 | 15473340000 ps | ||
| T14 | /workspace/coverage/default/41.prim_present_test.1787332382 | Mar 10 12:19:49 PM PDT 24 | Mar 10 12:20:53 PM PDT 24 | 10049580000 ps | ||
| T15 | /workspace/coverage/default/43.prim_present_test.500452397 | Mar 10 12:19:48 PM PDT 24 | Mar 10 12:20:24 PM PDT 24 | 5334480000 ps | ||
| T16 | /workspace/coverage/default/10.prim_present_test.2582170585 | Mar 10 12:23:19 PM PDT 24 | Mar 10 12:23:53 PM PDT 24 | 4408820000 ps | ||
| T17 | /workspace/coverage/default/7.prim_present_test.294818102 | Mar 10 12:17:08 PM PDT 24 | Mar 10 12:18:32 PM PDT 24 | 11523320000 ps | ||
| T18 | /workspace/coverage/default/21.prim_present_test.3508413977 | Mar 10 12:16:56 PM PDT 24 | Mar 10 12:18:25 PM PDT 24 | 15364840000 ps | ||
| T19 | /workspace/coverage/default/14.prim_present_test.2478298937 | Mar 10 12:17:22 PM PDT 24 | Mar 10 12:18:11 PM PDT 24 | 7244700000 ps | ||
| T20 | /workspace/coverage/default/0.prim_present_test.492969802 | Mar 10 12:17:22 PM PDT 24 | Mar 10 12:18:01 PM PDT 24 | 5514900000 ps | ||
| T21 | /workspace/coverage/default/42.prim_present_test.3536585521 | Mar 10 12:23:58 PM PDT 24 | Mar 10 12:24:34 PM PDT 24 | 4913500000 ps | ||
| T22 | /workspace/coverage/default/35.prim_present_test.4006782602 | Mar 10 12:23:58 PM PDT 24 | Mar 10 12:24:48 PM PDT 24 | 6948960000 ps | ||
| T23 | /workspace/coverage/default/3.prim_present_test.62351830 | Mar 10 12:17:04 PM PDT 24 | Mar 10 12:19:05 PM PDT 24 | 14333780000 ps | ||
| T24 | /workspace/coverage/default/19.prim_present_test.3739382522 | Mar 10 12:23:18 PM PDT 24 | Mar 10 12:24:48 PM PDT 24 | 12555000000 ps | ||
| T25 | /workspace/coverage/default/4.prim_present_test.3489624867 | Mar 10 12:17:06 PM PDT 24 | Mar 10 12:18:57 PM PDT 24 | 12791220000 ps | ||
| T26 | /workspace/coverage/default/29.prim_present_test.3798284090 | Mar 10 12:23:58 PM PDT 24 | Mar 10 12:24:32 PM PDT 24 | 4685960000 ps | ||
| T27 | /workspace/coverage/default/15.prim_present_test.2059047351 | Mar 10 12:18:59 PM PDT 24 | Mar 10 12:19:49 PM PDT 24 | 7609880000 ps | ||
| T28 | /workspace/coverage/default/23.prim_present_test.3782647310 | Mar 10 12:17:04 PM PDT 24 | Mar 10 12:19:03 PM PDT 24 | 13819180000 ps | ||
| T29 | /workspace/coverage/default/34.prim_present_test.3317159556 | Mar 10 12:17:06 PM PDT 24 | Mar 10 12:18:18 PM PDT 24 | 8111460000 ps | ||
| T30 | /workspace/coverage/default/36.prim_present_test.1266901596 | Mar 10 12:17:02 PM PDT 24 | Mar 10 12:17:51 PM PDT 24 | 7124420000 ps | ||
| T31 | /workspace/coverage/default/44.prim_present_test.2703206502 | Mar 10 12:17:47 PM PDT 24 | Mar 10 12:18:25 PM PDT 24 | 5101980000 ps | ||
| T32 | /workspace/coverage/default/1.prim_present_test.1198947162 | Mar 10 12:16:55 PM PDT 24 | Mar 10 12:17:18 PM PDT 24 | 3809280000 ps | ||
| T33 | /workspace/coverage/default/45.prim_present_test.254495220 | Mar 10 12:21:14 PM PDT 24 | Mar 10 12:22:15 PM PDT 24 | 9432680000 ps | ||
| T34 | /workspace/coverage/default/16.prim_present_test.4007450748 | Mar 10 12:17:05 PM PDT 24 | Mar 10 12:19:04 PM PDT 24 | 13969220000 ps | ||
| T35 | /workspace/coverage/default/20.prim_present_test.160552827 | Mar 10 12:17:07 PM PDT 24 | Mar 10 12:18:56 PM PDT 24 | 12941880000 ps | ||
| T36 | /workspace/coverage/default/48.prim_present_test.3309698373 | Mar 10 12:17:02 PM PDT 24 | Mar 10 12:17:46 PM PDT 24 | 6387860000 ps | ||
| T37 | /workspace/coverage/default/6.prim_present_test.2131015766 | Mar 10 12:21:21 PM PDT 24 | Mar 10 12:22:31 PM PDT 24 | 10946720000 ps | ||
| T38 | /workspace/coverage/default/5.prim_present_test.3451245341 | Mar 10 12:21:03 PM PDT 24 | Mar 10 12:21:59 PM PDT 24 | 8247860000 ps | ||
| T39 | /workspace/coverage/default/47.prim_present_test.3867151704 | Mar 10 12:17:02 PM PDT 24 | Mar 10 12:18:14 PM PDT 24 | 10640440000 ps | ||
| T40 | /workspace/coverage/default/30.prim_present_test.3696520841 | Mar 10 12:17:06 PM PDT 24 | Mar 10 12:18:35 PM PDT 24 | 10276500000 ps | ||
| T41 | /workspace/coverage/default/22.prim_present_test.541790425 | Mar 10 12:23:19 PM PDT 24 | Mar 10 12:24:54 PM PDT 24 | 13883660000 ps | ||
| T42 | /workspace/coverage/default/46.prim_present_test.2117262158 | Mar 10 12:17:02 PM PDT 24 | Mar 10 12:17:34 PM PDT 24 | 4559480000 ps | ||
| T43 | /workspace/coverage/default/13.prim_present_test.236263451 | Mar 10 12:19:23 PM PDT 24 | Mar 10 12:20:27 PM PDT 24 | 8950320000 ps | ||
| T44 | /workspace/coverage/default/38.prim_present_test.4228094670 | Mar 10 12:23:59 PM PDT 24 | Mar 10 12:25:33 PM PDT 24 | 14764680000 ps | ||
| T45 | /workspace/coverage/default/18.prim_present_test.3413945570 | Mar 10 12:23:19 PM PDT 24 | Mar 10 12:24:39 PM PDT 24 | 10776220000 ps | ||
| T46 | /workspace/coverage/default/39.prim_present_test.2123279276 | Mar 10 12:17:00 PM PDT 24 | Mar 10 12:17:45 PM PDT 24 | 6378560000 ps | ||
| T47 | /workspace/coverage/default/33.prim_present_test.3560805736 | Mar 10 12:17:24 PM PDT 24 | Mar 10 12:18:03 PM PDT 24 | 5345020000 ps | ||
| T48 | /workspace/coverage/default/24.prim_present_test.1966075524 | Mar 10 12:17:06 PM PDT 24 | Mar 10 12:19:02 PM PDT 24 | 13860720000 ps | ||
| T49 | /workspace/coverage/default/27.prim_present_test.3602103733 | Mar 10 12:23:01 PM PDT 24 | Mar 10 12:24:00 PM PDT 24 | 8770520000 ps | ||
| T50 | /workspace/coverage/default/32.prim_present_test.721024155 | Mar 10 12:17:02 PM PDT 24 | Mar 10 12:18:26 PM PDT 24 | 13114860000 ps |
| Test location | /workspace/coverage/default/11.prim_present_test.976160155 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 9014800000 ps |
| CPU time | 32.34 seconds |
| Started | Mar 10 12:21:02 PM PDT 24 |
| Finished | Mar 10 12:22:01 PM PDT 24 |
| Peak memory | 144772 kb |
| Host | smart-3823d00a-7743-4d94-9852-d023b76f4074 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=976160155 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.976160155 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/0.prim_present_test.492969802 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 5514900000 ps |
| CPU time | 20 seconds |
| Started | Mar 10 12:17:22 PM PDT 24 |
| Finished | Mar 10 12:18:01 PM PDT 24 |
| Peak memory | 143324 kb |
| Host | smart-8ebc6971-1fa6-48f8-8c70-6c59f8d25f73 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=492969802 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.492969802 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/1.prim_present_test.1198947162 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 3809280000 ps |
| CPU time | 12.63 seconds |
| Started | Mar 10 12:16:55 PM PDT 24 |
| Finished | Mar 10 12:17:18 PM PDT 24 |
| Peak memory | 145000 kb |
| Host | smart-6d0f8264-cfbb-4310-a21b-69bf4a53cbdc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1198947162 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.1198947162 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/10.prim_present_test.2582170585 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 4408820000 ps |
| CPU time | 17.52 seconds |
| Started | Mar 10 12:23:19 PM PDT 24 |
| Finished | Mar 10 12:23:53 PM PDT 24 |
| Peak memory | 144740 kb |
| Host | smart-99d1520d-1b65-4897-9158-6268df983fe8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2582170585 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.2582170585 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.682506001 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 13240720000 ps |
| CPU time | 42.3 seconds |
| Started | Mar 10 12:16:55 PM PDT 24 |
| Finished | Mar 10 12:18:13 PM PDT 24 |
| Peak memory | 145152 kb |
| Host | smart-b402d67f-f6cf-4621-ac64-6a54cbceef8d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=682506001 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.682506001 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.236263451 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 8950320000 ps |
| CPU time | 33.31 seconds |
| Started | Mar 10 12:19:23 PM PDT 24 |
| Finished | Mar 10 12:20:27 PM PDT 24 |
| Peak memory | 145056 kb |
| Host | smart-264567ef-3453-4f40-8169-f4834100033c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=236263451 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.236263451 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.2478298937 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 7244700000 ps |
| CPU time | 25.16 seconds |
| Started | Mar 10 12:17:22 PM PDT 24 |
| Finished | Mar 10 12:18:11 PM PDT 24 |
| Peak memory | 143236 kb |
| Host | smart-d0d97dc1-c91f-4b66-b16e-e8047f2bb8c2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2478298937 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.2478298937 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.2059047351 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 7609880000 ps |
| CPU time | 26.7 seconds |
| Started | Mar 10 12:18:59 PM PDT 24 |
| Finished | Mar 10 12:19:49 PM PDT 24 |
| Peak memory | 145056 kb |
| Host | smart-ed8e320f-2eab-4484-8ca8-2906feef97e0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2059047351 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.2059047351 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.4007450748 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 13969220000 ps |
| CPU time | 59.11 seconds |
| Started | Mar 10 12:17:05 PM PDT 24 |
| Finished | Mar 10 12:19:04 PM PDT 24 |
| Peak memory | 144316 kb |
| Host | smart-5f3606d4-20d6-4abb-a76a-0ef8d4e8f7b3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4007450748 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.4007450748 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.4261737175 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 9523200000 ps |
| CPU time | 33.22 seconds |
| Started | Mar 10 12:21:20 PM PDT 24 |
| Finished | Mar 10 12:22:22 PM PDT 24 |
| Peak memory | 144744 kb |
| Host | smart-425061a7-c6fd-43d4-9fa1-c43680d7b3c2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4261737175 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.4261737175 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.3413945570 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 10776220000 ps |
| CPU time | 42.1 seconds |
| Started | Mar 10 12:23:19 PM PDT 24 |
| Finished | Mar 10 12:24:39 PM PDT 24 |
| Peak memory | 144700 kb |
| Host | smart-4bb352dc-1121-4e22-bb7f-749fb191b52f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3413945570 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.3413945570 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.3739382522 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 12555000000 ps |
| CPU time | 47.34 seconds |
| Started | Mar 10 12:23:18 PM PDT 24 |
| Finished | Mar 10 12:24:48 PM PDT 24 |
| Peak memory | 144804 kb |
| Host | smart-28251129-d510-4c81-bd43-cb38399607ca |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3739382522 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.3739382522 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.1166502883 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 15473340000 ps |
| CPU time | 52.83 seconds |
| Started | Mar 10 12:23:02 PM PDT 24 |
| Finished | Mar 10 12:24:40 PM PDT 24 |
| Peak memory | 144584 kb |
| Host | smart-624af0c8-c211-40ba-b2c9-c0934172c0a9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1166502883 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.1166502883 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.160552827 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 12941880000 ps |
| CPU time | 54.26 seconds |
| Started | Mar 10 12:17:07 PM PDT 24 |
| Finished | Mar 10 12:18:56 PM PDT 24 |
| Peak memory | 144432 kb |
| Host | smart-ee1117d2-632c-4a32-84f2-f073de9d4342 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=160552827 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.160552827 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.3508413977 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 15364840000 ps |
| CPU time | 47.64 seconds |
| Started | Mar 10 12:16:56 PM PDT 24 |
| Finished | Mar 10 12:18:25 PM PDT 24 |
| Peak memory | 145152 kb |
| Host | smart-1eb7deed-fbf7-4825-b515-b5cd6bde78bf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3508413977 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.3508413977 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.541790425 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 13883660000 ps |
| CPU time | 50.23 seconds |
| Started | Mar 10 12:23:19 PM PDT 24 |
| Finished | Mar 10 12:24:54 PM PDT 24 |
| Peak memory | 144804 kb |
| Host | smart-a4f3775e-3f7d-40ca-af68-bd35aec3a3ef |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=541790425 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.541790425 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.3782647310 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 13819180000 ps |
| CPU time | 60.01 seconds |
| Started | Mar 10 12:17:04 PM PDT 24 |
| Finished | Mar 10 12:19:03 PM PDT 24 |
| Peak memory | 143892 kb |
| Host | smart-981dfe4b-c80d-446c-9d83-3bd6caf80c88 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3782647310 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.3782647310 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.1966075524 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 13860720000 ps |
| CPU time | 57.9 seconds |
| Started | Mar 10 12:17:06 PM PDT 24 |
| Finished | Mar 10 12:19:02 PM PDT 24 |
| Peak memory | 144432 kb |
| Host | smart-98278d1f-0eea-44ed-9930-27ac6abdc849 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1966075524 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.1966075524 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.537957779 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 7574540000 ps |
| CPU time | 33.74 seconds |
| Started | Mar 10 12:17:05 PM PDT 24 |
| Finished | Mar 10 12:18:13 PM PDT 24 |
| Peak memory | 144432 kb |
| Host | smart-66825158-7dd1-45c4-9726-71438540f98a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=537957779 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.537957779 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.1319157087 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 7027080000 ps |
| CPU time | 27.36 seconds |
| Started | Mar 10 12:17:21 PM PDT 24 |
| Finished | Mar 10 12:18:13 PM PDT 24 |
| Peak memory | 145056 kb |
| Host | smart-eb02043b-e57a-4e37-ba4b-009117612c93 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1319157087 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.1319157087 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.3602103733 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 8770520000 ps |
| CPU time | 30.8 seconds |
| Started | Mar 10 12:23:01 PM PDT 24 |
| Finished | Mar 10 12:24:00 PM PDT 24 |
| Peak memory | 143320 kb |
| Host | smart-e933cdb4-dbea-4035-a6f9-722726f0960c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3602103733 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.3602103733 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.1863542134 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 3286000000 ps |
| CPU time | 14.78 seconds |
| Started | Mar 10 12:17:07 PM PDT 24 |
| Finished | Mar 10 12:17:37 PM PDT 24 |
| Peak memory | 144932 kb |
| Host | smart-599731bc-e377-455c-b1d6-856cde6dfc78 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1863542134 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.1863542134 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.3798284090 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 4685960000 ps |
| CPU time | 18.29 seconds |
| Started | Mar 10 12:23:58 PM PDT 24 |
| Finished | Mar 10 12:24:32 PM PDT 24 |
| Peak memory | 142296 kb |
| Host | smart-c5c6adc8-ab32-4792-9e63-fb564b1e575b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3798284090 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.3798284090 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.62351830 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 14333780000 ps |
| CPU time | 60.74 seconds |
| Started | Mar 10 12:17:04 PM PDT 24 |
| Finished | Mar 10 12:19:05 PM PDT 24 |
| Peak memory | 143608 kb |
| Host | smart-2b0d3a22-6dcf-466e-b46d-386d27f93374 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=62351830 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.62351830 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.3696520841 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 10276500000 ps |
| CPU time | 43.42 seconds |
| Started | Mar 10 12:17:06 PM PDT 24 |
| Finished | Mar 10 12:18:35 PM PDT 24 |
| Peak memory | 144432 kb |
| Host | smart-811bf16c-e9c0-421c-8a69-5d7f36b0d675 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3696520841 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.3696520841 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.3177921582 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 5367340000 ps |
| CPU time | 17.63 seconds |
| Started | Mar 10 12:21:23 PM PDT 24 |
| Finished | Mar 10 12:21:56 PM PDT 24 |
| Peak memory | 144800 kb |
| Host | smart-837fe2e5-5c84-4ac0-9130-8ca4c3d2a620 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3177921582 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.3177921582 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.721024155 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 13114860000 ps |
| CPU time | 45.38 seconds |
| Started | Mar 10 12:17:02 PM PDT 24 |
| Finished | Mar 10 12:18:26 PM PDT 24 |
| Peak memory | 144316 kb |
| Host | smart-5e490ad5-1b8f-4b86-8a78-a22808df7933 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=721024155 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.721024155 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.3560805736 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 5345020000 ps |
| CPU time | 20.98 seconds |
| Started | Mar 10 12:17:24 PM PDT 24 |
| Finished | Mar 10 12:18:03 PM PDT 24 |
| Peak memory | 145056 kb |
| Host | smart-04f41ed8-92ea-427b-b55c-87964ca49792 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3560805736 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.3560805736 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.3317159556 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 8111460000 ps |
| CPU time | 35.71 seconds |
| Started | Mar 10 12:17:06 PM PDT 24 |
| Finished | Mar 10 12:18:18 PM PDT 24 |
| Peak memory | 144432 kb |
| Host | smart-c6005051-3ab9-441d-9654-9c498369037e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3317159556 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.3317159556 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.4006782602 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 6948960000 ps |
| CPU time | 26.61 seconds |
| Started | Mar 10 12:23:58 PM PDT 24 |
| Finished | Mar 10 12:24:48 PM PDT 24 |
| Peak memory | 142204 kb |
| Host | smart-84aa30f0-da88-4a41-9e6b-e2fed5578580 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4006782602 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.4006782602 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.1266901596 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 7124420000 ps |
| CPU time | 26.01 seconds |
| Started | Mar 10 12:17:02 PM PDT 24 |
| Finished | Mar 10 12:17:51 PM PDT 24 |
| Peak memory | 144428 kb |
| Host | smart-990d1e99-f9d5-4593-9fc4-3e77c09f9aac |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1266901596 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.1266901596 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.666851090 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 12918320000 ps |
| CPU time | 45.04 seconds |
| Started | Mar 10 12:23:59 PM PDT 24 |
| Finished | Mar 10 12:25:23 PM PDT 24 |
| Peak memory | 144632 kb |
| Host | smart-0febdac5-d873-44fc-9ee7-372ee02eb830 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=666851090 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.666851090 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.4228094670 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 14764680000 ps |
| CPU time | 50.31 seconds |
| Started | Mar 10 12:23:59 PM PDT 24 |
| Finished | Mar 10 12:25:33 PM PDT 24 |
| Peak memory | 144384 kb |
| Host | smart-dd07d32d-c356-4d82-aa26-e4749e3f04d8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4228094670 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.4228094670 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.2123279276 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 6378560000 ps |
| CPU time | 23.85 seconds |
| Started | Mar 10 12:17:00 PM PDT 24 |
| Finished | Mar 10 12:17:45 PM PDT 24 |
| Peak memory | 143872 kb |
| Host | smart-f7fea0c0-766a-4096-9377-492c2f5b7707 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2123279276 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.2123279276 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.3489624867 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 12791220000 ps |
| CPU time | 55.91 seconds |
| Started | Mar 10 12:17:06 PM PDT 24 |
| Finished | Mar 10 12:18:57 PM PDT 24 |
| Peak memory | 144432 kb |
| Host | smart-c7a60eed-1d25-40f7-9766-77fafbeeacbb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3489624867 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.3489624867 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.3811152445 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 3474480000 ps |
| CPU time | 13.79 seconds |
| Started | Mar 10 12:23:59 PM PDT 24 |
| Finished | Mar 10 12:24:25 PM PDT 24 |
| Peak memory | 144368 kb |
| Host | smart-a214fa62-c9af-4ce6-ab5a-d21d11841f25 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3811152445 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.3811152445 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.1787332382 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 10049580000 ps |
| CPU time | 35 seconds |
| Started | Mar 10 12:19:49 PM PDT 24 |
| Finished | Mar 10 12:20:53 PM PDT 24 |
| Peak memory | 144836 kb |
| Host | smart-dd49203b-4962-4ba3-86c1-9e208db381ba |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1787332382 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.1787332382 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.3536585521 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 4913500000 ps |
| CPU time | 18.96 seconds |
| Started | Mar 10 12:23:58 PM PDT 24 |
| Finished | Mar 10 12:24:34 PM PDT 24 |
| Peak memory | 143480 kb |
| Host | smart-1a59cf07-550b-4fa7-8499-8a37c3d8906b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3536585521 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.3536585521 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.500452397 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 5334480000 ps |
| CPU time | 19.61 seconds |
| Started | Mar 10 12:19:48 PM PDT 24 |
| Finished | Mar 10 12:20:24 PM PDT 24 |
| Peak memory | 144772 kb |
| Host | smart-750bf6bc-9bd4-4233-93d5-4e25aad08f47 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=500452397 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.500452397 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.2703206502 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 5101980000 ps |
| CPU time | 19.67 seconds |
| Started | Mar 10 12:17:47 PM PDT 24 |
| Finished | Mar 10 12:18:25 PM PDT 24 |
| Peak memory | 145056 kb |
| Host | smart-841b6e27-0ce4-46fe-814d-6dbf6a637c18 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2703206502 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.2703206502 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.254495220 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 9432680000 ps |
| CPU time | 33.5 seconds |
| Started | Mar 10 12:21:14 PM PDT 24 |
| Finished | Mar 10 12:22:15 PM PDT 24 |
| Peak memory | 144768 kb |
| Host | smart-06029cde-782f-491f-a76e-1fdd9065c45f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=254495220 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.254495220 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.2117262158 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 4559480000 ps |
| CPU time | 16.86 seconds |
| Started | Mar 10 12:17:02 PM PDT 24 |
| Finished | Mar 10 12:17:34 PM PDT 24 |
| Peak memory | 144248 kb |
| Host | smart-95ffdec3-88e1-46ba-960d-eb7bc13d9098 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2117262158 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.2117262158 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.3867151704 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 10640440000 ps |
| CPU time | 38.72 seconds |
| Started | Mar 10 12:17:02 PM PDT 24 |
| Finished | Mar 10 12:18:14 PM PDT 24 |
| Peak memory | 144428 kb |
| Host | smart-ffe2e7db-a686-42bb-9b6f-31f3604179d7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3867151704 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.3867151704 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.3309698373 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 6387860000 ps |
| CPU time | 23.83 seconds |
| Started | Mar 10 12:17:02 PM PDT 24 |
| Finished | Mar 10 12:17:46 PM PDT 24 |
| Peak memory | 144428 kb |
| Host | smart-6fc64361-f4f8-4a28-ad4f-d74897b8b050 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3309698373 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.3309698373 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.3526911013 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 10011140000 ps |
| CPU time | 42.93 seconds |
| Started | Mar 10 12:17:05 PM PDT 24 |
| Finished | Mar 10 12:18:32 PM PDT 24 |
| Peak memory | 144432 kb |
| Host | smart-5d08165d-fbe8-4a03-b230-53cd4545d283 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3526911013 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.3526911013 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.3451245341 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 8247860000 ps |
| CPU time | 30.41 seconds |
| Started | Mar 10 12:21:03 PM PDT 24 |
| Finished | Mar 10 12:21:59 PM PDT 24 |
| Peak memory | 144756 kb |
| Host | smart-48d6447b-ac5d-479d-ad50-a0314f960497 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3451245341 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.3451245341 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.2131015766 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 10946720000 ps |
| CPU time | 37.72 seconds |
| Started | Mar 10 12:21:21 PM PDT 24 |
| Finished | Mar 10 12:22:31 PM PDT 24 |
| Peak memory | 144756 kb |
| Host | smart-e5908501-25c2-45f0-b574-fb8f68cd268e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2131015766 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.2131015766 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.294818102 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 11523320000 ps |
| CPU time | 44.65 seconds |
| Started | Mar 10 12:17:08 PM PDT 24 |
| Finished | Mar 10 12:18:32 PM PDT 24 |
| Peak memory | 145056 kb |
| Host | smart-3f10a575-cf5a-4f56-a5eb-531ab089cbee |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=294818102 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.294818102 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.3618140288 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 13206620000 ps |
| CPU time | 42.27 seconds |
| Started | Mar 10 12:16:55 PM PDT 24 |
| Finished | Mar 10 12:18:14 PM PDT 24 |
| Peak memory | 145152 kb |
| Host | smart-e9182670-2b49-4017-8f14-dbcf7368f48d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3618140288 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.3618140288 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.2230346606 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 12639320000 ps |
| CPU time | 39.61 seconds |
| Started | Mar 10 12:16:55 PM PDT 24 |
| Finished | Mar 10 12:18:09 PM PDT 24 |
| Peak memory | 145156 kb |
| Host | smart-4cf31293-c2f2-41c4-b047-e9d2c339979c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2230346606 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.2230346606 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |