| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/16.prim_present_test.529720888 | ||
| Name |
|---|
| /workspace/coverage/default/0.prim_present_test.874224362 |
| /workspace/coverage/default/1.prim_present_test.3694223092 |
| /workspace/coverage/default/10.prim_present_test.3748746350 |
| /workspace/coverage/default/11.prim_present_test.198111261 |
| /workspace/coverage/default/12.prim_present_test.1680975321 |
| /workspace/coverage/default/13.prim_present_test.1605785267 |
| /workspace/coverage/default/14.prim_present_test.1440819947 |
| /workspace/coverage/default/15.prim_present_test.3676154412 |
| /workspace/coverage/default/17.prim_present_test.2588266373 |
| /workspace/coverage/default/18.prim_present_test.358274360 |
| /workspace/coverage/default/19.prim_present_test.3438702340 |
| /workspace/coverage/default/2.prim_present_test.2231468776 |
| /workspace/coverage/default/20.prim_present_test.2488022069 |
| /workspace/coverage/default/21.prim_present_test.1245195388 |
| /workspace/coverage/default/22.prim_present_test.1758770406 |
| /workspace/coverage/default/23.prim_present_test.1749891362 |
| /workspace/coverage/default/24.prim_present_test.3392589561 |
| /workspace/coverage/default/25.prim_present_test.782437699 |
| /workspace/coverage/default/26.prim_present_test.1178361081 |
| /workspace/coverage/default/27.prim_present_test.22477302 |
| /workspace/coverage/default/28.prim_present_test.1252035904 |
| /workspace/coverage/default/29.prim_present_test.2438804754 |
| /workspace/coverage/default/3.prim_present_test.13358138 |
| /workspace/coverage/default/30.prim_present_test.2089567293 |
| /workspace/coverage/default/31.prim_present_test.3835983122 |
| /workspace/coverage/default/32.prim_present_test.3201004774 |
| /workspace/coverage/default/33.prim_present_test.1998552014 |
| /workspace/coverage/default/34.prim_present_test.1630250052 |
| /workspace/coverage/default/35.prim_present_test.3933339190 |
| /workspace/coverage/default/36.prim_present_test.4005618797 |
| /workspace/coverage/default/37.prim_present_test.161308159 |
| /workspace/coverage/default/38.prim_present_test.3157797436 |
| /workspace/coverage/default/39.prim_present_test.1684508989 |
| /workspace/coverage/default/4.prim_present_test.1303713525 |
| /workspace/coverage/default/40.prim_present_test.4134382437 |
| /workspace/coverage/default/41.prim_present_test.3356360425 |
| /workspace/coverage/default/42.prim_present_test.4053668054 |
| /workspace/coverage/default/43.prim_present_test.3700535371 |
| /workspace/coverage/default/44.prim_present_test.3281186242 |
| /workspace/coverage/default/45.prim_present_test.731220404 |
| /workspace/coverage/default/46.prim_present_test.4245443599 |
| /workspace/coverage/default/47.prim_present_test.1902269798 |
| /workspace/coverage/default/48.prim_present_test.4172274110 |
| /workspace/coverage/default/49.prim_present_test.1536526161 |
| /workspace/coverage/default/5.prim_present_test.3576421644 |
| /workspace/coverage/default/6.prim_present_test.1345507816 |
| /workspace/coverage/default/7.prim_present_test.3601718706 |
| /workspace/coverage/default/8.prim_present_test.2498564957 |
| /workspace/coverage/default/9.prim_present_test.3427078134 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/36.prim_present_test.4005618797 | Mar 12 12:27:41 PM PDT 24 | Mar 12 12:28:21 PM PDT 24 | 5725700000 ps | ||
| T2 | /workspace/coverage/default/38.prim_present_test.3157797436 | Mar 12 12:27:46 PM PDT 24 | Mar 12 12:29:18 PM PDT 24 | 15196820000 ps | ||
| T3 | /workspace/coverage/default/43.prim_present_test.3700535371 | Mar 12 12:27:46 PM PDT 24 | Mar 12 12:28:30 PM PDT 24 | 5294800000 ps | ||
| T4 | /workspace/coverage/default/16.prim_present_test.529720888 | Mar 12 12:27:41 PM PDT 24 | Mar 12 12:29:01 PM PDT 24 | 13103080000 ps | ||
| T5 | /workspace/coverage/default/18.prim_present_test.358274360 | Mar 12 12:27:43 PM PDT 24 | Mar 12 12:29:26 PM PDT 24 | 15357400000 ps | ||
| T6 | /workspace/coverage/default/2.prim_present_test.2231468776 | Mar 12 12:27:35 PM PDT 24 | Mar 12 12:28:15 PM PDT 24 | 5573800000 ps | ||
| T7 | /workspace/coverage/default/45.prim_present_test.731220404 | Mar 12 12:27:41 PM PDT 24 | Mar 12 12:28:16 PM PDT 24 | 5411360000 ps | ||
| T8 | /workspace/coverage/default/20.prim_present_test.2488022069 | Mar 12 12:27:46 PM PDT 24 | Mar 12 12:29:19 PM PDT 24 | 12165640000 ps | ||
| T9 | /workspace/coverage/default/29.prim_present_test.2438804754 | Mar 12 12:27:46 PM PDT 24 | Mar 12 12:29:25 PM PDT 24 | 12990240000 ps | ||
| T10 | /workspace/coverage/default/8.prim_present_test.2498564957 | Mar 12 12:27:37 PM PDT 24 | Mar 12 12:28:37 PM PDT 24 | 8084800000 ps | ||
| T11 | /workspace/coverage/default/21.prim_present_test.1245195388 | Mar 12 12:27:45 PM PDT 24 | Mar 12 12:28:11 PM PDT 24 | 3834080000 ps | ||
| T12 | /workspace/coverage/default/22.prim_present_test.1758770406 | Mar 12 12:27:40 PM PDT 24 | Mar 12 12:28:52 PM PDT 24 | 10388720000 ps | ||
| T13 | /workspace/coverage/default/41.prim_present_test.3356360425 | Mar 12 12:27:40 PM PDT 24 | Mar 12 12:29:06 PM PDT 24 | 13091300000 ps | ||
| T14 | /workspace/coverage/default/28.prim_present_test.1252035904 | Mar 12 12:27:52 PM PDT 24 | Mar 12 12:28:21 PM PDT 24 | 4318920000 ps | ||
| T15 | /workspace/coverage/default/40.prim_present_test.4134382437 | Mar 12 12:27:44 PM PDT 24 | Mar 12 12:28:05 PM PDT 24 | 3385820000 ps | ||
| T16 | /workspace/coverage/default/44.prim_present_test.3281186242 | Mar 12 12:27:44 PM PDT 24 | Mar 12 12:29:03 PM PDT 24 | 10464980000 ps | ||
| T17 | /workspace/coverage/default/39.prim_present_test.1684508989 | Mar 12 12:27:40 PM PDT 24 | Mar 12 12:28:02 PM PDT 24 | 3293440000 ps | ||
| T18 | /workspace/coverage/default/3.prim_present_test.13358138 | Mar 12 12:27:28 PM PDT 24 | Mar 12 12:29:14 PM PDT 24 | 15046780000 ps | ||
| T19 | /workspace/coverage/default/25.prim_present_test.782437699 | Mar 12 12:27:43 PM PDT 24 | Mar 12 12:29:00 PM PDT 24 | 11931280000 ps | ||
| T20 | /workspace/coverage/default/12.prim_present_test.1680975321 | Mar 12 12:27:32 PM PDT 24 | Mar 12 12:28:00 PM PDT 24 | 4796940000 ps | ||
| T21 | /workspace/coverage/default/35.prim_present_test.3933339190 | Mar 12 12:27:40 PM PDT 24 | Mar 12 12:29:13 PM PDT 24 | 14145920000 ps | ||
| T22 | /workspace/coverage/default/30.prim_present_test.2089567293 | Mar 12 12:27:46 PM PDT 24 | Mar 12 12:28:42 PM PDT 24 | 6924780000 ps | ||
| T23 | /workspace/coverage/default/37.prim_present_test.161308159 | Mar 12 12:27:38 PM PDT 24 | Mar 12 12:28:08 PM PDT 24 | 5108180000 ps | ||
| T24 | /workspace/coverage/default/26.prim_present_test.1178361081 | Mar 12 12:27:40 PM PDT 24 | Mar 12 12:28:05 PM PDT 24 | 4256300000 ps | ||
| T25 | /workspace/coverage/default/48.prim_present_test.4172274110 | Mar 12 12:27:44 PM PDT 24 | Mar 12 12:28:34 PM PDT 24 | 6870220000 ps | ||
| T26 | /workspace/coverage/default/19.prim_present_test.3438702340 | Mar 12 12:27:43 PM PDT 24 | Mar 12 12:28:36 PM PDT 24 | 7588180000 ps | ||
| T27 | /workspace/coverage/default/32.prim_present_test.3201004774 | Mar 12 12:27:39 PM PDT 24 | Mar 12 12:29:07 PM PDT 24 | 15072200000 ps | ||
| T28 | /workspace/coverage/default/10.prim_present_test.3748746350 | Mar 12 12:27:36 PM PDT 24 | Mar 12 12:28:08 PM PDT 24 | 5466540000 ps | ||
| T29 | /workspace/coverage/default/46.prim_present_test.4245443599 | Mar 12 12:27:42 PM PDT 24 | Mar 12 12:28:27 PM PDT 24 | 5555820000 ps | ||
| T30 | /workspace/coverage/default/15.prim_present_test.3676154412 | Mar 12 12:27:42 PM PDT 24 | Mar 12 12:29:13 PM PDT 24 | 11602680000 ps | ||
| T31 | /workspace/coverage/default/24.prim_present_test.3392589561 | Mar 12 12:27:46 PM PDT 24 | Mar 12 12:28:57 PM PDT 24 | 9053240000 ps | ||
| T32 | /workspace/coverage/default/4.prim_present_test.1303713525 | Mar 12 12:27:33 PM PDT 24 | Mar 12 12:28:26 PM PDT 24 | 7653280000 ps | ||
| T33 | /workspace/coverage/default/49.prim_present_test.1536526161 | Mar 12 12:27:44 PM PDT 24 | Mar 12 12:28:52 PM PDT 24 | 9152440000 ps | ||
| T34 | /workspace/coverage/default/33.prim_present_test.1998552014 | Mar 12 12:27:40 PM PDT 24 | Mar 12 12:29:00 PM PDT 24 | 11877340000 ps | ||
| T35 | /workspace/coverage/default/7.prim_present_test.3601718706 | Mar 12 12:27:33 PM PDT 24 | Mar 12 12:28:10 PM PDT 24 | 4981700000 ps | ||
| T36 | /workspace/coverage/default/31.prim_present_test.3835983122 | Mar 12 12:27:39 PM PDT 24 | Mar 12 12:28:15 PM PDT 24 | 4871960000 ps | ||
| T37 | /workspace/coverage/default/6.prim_present_test.1345507816 | Mar 12 12:27:29 PM PDT 24 | Mar 12 12:29:10 PM PDT 24 | 14747320000 ps | ||
| T38 | /workspace/coverage/default/42.prim_present_test.4053668054 | Mar 12 12:27:42 PM PDT 24 | Mar 12 12:28:09 PM PDT 24 | 3124180000 ps | ||
| T39 | /workspace/coverage/default/14.prim_present_test.1440819947 | Mar 12 12:27:30 PM PDT 24 | Mar 12 12:29:14 PM PDT 24 | 13624500000 ps | ||
| T40 | /workspace/coverage/default/17.prim_present_test.2588266373 | Mar 12 12:27:40 PM PDT 24 | Mar 12 12:29:04 PM PDT 24 | 14100660000 ps | ||
| T41 | /workspace/coverage/default/23.prim_present_test.1749891362 | Mar 12 12:27:39 PM PDT 24 | Mar 12 12:28:59 PM PDT 24 | 11957940000 ps | ||
| T42 | /workspace/coverage/default/11.prim_present_test.198111261 | Mar 12 12:27:31 PM PDT 24 | Mar 12 12:27:57 PM PDT 24 | 4056040000 ps | ||
| T43 | /workspace/coverage/default/47.prim_present_test.1902269798 | Mar 12 12:27:45 PM PDT 24 | Mar 12 12:28:11 PM PDT 24 | 4198020000 ps | ||
| T44 | /workspace/coverage/default/5.prim_present_test.3576421644 | Mar 12 12:27:31 PM PDT 24 | Mar 12 12:28:15 PM PDT 24 | 7926700000 ps | ||
| T45 | /workspace/coverage/default/0.prim_present_test.874224362 | Mar 12 12:27:31 PM PDT 24 | Mar 12 12:28:39 PM PDT 24 | 9492820000 ps | ||
| T46 | /workspace/coverage/default/34.prim_present_test.1630250052 | Mar 12 12:27:39 PM PDT 24 | Mar 12 12:28:09 PM PDT 24 | 4185620000 ps | ||
| T47 | /workspace/coverage/default/9.prim_present_test.3427078134 | Mar 12 12:27:31 PM PDT 24 | Mar 12 12:28:12 PM PDT 24 | 6633380000 ps | ||
| T48 | /workspace/coverage/default/27.prim_present_test.22477302 | Mar 12 12:27:44 PM PDT 24 | Mar 12 12:28:53 PM PDT 24 | 9068740000 ps | ||
| T49 | /workspace/coverage/default/1.prim_present_test.3694223092 | Mar 12 12:27:31 PM PDT 24 | Mar 12 12:28:50 PM PDT 24 | 12372100000 ps | ||
| T50 | /workspace/coverage/default/13.prim_present_test.1605785267 | Mar 12 12:27:31 PM PDT 24 | Mar 12 12:27:59 PM PDT 24 | 3826020000 ps |
| Test location | /workspace/coverage/default/16.prim_present_test.529720888 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 13103080000 ps |
| CPU time | 43.31 seconds |
| Started | Mar 12 12:27:41 PM PDT 24 |
| Finished | Mar 12 12:29:01 PM PDT 24 |
| Peak memory | 144588 kb |
| Host | smart-3ac3d933-e391-43f5-b0c0-ebfb2770915f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=529720888 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.529720888 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/0.prim_present_test.874224362 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 9492820000 ps |
| CPU time | 34.96 seconds |
| Started | Mar 12 12:27:31 PM PDT 24 |
| Finished | Mar 12 12:28:39 PM PDT 24 |
| Peak memory | 144868 kb |
| Host | smart-cf1ab57a-3355-449a-a085-22a1d2b53faf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=874224362 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.874224362 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/1.prim_present_test.3694223092 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 12372100000 ps |
| CPU time | 42.71 seconds |
| Started | Mar 12 12:27:31 PM PDT 24 |
| Finished | Mar 12 12:28:50 PM PDT 24 |
| Peak memory | 144596 kb |
| Host | smart-5c744b4b-fd4d-46e3-85a0-e2704119eb6b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3694223092 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.3694223092 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/10.prim_present_test.3748746350 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 5466540000 ps |
| CPU time | 17.14 seconds |
| Started | Mar 12 12:27:36 PM PDT 24 |
| Finished | Mar 12 12:28:08 PM PDT 24 |
| Peak memory | 144616 kb |
| Host | smart-190d0a8d-7771-4a44-af39-b0f0830595df |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3748746350 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.3748746350 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/11.prim_present_test.198111261 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 4056040000 ps |
| CPU time | 14.11 seconds |
| Started | Mar 12 12:27:31 PM PDT 24 |
| Finished | Mar 12 12:27:57 PM PDT 24 |
| Peak memory | 144408 kb |
| Host | smart-a137df60-999f-4d46-9cae-a851aea2dc03 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=198111261 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.198111261 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.1680975321 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 4796940000 ps |
| CPU time | 15.31 seconds |
| Started | Mar 12 12:27:32 PM PDT 24 |
| Finished | Mar 12 12:28:00 PM PDT 24 |
| Peak memory | 144684 kb |
| Host | smart-f033b02d-ccca-4c10-8776-eba1a317dcd0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1680975321 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.1680975321 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.1605785267 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 3826020000 ps |
| CPU time | 14.63 seconds |
| Started | Mar 12 12:27:31 PM PDT 24 |
| Finished | Mar 12 12:27:59 PM PDT 24 |
| Peak memory | 144480 kb |
| Host | smart-392eda19-2339-44dc-99cd-b0cbaf41b47b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1605785267 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.1605785267 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.1440819947 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 13624500000 ps |
| CPU time | 54.11 seconds |
| Started | Mar 12 12:27:30 PM PDT 24 |
| Finished | Mar 12 12:29:14 PM PDT 24 |
| Peak memory | 144488 kb |
| Host | smart-db57da97-054f-4847-b014-e4476a59573a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1440819947 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.1440819947 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.3676154412 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 11602680000 ps |
| CPU time | 47.19 seconds |
| Started | Mar 12 12:27:42 PM PDT 24 |
| Finished | Mar 12 12:29:13 PM PDT 24 |
| Peak memory | 144652 kb |
| Host | smart-83a84d05-add4-4f9a-92d3-64ab3fe7298d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3676154412 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.3676154412 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.2588266373 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 14100660000 ps |
| CPU time | 46.56 seconds |
| Started | Mar 12 12:27:40 PM PDT 24 |
| Finished | Mar 12 12:29:04 PM PDT 24 |
| Peak memory | 144652 kb |
| Host | smart-5571374e-c14d-4a9d-a80c-44db348f4c40 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2588266373 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.2588266373 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.358274360 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 15357400000 ps |
| CPU time | 55.26 seconds |
| Started | Mar 12 12:27:43 PM PDT 24 |
| Finished | Mar 12 12:29:26 PM PDT 24 |
| Peak memory | 144632 kb |
| Host | smart-902dfb12-299b-4bf5-a629-c1f72a141d7f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=358274360 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.358274360 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.3438702340 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 7588180000 ps |
| CPU time | 28.4 seconds |
| Started | Mar 12 12:27:43 PM PDT 24 |
| Finished | Mar 12 12:28:36 PM PDT 24 |
| Peak memory | 144656 kb |
| Host | smart-0a56001b-df37-4fe0-9f53-23fe7a922695 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3438702340 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.3438702340 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.2231468776 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 5573800000 ps |
| CPU time | 21.07 seconds |
| Started | Mar 12 12:27:35 PM PDT 24 |
| Finished | Mar 12 12:28:15 PM PDT 24 |
| Peak memory | 144628 kb |
| Host | smart-ae28b537-9a4d-4b90-a736-c9f58ea0c1d2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2231468776 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.2231468776 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.2488022069 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 12165640000 ps |
| CPU time | 47.74 seconds |
| Started | Mar 12 12:27:46 PM PDT 24 |
| Finished | Mar 12 12:29:19 PM PDT 24 |
| Peak memory | 144552 kb |
| Host | smart-6a83a6b4-b8ea-4139-9e43-55e3b72dd40f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2488022069 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.2488022069 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.1245195388 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 3834080000 ps |
| CPU time | 14.02 seconds |
| Started | Mar 12 12:27:45 PM PDT 24 |
| Finished | Mar 12 12:28:11 PM PDT 24 |
| Peak memory | 144460 kb |
| Host | smart-1ef05ea4-e83f-46ca-8a8d-45ef276e06e6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1245195388 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.1245195388 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.1758770406 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 10388720000 ps |
| CPU time | 38.07 seconds |
| Started | Mar 12 12:27:40 PM PDT 24 |
| Finished | Mar 12 12:28:52 PM PDT 24 |
| Peak memory | 144620 kb |
| Host | smart-c4eb9be9-5762-40b9-a861-febd3eeab55c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1758770406 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.1758770406 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.1749891362 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 11957940000 ps |
| CPU time | 42.64 seconds |
| Started | Mar 12 12:27:39 PM PDT 24 |
| Finished | Mar 12 12:28:59 PM PDT 24 |
| Peak memory | 144648 kb |
| Host | smart-b7d1108d-e20d-460f-b2e9-56899defb40a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1749891362 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.1749891362 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.3392589561 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 9053240000 ps |
| CPU time | 36.2 seconds |
| Started | Mar 12 12:27:46 PM PDT 24 |
| Finished | Mar 12 12:28:57 PM PDT 24 |
| Peak memory | 144568 kb |
| Host | smart-7fc49dbd-f8d0-425b-abf4-f596b1ebeef6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3392589561 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.3392589561 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.782437699 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 11931280000 ps |
| CPU time | 41.23 seconds |
| Started | Mar 12 12:27:43 PM PDT 24 |
| Finished | Mar 12 12:29:00 PM PDT 24 |
| Peak memory | 144592 kb |
| Host | smart-23d333c1-12a6-4bcb-92f5-677fcac12839 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=782437699 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.782437699 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.1178361081 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 4256300000 ps |
| CPU time | 13.88 seconds |
| Started | Mar 12 12:27:40 PM PDT 24 |
| Finished | Mar 12 12:28:05 PM PDT 24 |
| Peak memory | 144544 kb |
| Host | smart-eb267ef6-1f3c-48d1-a07e-c2f86c007a34 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1178361081 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.1178361081 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.22477302 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 9068740000 ps |
| CPU time | 35.84 seconds |
| Started | Mar 12 12:27:44 PM PDT 24 |
| Finished | Mar 12 12:28:53 PM PDT 24 |
| Peak memory | 144696 kb |
| Host | smart-9a214676-59f5-48d7-81ff-ecd69b2c628a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=22477302 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.22477302 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.1252035904 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 4318920000 ps |
| CPU time | 15.92 seconds |
| Started | Mar 12 12:27:52 PM PDT 24 |
| Finished | Mar 12 12:28:21 PM PDT 24 |
| Peak memory | 144844 kb |
| Host | smart-7828a790-b23b-43f7-baf9-4697089c1b95 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1252035904 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.1252035904 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.2438804754 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 12990240000 ps |
| CPU time | 51.35 seconds |
| Started | Mar 12 12:27:46 PM PDT 24 |
| Finished | Mar 12 12:29:25 PM PDT 24 |
| Peak memory | 144572 kb |
| Host | smart-40b422c2-edb2-4496-b011-314daeec40f0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2438804754 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.2438804754 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.13358138 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 15046780000 ps |
| CPU time | 55.12 seconds |
| Started | Mar 12 12:27:28 PM PDT 24 |
| Finished | Mar 12 12:29:14 PM PDT 24 |
| Peak memory | 144552 kb |
| Host | smart-eb79267f-32c5-444e-90fc-d491c5ceb3b2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=13358138 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.13358138 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.2089567293 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 6924780000 ps |
| CPU time | 28.48 seconds |
| Started | Mar 12 12:27:46 PM PDT 24 |
| Finished | Mar 12 12:28:42 PM PDT 24 |
| Peak memory | 144652 kb |
| Host | smart-c7697ebc-0b3d-4af8-bd98-50f023a839ff |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2089567293 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.2089567293 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.3835983122 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 4871960000 ps |
| CPU time | 18.78 seconds |
| Started | Mar 12 12:27:39 PM PDT 24 |
| Finished | Mar 12 12:28:15 PM PDT 24 |
| Peak memory | 144564 kb |
| Host | smart-240e7887-2f3a-43d8-b33d-0858b2da68ac |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3835983122 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.3835983122 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.3201004774 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 15072200000 ps |
| CPU time | 47.37 seconds |
| Started | Mar 12 12:27:39 PM PDT 24 |
| Finished | Mar 12 12:29:07 PM PDT 24 |
| Peak memory | 144624 kb |
| Host | smart-4b6ca20d-7e53-4d70-8a5f-2e21c19879d8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3201004774 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.3201004774 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.1998552014 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 11877340000 ps |
| CPU time | 43.06 seconds |
| Started | Mar 12 12:27:40 PM PDT 24 |
| Finished | Mar 12 12:29:00 PM PDT 24 |
| Peak memory | 144584 kb |
| Host | smart-0e746832-684c-471e-9ff7-322fee689400 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1998552014 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.1998552014 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.1630250052 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 4185620000 ps |
| CPU time | 16.14 seconds |
| Started | Mar 12 12:27:39 PM PDT 24 |
| Finished | Mar 12 12:28:09 PM PDT 24 |
| Peak memory | 144496 kb |
| Host | smart-1deefb30-28aa-4dea-848c-2adf81afd83e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1630250052 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.1630250052 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.3933339190 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 14145920000 ps |
| CPU time | 50.33 seconds |
| Started | Mar 12 12:27:40 PM PDT 24 |
| Finished | Mar 12 12:29:13 PM PDT 24 |
| Peak memory | 144636 kb |
| Host | smart-39821778-5f94-41f9-a204-cca4bf5bafcc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3933339190 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.3933339190 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.4005618797 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 5725700000 ps |
| CPU time | 20.89 seconds |
| Started | Mar 12 12:27:41 PM PDT 24 |
| Finished | Mar 12 12:28:21 PM PDT 24 |
| Peak memory | 144712 kb |
| Host | smart-c2beb32b-f1db-48c8-95ba-45ad414255ee |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4005618797 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.4005618797 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.161308159 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 5108180000 ps |
| CPU time | 16.28 seconds |
| Started | Mar 12 12:27:38 PM PDT 24 |
| Finished | Mar 12 12:28:08 PM PDT 24 |
| Peak memory | 144576 kb |
| Host | smart-d61c98fe-ac14-40ff-bd28-e69a4a3a0b44 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=161308159 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.161308159 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.3157797436 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 15196820000 ps |
| CPU time | 50.68 seconds |
| Started | Mar 12 12:27:46 PM PDT 24 |
| Finished | Mar 12 12:29:18 PM PDT 24 |
| Peak memory | 144844 kb |
| Host | smart-a36d9c16-63ef-44f9-a469-27ddcb808cdd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3157797436 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.3157797436 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.1684508989 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 3293440000 ps |
| CPU time | 12.35 seconds |
| Started | Mar 12 12:27:40 PM PDT 24 |
| Finished | Mar 12 12:28:02 PM PDT 24 |
| Peak memory | 144404 kb |
| Host | smart-f84bcc0f-b881-47be-8cee-2748910e8bc0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1684508989 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.1684508989 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.1303713525 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 7653280000 ps |
| CPU time | 28.07 seconds |
| Started | Mar 12 12:27:33 PM PDT 24 |
| Finished | Mar 12 12:28:26 PM PDT 24 |
| Peak memory | 144640 kb |
| Host | smart-5df3d566-be7a-43e4-b92e-cc0932e74e3d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1303713525 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.1303713525 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.4134382437 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 3385820000 ps |
| CPU time | 11.15 seconds |
| Started | Mar 12 12:27:44 PM PDT 24 |
| Finished | Mar 12 12:28:05 PM PDT 24 |
| Peak memory | 144420 kb |
| Host | smart-b3ca23e2-bbc8-4453-aa4c-7e5b890d2e71 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4134382437 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.4134382437 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.3356360425 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 13091300000 ps |
| CPU time | 46.26 seconds |
| Started | Mar 12 12:27:40 PM PDT 24 |
| Finished | Mar 12 12:29:06 PM PDT 24 |
| Peak memory | 144640 kb |
| Host | smart-ceee4fde-e5aa-4987-b133-9c91b4e7cac8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3356360425 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.3356360425 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.4053668054 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 3124180000 ps |
| CPU time | 13.44 seconds |
| Started | Mar 12 12:27:42 PM PDT 24 |
| Finished | Mar 12 12:28:09 PM PDT 24 |
| Peak memory | 144348 kb |
| Host | smart-91a67906-3f82-4dd9-a50e-2e38c83b6edd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4053668054 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.4053668054 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.3700535371 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 5294800000 ps |
| CPU time | 22.36 seconds |
| Started | Mar 12 12:27:46 PM PDT 24 |
| Finished | Mar 12 12:28:30 PM PDT 24 |
| Peak memory | 144572 kb |
| Host | smart-be38826f-18e2-4deb-82e6-fccb34843ff5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3700535371 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.3700535371 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.3281186242 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 10464980000 ps |
| CPU time | 41.42 seconds |
| Started | Mar 12 12:27:44 PM PDT 24 |
| Finished | Mar 12 12:29:03 PM PDT 24 |
| Peak memory | 144700 kb |
| Host | smart-8bb4a2a4-d117-4f8c-a6d5-63da54bfeaf1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3281186242 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.3281186242 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.731220404 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 5411360000 ps |
| CPU time | 18.47 seconds |
| Started | Mar 12 12:27:41 PM PDT 24 |
| Finished | Mar 12 12:28:16 PM PDT 24 |
| Peak memory | 144668 kb |
| Host | smart-209ee9d3-fd3d-422d-85d5-bc9ebcc3db8f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=731220404 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.731220404 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.4245443599 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 5555820000 ps |
| CPU time | 22.99 seconds |
| Started | Mar 12 12:27:42 PM PDT 24 |
| Finished | Mar 12 12:28:27 PM PDT 24 |
| Peak memory | 144552 kb |
| Host | smart-f923054e-d916-461c-a0f5-8c50cae23cda |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4245443599 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.4245443599 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.1902269798 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 4198020000 ps |
| CPU time | 14.38 seconds |
| Started | Mar 12 12:27:45 PM PDT 24 |
| Finished | Mar 12 12:28:11 PM PDT 24 |
| Peak memory | 144420 kb |
| Host | smart-ffce12e3-b91a-488b-b491-20076f560c33 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1902269798 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.1902269798 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.4172274110 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 6870220000 ps |
| CPU time | 26.6 seconds |
| Started | Mar 12 12:27:44 PM PDT 24 |
| Finished | Mar 12 12:28:34 PM PDT 24 |
| Peak memory | 144660 kb |
| Host | smart-a0f9fcbd-9a53-4a2c-b375-f0fdcceeb38c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4172274110 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.4172274110 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.1536526161 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 9152440000 ps |
| CPU time | 35.11 seconds |
| Started | Mar 12 12:27:44 PM PDT 24 |
| Finished | Mar 12 12:28:52 PM PDT 24 |
| Peak memory | 144660 kb |
| Host | smart-1ceabf28-c5cf-4825-bee5-fccfe5e48f97 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1536526161 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.1536526161 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.3576421644 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 7926700000 ps |
| CPU time | 23.87 seconds |
| Started | Mar 12 12:27:31 PM PDT 24 |
| Finished | Mar 12 12:28:15 PM PDT 24 |
| Peak memory | 144600 kb |
| Host | smart-87019e87-28e6-4846-ade8-ca5764de536e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3576421644 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.3576421644 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.1345507816 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 14747320000 ps |
| CPU time | 54.08 seconds |
| Started | Mar 12 12:27:29 PM PDT 24 |
| Finished | Mar 12 12:29:10 PM PDT 24 |
| Peak memory | 144644 kb |
| Host | smart-d4c52329-751f-4ad0-87ca-41e0b7df8e6f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1345507816 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.1345507816 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.3601718706 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 4981700000 ps |
| CPU time | 19.35 seconds |
| Started | Mar 12 12:27:33 PM PDT 24 |
| Finished | Mar 12 12:28:10 PM PDT 24 |
| Peak memory | 144636 kb |
| Host | smart-d8e7898f-cc7c-4d83-a709-ce77ee752c2c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3601718706 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.3601718706 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.2498564957 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 8084800000 ps |
| CPU time | 31.26 seconds |
| Started | Mar 12 12:27:37 PM PDT 24 |
| Finished | Mar 12 12:28:37 PM PDT 24 |
| Peak memory | 144640 kb |
| Host | smart-7c3af15b-b9a0-43c1-9cc1-9129bf96c2a2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2498564957 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.2498564957 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.3427078134 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 6633380000 ps |
| CPU time | 22.34 seconds |
| Started | Mar 12 12:27:31 PM PDT 24 |
| Finished | Mar 12 12:28:12 PM PDT 24 |
| Peak memory | 144560 kb |
| Host | smart-56332896-19d7-4826-8abb-fd173d7281e3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3427078134 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.3427078134 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |