| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/13.prim_present_test.450316622 | ||
| Name |
|---|
| /workspace/coverage/default/0.prim_present_test.2891017006 |
| /workspace/coverage/default/1.prim_present_test.4115168848 |
| /workspace/coverage/default/10.prim_present_test.724628028 |
| /workspace/coverage/default/11.prim_present_test.1274895615 |
| /workspace/coverage/default/12.prim_present_test.3974106730 |
| /workspace/coverage/default/14.prim_present_test.146010738 |
| /workspace/coverage/default/15.prim_present_test.2789797243 |
| /workspace/coverage/default/16.prim_present_test.3100319170 |
| /workspace/coverage/default/17.prim_present_test.4241992955 |
| /workspace/coverage/default/18.prim_present_test.616524395 |
| /workspace/coverage/default/19.prim_present_test.3369265098 |
| /workspace/coverage/default/2.prim_present_test.583938752 |
| /workspace/coverage/default/20.prim_present_test.414438871 |
| /workspace/coverage/default/21.prim_present_test.2954621634 |
| /workspace/coverage/default/22.prim_present_test.2692481662 |
| /workspace/coverage/default/23.prim_present_test.481250899 |
| /workspace/coverage/default/24.prim_present_test.2624611766 |
| /workspace/coverage/default/25.prim_present_test.977237859 |
| /workspace/coverage/default/26.prim_present_test.1012913499 |
| /workspace/coverage/default/27.prim_present_test.1983782139 |
| /workspace/coverage/default/28.prim_present_test.3691199115 |
| /workspace/coverage/default/29.prim_present_test.3208001075 |
| /workspace/coverage/default/3.prim_present_test.200050633 |
| /workspace/coverage/default/30.prim_present_test.3635351341 |
| /workspace/coverage/default/31.prim_present_test.1448422334 |
| /workspace/coverage/default/32.prim_present_test.2926874676 |
| /workspace/coverage/default/33.prim_present_test.2143909690 |
| /workspace/coverage/default/34.prim_present_test.3502623296 |
| /workspace/coverage/default/35.prim_present_test.826356615 |
| /workspace/coverage/default/36.prim_present_test.2831320592 |
| /workspace/coverage/default/37.prim_present_test.4251249331 |
| /workspace/coverage/default/38.prim_present_test.1825279745 |
| /workspace/coverage/default/39.prim_present_test.4033792836 |
| /workspace/coverage/default/4.prim_present_test.4195391068 |
| /workspace/coverage/default/40.prim_present_test.750279648 |
| /workspace/coverage/default/41.prim_present_test.2346436961 |
| /workspace/coverage/default/42.prim_present_test.825986284 |
| /workspace/coverage/default/43.prim_present_test.1672380472 |
| /workspace/coverage/default/44.prim_present_test.2300829309 |
| /workspace/coverage/default/45.prim_present_test.729894080 |
| /workspace/coverage/default/46.prim_present_test.123787720 |
| /workspace/coverage/default/47.prim_present_test.3924984496 |
| /workspace/coverage/default/48.prim_present_test.1778953101 |
| /workspace/coverage/default/49.prim_present_test.3068268246 |
| /workspace/coverage/default/5.prim_present_test.3487453091 |
| /workspace/coverage/default/6.prim_present_test.1466865447 |
| /workspace/coverage/default/7.prim_present_test.348761097 |
| /workspace/coverage/default/8.prim_present_test.1712658897 |
| /workspace/coverage/default/9.prim_present_test.3848968131 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/38.prim_present_test.1825279745 | Mar 14 12:18:57 PM PDT 24 | Mar 14 12:19:25 PM PDT 24 | 4741140000 ps | ||
| T2 | /workspace/coverage/default/20.prim_present_test.414438871 | Mar 14 12:19:09 PM PDT 24 | Mar 14 12:20:26 PM PDT 24 | 12499820000 ps | ||
| T3 | /workspace/coverage/default/14.prim_present_test.146010738 | Mar 14 12:24:06 PM PDT 24 | Mar 14 12:25:18 PM PDT 24 | 12899100000 ps | ||
| T4 | /workspace/coverage/default/32.prim_present_test.2926874676 | Mar 14 12:24:08 PM PDT 24 | Mar 14 12:25:46 PM PDT 24 | 15155280000 ps | ||
| T5 | /workspace/coverage/default/31.prim_present_test.1448422334 | Mar 14 12:18:38 PM PDT 24 | Mar 14 12:20:14 PM PDT 24 | 13493680000 ps | ||
| T6 | /workspace/coverage/default/36.prim_present_test.2831320592 | Mar 14 12:18:37 PM PDT 24 | Mar 14 12:19:54 PM PDT 24 | 10455680000 ps | ||
| T7 | /workspace/coverage/default/34.prim_present_test.3502623296 | Mar 14 12:19:01 PM PDT 24 | Mar 14 12:20:05 PM PDT 24 | 10640440000 ps | ||
| T8 | /workspace/coverage/default/13.prim_present_test.450316622 | Mar 14 12:23:29 PM PDT 24 | Mar 14 12:23:53 PM PDT 24 | 3696440000 ps | ||
| T9 | /workspace/coverage/default/30.prim_present_test.3635351341 | Mar 14 12:24:24 PM PDT 24 | Mar 14 12:25:57 PM PDT 24 | 13599080000 ps | ||
| T10 | /workspace/coverage/default/39.prim_present_test.4033792836 | Mar 14 12:18:57 PM PDT 24 | Mar 14 12:19:17 PM PDT 24 | 3206020000 ps | ||
| T11 | /workspace/coverage/default/19.prim_present_test.3369265098 | Mar 14 12:20:28 PM PDT 24 | Mar 14 12:21:06 PM PDT 24 | 4809340000 ps | ||
| T12 | /workspace/coverage/default/6.prim_present_test.1466865447 | Mar 14 12:18:56 PM PDT 24 | Mar 14 12:20:16 PM PDT 24 | 12130920000 ps | ||
| T13 | /workspace/coverage/default/4.prim_present_test.4195391068 | Mar 14 12:21:02 PM PDT 24 | Mar 14 12:22:19 PM PDT 24 | 11383200000 ps | ||
| T14 | /workspace/coverage/default/9.prim_present_test.3848968131 | Mar 14 12:24:03 PM PDT 24 | Mar 14 12:24:36 PM PDT 24 | 5927820000 ps | ||
| T15 | /workspace/coverage/default/26.prim_present_test.1012913499 | Mar 14 12:24:16 PM PDT 24 | Mar 14 12:25:14 PM PDT 24 | 10204580000 ps | ||
| T16 | /workspace/coverage/default/43.prim_present_test.1672380472 | Mar 14 12:19:24 PM PDT 24 | Mar 14 12:20:23 PM PDT 24 | 8362560000 ps | ||
| T17 | /workspace/coverage/default/46.prim_present_test.123787720 | Mar 14 12:19:37 PM PDT 24 | Mar 14 12:21:17 PM PDT 24 | 15216660000 ps | ||
| T18 | /workspace/coverage/default/41.prim_present_test.2346436961 | Mar 14 12:24:02 PM PDT 24 | Mar 14 12:24:32 PM PDT 24 | 5868920000 ps | ||
| T19 | /workspace/coverage/default/7.prim_present_test.348761097 | Mar 14 12:23:25 PM PDT 24 | Mar 14 12:24:19 PM PDT 24 | 8869100000 ps | ||
| T20 | /workspace/coverage/default/16.prim_present_test.3100319170 | Mar 14 12:21:28 PM PDT 24 | Mar 14 12:21:50 PM PDT 24 | 3182460000 ps | ||
| T21 | /workspace/coverage/default/28.prim_present_test.3691199115 | Mar 14 12:24:24 PM PDT 24 | Mar 14 12:25:33 PM PDT 24 | 9879080000 ps | ||
| T22 | /workspace/coverage/default/37.prim_present_test.4251249331 | Mar 14 12:20:54 PM PDT 24 | Mar 14 12:22:11 PM PDT 24 | 10602620000 ps | ||
| T23 | /workspace/coverage/default/44.prim_present_test.2300829309 | Mar 14 12:24:08 PM PDT 24 | Mar 14 12:24:30 PM PDT 24 | 3267400000 ps | ||
| T24 | /workspace/coverage/default/42.prim_present_test.825986284 | Mar 14 12:19:44 PM PDT 24 | Mar 14 12:20:10 PM PDT 24 | 3555080000 ps | ||
| T25 | /workspace/coverage/default/48.prim_present_test.1778953101 | Mar 14 12:22:08 PM PDT 24 | Mar 14 12:22:54 PM PDT 24 | 6186360000 ps | ||
| T26 | /workspace/coverage/default/25.prim_present_test.977237859 | Mar 14 12:19:59 PM PDT 24 | Mar 14 12:21:36 PM PDT 24 | 13047280000 ps | ||
| T27 | /workspace/coverage/default/5.prim_present_test.3487453091 | Mar 14 12:23:39 PM PDT 24 | Mar 14 12:24:50 PM PDT 24 | 10498460000 ps | ||
| T28 | /workspace/coverage/default/35.prim_present_test.826356615 | Mar 14 12:18:38 PM PDT 24 | Mar 14 12:20:18 PM PDT 24 | 14914720000 ps | ||
| T29 | /workspace/coverage/default/45.prim_present_test.729894080 | Mar 14 12:19:34 PM PDT 24 | Mar 14 12:20:44 PM PDT 24 | 11060800000 ps | ||
| T30 | /workspace/coverage/default/40.prim_present_test.750279648 | Mar 14 12:22:17 PM PDT 24 | Mar 14 12:23:00 PM PDT 24 | 6431880000 ps | ||
| T31 | /workspace/coverage/default/1.prim_present_test.4115168848 | Mar 14 12:19:09 PM PDT 24 | Mar 14 12:20:37 PM PDT 24 | 14038660000 ps | ||
| T32 | /workspace/coverage/default/24.prim_present_test.2624611766 | Mar 14 12:24:18 PM PDT 24 | Mar 14 12:24:56 PM PDT 24 | 6232240000 ps | ||
| T33 | /workspace/coverage/default/23.prim_present_test.481250899 | Mar 14 12:19:59 PM PDT 24 | Mar 14 12:20:50 PM PDT 24 | 6630280000 ps | ||
| T34 | /workspace/coverage/default/11.prim_present_test.1274895615 | Mar 14 12:21:13 PM PDT 24 | Mar 14 12:22:49 PM PDT 24 | 15123040000 ps | ||
| T35 | /workspace/coverage/default/10.prim_present_test.724628028 | Mar 14 12:20:28 PM PDT 24 | Mar 14 12:21:00 PM PDT 24 | 4087040000 ps | ||
| T36 | /workspace/coverage/default/21.prim_present_test.2954621634 | Mar 14 12:20:29 PM PDT 24 | Mar 14 12:22:13 PM PDT 24 | 14170720000 ps | ||
| T37 | /workspace/coverage/default/2.prim_present_test.583938752 | Mar 14 12:18:43 PM PDT 24 | Mar 14 12:20:01 PM PDT 24 | 12725500000 ps | ||
| T38 | /workspace/coverage/default/0.prim_present_test.2891017006 | Mar 14 12:20:04 PM PDT 24 | Mar 14 12:21:36 PM PDT 24 | 14215980000 ps | ||
| T39 | /workspace/coverage/default/15.prim_present_test.2789797243 | Mar 14 12:20:12 PM PDT 24 | Mar 14 12:20:58 PM PDT 24 | 6291140000 ps | ||
| T40 | /workspace/coverage/default/18.prim_present_test.616524395 | Mar 14 12:24:24 PM PDT 24 | Mar 14 12:25:35 PM PDT 24 | 10047720000 ps | ||
| T41 | /workspace/coverage/default/27.prim_present_test.1983782139 | Mar 14 12:20:53 PM PDT 24 | Mar 14 12:21:37 PM PDT 24 | 5740580000 ps | ||
| T42 | /workspace/coverage/default/8.prim_present_test.1712658897 | Mar 14 12:23:26 PM PDT 24 | Mar 14 12:24:31 PM PDT 24 | 10863640000 ps | ||
| T43 | /workspace/coverage/default/12.prim_present_test.3974106730 | Mar 14 12:22:05 PM PDT 24 | Mar 14 12:23:27 PM PDT 24 | 12957380000 ps | ||
| T44 | /workspace/coverage/default/33.prim_present_test.2143909690 | Mar 14 12:20:54 PM PDT 24 | Mar 14 12:21:29 PM PDT 24 | 4553280000 ps | ||
| T45 | /workspace/coverage/default/47.prim_present_test.3924984496 | Mar 14 12:19:49 PM PDT 24 | Mar 14 12:20:20 PM PDT 24 | 5036880000 ps | ||
| T46 | /workspace/coverage/default/17.prim_present_test.4241992955 | Mar 14 12:24:18 PM PDT 24 | Mar 14 12:25:20 PM PDT 24 | 10469940000 ps | ||
| T47 | /workspace/coverage/default/3.prim_present_test.200050633 | Mar 14 12:18:37 PM PDT 24 | Mar 14 12:19:13 PM PDT 24 | 5526060000 ps | ||
| T48 | /workspace/coverage/default/22.prim_present_test.2692481662 | Mar 14 12:24:24 PM PDT 24 | Mar 14 12:25:57 PM PDT 24 | 13579860000 ps | ||
| T49 | /workspace/coverage/default/29.prim_present_test.3208001075 | Mar 14 12:24:24 PM PDT 24 | Mar 14 12:24:49 PM PDT 24 | 3266160000 ps | ||
| T50 | /workspace/coverage/default/49.prim_present_test.3068268246 | Mar 14 12:22:08 PM PDT 24 | Mar 14 12:23:34 PM PDT 24 | 12001340000 ps |
| Test location | /workspace/coverage/default/13.prim_present_test.450316622 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 3696440000 ps |
| CPU time | 12.9 seconds |
| Started | Mar 14 12:23:29 PM PDT 24 |
| Finished | Mar 14 12:23:53 PM PDT 24 |
| Peak memory | 144984 kb |
| Host | smart-6b27e320-0c81-42bf-8082-917506346c23 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=450316622 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.450316622 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/0.prim_present_test.2891017006 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 14215980000 ps |
| CPU time | 49.36 seconds |
| Started | Mar 14 12:20:04 PM PDT 24 |
| Finished | Mar 14 12:21:36 PM PDT 24 |
| Peak memory | 145068 kb |
| Host | smart-74de8a63-c550-4932-b87e-a848cf425434 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2891017006 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.2891017006 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/1.prim_present_test.4115168848 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 14038660000 ps |
| CPU time | 47.43 seconds |
| Started | Mar 14 12:19:09 PM PDT 24 |
| Finished | Mar 14 12:20:37 PM PDT 24 |
| Peak memory | 144984 kb |
| Host | smart-668fef85-b15f-4b65-9bbc-ebd4cbffa2b2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4115168848 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.4115168848 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/10.prim_present_test.724628028 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 4087040000 ps |
| CPU time | 16.84 seconds |
| Started | Mar 14 12:20:28 PM PDT 24 |
| Finished | Mar 14 12:21:00 PM PDT 24 |
| Peak memory | 144980 kb |
| Host | smart-167e0b95-65f4-4c7a-ac13-e548a01fa40c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=724628028 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.724628028 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/11.prim_present_test.1274895615 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 15123040000 ps |
| CPU time | 51.65 seconds |
| Started | Mar 14 12:21:13 PM PDT 24 |
| Finished | Mar 14 12:22:49 PM PDT 24 |
| Peak memory | 145080 kb |
| Host | smart-e20db837-5e47-4af0-b3c8-d97ce7949cec |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1274895615 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.1274895615 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.3974106730 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 12957380000 ps |
| CPU time | 43.79 seconds |
| Started | Mar 14 12:22:05 PM PDT 24 |
| Finished | Mar 14 12:23:27 PM PDT 24 |
| Peak memory | 145060 kb |
| Host | smart-66d2814d-afa0-4202-8fa1-d6f20f602424 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3974106730 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.3974106730 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.146010738 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 12899100000 ps |
| CPU time | 38.67 seconds |
| Started | Mar 14 12:24:06 PM PDT 24 |
| Finished | Mar 14 12:25:18 PM PDT 24 |
| Peak memory | 144944 kb |
| Host | smart-7d2221fd-0bc5-4dc2-abd6-4e53c3b6c864 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=146010738 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.146010738 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.2789797243 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 6291140000 ps |
| CPU time | 24.29 seconds |
| Started | Mar 14 12:20:12 PM PDT 24 |
| Finished | Mar 14 12:20:58 PM PDT 24 |
| Peak memory | 145128 kb |
| Host | smart-4a541fdb-09ad-4ed8-b541-5cd5f8d9b595 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2789797243 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.2789797243 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.3100319170 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 3182460000 ps |
| CPU time | 11.81 seconds |
| Started | Mar 14 12:21:28 PM PDT 24 |
| Finished | Mar 14 12:21:50 PM PDT 24 |
| Peak memory | 144932 kb |
| Host | smart-332f3414-8257-4d66-a5b2-3fbf1e3004f1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3100319170 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.3100319170 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.4241992955 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 10469940000 ps |
| CPU time | 33.58 seconds |
| Started | Mar 14 12:24:18 PM PDT 24 |
| Finished | Mar 14 12:25:20 PM PDT 24 |
| Peak memory | 145036 kb |
| Host | smart-e223d345-08d6-4002-b21a-81b3b4123c12 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4241992955 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.4241992955 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.616524395 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 10047720000 ps |
| CPU time | 36.86 seconds |
| Started | Mar 14 12:24:24 PM PDT 24 |
| Finished | Mar 14 12:25:35 PM PDT 24 |
| Peak memory | 143912 kb |
| Host | smart-b2a637a3-d4cd-451d-8383-bdf2e83432f7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=616524395 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.616524395 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.3369265098 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 4809340000 ps |
| CPU time | 19.7 seconds |
| Started | Mar 14 12:20:28 PM PDT 24 |
| Finished | Mar 14 12:21:06 PM PDT 24 |
| Peak memory | 145128 kb |
| Host | smart-8ac544f1-8681-4c09-a2f1-2698d423f46f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3369265098 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.3369265098 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.583938752 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 12725500000 ps |
| CPU time | 42.49 seconds |
| Started | Mar 14 12:18:43 PM PDT 24 |
| Finished | Mar 14 12:20:01 PM PDT 24 |
| Peak memory | 145156 kb |
| Host | smart-c515b695-cb3d-481b-8966-c80c9b4882d1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=583938752 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.583938752 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.414438871 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 12499820000 ps |
| CPU time | 41.72 seconds |
| Started | Mar 14 12:19:09 PM PDT 24 |
| Finished | Mar 14 12:20:26 PM PDT 24 |
| Peak memory | 145036 kb |
| Host | smart-f13cd031-bab4-4258-ba7b-ba8e188764ce |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=414438871 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.414438871 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.2954621634 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 14170720000 ps |
| CPU time | 54.86 seconds |
| Started | Mar 14 12:20:29 PM PDT 24 |
| Finished | Mar 14 12:22:13 PM PDT 24 |
| Peak memory | 145040 kb |
| Host | smart-ad489360-70ff-40c8-9d72-67e05b019b34 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2954621634 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.2954621634 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.2692481662 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 13579860000 ps |
| CPU time | 48.67 seconds |
| Started | Mar 14 12:24:24 PM PDT 24 |
| Finished | Mar 14 12:25:57 PM PDT 24 |
| Peak memory | 144964 kb |
| Host | smart-72237e55-6ddd-4668-a21b-7ffd10656e60 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2692481662 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.2692481662 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.481250899 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 6630280000 ps |
| CPU time | 27 seconds |
| Started | Mar 14 12:19:59 PM PDT 24 |
| Finished | Mar 14 12:20:50 PM PDT 24 |
| Peak memory | 145040 kb |
| Host | smart-55879f97-f36a-4213-9c52-0680aa9de613 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=481250899 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.481250899 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.2624611766 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 6232240000 ps |
| CPU time | 20.79 seconds |
| Started | Mar 14 12:24:18 PM PDT 24 |
| Finished | Mar 14 12:24:56 PM PDT 24 |
| Peak memory | 145036 kb |
| Host | smart-de27d2b6-9d84-4140-9e62-8b25f418074a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2624611766 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.2624611766 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.977237859 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 13047280000 ps |
| CPU time | 52.24 seconds |
| Started | Mar 14 12:19:59 PM PDT 24 |
| Finished | Mar 14 12:21:36 PM PDT 24 |
| Peak memory | 145040 kb |
| Host | smart-62ed85aa-ce7d-499b-81c5-6b3b829a6ce2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=977237859 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.977237859 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.1012913499 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 10204580000 ps |
| CPU time | 31.29 seconds |
| Started | Mar 14 12:24:16 PM PDT 24 |
| Finished | Mar 14 12:25:14 PM PDT 24 |
| Peak memory | 145036 kb |
| Host | smart-9e7dd54e-ca8c-4a7f-96c4-09bcff0c36c0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1012913499 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.1012913499 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.1983782139 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 5740580000 ps |
| CPU time | 23.31 seconds |
| Started | Mar 14 12:20:53 PM PDT 24 |
| Finished | Mar 14 12:21:37 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-1c20e30a-8193-4bdc-8edd-03f7c254e678 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1983782139 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.1983782139 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.3691199115 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 9879080000 ps |
| CPU time | 36.06 seconds |
| Started | Mar 14 12:24:24 PM PDT 24 |
| Finished | Mar 14 12:25:33 PM PDT 24 |
| Peak memory | 144360 kb |
| Host | smart-af24ffca-7399-499e-b3c6-b9fe6af641ce |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3691199115 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.3691199115 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.3208001075 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 3266160000 ps |
| CPU time | 12.5 seconds |
| Started | Mar 14 12:24:24 PM PDT 24 |
| Finished | Mar 14 12:24:49 PM PDT 24 |
| Peak memory | 144824 kb |
| Host | smart-e0943cf4-3f55-4c51-8b9d-e609727ade63 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3208001075 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.3208001075 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.200050633 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 5526060000 ps |
| CPU time | 19.23 seconds |
| Started | Mar 14 12:18:37 PM PDT 24 |
| Finished | Mar 14 12:19:13 PM PDT 24 |
| Peak memory | 144968 kb |
| Host | smart-cc728563-0a37-4db5-8041-b984a055e710 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=200050633 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.200050633 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.3635351341 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 13599080000 ps |
| CPU time | 48.86 seconds |
| Started | Mar 14 12:24:24 PM PDT 24 |
| Finished | Mar 14 12:25:57 PM PDT 24 |
| Peak memory | 144120 kb |
| Host | smart-c608f145-e0e1-4340-89d6-161258cfc95d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3635351341 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.3635351341 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.1448422334 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 13493680000 ps |
| CPU time | 51.03 seconds |
| Started | Mar 14 12:18:38 PM PDT 24 |
| Finished | Mar 14 12:20:14 PM PDT 24 |
| Peak memory | 144912 kb |
| Host | smart-049c819f-bfba-4f47-9a7b-93e931dcea32 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1448422334 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.1448422334 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.2926874676 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 15155280000 ps |
| CPU time | 52.15 seconds |
| Started | Mar 14 12:24:08 PM PDT 24 |
| Finished | Mar 14 12:25:46 PM PDT 24 |
| Peak memory | 143716 kb |
| Host | smart-5829edb0-5367-4031-a443-eff93f098098 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2926874676 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.2926874676 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.2143909690 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 4553280000 ps |
| CPU time | 18.94 seconds |
| Started | Mar 14 12:20:54 PM PDT 24 |
| Finished | Mar 14 12:21:29 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-83e547ff-5096-41dc-afc2-be6cf6418215 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2143909690 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.2143909690 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.3502623296 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 10640440000 ps |
| CPU time | 34.55 seconds |
| Started | Mar 14 12:19:01 PM PDT 24 |
| Finished | Mar 14 12:20:05 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-a54beccd-2fd5-451b-a02d-3637f5aeb52d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3502623296 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.3502623296 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.826356615 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 14914720000 ps |
| CPU time | 52.65 seconds |
| Started | Mar 14 12:18:38 PM PDT 24 |
| Finished | Mar 14 12:20:18 PM PDT 24 |
| Peak memory | 144908 kb |
| Host | smart-2274d3b0-14e7-4138-a0dd-2546ac4d667d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=826356615 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.826356615 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.2831320592 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 10455680000 ps |
| CPU time | 40.09 seconds |
| Started | Mar 14 12:18:37 PM PDT 24 |
| Finished | Mar 14 12:19:54 PM PDT 24 |
| Peak memory | 144896 kb |
| Host | smart-72246525-d6e9-4725-9421-b9e4e93c48ee |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2831320592 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.2831320592 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.4251249331 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 10602620000 ps |
| CPU time | 40.82 seconds |
| Started | Mar 14 12:20:54 PM PDT 24 |
| Finished | Mar 14 12:22:11 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-d1447619-7987-40c8-82a1-8f8675922c32 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4251249331 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.4251249331 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.1825279745 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 4741140000 ps |
| CPU time | 15.12 seconds |
| Started | Mar 14 12:18:57 PM PDT 24 |
| Finished | Mar 14 12:19:25 PM PDT 24 |
| Peak memory | 145072 kb |
| Host | smart-e9932149-1dbb-413d-a215-457b33929461 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1825279745 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.1825279745 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.4033792836 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 3206020000 ps |
| CPU time | 10.7 seconds |
| Started | Mar 14 12:18:57 PM PDT 24 |
| Finished | Mar 14 12:19:17 PM PDT 24 |
| Peak memory | 144920 kb |
| Host | smart-fc574ac9-7d8c-48f8-8d60-519d9baaaff0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4033792836 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.4033792836 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.4195391068 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 11383200000 ps |
| CPU time | 40.28 seconds |
| Started | Mar 14 12:21:02 PM PDT 24 |
| Finished | Mar 14 12:22:19 PM PDT 24 |
| Peak memory | 144868 kb |
| Host | smart-6dca170a-fade-4232-92df-50028b3217f4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4195391068 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.4195391068 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.750279648 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 6431880000 ps |
| CPU time | 22.87 seconds |
| Started | Mar 14 12:22:17 PM PDT 24 |
| Finished | Mar 14 12:23:00 PM PDT 24 |
| Peak memory | 145080 kb |
| Host | smart-61cbdce9-9cec-4309-83f1-d192c3834455 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=750279648 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.750279648 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.2346436961 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 5868920000 ps |
| CPU time | 16.32 seconds |
| Started | Mar 14 12:24:02 PM PDT 24 |
| Finished | Mar 14 12:24:32 PM PDT 24 |
| Peak memory | 144988 kb |
| Host | smart-d12295d0-8587-474c-980b-5db854228128 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2346436961 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.2346436961 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.825986284 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 3555080000 ps |
| CPU time | 13.97 seconds |
| Started | Mar 14 12:19:44 PM PDT 24 |
| Finished | Mar 14 12:20:10 PM PDT 24 |
| Peak memory | 145016 kb |
| Host | smart-de1a7621-9c1d-4518-8633-19cc5b6d01f2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=825986284 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.825986284 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.1672380472 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 8362560000 ps |
| CPU time | 30.41 seconds |
| Started | Mar 14 12:19:24 PM PDT 24 |
| Finished | Mar 14 12:20:23 PM PDT 24 |
| Peak memory | 144352 kb |
| Host | smart-e7d00252-48bb-46f1-980a-8d53be2a6d62 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1672380472 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.1672380472 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.2300829309 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 3267400000 ps |
| CPU time | 11.32 seconds |
| Started | Mar 14 12:24:08 PM PDT 24 |
| Finished | Mar 14 12:24:30 PM PDT 24 |
| Peak memory | 143896 kb |
| Host | smart-30d08f96-0ee8-4df5-8b35-e7f65b5b03d1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2300829309 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.2300829309 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.729894080 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 11060800000 ps |
| CPU time | 35.73 seconds |
| Started | Mar 14 12:19:34 PM PDT 24 |
| Finished | Mar 14 12:20:44 PM PDT 24 |
| Peak memory | 145044 kb |
| Host | smart-a809c221-243f-46d1-8d40-46aa1448e1e4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=729894080 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.729894080 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.123787720 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 15216660000 ps |
| CPU time | 53.5 seconds |
| Started | Mar 14 12:19:37 PM PDT 24 |
| Finished | Mar 14 12:21:17 PM PDT 24 |
| Peak memory | 145068 kb |
| Host | smart-ff123661-74cb-4bbd-81b2-36e5fa96d1f1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=123787720 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.123787720 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.3924984496 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 5036880000 ps |
| CPU time | 17.03 seconds |
| Started | Mar 14 12:19:49 PM PDT 24 |
| Finished | Mar 14 12:20:20 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-4cd4948e-e282-4573-b858-c14f03959d19 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3924984496 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.3924984496 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.1778953101 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 6186360000 ps |
| CPU time | 24.68 seconds |
| Started | Mar 14 12:22:08 PM PDT 24 |
| Finished | Mar 14 12:22:54 PM PDT 24 |
| Peak memory | 145148 kb |
| Host | smart-5964d4c1-8d4c-4f45-85f9-486de20721ed |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1778953101 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.1778953101 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.3068268246 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 12001340000 ps |
| CPU time | 46.34 seconds |
| Started | Mar 14 12:22:08 PM PDT 24 |
| Finished | Mar 14 12:23:34 PM PDT 24 |
| Peak memory | 145152 kb |
| Host | smart-377e9fd7-a863-4bf6-9a21-5c3c02614a3f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3068268246 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.3068268246 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.3487453091 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 10498460000 ps |
| CPU time | 36.99 seconds |
| Started | Mar 14 12:23:39 PM PDT 24 |
| Finished | Mar 14 12:24:50 PM PDT 24 |
| Peak memory | 144956 kb |
| Host | smart-4081e956-77f7-427c-98ed-71aae150b112 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3487453091 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.3487453091 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.1466865447 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 12130920000 ps |
| CPU time | 42.58 seconds |
| Started | Mar 14 12:18:56 PM PDT 24 |
| Finished | Mar 14 12:20:16 PM PDT 24 |
| Peak memory | 145092 kb |
| Host | smart-24643cbc-624f-402f-8dd9-723b646552a4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1466865447 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.1466865447 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.348761097 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 8869100000 ps |
| CPU time | 28.97 seconds |
| Started | Mar 14 12:23:25 PM PDT 24 |
| Finished | Mar 14 12:24:19 PM PDT 24 |
| Peak memory | 143908 kb |
| Host | smart-28e27337-301f-4c04-923d-c6f006ea8c59 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=348761097 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.348761097 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.1712658897 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 10863640000 ps |
| CPU time | 35.12 seconds |
| Started | Mar 14 12:23:26 PM PDT 24 |
| Finished | Mar 14 12:24:31 PM PDT 24 |
| Peak memory | 144772 kb |
| Host | smart-630c9508-a121-4d5a-a2e4-aba02e3d97ba |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1712658897 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.1712658897 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.3848968131 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 5927820000 ps |
| CPU time | 17.92 seconds |
| Started | Mar 14 12:24:03 PM PDT 24 |
| Finished | Mar 14 12:24:36 PM PDT 24 |
| Peak memory | 143924 kb |
| Host | smart-5a4935bb-5929-47d7-a85b-1bf6654e24a4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3848968131 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.3848968131 |
| Directory | /workspace/9.prim_present_test/latest |
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