| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/16.prim_present_test.799092261 | ||
| Name |
|---|
| /workspace/coverage/default/0.prim_present_test.3628294257 |
| /workspace/coverage/default/1.prim_present_test.4047994048 |
| /workspace/coverage/default/10.prim_present_test.1104780044 |
| /workspace/coverage/default/11.prim_present_test.1409384236 |
| /workspace/coverage/default/12.prim_present_test.420235940 |
| /workspace/coverage/default/13.prim_present_test.2232951035 |
| /workspace/coverage/default/14.prim_present_test.2367068117 |
| /workspace/coverage/default/15.prim_present_test.1256252629 |
| /workspace/coverage/default/17.prim_present_test.3093586192 |
| /workspace/coverage/default/18.prim_present_test.955381568 |
| /workspace/coverage/default/19.prim_present_test.1914935977 |
| /workspace/coverage/default/2.prim_present_test.3450127220 |
| /workspace/coverage/default/20.prim_present_test.1742566574 |
| /workspace/coverage/default/21.prim_present_test.929770004 |
| /workspace/coverage/default/22.prim_present_test.2803196995 |
| /workspace/coverage/default/23.prim_present_test.3599131335 |
| /workspace/coverage/default/24.prim_present_test.2385392314 |
| /workspace/coverage/default/25.prim_present_test.1852210963 |
| /workspace/coverage/default/26.prim_present_test.1113005875 |
| /workspace/coverage/default/27.prim_present_test.1201596896 |
| /workspace/coverage/default/28.prim_present_test.1243875041 |
| /workspace/coverage/default/29.prim_present_test.2732588926 |
| /workspace/coverage/default/3.prim_present_test.1389762441 |
| /workspace/coverage/default/30.prim_present_test.2989451786 |
| /workspace/coverage/default/31.prim_present_test.391833495 |
| /workspace/coverage/default/32.prim_present_test.2053573647 |
| /workspace/coverage/default/33.prim_present_test.275512376 |
| /workspace/coverage/default/34.prim_present_test.754496922 |
| /workspace/coverage/default/35.prim_present_test.1032230705 |
| /workspace/coverage/default/36.prim_present_test.1652050138 |
| /workspace/coverage/default/37.prim_present_test.3460985831 |
| /workspace/coverage/default/38.prim_present_test.2857266468 |
| /workspace/coverage/default/39.prim_present_test.856448829 |
| /workspace/coverage/default/4.prim_present_test.2819374673 |
| /workspace/coverage/default/40.prim_present_test.567244758 |
| /workspace/coverage/default/41.prim_present_test.1500598647 |
| /workspace/coverage/default/42.prim_present_test.3954519941 |
| /workspace/coverage/default/43.prim_present_test.581380414 |
| /workspace/coverage/default/44.prim_present_test.2419218805 |
| /workspace/coverage/default/45.prim_present_test.3780435923 |
| /workspace/coverage/default/46.prim_present_test.3124529 |
| /workspace/coverage/default/47.prim_present_test.4280542632 |
| /workspace/coverage/default/48.prim_present_test.3078694273 |
| /workspace/coverage/default/49.prim_present_test.3196168619 |
| /workspace/coverage/default/5.prim_present_test.3489182448 |
| /workspace/coverage/default/6.prim_present_test.2573774206 |
| /workspace/coverage/default/7.prim_present_test.980288654 |
| /workspace/coverage/default/8.prim_present_test.785296466 |
| /workspace/coverage/default/9.prim_present_test.1941526261 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/4.prim_present_test.2819374673 | Mar 17 12:28:31 PM PDT 24 | Mar 17 12:29:27 PM PDT 24 | 11749000000 ps | ||
| T2 | /workspace/coverage/default/25.prim_present_test.1852210963 | Mar 17 12:24:08 PM PDT 24 | Mar 17 12:25:28 PM PDT 24 | 12033580000 ps | ||
| T3 | /workspace/coverage/default/34.prim_present_test.754496922 | Mar 17 12:25:55 PM PDT 24 | Mar 17 12:26:41 PM PDT 24 | 6780940000 ps | ||
| T4 | /workspace/coverage/default/28.prim_present_test.1243875041 | Mar 17 12:25:53 PM PDT 24 | Mar 17 12:27:19 PM PDT 24 | 12862520000 ps | ||
| T5 | /workspace/coverage/default/36.prim_present_test.1652050138 | Mar 17 12:27:59 PM PDT 24 | Mar 17 12:29:21 PM PDT 24 | 14229000000 ps | ||
| T6 | /workspace/coverage/default/16.prim_present_test.799092261 | Mar 17 12:27:55 PM PDT 24 | Mar 17 12:28:47 PM PDT 24 | 7876480000 ps | ||
| T7 | /workspace/coverage/default/26.prim_present_test.1113005875 | Mar 17 12:28:11 PM PDT 24 | Mar 17 12:29:31 PM PDT 24 | 12168740000 ps | ||
| T8 | /workspace/coverage/default/3.prim_present_test.1389762441 | Mar 17 12:24:22 PM PDT 24 | Mar 17 12:24:40 PM PDT 24 | 3434800000 ps | ||
| T9 | /workspace/coverage/default/46.prim_present_test.3124529 | Mar 17 12:28:01 PM PDT 24 | Mar 17 12:29:03 PM PDT 24 | 9208860000 ps | ||
| T10 | /workspace/coverage/default/41.prim_present_test.1500598647 | Mar 17 12:28:01 PM PDT 24 | Mar 17 12:29:38 PM PDT 24 | 15072200000 ps | ||
| T11 | /workspace/coverage/default/39.prim_present_test.856448829 | Mar 17 12:24:16 PM PDT 24 | Mar 17 12:25:51 PM PDT 24 | 14248220000 ps | ||
| T12 | /workspace/coverage/default/13.prim_present_test.2232951035 | Mar 17 12:22:37 PM PDT 24 | Mar 17 12:23:53 PM PDT 24 | 13822900000 ps | ||
| T13 | /workspace/coverage/default/8.prim_present_test.785296466 | Mar 17 12:23:28 PM PDT 24 | Mar 17 12:24:41 PM PDT 24 | 10860540000 ps | ||
| T14 | /workspace/coverage/default/20.prim_present_test.1742566574 | Mar 17 12:27:56 PM PDT 24 | Mar 17 12:28:28 PM PDT 24 | 4702700000 ps | ||
| T15 | /workspace/coverage/default/38.prim_present_test.2857266468 | Mar 17 12:23:58 PM PDT 24 | Mar 17 12:25:47 PM PDT 24 | 15416300000 ps | ||
| T16 | /workspace/coverage/default/22.prim_present_test.2803196995 | Mar 17 12:24:08 PM PDT 24 | Mar 17 12:25:27 PM PDT 24 | 12470060000 ps | ||
| T17 | /workspace/coverage/default/45.prim_present_test.3780435923 | Mar 17 12:24:50 PM PDT 24 | Mar 17 12:25:29 PM PDT 24 | 5345640000 ps | ||
| T18 | /workspace/coverage/default/27.prim_present_test.1201596896 | Mar 17 12:27:55 PM PDT 24 | Mar 17 12:28:24 PM PDT 24 | 4930860000 ps | ||
| T19 | /workspace/coverage/default/23.prim_present_test.3599131335 | Mar 17 12:24:01 PM PDT 24 | Mar 17 12:24:57 PM PDT 24 | 8569640000 ps | ||
| T20 | /workspace/coverage/default/35.prim_present_test.1032230705 | Mar 17 12:25:04 PM PDT 24 | Mar 17 12:25:27 PM PDT 24 | 3400080000 ps | ||
| T21 | /workspace/coverage/default/15.prim_present_test.1256252629 | Mar 17 12:27:54 PM PDT 24 | Mar 17 12:29:23 PM PDT 24 | 14454060000 ps | ||
| T22 | /workspace/coverage/default/6.prim_present_test.2573774206 | Mar 17 12:22:50 PM PDT 24 | Mar 17 12:24:28 PM PDT 24 | 15005860000 ps | ||
| T23 | /workspace/coverage/default/29.prim_present_test.2732588926 | Mar 17 12:25:54 PM PDT 24 | Mar 17 12:26:28 PM PDT 24 | 4626440000 ps | ||
| T24 | /workspace/coverage/default/31.prim_present_test.391833495 | Mar 17 12:27:56 PM PDT 24 | Mar 17 12:28:59 PM PDT 24 | 10543100000 ps | ||
| T25 | /workspace/coverage/default/40.prim_present_test.567244758 | Mar 17 12:24:29 PM PDT 24 | Mar 17 12:25:59 PM PDT 24 | 13318220000 ps | ||
| T26 | /workspace/coverage/default/1.prim_present_test.4047994048 | Mar 17 12:26:17 PM PDT 24 | Mar 17 12:27:33 PM PDT 24 | 11337940000 ps | ||
| T27 | /workspace/coverage/default/43.prim_present_test.581380414 | Mar 17 12:24:44 PM PDT 24 | Mar 17 12:25:58 PM PDT 24 | 10487300000 ps | ||
| T28 | /workspace/coverage/default/33.prim_present_test.275512376 | Mar 17 12:23:33 PM PDT 24 | Mar 17 12:23:57 PM PDT 24 | 3406900000 ps | ||
| T29 | /workspace/coverage/default/10.prim_present_test.1104780044 | Mar 17 12:22:30 PM PDT 24 | Mar 17 12:23:08 PM PDT 24 | 6792720000 ps | ||
| T30 | /workspace/coverage/default/18.prim_present_test.955381568 | Mar 17 12:24:36 PM PDT 24 | Mar 17 12:25:35 PM PDT 24 | 8197020000 ps | ||
| T31 | /workspace/coverage/default/2.prim_present_test.3450127220 | Mar 17 12:28:01 PM PDT 24 | Mar 17 12:28:54 PM PDT 24 | 8765560000 ps | ||
| T32 | /workspace/coverage/default/30.prim_present_test.2989451786 | Mar 17 12:28:10 PM PDT 24 | Mar 17 12:29:08 PM PDT 24 | 8559100000 ps | ||
| T33 | /workspace/coverage/default/14.prim_present_test.2367068117 | Mar 17 12:22:38 PM PDT 24 | Mar 17 12:24:00 PM PDT 24 | 15057940000 ps | ||
| T34 | /workspace/coverage/default/17.prim_present_test.3093586192 | Mar 17 12:24:36 PM PDT 24 | Mar 17 12:25:55 PM PDT 24 | 11279660000 ps | ||
| T35 | /workspace/coverage/default/47.prim_present_test.4280542632 | Mar 17 12:27:28 PM PDT 24 | Mar 17 12:28:24 PM PDT 24 | 11029800000 ps | ||
| T36 | /workspace/coverage/default/32.prim_present_test.2053573647 | Mar 17 12:27:59 PM PDT 24 | Mar 17 12:28:32 PM PDT 24 | 5430580000 ps | ||
| T37 | /workspace/coverage/default/42.prim_present_test.3954519941 | Mar 17 12:24:44 PM PDT 24 | Mar 17 12:25:51 PM PDT 24 | 9139420000 ps | ||
| T38 | /workspace/coverage/default/24.prim_present_test.2385392314 | Mar 17 12:28:05 PM PDT 24 | Mar 17 12:29:00 PM PDT 24 | 9343400000 ps | ||
| T39 | /workspace/coverage/default/0.prim_present_test.3628294257 | Mar 17 12:23:24 PM PDT 24 | Mar 17 12:24:03 PM PDT 24 | 5653160000 ps | ||
| T40 | /workspace/coverage/default/7.prim_present_test.980288654 | Mar 17 12:23:19 PM PDT 24 | Mar 17 12:24:28 PM PDT 24 | 10333540000 ps | ||
| T41 | /workspace/coverage/default/5.prim_present_test.3489182448 | Mar 17 12:25:08 PM PDT 24 | Mar 17 12:26:05 PM PDT 24 | 8783540000 ps | ||
| T42 | /workspace/coverage/default/21.prim_present_test.929770004 | Mar 17 12:22:59 PM PDT 24 | Mar 17 12:24:25 PM PDT 24 | 15374140000 ps | ||
| T43 | /workspace/coverage/default/11.prim_present_test.1409384236 | Mar 17 12:22:56 PM PDT 24 | Mar 17 12:24:01 PM PDT 24 | 10637340000 ps | ||
| T44 | /workspace/coverage/default/12.prim_present_test.420235940 | Mar 17 12:23:57 PM PDT 24 | Mar 17 12:25:26 PM PDT 24 | 12993340000 ps | ||
| T45 | /workspace/coverage/default/44.prim_present_test.2419218805 | Mar 17 12:25:03 PM PDT 24 | Mar 17 12:26:36 PM PDT 24 | 13387040000 ps | ||
| T46 | /workspace/coverage/default/48.prim_present_test.3078694273 | Mar 17 12:24:29 PM PDT 24 | Mar 17 12:25:54 PM PDT 24 | 12450840000 ps | ||
| T47 | /workspace/coverage/default/19.prim_present_test.1914935977 | Mar 17 12:27:56 PM PDT 24 | Mar 17 12:29:35 PM PDT 24 | 15307800000 ps | ||
| T48 | /workspace/coverage/default/49.prim_present_test.3196168619 | Mar 17 12:23:37 PM PDT 24 | Mar 17 12:25:09 PM PDT 24 | 14156460000 ps | ||
| T49 | /workspace/coverage/default/9.prim_present_test.1941526261 | Mar 17 12:23:58 PM PDT 24 | Mar 17 12:24:41 PM PDT 24 | 6140480000 ps | ||
| T50 | /workspace/coverage/default/37.prim_present_test.3460985831 | Mar 17 12:26:14 PM PDT 24 | Mar 17 12:26:54 PM PDT 24 | 6584400000 ps |
| Test location | /workspace/coverage/default/16.prim_present_test.799092261 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 7876480000 ps |
| CPU time | 27.75 seconds |
| Started | Mar 17 12:27:55 PM PDT 24 |
| Finished | Mar 17 12:28:47 PM PDT 24 |
| Peak memory | 145008 kb |
| Host | smart-e50e636a-5664-4e53-8090-c439f4909579 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=799092261 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.799092261 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/0.prim_present_test.3628294257 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 5653160000 ps |
| CPU time | 21.31 seconds |
| Started | Mar 17 12:23:24 PM PDT 24 |
| Finished | Mar 17 12:24:03 PM PDT 24 |
| Peak memory | 145156 kb |
| Host | smart-532a998e-e629-40a2-8e04-69f36fcf62ab |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3628294257 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.3628294257 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/1.prim_present_test.4047994048 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 11337940000 ps |
| CPU time | 40.54 seconds |
| Started | Mar 17 12:26:17 PM PDT 24 |
| Finished | Mar 17 12:27:33 PM PDT 24 |
| Peak memory | 145052 kb |
| Host | smart-17ae2be6-8f7d-4494-b7a7-ab97645066cc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4047994048 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.4047994048 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/10.prim_present_test.1104780044 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 6792720000 ps |
| CPU time | 20.34 seconds |
| Started | Mar 17 12:22:30 PM PDT 24 |
| Finished | Mar 17 12:23:08 PM PDT 24 |
| Peak memory | 145352 kb |
| Host | smart-a77e00d9-9ad7-4ce4-ac02-c9100368c749 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1104780044 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.1104780044 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/11.prim_present_test.1409384236 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 10637340000 ps |
| CPU time | 34.94 seconds |
| Started | Mar 17 12:22:56 PM PDT 24 |
| Finished | Mar 17 12:24:01 PM PDT 24 |
| Peak memory | 145076 kb |
| Host | smart-47da143c-7294-4c0d-a70c-2e8e11815da9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1409384236 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.1409384236 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.420235940 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 12993340000 ps |
| CPU time | 47.51 seconds |
| Started | Mar 17 12:23:57 PM PDT 24 |
| Finished | Mar 17 12:25:26 PM PDT 24 |
| Peak memory | 144868 kb |
| Host | smart-1dd7dd5d-b7cf-4498-82b6-a777dff896a4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=420235940 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.420235940 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.2232951035 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 13822900000 ps |
| CPU time | 41.17 seconds |
| Started | Mar 17 12:22:37 PM PDT 24 |
| Finished | Mar 17 12:23:53 PM PDT 24 |
| Peak memory | 145348 kb |
| Host | smart-dfd184b2-f44c-4657-a269-f58aa1ea6a3a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2232951035 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.2232951035 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.2367068117 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 15057940000 ps |
| CPU time | 44.19 seconds |
| Started | Mar 17 12:22:38 PM PDT 24 |
| Finished | Mar 17 12:24:00 PM PDT 24 |
| Peak memory | 145348 kb |
| Host | smart-8b9d7d87-6ca6-40f3-84ae-1efd63c35d32 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2367068117 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.2367068117 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.1256252629 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 14454060000 ps |
| CPU time | 48.39 seconds |
| Started | Mar 17 12:27:54 PM PDT 24 |
| Finished | Mar 17 12:29:23 PM PDT 24 |
| Peak memory | 145004 kb |
| Host | smart-ee01f3d5-dbd7-4be3-94b6-bdf99cafeedf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1256252629 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.1256252629 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.3093586192 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 11279660000 ps |
| CPU time | 41.95 seconds |
| Started | Mar 17 12:24:36 PM PDT 24 |
| Finished | Mar 17 12:25:55 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-182b93b9-1175-4c27-8300-eebe1a7425ee |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3093586192 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.3093586192 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.955381568 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 8197020000 ps |
| CPU time | 31.35 seconds |
| Started | Mar 17 12:24:36 PM PDT 24 |
| Finished | Mar 17 12:25:35 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-f47c6256-a5f1-4fd3-9540-92835ceff434 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=955381568 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.955381568 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.1914935977 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 15307800000 ps |
| CPU time | 52.6 seconds |
| Started | Mar 17 12:27:56 PM PDT 24 |
| Finished | Mar 17 12:29:35 PM PDT 24 |
| Peak memory | 145012 kb |
| Host | smart-529d0d05-55aa-4043-9b55-a119f05596fe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1914935977 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.1914935977 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.3450127220 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 8765560000 ps |
| CPU time | 28.84 seconds |
| Started | Mar 17 12:28:01 PM PDT 24 |
| Finished | Mar 17 12:28:54 PM PDT 24 |
| Peak memory | 143968 kb |
| Host | smart-77c00f19-4582-4815-9f9d-8e3d49e29de1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3450127220 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.3450127220 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.1742566574 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 4702700000 ps |
| CPU time | 17.11 seconds |
| Started | Mar 17 12:27:56 PM PDT 24 |
| Finished | Mar 17 12:28:28 PM PDT 24 |
| Peak memory | 145008 kb |
| Host | smart-31d352cc-8403-498b-8056-75d22f3bdc4f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1742566574 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.1742566574 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.929770004 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 15374140000 ps |
| CPU time | 47.18 seconds |
| Started | Mar 17 12:22:59 PM PDT 24 |
| Finished | Mar 17 12:24:25 PM PDT 24 |
| Peak memory | 144944 kb |
| Host | smart-456e473d-f26a-4bfd-960e-d74554342be7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=929770004 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.929770004 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.2803196995 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 12470060000 ps |
| CPU time | 42.73 seconds |
| Started | Mar 17 12:24:08 PM PDT 24 |
| Finished | Mar 17 12:25:27 PM PDT 24 |
| Peak memory | 145024 kb |
| Host | smart-9c56b894-7785-4d77-addf-25937a480e4d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2803196995 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.2803196995 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.3599131335 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 8569640000 ps |
| CPU time | 30.11 seconds |
| Started | Mar 17 12:24:01 PM PDT 24 |
| Finished | Mar 17 12:24:57 PM PDT 24 |
| Peak memory | 145156 kb |
| Host | smart-bf706777-cdfb-40e0-becb-d7e638e7209d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3599131335 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.3599131335 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.2385392314 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 9343400000 ps |
| CPU time | 29.69 seconds |
| Started | Mar 17 12:28:05 PM PDT 24 |
| Finished | Mar 17 12:29:00 PM PDT 24 |
| Peak memory | 144828 kb |
| Host | smart-4ba03ea8-b8c4-41d2-8d8a-798a4e65ef75 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2385392314 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.2385392314 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.1852210963 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 12033580000 ps |
| CPU time | 42.4 seconds |
| Started | Mar 17 12:24:08 PM PDT 24 |
| Finished | Mar 17 12:25:28 PM PDT 24 |
| Peak memory | 145024 kb |
| Host | smart-78ef4f94-07c2-41f2-9ff0-82fc72871e05 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1852210963 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.1852210963 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.1113005875 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 12168740000 ps |
| CPU time | 42.44 seconds |
| Started | Mar 17 12:28:11 PM PDT 24 |
| Finished | Mar 17 12:29:31 PM PDT 24 |
| Peak memory | 144992 kb |
| Host | smart-311ca3f6-9e99-4f7a-88a3-2a4922cc5908 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1113005875 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.1113005875 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.1201596896 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 4930860000 ps |
| CPU time | 15.72 seconds |
| Started | Mar 17 12:27:55 PM PDT 24 |
| Finished | Mar 17 12:28:24 PM PDT 24 |
| Peak memory | 143608 kb |
| Host | smart-21a86c41-14dc-4dc3-8887-4cfa31d5d017 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1201596896 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.1201596896 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.1243875041 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 12862520000 ps |
| CPU time | 45.44 seconds |
| Started | Mar 17 12:25:53 PM PDT 24 |
| Finished | Mar 17 12:27:19 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-d1c0475a-49a0-4e89-81fd-1b3dfaadc86e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1243875041 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.1243875041 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.2732588926 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 4626440000 ps |
| CPU time | 17.94 seconds |
| Started | Mar 17 12:25:54 PM PDT 24 |
| Finished | Mar 17 12:26:28 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-70cc4ba5-a307-4daa-98f5-ac76a0ad7238 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2732588926 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.2732588926 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.1389762441 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 3434800000 ps |
| CPU time | 9.76 seconds |
| Started | Mar 17 12:24:22 PM PDT 24 |
| Finished | Mar 17 12:24:40 PM PDT 24 |
| Peak memory | 145204 kb |
| Host | smart-44b8d91a-9160-4681-bf0f-5412fc8f9886 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1389762441 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.1389762441 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.2989451786 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 8559100000 ps |
| CPU time | 30.43 seconds |
| Started | Mar 17 12:28:10 PM PDT 24 |
| Finished | Mar 17 12:29:08 PM PDT 24 |
| Peak memory | 144992 kb |
| Host | smart-a25da3b4-c1a8-4912-ab2a-b4ad13d7f830 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2989451786 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.2989451786 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.391833495 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 10543100000 ps |
| CPU time | 34.21 seconds |
| Started | Mar 17 12:27:56 PM PDT 24 |
| Finished | Mar 17 12:28:59 PM PDT 24 |
| Peak memory | 144820 kb |
| Host | smart-b9daaa2e-1484-4bab-83bb-7319c180128a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=391833495 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.391833495 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.2053573647 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 5430580000 ps |
| CPU time | 17.17 seconds |
| Started | Mar 17 12:27:59 PM PDT 24 |
| Finished | Mar 17 12:28:32 PM PDT 24 |
| Peak memory | 143736 kb |
| Host | smart-3819af8f-3841-4602-843f-2f7422ef92ef |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2053573647 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.2053573647 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.275512376 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 3406900000 ps |
| CPU time | 12.68 seconds |
| Started | Mar 17 12:23:33 PM PDT 24 |
| Finished | Mar 17 12:23:57 PM PDT 24 |
| Peak memory | 144996 kb |
| Host | smart-06c58d30-0f01-4f27-9dc5-0852d6a817fa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=275512376 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.275512376 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.754496922 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 6780940000 ps |
| CPU time | 24.32 seconds |
| Started | Mar 17 12:25:55 PM PDT 24 |
| Finished | Mar 17 12:26:41 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-db84799b-1915-4242-ac90-db9573b06afa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=754496922 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.754496922 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.1032230705 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 3400080000 ps |
| CPU time | 12.27 seconds |
| Started | Mar 17 12:25:04 PM PDT 24 |
| Finished | Mar 17 12:25:27 PM PDT 24 |
| Peak memory | 145008 kb |
| Host | smart-099515be-af34-4023-9456-2e2bc5935409 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1032230705 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.1032230705 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.1652050138 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 14229000000 ps |
| CPU time | 43.79 seconds |
| Started | Mar 17 12:27:59 PM PDT 24 |
| Finished | Mar 17 12:29:21 PM PDT 24 |
| Peak memory | 144048 kb |
| Host | smart-92bef9a6-9414-415c-bae6-9883c380caf8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1652050138 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.1652050138 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.3460985831 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 6584400000 ps |
| CPU time | 21.95 seconds |
| Started | Mar 17 12:26:14 PM PDT 24 |
| Finished | Mar 17 12:26:54 PM PDT 24 |
| Peak memory | 145156 kb |
| Host | smart-95a1b8e3-bcf8-43d6-9bba-36eee60546dc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3460985831 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.3460985831 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.2857266468 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 15416300000 ps |
| CPU time | 57.74 seconds |
| Started | Mar 17 12:23:58 PM PDT 24 |
| Finished | Mar 17 12:25:47 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-3a81731d-a573-4e89-9a1a-7f56d05afba2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2857266468 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.2857266468 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.856448829 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 14248220000 ps |
| CPU time | 49.97 seconds |
| Started | Mar 17 12:24:16 PM PDT 24 |
| Finished | Mar 17 12:25:51 PM PDT 24 |
| Peak memory | 145064 kb |
| Host | smart-f9c3f1a4-bee3-4e4f-82b8-cfd7e6332aff |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=856448829 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.856448829 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.2819374673 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 11749000000 ps |
| CPU time | 30.53 seconds |
| Started | Mar 17 12:28:31 PM PDT 24 |
| Finished | Mar 17 12:29:27 PM PDT 24 |
| Peak memory | 145032 kb |
| Host | smart-77dfc4bf-e3fa-4b4c-82df-2e8a245bf88f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2819374673 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.2819374673 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.567244758 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 13318220000 ps |
| CPU time | 48.54 seconds |
| Started | Mar 17 12:24:29 PM PDT 24 |
| Finished | Mar 17 12:25:59 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-5c175399-1dec-478b-ad63-274c08b062c8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=567244758 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.567244758 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.1500598647 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 15072200000 ps |
| CPU time | 52.1 seconds |
| Started | Mar 17 12:28:01 PM PDT 24 |
| Finished | Mar 17 12:29:38 PM PDT 24 |
| Peak memory | 145036 kb |
| Host | smart-def06065-27a0-42a8-8b6e-3aca4962d540 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1500598647 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.1500598647 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.3954519941 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 9139420000 ps |
| CPU time | 35.31 seconds |
| Started | Mar 17 12:24:44 PM PDT 24 |
| Finished | Mar 17 12:25:51 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-60fe76d3-6d1e-4f30-ae6b-8763f2bb678c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3954519941 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.3954519941 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.581380414 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 10487300000 ps |
| CPU time | 39.13 seconds |
| Started | Mar 17 12:24:44 PM PDT 24 |
| Finished | Mar 17 12:25:58 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-eb8d1f27-a087-405e-a877-1f87da31735b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=581380414 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.581380414 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.2419218805 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 13387040000 ps |
| CPU time | 49.01 seconds |
| Started | Mar 17 12:25:03 PM PDT 24 |
| Finished | Mar 17 12:26:36 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-e2b6e41d-f9ba-48e5-a3d0-d8ab96b9d88f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2419218805 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.2419218805 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.3780435923 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 5345640000 ps |
| CPU time | 20.38 seconds |
| Started | Mar 17 12:24:50 PM PDT 24 |
| Finished | Mar 17 12:25:29 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-f4c6b904-d311-403b-9e30-7c47f40a2746 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3780435923 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.3780435923 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.3124529 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 9208860000 ps |
| CPU time | 32.67 seconds |
| Started | Mar 17 12:28:01 PM PDT 24 |
| Finished | Mar 17 12:29:03 PM PDT 24 |
| Peak memory | 145044 kb |
| Host | smart-c670a719-4308-4368-bbd6-48080a5ac716 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3124529 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.3124529 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.4280542632 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 11029800000 ps |
| CPU time | 31.48 seconds |
| Started | Mar 17 12:27:28 PM PDT 24 |
| Finished | Mar 17 12:28:24 PM PDT 24 |
| Peak memory | 144796 kb |
| Host | smart-a30faa54-8943-459c-93e1-3c93e3d5fe97 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4280542632 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.4280542632 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.3078694273 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 12450840000 ps |
| CPU time | 45.58 seconds |
| Started | Mar 17 12:24:29 PM PDT 24 |
| Finished | Mar 17 12:25:54 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-1ed47ca5-4b8b-43ad-b834-6f5a576472e5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3078694273 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.3078694273 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.3196168619 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 14156460000 ps |
| CPU time | 48.69 seconds |
| Started | Mar 17 12:23:37 PM PDT 24 |
| Finished | Mar 17 12:25:09 PM PDT 24 |
| Peak memory | 145072 kb |
| Host | smart-ae3e65b7-d974-4f33-b5e7-0c3d2b478156 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3196168619 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.3196168619 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.3489182448 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 8783540000 ps |
| CPU time | 30.32 seconds |
| Started | Mar 17 12:25:08 PM PDT 24 |
| Finished | Mar 17 12:26:05 PM PDT 24 |
| Peak memory | 145032 kb |
| Host | smart-dcdff32d-b230-4e45-8a86-42d4f843f622 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3489182448 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.3489182448 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.2573774206 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 15005860000 ps |
| CPU time | 51.87 seconds |
| Started | Mar 17 12:22:50 PM PDT 24 |
| Finished | Mar 17 12:24:28 PM PDT 24 |
| Peak memory | 144992 kb |
| Host | smart-3ac1282b-990a-49bf-a2b7-959ada4c3e0e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2573774206 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.2573774206 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.980288654 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 10333540000 ps |
| CPU time | 37.27 seconds |
| Started | Mar 17 12:23:19 PM PDT 24 |
| Finished | Mar 17 12:24:28 PM PDT 24 |
| Peak memory | 145140 kb |
| Host | smart-e01fb130-1480-4062-9589-dbef3c208c87 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=980288654 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.980288654 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.785296466 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 10860540000 ps |
| CPU time | 39.29 seconds |
| Started | Mar 17 12:23:28 PM PDT 24 |
| Finished | Mar 17 12:24:41 PM PDT 24 |
| Peak memory | 145152 kb |
| Host | smart-f153c973-1f36-4d41-b49a-99f04cfc3a2d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=785296466 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.785296466 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.1941526261 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 6140480000 ps |
| CPU time | 22.25 seconds |
| Started | Mar 17 12:23:58 PM PDT 24 |
| Finished | Mar 17 12:24:41 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-e59f79da-a6dc-4132-8225-06cd0e1bb934 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1941526261 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.1941526261 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |