| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/0.prim_present_test.4038066561 | ||
| Name |
|---|
| /workspace/coverage/default/1.prim_present_test.4027067775 |
| /workspace/coverage/default/10.prim_present_test.368658811 |
| /workspace/coverage/default/11.prim_present_test.412559 |
| /workspace/coverage/default/12.prim_present_test.2143683435 |
| /workspace/coverage/default/13.prim_present_test.4025118400 |
| /workspace/coverage/default/14.prim_present_test.1577403887 |
| /workspace/coverage/default/15.prim_present_test.3933187903 |
| /workspace/coverage/default/16.prim_present_test.324516425 |
| /workspace/coverage/default/17.prim_present_test.3170357031 |
| /workspace/coverage/default/18.prim_present_test.3782775067 |
| /workspace/coverage/default/19.prim_present_test.3647982388 |
| /workspace/coverage/default/2.prim_present_test.423287986 |
| /workspace/coverage/default/20.prim_present_test.1619299663 |
| /workspace/coverage/default/21.prim_present_test.2659061646 |
| /workspace/coverage/default/22.prim_present_test.622871826 |
| /workspace/coverage/default/23.prim_present_test.2699417722 |
| /workspace/coverage/default/24.prim_present_test.3138053390 |
| /workspace/coverage/default/25.prim_present_test.103559146 |
| /workspace/coverage/default/26.prim_present_test.3667175492 |
| /workspace/coverage/default/27.prim_present_test.1793024268 |
| /workspace/coverage/default/28.prim_present_test.4262382467 |
| /workspace/coverage/default/29.prim_present_test.1080637141 |
| /workspace/coverage/default/3.prim_present_test.1230713046 |
| /workspace/coverage/default/30.prim_present_test.1370062141 |
| /workspace/coverage/default/31.prim_present_test.3905609808 |
| /workspace/coverage/default/32.prim_present_test.3233345812 |
| /workspace/coverage/default/33.prim_present_test.3710220683 |
| /workspace/coverage/default/34.prim_present_test.644307832 |
| /workspace/coverage/default/35.prim_present_test.4138560158 |
| /workspace/coverage/default/36.prim_present_test.246345837 |
| /workspace/coverage/default/37.prim_present_test.4268303592 |
| /workspace/coverage/default/38.prim_present_test.3438839509 |
| /workspace/coverage/default/39.prim_present_test.2643028032 |
| /workspace/coverage/default/4.prim_present_test.4211255295 |
| /workspace/coverage/default/40.prim_present_test.1862623135 |
| /workspace/coverage/default/41.prim_present_test.2049474127 |
| /workspace/coverage/default/42.prim_present_test.3678198188 |
| /workspace/coverage/default/43.prim_present_test.561953915 |
| /workspace/coverage/default/44.prim_present_test.3553416632 |
| /workspace/coverage/default/45.prim_present_test.881286757 |
| /workspace/coverage/default/46.prim_present_test.3399352572 |
| /workspace/coverage/default/47.prim_present_test.3580764136 |
| /workspace/coverage/default/48.prim_present_test.413065897 |
| /workspace/coverage/default/49.prim_present_test.2242989623 |
| /workspace/coverage/default/5.prim_present_test.2396147585 |
| /workspace/coverage/default/6.prim_present_test.1968060700 |
| /workspace/coverage/default/7.prim_present_test.2388105553 |
| /workspace/coverage/default/8.prim_present_test.3127081743 |
| /workspace/coverage/default/9.prim_present_test.3021494774 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/13.prim_present_test.4025118400 | Mar 19 12:18:03 PM PDT 24 | Mar 19 12:19:30 PM PDT 24 | 11694440000 ps | ||
| T2 | /workspace/coverage/default/5.prim_present_test.2396147585 | Mar 19 12:17:59 PM PDT 24 | Mar 19 12:18:22 PM PDT 24 | 3618940000 ps | ||
| T3 | /workspace/coverage/default/0.prim_present_test.4038066561 | Mar 19 12:24:05 PM PDT 24 | Mar 19 12:24:41 PM PDT 24 | 5500640000 ps | ||
| T4 | /workspace/coverage/default/38.prim_present_test.3438839509 | Mar 19 12:24:06 PM PDT 24 | Mar 19 12:24:30 PM PDT 24 | 3873140000 ps | ||
| T5 | /workspace/coverage/default/48.prim_present_test.413065897 | Mar 19 12:20:16 PM PDT 24 | Mar 19 12:20:58 PM PDT 24 | 5411360000 ps | ||
| T6 | /workspace/coverage/default/3.prim_present_test.1230713046 | Mar 19 12:20:15 PM PDT 24 | Mar 19 12:21:29 PM PDT 24 | 9567220000 ps | ||
| T7 | /workspace/coverage/default/23.prim_present_test.2699417722 | Mar 19 12:23:49 PM PDT 24 | Mar 19 12:25:16 PM PDT 24 | 15200540000 ps | ||
| T8 | /workspace/coverage/default/2.prim_present_test.423287986 | Mar 19 12:18:05 PM PDT 24 | Mar 19 12:19:01 PM PDT 24 | 7449920000 ps | ||
| T9 | /workspace/coverage/default/27.prim_present_test.1793024268 | Mar 19 12:18:10 PM PDT 24 | Mar 19 12:18:38 PM PDT 24 | 3677840000 ps | ||
| T10 | /workspace/coverage/default/47.prim_present_test.3580764136 | Mar 19 12:18:38 PM PDT 24 | Mar 19 12:19:22 PM PDT 24 | 6689180000 ps | ||
| T11 | /workspace/coverage/default/35.prim_present_test.4138560158 | Mar 19 12:18:27 PM PDT 24 | Mar 19 12:19:56 PM PDT 24 | 11639880000 ps | ||
| T12 | /workspace/coverage/default/44.prim_present_test.3553416632 | Mar 19 12:18:16 PM PDT 24 | Mar 19 12:18:44 PM PDT 24 | 3738600000 ps | ||
| T13 | /workspace/coverage/default/18.prim_present_test.3782775067 | Mar 19 12:21:20 PM PDT 24 | Mar 19 12:22:09 PM PDT 24 | 7085980000 ps | ||
| T14 | /workspace/coverage/default/41.prim_present_test.2049474127 | Mar 19 12:18:02 PM PDT 24 | Mar 19 12:19:03 PM PDT 24 | 8053800000 ps | ||
| T15 | /workspace/coverage/default/8.prim_present_test.3127081743 | Mar 19 12:18:03 PM PDT 24 | Mar 19 12:19:13 PM PDT 24 | 9378740000 ps | ||
| T16 | /workspace/coverage/default/7.prim_present_test.2388105553 | Mar 19 12:18:37 PM PDT 24 | Mar 19 12:19:13 PM PDT 24 | 5480800000 ps | ||
| T17 | /workspace/coverage/default/28.prim_present_test.4262382467 | Mar 19 12:24:16 PM PDT 24 | Mar 19 12:25:32 PM PDT 24 | 12177420000 ps | ||
| T18 | /workspace/coverage/default/1.prim_present_test.4027067775 | Mar 19 12:18:53 PM PDT 24 | Mar 19 12:19:18 PM PDT 24 | 3871280000 ps | ||
| T19 | /workspace/coverage/default/4.prim_present_test.4211255295 | Mar 19 12:24:43 PM PDT 24 | Mar 19 12:25:40 PM PDT 24 | 7263920000 ps | ||
| T20 | /workspace/coverage/default/39.prim_present_test.2643028032 | Mar 19 12:24:12 PM PDT 24 | Mar 19 12:25:43 PM PDT 24 | 14411900000 ps | ||
| T21 | /workspace/coverage/default/17.prim_present_test.3170357031 | Mar 19 12:20:16 PM PDT 24 | Mar 19 12:21:45 PM PDT 24 | 12426040000 ps | ||
| T22 | /workspace/coverage/default/31.prim_present_test.3905609808 | Mar 19 12:18:05 PM PDT 24 | Mar 19 12:18:51 PM PDT 24 | 6415760000 ps | ||
| T23 | /workspace/coverage/default/46.prim_present_test.3399352572 | Mar 19 12:18:00 PM PDT 24 | Mar 19 12:19:08 PM PDT 24 | 11595240000 ps | ||
| T24 | /workspace/coverage/default/36.prim_present_test.246345837 | Mar 19 12:18:08 PM PDT 24 | Mar 19 12:18:38 PM PDT 24 | 4142220000 ps | ||
| T25 | /workspace/coverage/default/9.prim_present_test.3021494774 | Mar 19 12:24:43 PM PDT 24 | Mar 19 12:26:23 PM PDT 24 | 14946340000 ps | ||
| T26 | /workspace/coverage/default/19.prim_present_test.3647982388 | Mar 19 12:18:08 PM PDT 24 | Mar 19 12:18:52 PM PDT 24 | 6198140000 ps | ||
| T27 | /workspace/coverage/default/24.prim_present_test.3138053390 | Mar 19 12:18:10 PM PDT 24 | Mar 19 12:19:31 PM PDT 24 | 11277800000 ps | ||
| T28 | /workspace/coverage/default/43.prim_present_test.561953915 | Mar 19 12:18:07 PM PDT 24 | Mar 19 12:18:57 PM PDT 24 | 6748700000 ps | ||
| T29 | /workspace/coverage/default/10.prim_present_test.368658811 | Mar 19 12:23:49 PM PDT 24 | Mar 19 12:25:11 PM PDT 24 | 14101280000 ps | ||
| T30 | /workspace/coverage/default/45.prim_present_test.881286757 | Mar 19 12:19:51 PM PDT 24 | Mar 19 12:21:14 PM PDT 24 | 14712600000 ps | ||
| T31 | /workspace/coverage/default/26.prim_present_test.3667175492 | Mar 19 12:18:00 PM PDT 24 | Mar 19 12:19:54 PM PDT 24 | 14233960000 ps | ||
| T32 | /workspace/coverage/default/16.prim_present_test.324516425 | Mar 19 12:18:33 PM PDT 24 | Mar 19 12:19:13 PM PDT 24 | 4737420000 ps | ||
| T33 | /workspace/coverage/default/42.prim_present_test.3678198188 | Mar 19 12:17:56 PM PDT 24 | Mar 19 12:19:19 PM PDT 24 | 14354860000 ps | ||
| T34 | /workspace/coverage/default/21.prim_present_test.2659061646 | Mar 19 12:18:03 PM PDT 24 | Mar 19 12:19:16 PM PDT 24 | 9760040000 ps | ||
| T35 | /workspace/coverage/default/22.prim_present_test.622871826 | Mar 19 12:18:27 PM PDT 24 | Mar 19 12:20:06 PM PDT 24 | 15465280000 ps | ||
| T36 | /workspace/coverage/default/32.prim_present_test.3233345812 | Mar 19 12:24:25 PM PDT 24 | Mar 19 12:26:01 PM PDT 24 | 13964880000 ps | ||
| T37 | /workspace/coverage/default/20.prim_present_test.1619299663 | Mar 19 12:24:46 PM PDT 24 | Mar 19 12:26:01 PM PDT 24 | 11086840000 ps | ||
| T38 | /workspace/coverage/default/11.prim_present_test.412559 | Mar 19 12:18:09 PM PDT 24 | Mar 19 12:19:29 PM PDT 24 | 10641680000 ps | ||
| T39 | /workspace/coverage/default/6.prim_present_test.1968060700 | Mar 19 12:18:10 PM PDT 24 | Mar 19 12:18:48 PM PDT 24 | 4802520000 ps | ||
| T40 | /workspace/coverage/default/40.prim_present_test.1862623135 | Mar 19 12:18:08 PM PDT 24 | Mar 19 12:19:09 PM PDT 24 | 8675660000 ps | ||
| T41 | /workspace/coverage/default/49.prim_present_test.2242989623 | Mar 19 12:23:17 PM PDT 24 | Mar 19 12:23:54 PM PDT 24 | 4879400000 ps | ||
| T42 | /workspace/coverage/default/34.prim_present_test.644307832 | Mar 19 12:17:55 PM PDT 24 | Mar 19 12:19:14 PM PDT 24 | 13646820000 ps | ||
| T43 | /workspace/coverage/default/30.prim_present_test.1370062141 | Mar 19 12:18:08 PM PDT 24 | Mar 19 12:19:27 PM PDT 24 | 11460080000 ps | ||
| T44 | /workspace/coverage/default/25.prim_present_test.103559146 | Mar 19 12:18:01 PM PDT 24 | Mar 19 12:19:06 PM PDT 24 | 7289340000 ps | ||
| T45 | /workspace/coverage/default/12.prim_present_test.2143683435 | Mar 19 12:18:01 PM PDT 24 | Mar 19 12:18:58 PM PDT 24 | 6407700000 ps | ||
| T46 | /workspace/coverage/default/33.prim_present_test.3710220683 | Mar 19 12:18:30 PM PDT 24 | Mar 19 12:18:58 PM PDT 24 | 3937620000 ps | ||
| T47 | /workspace/coverage/default/14.prim_present_test.1577403887 | Mar 19 12:18:13 PM PDT 24 | Mar 19 12:18:52 PM PDT 24 | 5090820000 ps | ||
| T48 | /workspace/coverage/default/37.prim_present_test.4268303592 | Mar 19 12:18:08 PM PDT 24 | Mar 19 12:19:44 PM PDT 24 | 13867540000 ps | ||
| T49 | /workspace/coverage/default/29.prim_present_test.1080637141 | Mar 19 12:18:01 PM PDT 24 | Mar 19 12:19:05 PM PDT 24 | 7195100000 ps | ||
| T50 | /workspace/coverage/default/15.prim_present_test.3933187903 | Mar 19 12:19:32 PM PDT 24 | Mar 19 12:20:08 PM PDT 24 | 5136700000 ps |
| Test location | /workspace/coverage/default/0.prim_present_test.4038066561 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 5500640000 ps |
| CPU time | 19.07 seconds |
| Started | Mar 19 12:24:05 PM PDT 24 |
| Finished | Mar 19 12:24:41 PM PDT 24 |
| Peak memory | 144884 kb |
| Host | smart-8960330b-7829-45dc-a856-a585ac37e2bb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4038066561 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.4038066561 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/1.prim_present_test.4027067775 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 3871280000 ps |
| CPU time | 13.84 seconds |
| Started | Mar 19 12:18:53 PM PDT 24 |
| Finished | Mar 19 12:19:18 PM PDT 24 |
| Peak memory | 144480 kb |
| Host | smart-cadb407d-197e-4d29-9b0c-3e2dcaa109dd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4027067775 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.4027067775 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/10.prim_present_test.368658811 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 14101280000 ps |
| CPU time | 44.24 seconds |
| Started | Mar 19 12:23:49 PM PDT 24 |
| Finished | Mar 19 12:25:11 PM PDT 24 |
| Peak memory | 143472 kb |
| Host | smart-5c0ca2f1-bff9-4cd3-98d4-f3d97a7c8821 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=368658811 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.368658811 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/11.prim_present_test.412559 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 10641680000 ps |
| CPU time | 41.74 seconds |
| Started | Mar 19 12:18:09 PM PDT 24 |
| Finished | Mar 19 12:19:29 PM PDT 24 |
| Peak memory | 144960 kb |
| Host | smart-530e5ebf-85c4-4838-bb79-73eb9510d334 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=412559 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace /coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.412559 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.2143683435 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 6407700000 ps |
| CPU time | 28.79 seconds |
| Started | Mar 19 12:18:01 PM PDT 24 |
| Finished | Mar 19 12:18:58 PM PDT 24 |
| Peak memory | 143768 kb |
| Host | smart-578cc459-eece-41f6-96f8-d4831bb8c521 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2143683435 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.2143683435 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.4025118400 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 11694440000 ps |
| CPU time | 46.3 seconds |
| Started | Mar 19 12:18:03 PM PDT 24 |
| Finished | Mar 19 12:19:30 PM PDT 24 |
| Peak memory | 145128 kb |
| Host | smart-150f12e4-e4ed-4e94-b6f9-a675dc3c4140 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4025118400 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.4025118400 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.1577403887 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 5090820000 ps |
| CPU time | 20.68 seconds |
| Started | Mar 19 12:18:13 PM PDT 24 |
| Finished | Mar 19 12:18:52 PM PDT 24 |
| Peak memory | 145144 kb |
| Host | smart-44addbe6-8269-4fd6-89b2-ae462a2d7294 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1577403887 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.1577403887 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.3933187903 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 5136700000 ps |
| CPU time | 18.88 seconds |
| Started | Mar 19 12:19:32 PM PDT 24 |
| Finished | Mar 19 12:20:08 PM PDT 24 |
| Peak memory | 144880 kb |
| Host | smart-19c3fe96-20bb-47dd-88bd-5aca7d31d7df |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3933187903 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.3933187903 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.324516425 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 4737420000 ps |
| CPU time | 20.06 seconds |
| Started | Mar 19 12:18:33 PM PDT 24 |
| Finished | Mar 19 12:19:13 PM PDT 24 |
| Peak memory | 144968 kb |
| Host | smart-f50f22c2-c15e-4bdd-99cb-3d314352c69c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=324516425 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.324516425 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.3170357031 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 12426040000 ps |
| CPU time | 46.78 seconds |
| Started | Mar 19 12:20:16 PM PDT 24 |
| Finished | Mar 19 12:21:45 PM PDT 24 |
| Peak memory | 145132 kb |
| Host | smart-26bb7cd3-8931-4613-b343-0f7ecd0f2adf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3170357031 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.3170357031 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.3782775067 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 7085980000 ps |
| CPU time | 26.37 seconds |
| Started | Mar 19 12:21:20 PM PDT 24 |
| Finished | Mar 19 12:22:09 PM PDT 24 |
| Peak memory | 144916 kb |
| Host | smart-867f54a2-232a-4040-94cd-4a7f3ffe209c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3782775067 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.3782775067 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.3647982388 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 6198140000 ps |
| CPU time | 23.09 seconds |
| Started | Mar 19 12:18:08 PM PDT 24 |
| Finished | Mar 19 12:18:52 PM PDT 24 |
| Peak memory | 144816 kb |
| Host | smart-b4ee0621-87f1-41da-834e-f3cb6c7d764e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3647982388 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.3647982388 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.423287986 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 7449920000 ps |
| CPU time | 29.11 seconds |
| Started | Mar 19 12:18:05 PM PDT 24 |
| Finished | Mar 19 12:19:01 PM PDT 24 |
| Peak memory | 145064 kb |
| Host | smart-b2fbc328-37c6-4725-859c-c44533b39608 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=423287986 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.423287986 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.1619299663 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 11086840000 ps |
| CPU time | 38.96 seconds |
| Started | Mar 19 12:24:46 PM PDT 24 |
| Finished | Mar 19 12:26:01 PM PDT 24 |
| Peak memory | 144892 kb |
| Host | smart-d26c5da8-ad53-4a4c-9782-b4db3339ff34 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1619299663 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.1619299663 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.2659061646 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 9760040000 ps |
| CPU time | 38.51 seconds |
| Started | Mar 19 12:18:03 PM PDT 24 |
| Finished | Mar 19 12:19:16 PM PDT 24 |
| Peak memory | 145132 kb |
| Host | smart-12ef5d3c-71a0-4fa7-9e5b-c00d00780f91 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2659061646 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.2659061646 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.622871826 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 15465280000 ps |
| CPU time | 53.48 seconds |
| Started | Mar 19 12:18:27 PM PDT 24 |
| Finished | Mar 19 12:20:06 PM PDT 24 |
| Peak memory | 144028 kb |
| Host | smart-1fe11ddc-7bf3-4ac3-9b5f-36b1f8b3821e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=622871826 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.622871826 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.2699417722 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 15200540000 ps |
| CPU time | 47.02 seconds |
| Started | Mar 19 12:23:49 PM PDT 24 |
| Finished | Mar 19 12:25:16 PM PDT 24 |
| Peak memory | 143252 kb |
| Host | smart-df9a46c0-746f-49f7-97d6-ca4ead86f94d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2699417722 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.2699417722 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.3138053390 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 11277800000 ps |
| CPU time | 42.67 seconds |
| Started | Mar 19 12:18:10 PM PDT 24 |
| Finished | Mar 19 12:19:31 PM PDT 24 |
| Peak memory | 144968 kb |
| Host | smart-4c9b19db-5b73-40f7-b07e-be5216feb185 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3138053390 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.3138053390 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.103559146 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 7289340000 ps |
| CPU time | 32.65 seconds |
| Started | Mar 19 12:18:01 PM PDT 24 |
| Finished | Mar 19 12:19:06 PM PDT 24 |
| Peak memory | 143512 kb |
| Host | smart-a807beda-5414-48f4-9dd4-4b1709bb54ec |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=103559146 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.103559146 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.3667175492 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 14233960000 ps |
| CPU time | 58.37 seconds |
| Started | Mar 19 12:18:00 PM PDT 24 |
| Finished | Mar 19 12:19:54 PM PDT 24 |
| Peak memory | 143312 kb |
| Host | smart-c791c7f1-840f-4020-a98c-768bb2b2172f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3667175492 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.3667175492 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.1793024268 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 3677840000 ps |
| CPU time | 14.34 seconds |
| Started | Mar 19 12:18:10 PM PDT 24 |
| Finished | Mar 19 12:18:38 PM PDT 24 |
| Peak memory | 144996 kb |
| Host | smart-4f106880-13a3-4938-ab91-3fabe112a6ff |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1793024268 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.1793024268 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.4262382467 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 12177420000 ps |
| CPU time | 39.62 seconds |
| Started | Mar 19 12:24:16 PM PDT 24 |
| Finished | Mar 19 12:25:32 PM PDT 24 |
| Peak memory | 144060 kb |
| Host | smart-ad4ab24a-dc29-49ab-b3dd-01ca82265b3e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4262382467 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.4262382467 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.1080637141 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 7195100000 ps |
| CPU time | 32.72 seconds |
| Started | Mar 19 12:18:01 PM PDT 24 |
| Finished | Mar 19 12:19:05 PM PDT 24 |
| Peak memory | 143800 kb |
| Host | smart-38d892c4-4d5b-4700-a30c-1af8330702e9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1080637141 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.1080637141 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.1230713046 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 9567220000 ps |
| CPU time | 38.69 seconds |
| Started | Mar 19 12:20:15 PM PDT 24 |
| Finished | Mar 19 12:21:29 PM PDT 24 |
| Peak memory | 144948 kb |
| Host | smart-7270bbc4-100b-4de6-8734-11a67f5f073d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1230713046 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.1230713046 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.1370062141 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 11460080000 ps |
| CPU time | 41.97 seconds |
| Started | Mar 19 12:18:08 PM PDT 24 |
| Finished | Mar 19 12:19:27 PM PDT 24 |
| Peak memory | 143540 kb |
| Host | smart-3239dc0f-1fae-423e-a4c2-3459e1eb9dbd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1370062141 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.1370062141 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.3905609808 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 6415760000 ps |
| CPU time | 24.07 seconds |
| Started | Mar 19 12:18:05 PM PDT 24 |
| Finished | Mar 19 12:18:51 PM PDT 24 |
| Peak memory | 145004 kb |
| Host | smart-420c983f-c837-4f9f-b8e3-cde578ee62d2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3905609808 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.3905609808 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.3233345812 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 13964880000 ps |
| CPU time | 49.93 seconds |
| Started | Mar 19 12:24:25 PM PDT 24 |
| Finished | Mar 19 12:26:01 PM PDT 24 |
| Peak memory | 143880 kb |
| Host | smart-01f0baf2-733d-4931-a950-c7fe1c3385b6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3233345812 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.3233345812 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.3710220683 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 3937620000 ps |
| CPU time | 14.67 seconds |
| Started | Mar 19 12:18:30 PM PDT 24 |
| Finished | Mar 19 12:18:58 PM PDT 24 |
| Peak memory | 145064 kb |
| Host | smart-0287b9a2-421e-4dfc-a5aa-60cfded21a4c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3710220683 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.3710220683 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.644307832 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 13646820000 ps |
| CPU time | 42.11 seconds |
| Started | Mar 19 12:17:55 PM PDT 24 |
| Finished | Mar 19 12:19:14 PM PDT 24 |
| Peak memory | 145400 kb |
| Host | smart-b937fbf4-bf5b-4940-b632-48d7d429fc01 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=644307832 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.644307832 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.4138560158 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 11639880000 ps |
| CPU time | 45.71 seconds |
| Started | Mar 19 12:18:27 PM PDT 24 |
| Finished | Mar 19 12:19:56 PM PDT 24 |
| Peak memory | 144968 kb |
| Host | smart-1cfb6ace-827a-4ed6-ae76-273091964f95 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4138560158 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.4138560158 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.246345837 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 4142220000 ps |
| CPU time | 16.27 seconds |
| Started | Mar 19 12:18:08 PM PDT 24 |
| Finished | Mar 19 12:18:38 PM PDT 24 |
| Peak memory | 143260 kb |
| Host | smart-3f01241e-6ac8-4dbb-9b11-29c52bd27315 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=246345837 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.246345837 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.4268303592 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 13867540000 ps |
| CPU time | 50.89 seconds |
| Started | Mar 19 12:18:08 PM PDT 24 |
| Finished | Mar 19 12:19:44 PM PDT 24 |
| Peak memory | 144192 kb |
| Host | smart-48ce1401-322e-4946-935a-ac77bafbf384 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4268303592 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.4268303592 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.3438839509 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 3873140000 ps |
| CPU time | 12.53 seconds |
| Started | Mar 19 12:24:06 PM PDT 24 |
| Finished | Mar 19 12:24:30 PM PDT 24 |
| Peak memory | 143876 kb |
| Host | smart-0256e3f3-71b8-4c24-adde-f27380c6c0b1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3438839509 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.3438839509 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.2643028032 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 14411900000 ps |
| CPU time | 48.25 seconds |
| Started | Mar 19 12:24:12 PM PDT 24 |
| Finished | Mar 19 12:25:43 PM PDT 24 |
| Peak memory | 143556 kb |
| Host | smart-183439ab-7bdf-4bd2-a862-23776c576d57 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2643028032 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.2643028032 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.4211255295 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 7263920000 ps |
| CPU time | 28.91 seconds |
| Started | Mar 19 12:24:43 PM PDT 24 |
| Finished | Mar 19 12:25:40 PM PDT 24 |
| Peak memory | 144892 kb |
| Host | smart-e2da7b2e-e457-4ca3-937e-7dd56e701b58 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4211255295 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.4211255295 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.1862623135 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 8675660000 ps |
| CPU time | 32.18 seconds |
| Started | Mar 19 12:18:08 PM PDT 24 |
| Finished | Mar 19 12:19:09 PM PDT 24 |
| Peak memory | 143524 kb |
| Host | smart-3adfa6cc-3e55-42ce-86cd-4a9e5813d036 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1862623135 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.1862623135 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.2049474127 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 8053800000 ps |
| CPU time | 32.25 seconds |
| Started | Mar 19 12:18:02 PM PDT 24 |
| Finished | Mar 19 12:19:03 PM PDT 24 |
| Peak memory | 144988 kb |
| Host | smart-95d37849-2a41-448d-8cf5-fa6129457315 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2049474127 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.2049474127 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.3678198188 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 14354860000 ps |
| CPU time | 44.63 seconds |
| Started | Mar 19 12:17:56 PM PDT 24 |
| Finished | Mar 19 12:19:19 PM PDT 24 |
| Peak memory | 145396 kb |
| Host | smart-f263fadc-c241-490f-a0a1-b7f5b6d18451 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3678198188 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.3678198188 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.561953915 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 6748700000 ps |
| CPU time | 25.91 seconds |
| Started | Mar 19 12:18:07 PM PDT 24 |
| Finished | Mar 19 12:18:57 PM PDT 24 |
| Peak memory | 145144 kb |
| Host | smart-4ff1621b-87db-4776-8610-5cbd446f5e1a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=561953915 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.561953915 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.3553416632 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 3738600000 ps |
| CPU time | 15.03 seconds |
| Started | Mar 19 12:18:16 PM PDT 24 |
| Finished | Mar 19 12:18:44 PM PDT 24 |
| Peak memory | 144820 kb |
| Host | smart-1ec15d9c-55d1-494f-ba72-047e2a8d7b9e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3553416632 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.3553416632 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.881286757 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 14712600000 ps |
| CPU time | 44.18 seconds |
| Started | Mar 19 12:19:51 PM PDT 24 |
| Finished | Mar 19 12:21:14 PM PDT 24 |
| Peak memory | 145400 kb |
| Host | smart-acfdc241-c2f2-4fa0-8774-2d0f295539e8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=881286757 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.881286757 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.3399352572 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 11595240000 ps |
| CPU time | 36.23 seconds |
| Started | Mar 19 12:18:00 PM PDT 24 |
| Finished | Mar 19 12:19:08 PM PDT 24 |
| Peak memory | 145396 kb |
| Host | smart-26940c38-9e51-41ee-b72d-8cb36a6b6950 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3399352572 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.3399352572 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.3580764136 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 6689180000 ps |
| CPU time | 23.38 seconds |
| Started | Mar 19 12:18:38 PM PDT 24 |
| Finished | Mar 19 12:19:22 PM PDT 24 |
| Peak memory | 144916 kb |
| Host | smart-fef9cc10-252a-4626-b7d0-3cd6a9a439c7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3580764136 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.3580764136 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.413065897 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 5411360000 ps |
| CPU time | 22.28 seconds |
| Started | Mar 19 12:20:16 PM PDT 24 |
| Finished | Mar 19 12:20:58 PM PDT 24 |
| Peak memory | 145128 kb |
| Host | smart-40c284fd-8e96-4830-9339-a31de95502d6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=413065897 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.413065897 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.2242989623 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 4879400000 ps |
| CPU time | 18.94 seconds |
| Started | Mar 19 12:23:17 PM PDT 24 |
| Finished | Mar 19 12:23:54 PM PDT 24 |
| Peak memory | 144600 kb |
| Host | smart-25a3555d-fcaf-4916-8b09-f6bb00a6664e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2242989623 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.2242989623 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.2396147585 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 3618940000 ps |
| CPU time | 12.01 seconds |
| Started | Mar 19 12:17:59 PM PDT 24 |
| Finished | Mar 19 12:18:22 PM PDT 24 |
| Peak memory | 145248 kb |
| Host | smart-c0b5ade1-3cbe-4189-ad07-63862d3f4ec4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2396147585 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.2396147585 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.1968060700 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 4802520000 ps |
| CPU time | 19.53 seconds |
| Started | Mar 19 12:18:10 PM PDT 24 |
| Finished | Mar 19 12:18:48 PM PDT 24 |
| Peak memory | 145144 kb |
| Host | smart-d806fc83-1c8d-4d1a-b4fd-8b94f68afb72 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1968060700 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.1968060700 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.2388105553 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 5480800000 ps |
| CPU time | 19.1 seconds |
| Started | Mar 19 12:18:37 PM PDT 24 |
| Finished | Mar 19 12:19:13 PM PDT 24 |
| Peak memory | 144844 kb |
| Host | smart-fac0fc97-6883-4df8-bbd2-25c1e8a7f194 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2388105553 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.2388105553 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.3127081743 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 9378740000 ps |
| CPU time | 36.88 seconds |
| Started | Mar 19 12:18:03 PM PDT 24 |
| Finished | Mar 19 12:19:13 PM PDT 24 |
| Peak memory | 145128 kb |
| Host | smart-f2e416f9-498b-447f-ad2e-47a25867a00a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3127081743 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.3127081743 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.3021494774 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 14946340000 ps |
| CPU time | 52.48 seconds |
| Started | Mar 19 12:24:43 PM PDT 24 |
| Finished | Mar 19 12:26:23 PM PDT 24 |
| Peak memory | 144892 kb |
| Host | smart-f97fdfa4-d41a-44ff-9f27-ecc43ee55c9f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3021494774 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.3021494774 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |