| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/1.prim_present_test.2027045376 | ||
| Name |
|---|
| /workspace/coverage/default/0.prim_present_test.1578872379 |
| /workspace/coverage/default/10.prim_present_test.1095355847 |
| /workspace/coverage/default/11.prim_present_test.2500438021 |
| /workspace/coverage/default/12.prim_present_test.3089750726 |
| /workspace/coverage/default/13.prim_present_test.2156015227 |
| /workspace/coverage/default/14.prim_present_test.2865673241 |
| /workspace/coverage/default/15.prim_present_test.3653212792 |
| /workspace/coverage/default/16.prim_present_test.3739654324 |
| /workspace/coverage/default/17.prim_present_test.3086632383 |
| /workspace/coverage/default/18.prim_present_test.2260067667 |
| /workspace/coverage/default/19.prim_present_test.2235517382 |
| /workspace/coverage/default/2.prim_present_test.3389478819 |
| /workspace/coverage/default/20.prim_present_test.3932479531 |
| /workspace/coverage/default/21.prim_present_test.1549365428 |
| /workspace/coverage/default/22.prim_present_test.2866967207 |
| /workspace/coverage/default/23.prim_present_test.2938074279 |
| /workspace/coverage/default/24.prim_present_test.243771695 |
| /workspace/coverage/default/25.prim_present_test.239577831 |
| /workspace/coverage/default/26.prim_present_test.2175180078 |
| /workspace/coverage/default/27.prim_present_test.2546483151 |
| /workspace/coverage/default/28.prim_present_test.3090544616 |
| /workspace/coverage/default/29.prim_present_test.1838627370 |
| /workspace/coverage/default/3.prim_present_test.3946676653 |
| /workspace/coverage/default/30.prim_present_test.3953727937 |
| /workspace/coverage/default/31.prim_present_test.2282816145 |
| /workspace/coverage/default/32.prim_present_test.372723034 |
| /workspace/coverage/default/33.prim_present_test.4241260223 |
| /workspace/coverage/default/34.prim_present_test.381511151 |
| /workspace/coverage/default/35.prim_present_test.2932863187 |
| /workspace/coverage/default/36.prim_present_test.3822001085 |
| /workspace/coverage/default/37.prim_present_test.632988269 |
| /workspace/coverage/default/38.prim_present_test.3722415953 |
| /workspace/coverage/default/39.prim_present_test.4149507963 |
| /workspace/coverage/default/4.prim_present_test.2658605850 |
| /workspace/coverage/default/40.prim_present_test.512332712 |
| /workspace/coverage/default/41.prim_present_test.4120023485 |
| /workspace/coverage/default/42.prim_present_test.1272052512 |
| /workspace/coverage/default/43.prim_present_test.4248422949 |
| /workspace/coverage/default/44.prim_present_test.3660077417 |
| /workspace/coverage/default/45.prim_present_test.2888678632 |
| /workspace/coverage/default/46.prim_present_test.3460621603 |
| /workspace/coverage/default/47.prim_present_test.3295760389 |
| /workspace/coverage/default/48.prim_present_test.4137607652 |
| /workspace/coverage/default/49.prim_present_test.1269864600 |
| /workspace/coverage/default/5.prim_present_test.157910388 |
| /workspace/coverage/default/6.prim_present_test.3532964938 |
| /workspace/coverage/default/7.prim_present_test.872669775 |
| /workspace/coverage/default/8.prim_present_test.3281830281 |
| /workspace/coverage/default/9.prim_present_test.1305654832 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/2.prim_present_test.3389478819 | Mar 21 12:24:31 PM PDT 24 | Mar 21 12:25:09 PM PDT 24 | 5402680000 ps | ||
| T2 | /workspace/coverage/default/28.prim_present_test.3090544616 | Mar 21 12:24:35 PM PDT 24 | Mar 21 12:25:17 PM PDT 24 | 7982500000 ps | ||
| T3 | /workspace/coverage/default/23.prim_present_test.2938074279 | Mar 21 12:24:46 PM PDT 24 | Mar 21 12:26:12 PM PDT 24 | 13714400000 ps | ||
| T4 | /workspace/coverage/default/19.prim_present_test.2235517382 | Mar 21 12:24:32 PM PDT 24 | Mar 21 12:26:05 PM PDT 24 | 12322500000 ps | ||
| T5 | /workspace/coverage/default/40.prim_present_test.512332712 | Mar 21 12:24:50 PM PDT 24 | Mar 21 12:26:29 PM PDT 24 | 14173200000 ps | ||
| T6 | /workspace/coverage/default/1.prim_present_test.2027045376 | Mar 21 12:24:33 PM PDT 24 | Mar 21 12:25:14 PM PDT 24 | 5844740000 ps | ||
| T7 | /workspace/coverage/default/46.prim_present_test.3460621603 | Mar 21 12:24:43 PM PDT 24 | Mar 21 12:25:13 PM PDT 24 | 4094480000 ps | ||
| T8 | /workspace/coverage/default/48.prim_present_test.4137607652 | Mar 21 12:24:45 PM PDT 24 | Mar 21 12:26:26 PM PDT 24 | 14881240000 ps | ||
| T9 | /workspace/coverage/default/14.prim_present_test.2865673241 | Mar 21 12:24:31 PM PDT 24 | Mar 21 12:25:45 PM PDT 24 | 9233040000 ps | ||
| T10 | /workspace/coverage/default/3.prim_present_test.3946676653 | Mar 21 12:24:17 PM PDT 24 | Mar 21 12:24:54 PM PDT 24 | 5389660000 ps | ||
| T11 | /workspace/coverage/default/47.prim_present_test.3295760389 | Mar 21 12:24:40 PM PDT 24 | Mar 21 12:25:22 PM PDT 24 | 6459780000 ps | ||
| T12 | /workspace/coverage/default/30.prim_present_test.3953727937 | Mar 21 12:24:44 PM PDT 24 | Mar 21 12:25:40 PM PDT 24 | 9782360000 ps | ||
| T13 | /workspace/coverage/default/29.prim_present_test.1838627370 | Mar 21 12:24:30 PM PDT 24 | Mar 21 12:26:15 PM PDT 24 | 15269980000 ps | ||
| T14 | /workspace/coverage/default/6.prim_present_test.3532964938 | Mar 21 12:24:33 PM PDT 24 | Mar 21 12:26:17 PM PDT 24 | 14796300000 ps | ||
| T15 | /workspace/coverage/default/36.prim_present_test.3822001085 | Mar 21 12:24:44 PM PDT 24 | Mar 21 12:25:33 PM PDT 24 | 8712240000 ps | ||
| T16 | /workspace/coverage/default/31.prim_present_test.2282816145 | Mar 21 12:24:41 PM PDT 24 | Mar 21 12:25:04 PM PDT 24 | 3608400000 ps | ||
| T17 | /workspace/coverage/default/15.prim_present_test.3653212792 | Mar 21 12:24:20 PM PDT 24 | Mar 21 12:25:37 PM PDT 24 | 10366400000 ps | ||
| T18 | /workspace/coverage/default/21.prim_present_test.1549365428 | Mar 21 12:24:35 PM PDT 24 | Mar 21 12:26:06 PM PDT 24 | 14455300000 ps | ||
| T19 | /workspace/coverage/default/17.prim_present_test.3086632383 | Mar 21 12:24:19 PM PDT 24 | Mar 21 12:24:58 PM PDT 24 | 6054920000 ps | ||
| T20 | /workspace/coverage/default/0.prim_present_test.1578872379 | Mar 21 12:24:33 PM PDT 24 | Mar 21 12:25:10 PM PDT 24 | 5415080000 ps | ||
| T21 | /workspace/coverage/default/9.prim_present_test.1305654832 | Mar 21 12:24:20 PM PDT 24 | Mar 21 12:24:52 PM PDT 24 | 5392760000 ps | ||
| T22 | /workspace/coverage/default/26.prim_present_test.2175180078 | Mar 21 12:24:27 PM PDT 24 | Mar 21 12:24:58 PM PDT 24 | 4177560000 ps | ||
| T23 | /workspace/coverage/default/37.prim_present_test.632988269 | Mar 21 12:24:38 PM PDT 24 | Mar 21 12:25:08 PM PDT 24 | 4436100000 ps | ||
| T24 | /workspace/coverage/default/20.prim_present_test.3932479531 | Mar 21 12:24:42 PM PDT 24 | Mar 21 12:25:45 PM PDT 24 | 9120200000 ps | ||
| T25 | /workspace/coverage/default/4.prim_present_test.2658605850 | Mar 21 12:24:39 PM PDT 24 | Mar 21 12:26:05 PM PDT 24 | 13995880000 ps | ||
| T26 | /workspace/coverage/default/35.prim_present_test.2932863187 | Mar 21 12:24:43 PM PDT 24 | Mar 21 12:26:08 PM PDT 24 | 13538320000 ps | ||
| T27 | /workspace/coverage/default/41.prim_present_test.4120023485 | Mar 21 12:24:39 PM PDT 24 | Mar 21 12:25:23 PM PDT 24 | 6877660000 ps | ||
| T28 | /workspace/coverage/default/44.prim_present_test.3660077417 | Mar 21 12:24:48 PM PDT 24 | Mar 21 12:26:04 PM PDT 24 | 12915840000 ps | ||
| T29 | /workspace/coverage/default/32.prim_present_test.372723034 | Mar 21 12:24:49 PM PDT 24 | Mar 21 12:25:59 PM PDT 24 | 11483640000 ps | ||
| T30 | /workspace/coverage/default/16.prim_present_test.3739654324 | Mar 21 12:24:54 PM PDT 24 | Mar 21 12:25:42 PM PDT 24 | 7483400000 ps | ||
| T31 | /workspace/coverage/default/5.prim_present_test.157910388 | Mar 21 12:24:17 PM PDT 24 | Mar 21 12:25:58 PM PDT 24 | 12801760000 ps | ||
| T32 | /workspace/coverage/default/8.prim_present_test.3281830281 | Mar 21 12:24:39 PM PDT 24 | Mar 21 12:25:31 PM PDT 24 | 7669400000 ps | ||
| T33 | /workspace/coverage/default/49.prim_present_test.1269864600 | Mar 21 12:24:39 PM PDT 24 | Mar 21 12:25:51 PM PDT 24 | 11628720000 ps | ||
| T34 | /workspace/coverage/default/10.prim_present_test.1095355847 | Mar 21 12:24:39 PM PDT 24 | Mar 21 12:25:41 PM PDT 24 | 9973320000 ps | ||
| T35 | /workspace/coverage/default/43.prim_present_test.4248422949 | Mar 21 12:24:34 PM PDT 24 | Mar 21 12:24:59 PM PDT 24 | 3927080000 ps | ||
| T36 | /workspace/coverage/default/7.prim_present_test.872669775 | Mar 21 12:24:18 PM PDT 24 | Mar 21 12:25:35 PM PDT 24 | 9720980000 ps | ||
| T37 | /workspace/coverage/default/33.prim_present_test.4241260223 | Mar 21 12:24:35 PM PDT 24 | Mar 21 12:25:39 PM PDT 24 | 9722840000 ps | ||
| T38 | /workspace/coverage/default/42.prim_present_test.1272052512 | Mar 21 12:24:39 PM PDT 24 | Mar 21 12:26:18 PM PDT 24 | 14959360000 ps | ||
| T39 | /workspace/coverage/default/18.prim_present_test.2260067667 | Mar 21 12:24:35 PM PDT 24 | Mar 21 12:26:00 PM PDT 24 | 11428460000 ps | ||
| T40 | /workspace/coverage/default/27.prim_present_test.2546483151 | Mar 21 12:24:42 PM PDT 24 | Mar 21 12:25:06 PM PDT 24 | 4808100000 ps | ||
| T41 | /workspace/coverage/default/24.prim_present_test.243771695 | Mar 21 12:24:39 PM PDT 24 | Mar 21 12:25:45 PM PDT 24 | 10707400000 ps | ||
| T42 | /workspace/coverage/default/45.prim_present_test.2888678632 | Mar 21 12:24:36 PM PDT 24 | Mar 21 12:25:18 PM PDT 24 | 7371800000 ps | ||
| T43 | /workspace/coverage/default/12.prim_present_test.3089750726 | Mar 21 12:24:33 PM PDT 24 | Mar 21 12:26:22 PM PDT 24 | 15475200000 ps | ||
| T44 | /workspace/coverage/default/25.prim_present_test.239577831 | Mar 21 12:24:34 PM PDT 24 | Mar 21 12:26:01 PM PDT 24 | 15155280000 ps | ||
| T45 | /workspace/coverage/default/39.prim_present_test.4149507963 | Mar 21 12:24:43 PM PDT 24 | Mar 21 12:25:14 PM PDT 24 | 4397660000 ps | ||
| T46 | /workspace/coverage/default/11.prim_present_test.2500438021 | Mar 21 12:24:29 PM PDT 24 | Mar 21 12:25:37 PM PDT 24 | 10372600000 ps | ||
| T47 | /workspace/coverage/default/13.prim_present_test.2156015227 | Mar 21 12:24:33 PM PDT 24 | Mar 21 12:26:16 PM PDT 24 | 15481400000 ps | ||
| T48 | /workspace/coverage/default/34.prim_present_test.381511151 | Mar 21 12:24:45 PM PDT 24 | Mar 21 12:25:40 PM PDT 24 | 8118900000 ps | ||
| T49 | /workspace/coverage/default/38.prim_present_test.3722415953 | Mar 21 12:24:33 PM PDT 24 | Mar 21 12:25:43 PM PDT 24 | 10911380000 ps | ||
| T50 | /workspace/coverage/default/22.prim_present_test.2866967207 | Mar 21 12:24:32 PM PDT 24 | Mar 21 12:25:16 PM PDT 24 | 5924720000 ps |
| Test location | /workspace/coverage/default/1.prim_present_test.2027045376 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 5844740000 ps |
| CPU time | 21.09 seconds |
| Started | Mar 21 12:24:33 PM PDT 24 |
| Finished | Mar 21 12:25:14 PM PDT 24 |
| Peak memory | 145016 kb |
| Host | smart-3d3390e9-a125-4bf9-b9ee-872f17518258 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2027045376 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.2027045376 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/0.prim_present_test.1578872379 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 5415080000 ps |
| CPU time | 19.39 seconds |
| Started | Mar 21 12:24:33 PM PDT 24 |
| Finished | Mar 21 12:25:10 PM PDT 24 |
| Peak memory | 145040 kb |
| Host | smart-68c08748-04c4-4b99-879d-0037caa58552 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1578872379 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.1578872379 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/10.prim_present_test.1095355847 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 9973320000 ps |
| CPU time | 33.17 seconds |
| Started | Mar 21 12:24:39 PM PDT 24 |
| Finished | Mar 21 12:25:41 PM PDT 24 |
| Peak memory | 145044 kb |
| Host | smart-8107282d-d247-4483-97c6-423b2fd1dcc7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1095355847 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.1095355847 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/11.prim_present_test.2500438021 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 10372600000 ps |
| CPU time | 35.65 seconds |
| Started | Mar 21 12:24:29 PM PDT 24 |
| Finished | Mar 21 12:25:37 PM PDT 24 |
| Peak memory | 145044 kb |
| Host | smart-d1aaf469-cc8c-4d7e-8164-ed6cdd59fd1f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2500438021 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.2500438021 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.3089750726 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 15475200000 ps |
| CPU time | 56.07 seconds |
| Started | Mar 21 12:24:33 PM PDT 24 |
| Finished | Mar 21 12:26:22 PM PDT 24 |
| Peak memory | 145020 kb |
| Host | smart-fb3951c1-2fe2-4942-998a-063cd6d5697f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3089750726 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.3089750726 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.2156015227 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 15481400000 ps |
| CPU time | 54.15 seconds |
| Started | Mar 21 12:24:33 PM PDT 24 |
| Finished | Mar 21 12:26:16 PM PDT 24 |
| Peak memory | 144980 kb |
| Host | smart-9dbbc976-da79-4928-aa02-760116db123a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2156015227 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.2156015227 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.2865673241 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 9233040000 ps |
| CPU time | 39.21 seconds |
| Started | Mar 21 12:24:31 PM PDT 24 |
| Finished | Mar 21 12:25:45 PM PDT 24 |
| Peak memory | 145120 kb |
| Host | smart-66c07a85-61a0-4e50-81a5-92aaf753045c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2865673241 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.2865673241 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.3653212792 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 10366400000 ps |
| CPU time | 38.28 seconds |
| Started | Mar 21 12:24:20 PM PDT 24 |
| Finished | Mar 21 12:25:37 PM PDT 24 |
| Peak memory | 144996 kb |
| Host | smart-eeb03d45-a49c-40bf-b78f-ac463390d2e0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3653212792 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.3653212792 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.3739654324 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 7483400000 ps |
| CPU time | 26.37 seconds |
| Started | Mar 21 12:24:54 PM PDT 24 |
| Finished | Mar 21 12:25:42 PM PDT 24 |
| Peak memory | 144996 kb |
| Host | smart-7c057bb3-f06a-4584-9491-1d4d44d140ee |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3739654324 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.3739654324 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.3086632383 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 6054920000 ps |
| CPU time | 21.08 seconds |
| Started | Mar 21 12:24:19 PM PDT 24 |
| Finished | Mar 21 12:24:58 PM PDT 24 |
| Peak memory | 144964 kb |
| Host | smart-d3272d93-b41e-4a79-80b0-3d8295001ddc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3086632383 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.3086632383 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.2260067667 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 11428460000 ps |
| CPU time | 44.08 seconds |
| Started | Mar 21 12:24:35 PM PDT 24 |
| Finished | Mar 21 12:26:00 PM PDT 24 |
| Peak memory | 145020 kb |
| Host | smart-661a3609-bf63-49bd-97bb-63a5770f29e1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2260067667 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.2260067667 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.2235517382 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 12322500000 ps |
| CPU time | 48.07 seconds |
| Started | Mar 21 12:24:32 PM PDT 24 |
| Finished | Mar 21 12:26:05 PM PDT 24 |
| Peak memory | 145020 kb |
| Host | smart-07f392f0-6d58-463e-84a7-8947a499007a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2235517382 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.2235517382 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.3389478819 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 5402680000 ps |
| CPU time | 19.52 seconds |
| Started | Mar 21 12:24:31 PM PDT 24 |
| Finished | Mar 21 12:25:09 PM PDT 24 |
| Peak memory | 145040 kb |
| Host | smart-ec0d3f69-476c-4c94-9515-8a4f293178f2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3389478819 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.3389478819 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.3932479531 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 9120200000 ps |
| CPU time | 33.26 seconds |
| Started | Mar 21 12:24:42 PM PDT 24 |
| Finished | Mar 21 12:25:45 PM PDT 24 |
| Peak memory | 144996 kb |
| Host | smart-0a096254-534c-475d-a23a-5b6c7254ea23 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3932479531 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.3932479531 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.1549365428 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 14455300000 ps |
| CPU time | 48.92 seconds |
| Started | Mar 21 12:24:35 PM PDT 24 |
| Finished | Mar 21 12:26:06 PM PDT 24 |
| Peak memory | 145008 kb |
| Host | smart-ef4e25b8-75e9-499b-87b4-c8db786f9003 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1549365428 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.1549365428 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.2866967207 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 5924720000 ps |
| CPU time | 23.2 seconds |
| Started | Mar 21 12:24:32 PM PDT 24 |
| Finished | Mar 21 12:25:16 PM PDT 24 |
| Peak memory | 145044 kb |
| Host | smart-02c8734e-d520-40bc-89d1-f53261250dd9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2866967207 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.2866967207 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.2938074279 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 13714400000 ps |
| CPU time | 45.93 seconds |
| Started | Mar 21 12:24:46 PM PDT 24 |
| Finished | Mar 21 12:26:12 PM PDT 24 |
| Peak memory | 144980 kb |
| Host | smart-13d61777-5177-439a-b7fd-24a6416e6eb1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2938074279 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.2938074279 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.243771695 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 10707400000 ps |
| CPU time | 35.02 seconds |
| Started | Mar 21 12:24:39 PM PDT 24 |
| Finished | Mar 21 12:25:45 PM PDT 24 |
| Peak memory | 143468 kb |
| Host | smart-6aa84511-907e-4e04-b9ee-9125b097e4a4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=243771695 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.243771695 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.239577831 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 15155280000 ps |
| CPU time | 47.89 seconds |
| Started | Mar 21 12:24:34 PM PDT 24 |
| Finished | Mar 21 12:26:01 PM PDT 24 |
| Peak memory | 145036 kb |
| Host | smart-f4d97b51-5b6e-4693-8651-11233618c363 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=239577831 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.239577831 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.2175180078 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 4177560000 ps |
| CPU time | 16.58 seconds |
| Started | Mar 21 12:24:27 PM PDT 24 |
| Finished | Mar 21 12:24:58 PM PDT 24 |
| Peak memory | 144892 kb |
| Host | smart-a594088b-4b09-4ef9-9b6d-6a92c07b06fd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2175180078 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.2175180078 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.2546483151 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 4808100000 ps |
| CPU time | 13.12 seconds |
| Started | Mar 21 12:24:42 PM PDT 24 |
| Finished | Mar 21 12:25:06 PM PDT 24 |
| Peak memory | 145008 kb |
| Host | smart-901d9602-0ba3-4a73-ade8-56d25821abdb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2546483151 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.2546483151 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.3090544616 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 7982500000 ps |
| CPU time | 23.04 seconds |
| Started | Mar 21 12:24:35 PM PDT 24 |
| Finished | Mar 21 12:25:17 PM PDT 24 |
| Peak memory | 145040 kb |
| Host | smart-5755832d-a546-4d47-b204-00d619e7dd4a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3090544616 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.3090544616 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.1838627370 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 15269980000 ps |
| CPU time | 55.3 seconds |
| Started | Mar 21 12:24:30 PM PDT 24 |
| Finished | Mar 21 12:26:15 PM PDT 24 |
| Peak memory | 145148 kb |
| Host | smart-214b2fd5-2881-4784-9ac7-ac289f17182b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1838627370 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.1838627370 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.3946676653 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 5389660000 ps |
| CPU time | 19.33 seconds |
| Started | Mar 21 12:24:17 PM PDT 24 |
| Finished | Mar 21 12:24:54 PM PDT 24 |
| Peak memory | 144868 kb |
| Host | smart-541ee0a4-bf3c-46fa-9b9c-ca351c1bea8d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3946676653 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.3946676653 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.3953727937 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 9782360000 ps |
| CPU time | 30.18 seconds |
| Started | Mar 21 12:24:44 PM PDT 24 |
| Finished | Mar 21 12:25:40 PM PDT 24 |
| Peak memory | 145000 kb |
| Host | smart-999640eb-7b75-4211-b2d3-95dbbda34c0b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3953727937 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.3953727937 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.2282816145 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 3608400000 ps |
| CPU time | 12.48 seconds |
| Started | Mar 21 12:24:41 PM PDT 24 |
| Finished | Mar 21 12:25:04 PM PDT 24 |
| Peak memory | 144596 kb |
| Host | smart-46cb6a93-3b75-4fe8-9c67-92fa5b2d76bd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2282816145 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.2282816145 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.372723034 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 11483640000 ps |
| CPU time | 37.46 seconds |
| Started | Mar 21 12:24:49 PM PDT 24 |
| Finished | Mar 21 12:25:59 PM PDT 24 |
| Peak memory | 145000 kb |
| Host | smart-d51ad195-2e4f-40e3-9c98-c437550e68f2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=372723034 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.372723034 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.4241260223 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 9722840000 ps |
| CPU time | 33.95 seconds |
| Started | Mar 21 12:24:35 PM PDT 24 |
| Finished | Mar 21 12:25:39 PM PDT 24 |
| Peak memory | 145036 kb |
| Host | smart-b1009da8-3d29-4f3d-b031-24b0eeb7f46a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4241260223 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.4241260223 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.381511151 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 8118900000 ps |
| CPU time | 29.25 seconds |
| Started | Mar 21 12:24:45 PM PDT 24 |
| Finished | Mar 21 12:25:40 PM PDT 24 |
| Peak memory | 145012 kb |
| Host | smart-750b8f5f-b906-4779-a15f-0d2997120876 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=381511151 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.381511151 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.2932863187 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 13538320000 ps |
| CPU time | 46.13 seconds |
| Started | Mar 21 12:24:43 PM PDT 24 |
| Finished | Mar 21 12:26:08 PM PDT 24 |
| Peak memory | 145004 kb |
| Host | smart-353b4237-410b-4be7-9055-fddf224d6e30 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2932863187 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.2932863187 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.3822001085 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 8712240000 ps |
| CPU time | 25.85 seconds |
| Started | Mar 21 12:24:44 PM PDT 24 |
| Finished | Mar 21 12:25:33 PM PDT 24 |
| Peak memory | 145008 kb |
| Host | smart-6022e249-00c4-48a0-bc89-7f15c7b7b390 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3822001085 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.3822001085 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.632988269 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 4436100000 ps |
| CPU time | 15.89 seconds |
| Started | Mar 21 12:24:38 PM PDT 24 |
| Finished | Mar 21 12:25:08 PM PDT 24 |
| Peak memory | 145036 kb |
| Host | smart-3d4a4bbd-dde3-4119-997e-aa84201db099 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=632988269 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.632988269 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.3722415953 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 10911380000 ps |
| CPU time | 37.02 seconds |
| Started | Mar 21 12:24:33 PM PDT 24 |
| Finished | Mar 21 12:25:43 PM PDT 24 |
| Peak memory | 145044 kb |
| Host | smart-4ca2b999-f643-41b6-a35f-cc34fc9d145d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3722415953 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.3722415953 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.4149507963 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 4397660000 ps |
| CPU time | 16.06 seconds |
| Started | Mar 21 12:24:43 PM PDT 24 |
| Finished | Mar 21 12:25:14 PM PDT 24 |
| Peak memory | 145004 kb |
| Host | smart-686459e8-29ac-420d-8370-34ca470b151c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4149507963 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.4149507963 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.2658605850 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 13995880000 ps |
| CPU time | 46.15 seconds |
| Started | Mar 21 12:24:39 PM PDT 24 |
| Finished | Mar 21 12:26:05 PM PDT 24 |
| Peak memory | 144904 kb |
| Host | smart-1fde06f7-3898-4593-83b9-c1cb5df5f1a1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2658605850 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.2658605850 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.512332712 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 14173200000 ps |
| CPU time | 52.13 seconds |
| Started | Mar 21 12:24:50 PM PDT 24 |
| Finished | Mar 21 12:26:29 PM PDT 24 |
| Peak memory | 144948 kb |
| Host | smart-b443b615-d550-4a91-85b7-184ba32871a6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=512332712 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.512332712 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.4120023485 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 6877660000 ps |
| CPU time | 23.45 seconds |
| Started | Mar 21 12:24:39 PM PDT 24 |
| Finished | Mar 21 12:25:23 PM PDT 24 |
| Peak memory | 143444 kb |
| Host | smart-ca5943b9-307f-4766-aa12-3c79a08512ca |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4120023485 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.4120023485 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.1272052512 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 14959360000 ps |
| CPU time | 52.47 seconds |
| Started | Mar 21 12:24:39 PM PDT 24 |
| Finished | Mar 21 12:26:18 PM PDT 24 |
| Peak memory | 144996 kb |
| Host | smart-97dccaf1-61b2-440f-ab99-7739d1e3cd1c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1272052512 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.1272052512 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.4248422949 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 3927080000 ps |
| CPU time | 13.18 seconds |
| Started | Mar 21 12:24:34 PM PDT 24 |
| Finished | Mar 21 12:24:59 PM PDT 24 |
| Peak memory | 144896 kb |
| Host | smart-61012d95-9a71-4051-9df3-ba85bfca43ab |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4248422949 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.4248422949 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.3660077417 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 12915840000 ps |
| CPU time | 40.52 seconds |
| Started | Mar 21 12:24:48 PM PDT 24 |
| Finished | Mar 21 12:26:04 PM PDT 24 |
| Peak memory | 145036 kb |
| Host | smart-d192e2a0-2a8f-4b01-8852-81f4fa96b05f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3660077417 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.3660077417 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.2888678632 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 7371800000 ps |
| CPU time | 22.5 seconds |
| Started | Mar 21 12:24:36 PM PDT 24 |
| Finished | Mar 21 12:25:18 PM PDT 24 |
| Peak memory | 145008 kb |
| Host | smart-9dc0001a-2684-4cc2-a3c5-eeeb76867d11 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2888678632 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.2888678632 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.3460621603 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4094480000 ps |
| CPU time | 15.86 seconds |
| Started | Mar 21 12:24:43 PM PDT 24 |
| Finished | Mar 21 12:25:13 PM PDT 24 |
| Peak memory | 144848 kb |
| Host | smart-dbc8dc1d-f585-4939-9772-cc58813bdf08 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3460621603 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.3460621603 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.3295760389 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 6459780000 ps |
| CPU time | 22.8 seconds |
| Started | Mar 21 12:24:40 PM PDT 24 |
| Finished | Mar 21 12:25:22 PM PDT 24 |
| Peak memory | 145008 kb |
| Host | smart-ad677384-b39f-43a2-8bb4-97906020873a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3295760389 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.3295760389 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.4137607652 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 14881240000 ps |
| CPU time | 53.5 seconds |
| Started | Mar 21 12:24:45 PM PDT 24 |
| Finished | Mar 21 12:26:26 PM PDT 24 |
| Peak memory | 145132 kb |
| Host | smart-16b67b78-c839-46d2-ac5d-05cf41a707d8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4137607652 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.4137607652 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.1269864600 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 11628720000 ps |
| CPU time | 38.84 seconds |
| Started | Mar 21 12:24:39 PM PDT 24 |
| Finished | Mar 21 12:25:51 PM PDT 24 |
| Peak memory | 145000 kb |
| Host | smart-d5cea773-d8c2-4878-9a88-0dbb39e5bc56 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1269864600 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.1269864600 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.157910388 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 12801760000 ps |
| CPU time | 51.28 seconds |
| Started | Mar 21 12:24:17 PM PDT 24 |
| Finished | Mar 21 12:25:58 PM PDT 24 |
| Peak memory | 144984 kb |
| Host | smart-993c1f26-a66f-4a0c-814c-7fee42c977b1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=157910388 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.157910388 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.3532964938 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 14796300000 ps |
| CPU time | 53.62 seconds |
| Started | Mar 21 12:24:33 PM PDT 24 |
| Finished | Mar 21 12:26:17 PM PDT 24 |
| Peak memory | 145016 kb |
| Host | smart-b4576aa0-ccc0-4924-812d-9d20c81df02b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3532964938 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.3532964938 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.872669775 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 9720980000 ps |
| CPU time | 38.88 seconds |
| Started | Mar 21 12:24:18 PM PDT 24 |
| Finished | Mar 21 12:25:35 PM PDT 24 |
| Peak memory | 144984 kb |
| Host | smart-24b1f648-626e-4d96-85aa-0787c43a0e1a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=872669775 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.872669775 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.3281830281 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 7669400000 ps |
| CPU time | 27.4 seconds |
| Started | Mar 21 12:24:39 PM PDT 24 |
| Finished | Mar 21 12:25:31 PM PDT 24 |
| Peak memory | 144996 kb |
| Host | smart-d2df1264-8da2-4496-8629-aaa3eeccd524 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3281830281 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.3281830281 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.1305654832 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 5392760000 ps |
| CPU time | 17.29 seconds |
| Started | Mar 21 12:24:20 PM PDT 24 |
| Finished | Mar 21 12:24:52 PM PDT 24 |
| Peak memory | 144996 kb |
| Host | smart-6210bbb3-f167-45fb-b48d-bce4fca6c49b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1305654832 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.1305654832 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |