| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/12.prim_present_test.3636362541 | ||
| Name |
|---|
| /workspace/coverage/default/0.prim_present_test.3737542561 |
| /workspace/coverage/default/1.prim_present_test.2438108055 |
| /workspace/coverage/default/10.prim_present_test.3691281676 |
| /workspace/coverage/default/11.prim_present_test.2947241106 |
| /workspace/coverage/default/13.prim_present_test.1979974526 |
| /workspace/coverage/default/14.prim_present_test.3957044970 |
| /workspace/coverage/default/15.prim_present_test.3660444186 |
| /workspace/coverage/default/16.prim_present_test.961588942 |
| /workspace/coverage/default/17.prim_present_test.3401915523 |
| /workspace/coverage/default/18.prim_present_test.2740976385 |
| /workspace/coverage/default/19.prim_present_test.3286602456 |
| /workspace/coverage/default/2.prim_present_test.2390097643 |
| /workspace/coverage/default/20.prim_present_test.2270804101 |
| /workspace/coverage/default/21.prim_present_test.2591070182 |
| /workspace/coverage/default/22.prim_present_test.3395196439 |
| /workspace/coverage/default/23.prim_present_test.559345927 |
| /workspace/coverage/default/24.prim_present_test.771439401 |
| /workspace/coverage/default/25.prim_present_test.4123820216 |
| /workspace/coverage/default/26.prim_present_test.2847738960 |
| /workspace/coverage/default/27.prim_present_test.1529083008 |
| /workspace/coverage/default/28.prim_present_test.3516618161 |
| /workspace/coverage/default/29.prim_present_test.229414756 |
| /workspace/coverage/default/3.prim_present_test.3351261341 |
| /workspace/coverage/default/30.prim_present_test.2355060649 |
| /workspace/coverage/default/31.prim_present_test.140578579 |
| /workspace/coverage/default/32.prim_present_test.2089785888 |
| /workspace/coverage/default/33.prim_present_test.1765595369 |
| /workspace/coverage/default/34.prim_present_test.1137392170 |
| /workspace/coverage/default/35.prim_present_test.3850743218 |
| /workspace/coverage/default/36.prim_present_test.126147228 |
| /workspace/coverage/default/37.prim_present_test.1224352498 |
| /workspace/coverage/default/38.prim_present_test.2983860885 |
| /workspace/coverage/default/39.prim_present_test.461260837 |
| /workspace/coverage/default/4.prim_present_test.1305541618 |
| /workspace/coverage/default/40.prim_present_test.4016158961 |
| /workspace/coverage/default/41.prim_present_test.1624402666 |
| /workspace/coverage/default/42.prim_present_test.3020135308 |
| /workspace/coverage/default/43.prim_present_test.2844178274 |
| /workspace/coverage/default/44.prim_present_test.2202218613 |
| /workspace/coverage/default/45.prim_present_test.1874145260 |
| /workspace/coverage/default/46.prim_present_test.3542079953 |
| /workspace/coverage/default/47.prim_present_test.1805294210 |
| /workspace/coverage/default/48.prim_present_test.3134145845 |
| /workspace/coverage/default/49.prim_present_test.2818334413 |
| /workspace/coverage/default/5.prim_present_test.2610274203 |
| /workspace/coverage/default/6.prim_present_test.322774550 |
| /workspace/coverage/default/7.prim_present_test.1546203205 |
| /workspace/coverage/default/8.prim_present_test.3715372994 |
| /workspace/coverage/default/9.prim_present_test.4045949254 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/6.prim_present_test.322774550 | Mar 24 12:22:13 PM PDT 24 | Mar 24 12:23:55 PM PDT 24 | 14383380000 ps | ||
| T2 | /workspace/coverage/default/12.prim_present_test.3636362541 | Mar 24 12:16:00 PM PDT 24 | Mar 24 12:17:02 PM PDT 24 | 7165960000 ps | ||
| T3 | /workspace/coverage/default/13.prim_present_test.1979974526 | Mar 24 12:22:12 PM PDT 24 | Mar 24 12:23:18 PM PDT 24 | 10106620000 ps | ||
| T4 | /workspace/coverage/default/21.prim_present_test.2591070182 | Mar 24 12:15:55 PM PDT 24 | Mar 24 12:16:22 PM PDT 24 | 3654280000 ps | ||
| T5 | /workspace/coverage/default/23.prim_present_test.559345927 | Mar 24 12:15:55 PM PDT 24 | Mar 24 12:17:26 PM PDT 24 | 13279160000 ps | ||
| T6 | /workspace/coverage/default/14.prim_present_test.3957044970 | Mar 24 12:15:38 PM PDT 24 | Mar 24 12:16:16 PM PDT 24 | 5379740000 ps | ||
| T7 | /workspace/coverage/default/48.prim_present_test.3134145845 | Mar 24 12:22:12 PM PDT 24 | Mar 24 12:22:39 PM PDT 24 | 3822300000 ps | ||
| T8 | /workspace/coverage/default/5.prim_present_test.2610274203 | Mar 24 12:16:00 PM PDT 24 | Mar 24 12:17:21 PM PDT 24 | 10166140000 ps | ||
| T9 | /workspace/coverage/default/36.prim_present_test.126147228 | Mar 24 12:18:06 PM PDT 24 | Mar 24 12:18:57 PM PDT 24 | 7918640000 ps | ||
| T10 | /workspace/coverage/default/45.prim_present_test.1874145260 | Mar 24 12:20:14 PM PDT 24 | Mar 24 12:21:25 PM PDT 24 | 13004500000 ps | ||
| T11 | /workspace/coverage/default/43.prim_present_test.2844178274 | Mar 24 12:22:42 PM PDT 24 | Mar 24 12:23:36 PM PDT 24 | 8437580000 ps | ||
| T12 | /workspace/coverage/default/4.prim_present_test.1305541618 | Mar 24 12:20:04 PM PDT 24 | Mar 24 12:20:57 PM PDT 24 | 6426300000 ps | ||
| T13 | /workspace/coverage/default/9.prim_present_test.4045949254 | Mar 24 12:19:08 PM PDT 24 | Mar 24 12:19:53 PM PDT 24 | 7358160000 ps | ||
| T14 | /workspace/coverage/default/0.prim_present_test.3737542561 | Mar 24 12:18:04 PM PDT 24 | Mar 24 12:18:37 PM PDT 24 | 4738660000 ps | ||
| T15 | /workspace/coverage/default/10.prim_present_test.3691281676 | Mar 24 12:23:10 PM PDT 24 | Mar 24 12:24:04 PM PDT 24 | 8396040000 ps | ||
| T16 | /workspace/coverage/default/2.prim_present_test.2390097643 | Mar 24 12:23:03 PM PDT 24 | Mar 24 12:24:19 PM PDT 24 | 11948020000 ps | ||
| T17 | /workspace/coverage/default/44.prim_present_test.2202218613 | Mar 24 12:19:39 PM PDT 24 | Mar 24 12:20:56 PM PDT 24 | 12889800000 ps | ||
| T18 | /workspace/coverage/default/22.prim_present_test.3395196439 | Mar 24 12:15:57 PM PDT 24 | Mar 24 12:16:39 PM PDT 24 | 6124980000 ps | ||
| T19 | /workspace/coverage/default/30.prim_present_test.2355060649 | Mar 24 12:20:01 PM PDT 24 | Mar 24 12:21:24 PM PDT 24 | 12288400000 ps | ||
| T20 | /workspace/coverage/default/37.prim_present_test.1224352498 | Mar 24 12:15:41 PM PDT 24 | Mar 24 12:17:11 PM PDT 24 | 11104200000 ps | ||
| T21 | /workspace/coverage/default/27.prim_present_test.1529083008 | Mar 24 12:20:02 PM PDT 24 | Mar 24 12:21:26 PM PDT 24 | 12233840000 ps | ||
| T22 | /workspace/coverage/default/31.prim_present_test.140578579 | Mar 24 12:21:56 PM PDT 24 | Mar 24 12:23:08 PM PDT 24 | 13473840000 ps | ||
| T23 | /workspace/coverage/default/41.prim_present_test.1624402666 | Mar 24 12:20:23 PM PDT 24 | Mar 24 12:21:19 PM PDT 24 | 9406020000 ps | ||
| T24 | /workspace/coverage/default/25.prim_present_test.4123820216 | Mar 24 12:19:01 PM PDT 24 | Mar 24 12:20:37 PM PDT 24 | 12384500000 ps | ||
| T25 | /workspace/coverage/default/32.prim_present_test.2089785888 | Mar 24 12:17:32 PM PDT 24 | Mar 24 12:18:36 PM PDT 24 | 9600700000 ps | ||
| T26 | /workspace/coverage/default/38.prim_present_test.2983860885 | Mar 24 12:15:52 PM PDT 24 | Mar 24 12:16:41 PM PDT 24 | 8837480000 ps | ||
| T27 | /workspace/coverage/default/47.prim_present_test.1805294210 | Mar 24 12:22:52 PM PDT 24 | Mar 24 12:23:51 PM PDT 24 | 9209480000 ps | ||
| T28 | /workspace/coverage/default/8.prim_present_test.3715372994 | Mar 24 12:21:54 PM PDT 24 | Mar 24 12:22:35 PM PDT 24 | 7333360000 ps | ||
| T29 | /workspace/coverage/default/33.prim_present_test.1765595369 | Mar 24 12:20:05 PM PDT 24 | Mar 24 12:20:46 PM PDT 24 | 7771700000 ps | ||
| T30 | /workspace/coverage/default/17.prim_present_test.3401915523 | Mar 24 12:15:41 PM PDT 24 | Mar 24 12:16:31 PM PDT 24 | 5956340000 ps | ||
| T31 | /workspace/coverage/default/28.prim_present_test.3516618161 | Mar 24 12:17:47 PM PDT 24 | Mar 24 12:18:07 PM PDT 24 | 3489980000 ps | ||
| T32 | /workspace/coverage/default/11.prim_present_test.2947241106 | Mar 24 12:15:57 PM PDT 24 | Mar 24 12:16:40 PM PDT 24 | 6226040000 ps | ||
| T33 | /workspace/coverage/default/15.prim_present_test.3660444186 | Mar 24 12:22:27 PM PDT 24 | Mar 24 12:23:27 PM PDT 24 | 10960980000 ps | ||
| T34 | /workspace/coverage/default/26.prim_present_test.2847738960 | Mar 24 12:22:46 PM PDT 24 | Mar 24 12:23:41 PM PDT 24 | 9406640000 ps | ||
| T35 | /workspace/coverage/default/16.prim_present_test.961588942 | Mar 24 12:18:54 PM PDT 24 | Mar 24 12:20:16 PM PDT 24 | 14540240000 ps | ||
| T36 | /workspace/coverage/default/1.prim_present_test.2438108055 | Mar 24 12:15:26 PM PDT 24 | Mar 24 12:16:19 PM PDT 24 | 7217420000 ps | ||
| T37 | /workspace/coverage/default/20.prim_present_test.2270804101 | Mar 24 12:18:04 PM PDT 24 | Mar 24 12:19:31 PM PDT 24 | 12836480000 ps | ||
| T38 | /workspace/coverage/default/7.prim_present_test.1546203205 | Mar 24 12:15:38 PM PDT 24 | Mar 24 12:16:41 PM PDT 24 | 8786020000 ps | ||
| T39 | /workspace/coverage/default/24.prim_present_test.771439401 | Mar 24 12:20:08 PM PDT 24 | Mar 24 12:20:32 PM PDT 24 | 3953740000 ps | ||
| T40 | /workspace/coverage/default/29.prim_present_test.229414756 | Mar 24 12:15:56 PM PDT 24 | Mar 24 12:16:38 PM PDT 24 | 5547760000 ps | ||
| T41 | /workspace/coverage/default/46.prim_present_test.3542079953 | Mar 24 12:19:49 PM PDT 24 | Mar 24 12:20:59 PM PDT 24 | 9943560000 ps | ||
| T42 | /workspace/coverage/default/19.prim_present_test.3286602456 | Mar 24 12:22:12 PM PDT 24 | Mar 24 12:23:39 PM PDT 24 | 12972260000 ps | ||
| T43 | /workspace/coverage/default/3.prim_present_test.3351261341 | Mar 24 12:21:59 PM PDT 24 | Mar 24 12:22:58 PM PDT 24 | 10380660000 ps | ||
| T44 | /workspace/coverage/default/49.prim_present_test.2818334413 | Mar 24 12:20:02 PM PDT 24 | Mar 24 12:20:58 PM PDT 24 | 7946540000 ps | ||
| T45 | /workspace/coverage/default/34.prim_present_test.1137392170 | Mar 24 12:18:04 PM PDT 24 | Mar 24 12:19:39 PM PDT 24 | 14432980000 ps | ||
| T46 | /workspace/coverage/default/35.prim_present_test.3850743218 | Mar 24 12:20:05 PM PDT 24 | Mar 24 12:21:27 PM PDT 24 | 10439560000 ps | ||
| T47 | /workspace/coverage/default/18.prim_present_test.2740976385 | Mar 24 12:15:43 PM PDT 24 | Mar 24 12:16:35 PM PDT 24 | 7796500000 ps | ||
| T48 | /workspace/coverage/default/40.prim_present_test.4016158961 | Mar 24 12:20:43 PM PDT 24 | Mar 24 12:21:07 PM PDT 24 | 4593580000 ps | ||
| T49 | /workspace/coverage/default/39.prim_present_test.461260837 | Mar 24 12:22:12 PM PDT 24 | Mar 24 12:23:34 PM PDT 24 | 12178040000 ps | ||
| T50 | /workspace/coverage/default/42.prim_present_test.3020135308 | Mar 24 12:19:49 PM PDT 24 | Mar 24 12:21:14 PM PDT 24 | 12197880000 ps |
| Test location | /workspace/coverage/default/12.prim_present_test.3636362541 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 7165960000 ps |
| CPU time | 31.9 seconds |
| Started | Mar 24 12:16:00 PM PDT 24 |
| Finished | Mar 24 12:17:02 PM PDT 24 |
| Peak memory | 145320 kb |
| Host | smart-d3975020-9cd7-4d1b-9dd7-04475f05e574 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3636362541 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.3636362541 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/0.prim_present_test.3737542561 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 4738660000 ps |
| CPU time | 17.81 seconds |
| Started | Mar 24 12:18:04 PM PDT 24 |
| Finished | Mar 24 12:18:37 PM PDT 24 |
| Peak memory | 144868 kb |
| Host | smart-eafb6c6e-b3c1-4858-b0da-ee47d28d47f4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3737542561 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.3737542561 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/1.prim_present_test.2438108055 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 7217420000 ps |
| CPU time | 27.73 seconds |
| Started | Mar 24 12:15:26 PM PDT 24 |
| Finished | Mar 24 12:16:19 PM PDT 24 |
| Peak memory | 144972 kb |
| Host | smart-17bbbe09-2791-427f-8487-104007174db4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2438108055 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.2438108055 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/10.prim_present_test.3691281676 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 8396040000 ps |
| CPU time | 28.7 seconds |
| Started | Mar 24 12:23:10 PM PDT 24 |
| Finished | Mar 24 12:24:04 PM PDT 24 |
| Peak memory | 145028 kb |
| Host | smart-4b23c744-fb46-4da5-bedc-ef5732380925 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3691281676 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.3691281676 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/11.prim_present_test.2947241106 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 6226040000 ps |
| CPU time | 23.8 seconds |
| Started | Mar 24 12:15:57 PM PDT 24 |
| Finished | Mar 24 12:16:40 PM PDT 24 |
| Peak memory | 145156 kb |
| Host | smart-90c3b9ca-6c39-49ab-826b-15dd0bade13b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2947241106 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.2947241106 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.1979974526 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 10106620000 ps |
| CPU time | 35.58 seconds |
| Started | Mar 24 12:22:12 PM PDT 24 |
| Finished | Mar 24 12:23:18 PM PDT 24 |
| Peak memory | 144564 kb |
| Host | smart-63b9a2bf-a93a-46eb-a139-cde99b437b24 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1979974526 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.1979974526 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.3957044970 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 5379740000 ps |
| CPU time | 20.42 seconds |
| Started | Mar 24 12:15:38 PM PDT 24 |
| Finished | Mar 24 12:16:16 PM PDT 24 |
| Peak memory | 145308 kb |
| Host | smart-f2f1ca6a-3d27-4451-a927-64969f288f48 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3957044970 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.3957044970 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.3660444186 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 10960980000 ps |
| CPU time | 32.06 seconds |
| Started | Mar 24 12:22:27 PM PDT 24 |
| Finished | Mar 24 12:23:27 PM PDT 24 |
| Peak memory | 145048 kb |
| Host | smart-7c2e7d0f-d973-4f8b-8193-fcfb5be2e484 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3660444186 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.3660444186 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.961588942 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 14540240000 ps |
| CPU time | 45.58 seconds |
| Started | Mar 24 12:18:54 PM PDT 24 |
| Finished | Mar 24 12:20:16 PM PDT 24 |
| Peak memory | 145024 kb |
| Host | smart-69cb3a16-6a64-4750-86eb-ab44f68836ca |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=961588942 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.961588942 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.3401915523 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 5956340000 ps |
| CPU time | 25.8 seconds |
| Started | Mar 24 12:15:41 PM PDT 24 |
| Finished | Mar 24 12:16:31 PM PDT 24 |
| Peak memory | 145320 kb |
| Host | smart-45576dea-ed97-4dee-9777-9c9e9842175f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3401915523 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.3401915523 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.2740976385 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 7796500000 ps |
| CPU time | 27.98 seconds |
| Started | Mar 24 12:15:43 PM PDT 24 |
| Finished | Mar 24 12:16:35 PM PDT 24 |
| Peak memory | 145156 kb |
| Host | smart-67e0daf3-f601-4c11-8158-cc91de8e76f3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2740976385 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.2740976385 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.3286602456 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 12972260000 ps |
| CPU time | 46.19 seconds |
| Started | Mar 24 12:22:12 PM PDT 24 |
| Finished | Mar 24 12:23:39 PM PDT 24 |
| Peak memory | 144736 kb |
| Host | smart-629b4be9-7f5d-450d-a703-ed405a76de75 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3286602456 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.3286602456 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.2390097643 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 11948020000 ps |
| CPU time | 40.54 seconds |
| Started | Mar 24 12:23:03 PM PDT 24 |
| Finished | Mar 24 12:24:19 PM PDT 24 |
| Peak memory | 145052 kb |
| Host | smart-07521b05-bdbd-445a-ba8c-b0a24a589186 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2390097643 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.2390097643 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.2270804101 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 12836480000 ps |
| CPU time | 46.49 seconds |
| Started | Mar 24 12:18:04 PM PDT 24 |
| Finished | Mar 24 12:19:31 PM PDT 24 |
| Peak memory | 144872 kb |
| Host | smart-8d837405-27e4-4bad-83d8-567e5b95d04f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2270804101 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.2270804101 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.2591070182 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 3654280000 ps |
| CPU time | 14.36 seconds |
| Started | Mar 24 12:15:55 PM PDT 24 |
| Finished | Mar 24 12:16:22 PM PDT 24 |
| Peak memory | 145160 kb |
| Host | smart-76128991-4456-4936-bbde-ca8e9daa313f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2591070182 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.2591070182 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.3395196439 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 6124980000 ps |
| CPU time | 22.54 seconds |
| Started | Mar 24 12:15:57 PM PDT 24 |
| Finished | Mar 24 12:16:39 PM PDT 24 |
| Peak memory | 145152 kb |
| Host | smart-fcb7dbf7-78f4-46ec-b69b-f7d2c4aeb2b2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3395196439 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.3395196439 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.559345927 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 13279160000 ps |
| CPU time | 48.82 seconds |
| Started | Mar 24 12:15:55 PM PDT 24 |
| Finished | Mar 24 12:17:26 PM PDT 24 |
| Peak memory | 145308 kb |
| Host | smart-91c9299d-9318-48ce-b93d-f4caf11eb453 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=559345927 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.559345927 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.771439401 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 3953740000 ps |
| CPU time | 12.22 seconds |
| Started | Mar 24 12:20:08 PM PDT 24 |
| Finished | Mar 24 12:20:32 PM PDT 24 |
| Peak memory | 144904 kb |
| Host | smart-fd8bd117-8e9e-4f70-a322-d973c3c3a814 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=771439401 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.771439401 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.4123820216 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 12384500000 ps |
| CPU time | 50 seconds |
| Started | Mar 24 12:19:01 PM PDT 24 |
| Finished | Mar 24 12:20:37 PM PDT 24 |
| Peak memory | 145320 kb |
| Host | smart-72421b05-9e42-44c8-9b99-5dc1536c57ef |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4123820216 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.4123820216 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.2847738960 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 9406640000 ps |
| CPU time | 29.43 seconds |
| Started | Mar 24 12:22:46 PM PDT 24 |
| Finished | Mar 24 12:23:41 PM PDT 24 |
| Peak memory | 145024 kb |
| Host | smart-4b95dcab-06d3-4543-afb3-123996a7660a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2847738960 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.2847738960 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.1529083008 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 12233840000 ps |
| CPU time | 44.26 seconds |
| Started | Mar 24 12:20:02 PM PDT 24 |
| Finished | Mar 24 12:21:26 PM PDT 24 |
| Peak memory | 144452 kb |
| Host | smart-f32da9ba-2905-4775-8c64-bb4cd501911e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1529083008 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.1529083008 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.3516618161 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 3489980000 ps |
| CPU time | 10.51 seconds |
| Started | Mar 24 12:17:47 PM PDT 24 |
| Finished | Mar 24 12:18:07 PM PDT 24 |
| Peak memory | 143640 kb |
| Host | smart-54f698dd-74af-4df9-9b25-d35c6f4da6ce |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3516618161 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.3516618161 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.229414756 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 5547760000 ps |
| CPU time | 21.5 seconds |
| Started | Mar 24 12:15:56 PM PDT 24 |
| Finished | Mar 24 12:16:38 PM PDT 24 |
| Peak memory | 145064 kb |
| Host | smart-de5868d0-69ef-49cc-b0ad-e64cc4492b43 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=229414756 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.229414756 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.3351261341 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 10380660000 ps |
| CPU time | 30.86 seconds |
| Started | Mar 24 12:21:59 PM PDT 24 |
| Finished | Mar 24 12:22:58 PM PDT 24 |
| Peak memory | 143788 kb |
| Host | smart-e1cefadb-334d-4c06-9153-8dfb7ca52961 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3351261341 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.3351261341 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.2355060649 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 12288400000 ps |
| CPU time | 43.39 seconds |
| Started | Mar 24 12:20:01 PM PDT 24 |
| Finished | Mar 24 12:21:24 PM PDT 24 |
| Peak memory | 143880 kb |
| Host | smart-0b89d20e-4af2-40c8-a718-b3899af6ba73 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2355060649 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.2355060649 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.140578579 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 13473840000 ps |
| CPU time | 38.46 seconds |
| Started | Mar 24 12:21:56 PM PDT 24 |
| Finished | Mar 24 12:23:08 PM PDT 24 |
| Peak memory | 143552 kb |
| Host | smart-a4fad6e9-7231-4ffe-9470-0e8a0c0a3afe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=140578579 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.140578579 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.2089785888 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 9600700000 ps |
| CPU time | 33.73 seconds |
| Started | Mar 24 12:17:32 PM PDT 24 |
| Finished | Mar 24 12:18:36 PM PDT 24 |
| Peak memory | 145164 kb |
| Host | smart-c66a9745-66eb-450a-9bee-17ec7698fb78 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2089785888 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.2089785888 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.1765595369 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 7771700000 ps |
| CPU time | 21.88 seconds |
| Started | Mar 24 12:20:05 PM PDT 24 |
| Finished | Mar 24 12:20:46 PM PDT 24 |
| Peak memory | 144512 kb |
| Host | smart-871d5baf-a45a-43cf-8d63-1c00ab886ccc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1765595369 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.1765595369 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.1137392170 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 14432980000 ps |
| CPU time | 50.87 seconds |
| Started | Mar 24 12:18:04 PM PDT 24 |
| Finished | Mar 24 12:19:39 PM PDT 24 |
| Peak memory | 144872 kb |
| Host | smart-4bb2c49e-fd62-453e-be18-0e06bfdf2ed7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1137392170 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.1137392170 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.3850743218 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 10439560000 ps |
| CPU time | 42.79 seconds |
| Started | Mar 24 12:20:05 PM PDT 24 |
| Finished | Mar 24 12:21:27 PM PDT 24 |
| Peak memory | 145320 kb |
| Host | smart-df99f59a-cde5-4100-b933-cb6ea123d290 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3850743218 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.3850743218 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.126147228 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 7918640000 ps |
| CPU time | 27.27 seconds |
| Started | Mar 24 12:18:06 PM PDT 24 |
| Finished | Mar 24 12:18:57 PM PDT 24 |
| Peak memory | 145120 kb |
| Host | smart-1b80ed77-e3b5-4ede-9935-c3c557b08f08 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=126147228 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.126147228 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.1224352498 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 11104200000 ps |
| CPU time | 46.37 seconds |
| Started | Mar 24 12:15:41 PM PDT 24 |
| Finished | Mar 24 12:17:11 PM PDT 24 |
| Peak memory | 145320 kb |
| Host | smart-aaf4c90e-cdf8-4b6b-ad20-a7c49301b37c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1224352498 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.1224352498 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.2983860885 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 8837480000 ps |
| CPU time | 26.31 seconds |
| Started | Mar 24 12:15:52 PM PDT 24 |
| Finished | Mar 24 12:16:41 PM PDT 24 |
| Peak memory | 145400 kb |
| Host | smart-fd86394e-f305-4098-a540-ad1fa33cc588 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2983860885 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.2983860885 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.461260837 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 12178040000 ps |
| CPU time | 44.63 seconds |
| Started | Mar 24 12:22:12 PM PDT 24 |
| Finished | Mar 24 12:23:34 PM PDT 24 |
| Peak memory | 144172 kb |
| Host | smart-9a464af3-b4cc-478c-b66d-b9310779c8f9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=461260837 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.461260837 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.1305541618 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 6426300000 ps |
| CPU time | 27.67 seconds |
| Started | Mar 24 12:20:04 PM PDT 24 |
| Finished | Mar 24 12:20:57 PM PDT 24 |
| Peak memory | 145320 kb |
| Host | smart-0b74f393-db77-441a-b1a3-c8f8e4de72ad |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1305541618 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.1305541618 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.4016158961 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 4593580000 ps |
| CPU time | 12.97 seconds |
| Started | Mar 24 12:20:43 PM PDT 24 |
| Finished | Mar 24 12:21:07 PM PDT 24 |
| Peak memory | 143472 kb |
| Host | smart-1f2e5530-0d0d-4aa5-8c79-8ef6c34ab8f1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4016158961 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.4016158961 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.1624402666 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 9406020000 ps |
| CPU time | 29.96 seconds |
| Started | Mar 24 12:20:23 PM PDT 24 |
| Finished | Mar 24 12:21:19 PM PDT 24 |
| Peak memory | 145020 kb |
| Host | smart-b9b9fa1d-3b07-4fa1-89ac-809d39190a3d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1624402666 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.1624402666 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.3020135308 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 12197880000 ps |
| CPU time | 45.07 seconds |
| Started | Mar 24 12:19:49 PM PDT 24 |
| Finished | Mar 24 12:21:14 PM PDT 24 |
| Peak memory | 144996 kb |
| Host | smart-e9f26896-bbb4-4591-ad95-cc87590cc926 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3020135308 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.3020135308 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.2844178274 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 8437580000 ps |
| CPU time | 26.5 seconds |
| Started | Mar 24 12:22:42 PM PDT 24 |
| Finished | Mar 24 12:23:36 PM PDT 24 |
| Peak memory | 145020 kb |
| Host | smart-59920e88-02bf-417f-aac4-f1c6c6913ffa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2844178274 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.2844178274 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.2202218613 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 12889800000 ps |
| CPU time | 41.93 seconds |
| Started | Mar 24 12:19:39 PM PDT 24 |
| Finished | Mar 24 12:20:56 PM PDT 24 |
| Peak memory | 145036 kb |
| Host | smart-608f6171-5fa1-4f70-8425-949272dd152b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2202218613 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.2202218613 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.1874145260 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 13004500000 ps |
| CPU time | 39.32 seconds |
| Started | Mar 24 12:20:14 PM PDT 24 |
| Finished | Mar 24 12:21:25 PM PDT 24 |
| Peak memory | 145048 kb |
| Host | smart-4cd33c40-0b39-4005-97bc-b1d87bf6c6f5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1874145260 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.1874145260 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.3542079953 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 9943560000 ps |
| CPU time | 37.54 seconds |
| Started | Mar 24 12:19:49 PM PDT 24 |
| Finished | Mar 24 12:20:59 PM PDT 24 |
| Peak memory | 144992 kb |
| Host | smart-7ac67b96-9f56-4cf4-ad1a-a50d0d8bb77f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3542079953 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.3542079953 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.1805294210 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 9209480000 ps |
| CPU time | 31.25 seconds |
| Started | Mar 24 12:22:52 PM PDT 24 |
| Finished | Mar 24 12:23:51 PM PDT 24 |
| Peak memory | 145008 kb |
| Host | smart-ee045e04-fa06-4791-9bd6-bc1318ab11e3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1805294210 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.1805294210 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.3134145845 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 3822300000 ps |
| CPU time | 13.71 seconds |
| Started | Mar 24 12:22:12 PM PDT 24 |
| Finished | Mar 24 12:22:39 PM PDT 24 |
| Peak memory | 144696 kb |
| Host | smart-f2e44a9c-b158-4ff3-816c-6037641de39d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3134145845 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.3134145845 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.2818334413 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 7946540000 ps |
| CPU time | 29.71 seconds |
| Started | Mar 24 12:20:02 PM PDT 24 |
| Finished | Mar 24 12:20:58 PM PDT 24 |
| Peak memory | 144440 kb |
| Host | smart-fa568a05-f65d-40cd-81aa-3dae60424e5c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2818334413 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.2818334413 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.2610274203 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 10166140000 ps |
| CPU time | 41.97 seconds |
| Started | Mar 24 12:16:00 PM PDT 24 |
| Finished | Mar 24 12:17:21 PM PDT 24 |
| Peak memory | 145320 kb |
| Host | smart-0b03079e-6ab1-49e7-afe7-a226e64c6e31 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2610274203 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.2610274203 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.322774550 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 14383380000 ps |
| CPU time | 54.01 seconds |
| Started | Mar 24 12:22:13 PM PDT 24 |
| Finished | Mar 24 12:23:55 PM PDT 24 |
| Peak memory | 144992 kb |
| Host | smart-68499d91-3a9f-4a1a-8721-f6915aac8ce7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=322774550 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.322774550 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.1546203205 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 8786020000 ps |
| CPU time | 33.35 seconds |
| Started | Mar 24 12:15:38 PM PDT 24 |
| Finished | Mar 24 12:16:41 PM PDT 24 |
| Peak memory | 145308 kb |
| Host | smart-aa2e5c0d-7c17-4d71-824f-b19d970effa2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1546203205 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.1546203205 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.3715372994 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 7333360000 ps |
| CPU time | 22.13 seconds |
| Started | Mar 24 12:21:54 PM PDT 24 |
| Finished | Mar 24 12:22:35 PM PDT 24 |
| Peak memory | 145020 kb |
| Host | smart-c714fbe6-f484-4055-a75d-edc954180637 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3715372994 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.3715372994 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.4045949254 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 7358160000 ps |
| CPU time | 24.36 seconds |
| Started | Mar 24 12:19:08 PM PDT 24 |
| Finished | Mar 24 12:19:53 PM PDT 24 |
| Peak memory | 145032 kb |
| Host | smart-47133606-17e2-4067-8be8-d8ea4f584f24 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4045949254 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.4045949254 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |