| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/0.prim_present_test.2798219447 | ||
| Name |
|---|
| /workspace/coverage/default/1.prim_present_test.4226050282 |
| /workspace/coverage/default/10.prim_present_test.1166691454 |
| /workspace/coverage/default/11.prim_present_test.4274623328 |
| /workspace/coverage/default/12.prim_present_test.4075209260 |
| /workspace/coverage/default/13.prim_present_test.255478199 |
| /workspace/coverage/default/14.prim_present_test.4096868145 |
| /workspace/coverage/default/15.prim_present_test.3775525589 |
| /workspace/coverage/default/16.prim_present_test.1107818531 |
| /workspace/coverage/default/17.prim_present_test.1325240414 |
| /workspace/coverage/default/18.prim_present_test.2347023773 |
| /workspace/coverage/default/19.prim_present_test.622630578 |
| /workspace/coverage/default/2.prim_present_test.1116513155 |
| /workspace/coverage/default/20.prim_present_test.480885958 |
| /workspace/coverage/default/21.prim_present_test.858514909 |
| /workspace/coverage/default/22.prim_present_test.3617957837 |
| /workspace/coverage/default/23.prim_present_test.2253355734 |
| /workspace/coverage/default/24.prim_present_test.2920933911 |
| /workspace/coverage/default/25.prim_present_test.3347357454 |
| /workspace/coverage/default/26.prim_present_test.432184815 |
| /workspace/coverage/default/27.prim_present_test.2622394966 |
| /workspace/coverage/default/28.prim_present_test.3164279675 |
| /workspace/coverage/default/29.prim_present_test.4241772171 |
| /workspace/coverage/default/3.prim_present_test.3879124806 |
| /workspace/coverage/default/30.prim_present_test.1477271355 |
| /workspace/coverage/default/31.prim_present_test.1194848019 |
| /workspace/coverage/default/32.prim_present_test.3893220127 |
| /workspace/coverage/default/33.prim_present_test.3686079258 |
| /workspace/coverage/default/34.prim_present_test.115451369 |
| /workspace/coverage/default/35.prim_present_test.3748236875 |
| /workspace/coverage/default/36.prim_present_test.4077533383 |
| /workspace/coverage/default/37.prim_present_test.2328628894 |
| /workspace/coverage/default/38.prim_present_test.1445089680 |
| /workspace/coverage/default/39.prim_present_test.2746998614 |
| /workspace/coverage/default/4.prim_present_test.1296577368 |
| /workspace/coverage/default/40.prim_present_test.2705269285 |
| /workspace/coverage/default/41.prim_present_test.2818583068 |
| /workspace/coverage/default/42.prim_present_test.4111559712 |
| /workspace/coverage/default/43.prim_present_test.3774607852 |
| /workspace/coverage/default/44.prim_present_test.1752689328 |
| /workspace/coverage/default/45.prim_present_test.1563360321 |
| /workspace/coverage/default/46.prim_present_test.706990522 |
| /workspace/coverage/default/47.prim_present_test.259274185 |
| /workspace/coverage/default/48.prim_present_test.2195043921 |
| /workspace/coverage/default/49.prim_present_test.447493986 |
| /workspace/coverage/default/5.prim_present_test.888190356 |
| /workspace/coverage/default/6.prim_present_test.812184851 |
| /workspace/coverage/default/7.prim_present_test.2070421906 |
| /workspace/coverage/default/8.prim_present_test.3324958001 |
| /workspace/coverage/default/9.prim_present_test.1714924959 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/31.prim_present_test.1194848019 | Mar 26 12:20:25 PM PDT 24 | Mar 26 12:21:37 PM PDT 24 | 10377560000 ps | ||
| T2 | /workspace/coverage/default/35.prim_present_test.3748236875 | Mar 26 12:20:47 PM PDT 24 | Mar 26 12:21:51 PM PDT 24 | 8277620000 ps | ||
| T3 | /workspace/coverage/default/0.prim_present_test.2798219447 | Mar 26 12:20:20 PM PDT 24 | Mar 26 12:21:16 PM PDT 24 | 7591900000 ps | ||
| T4 | /workspace/coverage/default/47.prim_present_test.259274185 | Mar 26 12:22:36 PM PDT 24 | Mar 26 12:24:18 PM PDT 24 | 15057320000 ps | ||
| T5 | /workspace/coverage/default/30.prim_present_test.1477271355 | Mar 26 12:22:27 PM PDT 24 | Mar 26 12:23:32 PM PDT 24 | 9383700000 ps | ||
| T6 | /workspace/coverage/default/11.prim_present_test.4274623328 | Mar 26 12:20:19 PM PDT 24 | Mar 26 12:22:00 PM PDT 24 | 14074620000 ps | ||
| T7 | /workspace/coverage/default/12.prim_present_test.4075209260 | Mar 26 12:20:19 PM PDT 24 | Mar 26 12:21:20 PM PDT 24 | 8280720000 ps | ||
| T8 | /workspace/coverage/default/27.prim_present_test.2622394966 | Mar 26 12:20:20 PM PDT 24 | Mar 26 12:21:22 PM PDT 24 | 10742740000 ps | ||
| T9 | /workspace/coverage/default/16.prim_present_test.1107818531 | Mar 26 12:27:07 PM PDT 24 | Mar 26 12:27:47 PM PDT 24 | 8376200000 ps | ||
| T10 | /workspace/coverage/default/48.prim_present_test.2195043921 | Mar 26 12:25:15 PM PDT 24 | Mar 26 12:26:45 PM PDT 24 | 14734920000 ps | ||
| T11 | /workspace/coverage/default/33.prim_present_test.3686079258 | Mar 26 12:26:11 PM PDT 24 | Mar 26 12:27:15 PM PDT 24 | 11701880000 ps | ||
| T12 | /workspace/coverage/default/41.prim_present_test.2818583068 | Mar 26 12:20:30 PM PDT 24 | Mar 26 12:21:11 PM PDT 24 | 5383460000 ps | ||
| T13 | /workspace/coverage/default/10.prim_present_test.1166691454 | Mar 26 12:27:07 PM PDT 24 | Mar 26 12:28:06 PM PDT 24 | 11115980000 ps | ||
| T14 | /workspace/coverage/default/14.prim_present_test.4096868145 | Mar 26 12:21:08 PM PDT 24 | Mar 26 12:22:44 PM PDT 24 | 15080260000 ps | ||
| T15 | /workspace/coverage/default/21.prim_present_test.858514909 | Mar 26 12:20:46 PM PDT 24 | Mar 26 12:21:49 PM PDT 24 | 8000480000 ps | ||
| T16 | /workspace/coverage/default/29.prim_present_test.4241772171 | Mar 26 12:25:07 PM PDT 24 | Mar 26 12:26:19 PM PDT 24 | 11298880000 ps | ||
| T17 | /workspace/coverage/default/7.prim_present_test.2070421906 | Mar 26 12:20:20 PM PDT 24 | Mar 26 12:21:28 PM PDT 24 | 9544280000 ps | ||
| T18 | /workspace/coverage/default/40.prim_present_test.2705269285 | Mar 26 12:20:31 PM PDT 24 | Mar 26 12:21:46 PM PDT 24 | 10055780000 ps | ||
| T19 | /workspace/coverage/default/18.prim_present_test.2347023773 | Mar 26 12:21:48 PM PDT 24 | Mar 26 12:23:33 PM PDT 24 | 15171400000 ps | ||
| T20 | /workspace/coverage/default/23.prim_present_test.2253355734 | Mar 26 12:20:16 PM PDT 24 | Mar 26 12:21:05 PM PDT 24 | 7200680000 ps | ||
| T21 | /workspace/coverage/default/5.prim_present_test.888190356 | Mar 26 12:20:16 PM PDT 24 | Mar 26 12:21:02 PM PDT 24 | 7610500000 ps | ||
| T22 | /workspace/coverage/default/4.prim_present_test.1296577368 | Mar 26 12:20:07 PM PDT 24 | Mar 26 12:20:46 PM PDT 24 | 7165340000 ps | ||
| T23 | /workspace/coverage/default/22.prim_present_test.3617957837 | Mar 26 12:21:38 PM PDT 24 | Mar 26 12:22:41 PM PDT 24 | 8751300000 ps | ||
| T24 | /workspace/coverage/default/19.prim_present_test.622630578 | Mar 26 12:20:30 PM PDT 24 | Mar 26 12:22:00 PM PDT 24 | 12600260000 ps | ||
| T25 | /workspace/coverage/default/1.prim_present_test.4226050282 | Mar 26 12:20:18 PM PDT 24 | Mar 26 12:21:12 PM PDT 24 | 7922360000 ps | ||
| T26 | /workspace/coverage/default/42.prim_present_test.4111559712 | Mar 26 12:25:28 PM PDT 24 | Mar 26 12:26:23 PM PDT 24 | 8218720000 ps | ||
| T27 | /workspace/coverage/default/25.prim_present_test.3347357454 | Mar 26 12:20:28 PM PDT 24 | Mar 26 12:21:01 PM PDT 24 | 4285440000 ps | ||
| T28 | /workspace/coverage/default/45.prim_present_test.1563360321 | Mar 26 12:20:30 PM PDT 24 | Mar 26 12:20:58 PM PDT 24 | 3723720000 ps | ||
| T29 | /workspace/coverage/default/28.prim_present_test.3164279675 | Mar 26 12:21:47 PM PDT 24 | Mar 26 12:23:15 PM PDT 24 | 12446500000 ps | ||
| T30 | /workspace/coverage/default/13.prim_present_test.255478199 | Mar 26 12:20:17 PM PDT 24 | Mar 26 12:20:41 PM PDT 24 | 3581740000 ps | ||
| T31 | /workspace/coverage/default/2.prim_present_test.1116513155 | Mar 26 12:20:17 PM PDT 24 | Mar 26 12:21:35 PM PDT 24 | 11626860000 ps | ||
| T32 | /workspace/coverage/default/20.prim_present_test.480885958 | Mar 26 12:20:32 PM PDT 24 | Mar 26 12:22:09 PM PDT 24 | 14165760000 ps | ||
| T33 | /workspace/coverage/default/38.prim_present_test.1445089680 | Mar 26 12:22:42 PM PDT 24 | Mar 26 12:24:21 PM PDT 24 | 14073380000 ps | ||
| T34 | /workspace/coverage/default/6.prim_present_test.812184851 | Mar 26 12:20:20 PM PDT 24 | Mar 26 12:20:56 PM PDT 24 | 4629540000 ps | ||
| T35 | /workspace/coverage/default/9.prim_present_test.1714924959 | Mar 26 12:20:18 PM PDT 24 | Mar 26 12:21:49 PM PDT 24 | 13467640000 ps | ||
| T36 | /workspace/coverage/default/24.prim_present_test.2920933911 | Mar 26 12:20:30 PM PDT 24 | Mar 26 12:21:34 PM PDT 24 | 8608080000 ps | ||
| T37 | /workspace/coverage/default/49.prim_present_test.447493986 | Mar 26 12:21:34 PM PDT 24 | Mar 26 12:22:36 PM PDT 24 | 9559780000 ps | ||
| T38 | /workspace/coverage/default/39.prim_present_test.2746998614 | Mar 26 12:21:38 PM PDT 24 | Mar 26 12:23:09 PM PDT 24 | 13021240000 ps | ||
| T39 | /workspace/coverage/default/3.prim_present_test.3879124806 | Mar 26 12:20:11 PM PDT 24 | Mar 26 12:21:03 PM PDT 24 | 6867740000 ps | ||
| T40 | /workspace/coverage/default/44.prim_present_test.1752689328 | Mar 26 12:27:06 PM PDT 24 | Mar 26 12:28:07 PM PDT 24 | 11222000000 ps | ||
| T41 | /workspace/coverage/default/36.prim_present_test.4077533383 | Mar 26 12:20:49 PM PDT 24 | Mar 26 12:21:35 PM PDT 24 | 6824340000 ps | ||
| T42 | /workspace/coverage/default/46.prim_present_test.706990522 | Mar 26 12:25:07 PM PDT 24 | Mar 26 12:26:25 PM PDT 24 | 12503540000 ps | ||
| T43 | /workspace/coverage/default/32.prim_present_test.3893220127 | Mar 26 12:22:41 PM PDT 24 | Mar 26 12:24:16 PM PDT 24 | 13524680000 ps | ||
| T44 | /workspace/coverage/default/15.prim_present_test.3775525589 | Mar 26 12:21:47 PM PDT 24 | Mar 26 12:22:44 PM PDT 24 | 7740080000 ps | ||
| T45 | /workspace/coverage/default/34.prim_present_test.115451369 | Mar 26 12:20:30 PM PDT 24 | Mar 26 12:21:49 PM PDT 24 | 10781800000 ps | ||
| T46 | /workspace/coverage/default/26.prim_present_test.432184815 | Mar 26 12:25:17 PM PDT 24 | Mar 26 12:25:48 PM PDT 24 | 4749820000 ps | ||
| T47 | /workspace/coverage/default/17.prim_present_test.1325240414 | Mar 26 12:21:47 PM PDT 24 | Mar 26 12:22:51 PM PDT 24 | 8810820000 ps | ||
| T48 | /workspace/coverage/default/37.prim_present_test.2328628894 | Mar 26 12:26:22 PM PDT 24 | Mar 26 12:26:41 PM PDT 24 | 3266160000 ps | ||
| T49 | /workspace/coverage/default/43.prim_present_test.3774607852 | Mar 26 12:21:38 PM PDT 24 | Mar 26 12:23:10 PM PDT 24 | 13051620000 ps | ||
| T50 | /workspace/coverage/default/8.prim_present_test.3324958001 | Mar 26 12:20:20 PM PDT 24 | Mar 26 12:21:58 PM PDT 24 | 14612780000 ps |
| Test location | /workspace/coverage/default/0.prim_present_test.2798219447 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 7591900000 ps |
| CPU time | 29.8 seconds |
| Started | Mar 26 12:20:20 PM PDT 24 |
| Finished | Mar 26 12:21:16 PM PDT 24 |
| Peak memory | 142748 kb |
| Host | smart-45205bfd-32cc-422f-8f79-4ef2ccefd200 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2798219447 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.2798219447 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/1.prim_present_test.4226050282 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 7922360000 ps |
| CPU time | 28.74 seconds |
| Started | Mar 26 12:20:18 PM PDT 24 |
| Finished | Mar 26 12:21:12 PM PDT 24 |
| Peak memory | 145300 kb |
| Host | smart-f9b9184a-f477-46db-b783-16f4edb6bf6b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4226050282 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.4226050282 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/10.prim_present_test.1166691454 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 11115980000 ps |
| CPU time | 32.4 seconds |
| Started | Mar 26 12:27:07 PM PDT 24 |
| Finished | Mar 26 12:28:06 PM PDT 24 |
| Peak memory | 144504 kb |
| Host | smart-35bf23d9-3ba5-4f79-ab10-cb6a91867e6b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1166691454 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.1166691454 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/11.prim_present_test.4274623328 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 14074620000 ps |
| CPU time | 52 seconds |
| Started | Mar 26 12:20:19 PM PDT 24 |
| Finished | Mar 26 12:22:00 PM PDT 24 |
| Peak memory | 143664 kb |
| Host | smart-934f4a1a-eea3-45ff-830b-41a576bd54f7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4274623328 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.4274623328 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.4075209260 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 8280720000 ps |
| CPU time | 31.54 seconds |
| Started | Mar 26 12:20:19 PM PDT 24 |
| Finished | Mar 26 12:21:20 PM PDT 24 |
| Peak memory | 143820 kb |
| Host | smart-8d93e822-e016-4997-b0b4-f4bbc801bb43 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4075209260 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.4075209260 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.255478199 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 3581740000 ps |
| CPU time | 12.65 seconds |
| Started | Mar 26 12:20:17 PM PDT 24 |
| Finished | Mar 26 12:20:41 PM PDT 24 |
| Peak memory | 144808 kb |
| Host | smart-0fe2c173-5cca-4e8e-9f27-ce9f8dd36a69 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=255478199 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.255478199 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.4096868145 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 15080260000 ps |
| CPU time | 51.51 seconds |
| Started | Mar 26 12:21:08 PM PDT 24 |
| Finished | Mar 26 12:22:44 PM PDT 24 |
| Peak memory | 145044 kb |
| Host | smart-16fe0e30-1678-44e9-9201-56587662fc1f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4096868145 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.4096868145 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.3775525589 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 7740080000 ps |
| CPU time | 28.81 seconds |
| Started | Mar 26 12:21:47 PM PDT 24 |
| Finished | Mar 26 12:22:44 PM PDT 24 |
| Peak memory | 144628 kb |
| Host | smart-54e32d51-e1dc-4b6d-bea7-609840898dd5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3775525589 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.3775525589 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.1107818531 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 8376200000 ps |
| CPU time | 22.72 seconds |
| Started | Mar 26 12:27:07 PM PDT 24 |
| Finished | Mar 26 12:27:47 PM PDT 24 |
| Peak memory | 144872 kb |
| Host | smart-6acc12d7-52a7-4939-ac32-ec036a89c156 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1107818531 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.1107818531 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.1325240414 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 8810820000 ps |
| CPU time | 32.67 seconds |
| Started | Mar 26 12:21:47 PM PDT 24 |
| Finished | Mar 26 12:22:51 PM PDT 24 |
| Peak memory | 144640 kb |
| Host | smart-6707723e-7bda-4eb6-acf5-e06fc7f000d0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1325240414 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.1325240414 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.2347023773 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 15171400000 ps |
| CPU time | 55.27 seconds |
| Started | Mar 26 12:21:48 PM PDT 24 |
| Finished | Mar 26 12:23:33 PM PDT 24 |
| Peak memory | 144664 kb |
| Host | smart-8d0f191d-56a9-4cf0-b404-b2e2d696755f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2347023773 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.2347023773 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.622630578 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 12600260000 ps |
| CPU time | 47.76 seconds |
| Started | Mar 26 12:20:30 PM PDT 24 |
| Finished | Mar 26 12:22:00 PM PDT 24 |
| Peak memory | 145140 kb |
| Host | smart-053c3c3d-976c-455d-9ce0-0f1cda976091 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=622630578 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.622630578 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.1116513155 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 11626860000 ps |
| CPU time | 41.78 seconds |
| Started | Mar 26 12:20:17 PM PDT 24 |
| Finished | Mar 26 12:21:35 PM PDT 24 |
| Peak memory | 145300 kb |
| Host | smart-525ed505-da9f-4d8c-869a-9b0a4788beb9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1116513155 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.1116513155 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.480885958 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 14165760000 ps |
| CPU time | 52.14 seconds |
| Started | Mar 26 12:20:32 PM PDT 24 |
| Finished | Mar 26 12:22:09 PM PDT 24 |
| Peak memory | 144636 kb |
| Host | smart-5f48abc2-321b-467e-a728-8762b3229ac8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=480885958 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.480885958 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.858514909 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 8000480000 ps |
| CPU time | 32.26 seconds |
| Started | Mar 26 12:20:46 PM PDT 24 |
| Finished | Mar 26 12:21:49 PM PDT 24 |
| Peak memory | 144600 kb |
| Host | smart-f840cfb8-642d-445a-8087-822085706879 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=858514909 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.858514909 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.3617957837 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 8751300000 ps |
| CPU time | 31.77 seconds |
| Started | Mar 26 12:21:38 PM PDT 24 |
| Finished | Mar 26 12:22:41 PM PDT 24 |
| Peak memory | 143872 kb |
| Host | smart-fa4962a0-8738-4562-b625-1f8c8ac373a6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3617957837 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.3617957837 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.2253355734 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 7200680000 ps |
| CPU time | 25.42 seconds |
| Started | Mar 26 12:20:16 PM PDT 24 |
| Finished | Mar 26 12:21:05 PM PDT 24 |
| Peak memory | 144612 kb |
| Host | smart-4cd7383b-30ce-4687-a407-babff264975a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2253355734 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.2253355734 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.2920933911 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 8608080000 ps |
| CPU time | 33.33 seconds |
| Started | Mar 26 12:20:30 PM PDT 24 |
| Finished | Mar 26 12:21:34 PM PDT 24 |
| Peak memory | 145140 kb |
| Host | smart-3970ed80-3b0f-43e4-a85a-d967c791d89f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2920933911 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.2920933911 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.3347357454 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 4285440000 ps |
| CPU time | 17.11 seconds |
| Started | Mar 26 12:20:28 PM PDT 24 |
| Finished | Mar 26 12:21:01 PM PDT 24 |
| Peak memory | 144992 kb |
| Host | smart-54cbb416-47d1-4195-a846-b6bd68cd5709 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3347357454 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.3347357454 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.432184815 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 4749820000 ps |
| CPU time | 16.26 seconds |
| Started | Mar 26 12:25:17 PM PDT 24 |
| Finished | Mar 26 12:25:48 PM PDT 24 |
| Peak memory | 145144 kb |
| Host | smart-579f5e73-d44e-4691-89ff-84bc45f1e915 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=432184815 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.432184815 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.2622394966 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 10742740000 ps |
| CPU time | 34.6 seconds |
| Started | Mar 26 12:20:20 PM PDT 24 |
| Finished | Mar 26 12:21:22 PM PDT 24 |
| Peak memory | 145044 kb |
| Host | smart-f3d3ac03-5fc0-4f80-99b7-6a58f510d256 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2622394966 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.2622394966 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.3164279675 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 12446500000 ps |
| CPU time | 45.11 seconds |
| Started | Mar 26 12:21:47 PM PDT 24 |
| Finished | Mar 26 12:23:15 PM PDT 24 |
| Peak memory | 144664 kb |
| Host | smart-5f82d6a0-424f-4d09-a2b8-f82aba045aa5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3164279675 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.3164279675 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.4241772171 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 11298880000 ps |
| CPU time | 38.67 seconds |
| Started | Mar 26 12:25:07 PM PDT 24 |
| Finished | Mar 26 12:26:19 PM PDT 24 |
| Peak memory | 143360 kb |
| Host | smart-cbc47b55-765c-4e0c-91db-9d7ed185acfe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4241772171 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.4241772171 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.3879124806 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 6867740000 ps |
| CPU time | 26.91 seconds |
| Started | Mar 26 12:20:11 PM PDT 24 |
| Finished | Mar 26 12:21:03 PM PDT 24 |
| Peak memory | 144996 kb |
| Host | smart-cf6104eb-e727-4be0-89b1-1a88e88356ce |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3879124806 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.3879124806 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.1477271355 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 9383700000 ps |
| CPU time | 35.13 seconds |
| Started | Mar 26 12:22:27 PM PDT 24 |
| Finished | Mar 26 12:23:32 PM PDT 24 |
| Peak memory | 145092 kb |
| Host | smart-43782b39-efd9-41e3-ae92-5100961712bf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1477271355 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.1477271355 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.1194848019 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 10377560000 ps |
| CPU time | 37.89 seconds |
| Started | Mar 26 12:20:25 PM PDT 24 |
| Finished | Mar 26 12:21:37 PM PDT 24 |
| Peak memory | 144600 kb |
| Host | smart-b0296687-26fa-46d7-9d90-05cd6e8418f0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1194848019 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.1194848019 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.3893220127 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 13524680000 ps |
| CPU time | 50.47 seconds |
| Started | Mar 26 12:22:41 PM PDT 24 |
| Finished | Mar 26 12:24:16 PM PDT 24 |
| Peak memory | 145300 kb |
| Host | smart-21b04f66-653c-4cf5-a1dd-1f2ec8917269 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3893220127 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.3893220127 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.3686079258 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 11701880000 ps |
| CPU time | 34.36 seconds |
| Started | Mar 26 12:26:11 PM PDT 24 |
| Finished | Mar 26 12:27:15 PM PDT 24 |
| Peak memory | 144000 kb |
| Host | smart-9fcd415b-589e-45dc-9eeb-b88e47e830ca |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3686079258 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.3686079258 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.115451369 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 10781800000 ps |
| CPU time | 41.64 seconds |
| Started | Mar 26 12:20:30 PM PDT 24 |
| Finished | Mar 26 12:21:49 PM PDT 24 |
| Peak memory | 145140 kb |
| Host | smart-e2fbbfe4-dde1-430a-b582-5b8a948fb176 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=115451369 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.115451369 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.3748236875 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 8277620000 ps |
| CPU time | 32.86 seconds |
| Started | Mar 26 12:20:47 PM PDT 24 |
| Finished | Mar 26 12:21:51 PM PDT 24 |
| Peak memory | 144596 kb |
| Host | smart-d73ae6b3-77b0-40e5-a85a-b6bd79264110 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3748236875 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.3748236875 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.4077533383 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 6824340000 ps |
| CPU time | 24.49 seconds |
| Started | Mar 26 12:20:49 PM PDT 24 |
| Finished | Mar 26 12:21:35 PM PDT 24 |
| Peak memory | 144640 kb |
| Host | smart-13c90f86-3bf3-4d8f-bdef-d79d373d04ee |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4077533383 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.4077533383 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.2328628894 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 3266160000 ps |
| CPU time | 10.22 seconds |
| Started | Mar 26 12:26:22 PM PDT 24 |
| Finished | Mar 26 12:26:41 PM PDT 24 |
| Peak memory | 144704 kb |
| Host | smart-d64ab1f8-333e-49e6-8f12-1cb2765c6b14 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2328628894 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.2328628894 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.1445089680 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 14073380000 ps |
| CPU time | 52.23 seconds |
| Started | Mar 26 12:22:42 PM PDT 24 |
| Finished | Mar 26 12:24:21 PM PDT 24 |
| Peak memory | 145300 kb |
| Host | smart-59fec33a-f8c0-464f-93f4-698dd8a8e6ac |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1445089680 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.1445089680 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.2746998614 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 13021240000 ps |
| CPU time | 46.85 seconds |
| Started | Mar 26 12:21:38 PM PDT 24 |
| Finished | Mar 26 12:23:09 PM PDT 24 |
| Peak memory | 143080 kb |
| Host | smart-c93a20a7-e57b-4e4c-a446-3ac43fb15b26 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2746998614 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.2746998614 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.1296577368 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 7165340000 ps |
| CPU time | 21.44 seconds |
| Started | Mar 26 12:20:07 PM PDT 24 |
| Finished | Mar 26 12:20:46 PM PDT 24 |
| Peak memory | 145372 kb |
| Host | smart-26e1b2f7-6a5f-4e1f-ae53-98747519adec |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1296577368 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.1296577368 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.2705269285 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 10055780000 ps |
| CPU time | 38.62 seconds |
| Started | Mar 26 12:20:31 PM PDT 24 |
| Finished | Mar 26 12:21:46 PM PDT 24 |
| Peak memory | 144604 kb |
| Host | smart-922c0acf-15e7-4514-936c-66f7a48f3a4f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2705269285 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.2705269285 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.2818583068 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 5383460000 ps |
| CPU time | 21.02 seconds |
| Started | Mar 26 12:20:30 PM PDT 24 |
| Finished | Mar 26 12:21:11 PM PDT 24 |
| Peak memory | 145140 kb |
| Host | smart-3fb375a0-7f3c-49f7-a39b-d1880041158c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2818583068 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.2818583068 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.4111559712 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 8218720000 ps |
| CPU time | 28.92 seconds |
| Started | Mar 26 12:25:28 PM PDT 24 |
| Finished | Mar 26 12:26:23 PM PDT 24 |
| Peak memory | 143908 kb |
| Host | smart-d82846a9-9b6c-4402-8aec-cc0fd2b0b440 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4111559712 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.4111559712 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.3774607852 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 13051620000 ps |
| CPU time | 47.35 seconds |
| Started | Mar 26 12:21:38 PM PDT 24 |
| Finished | Mar 26 12:23:10 PM PDT 24 |
| Peak memory | 142816 kb |
| Host | smart-8418ae75-f22e-47bc-b811-179c3d64929d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3774607852 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.3774607852 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.1752689328 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 11222000000 ps |
| CPU time | 32.61 seconds |
| Started | Mar 26 12:27:06 PM PDT 24 |
| Finished | Mar 26 12:28:07 PM PDT 24 |
| Peak memory | 143764 kb |
| Host | smart-68b89ac9-3213-452c-b8ec-a988a7e05e1d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1752689328 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.1752689328 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.1563360321 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 3723720000 ps |
| CPU time | 14.89 seconds |
| Started | Mar 26 12:20:30 PM PDT 24 |
| Finished | Mar 26 12:20:58 PM PDT 24 |
| Peak memory | 144992 kb |
| Host | smart-45427850-6613-4769-8c4d-363d8e79e2d7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1563360321 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.1563360321 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.706990522 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 12503540000 ps |
| CPU time | 41.57 seconds |
| Started | Mar 26 12:25:07 PM PDT 24 |
| Finished | Mar 26 12:26:25 PM PDT 24 |
| Peak memory | 143376 kb |
| Host | smart-d2d760d9-66ba-4e3f-a0c0-6890fe828d18 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=706990522 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.706990522 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.259274185 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 15057320000 ps |
| CPU time | 54.89 seconds |
| Started | Mar 26 12:22:36 PM PDT 24 |
| Finished | Mar 26 12:24:18 PM PDT 24 |
| Peak memory | 145088 kb |
| Host | smart-c02794a4-b2d3-4a1f-bbfa-98b28a6bc726 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=259274185 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.259274185 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.2195043921 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 14734920000 ps |
| CPU time | 48.21 seconds |
| Started | Mar 26 12:25:15 PM PDT 24 |
| Finished | Mar 26 12:26:45 PM PDT 24 |
| Peak memory | 144628 kb |
| Host | smart-a145e520-aa79-4e60-8fdf-1abead17ecec |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2195043921 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.2195043921 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.447493986 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 9559780000 ps |
| CPU time | 33.07 seconds |
| Started | Mar 26 12:21:34 PM PDT 24 |
| Finished | Mar 26 12:22:36 PM PDT 24 |
| Peak memory | 144832 kb |
| Host | smart-a3b967e7-ca97-4ff7-98a8-d17e1017a359 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=447493986 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.447493986 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.888190356 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 7610500000 ps |
| CPU time | 24.9 seconds |
| Started | Mar 26 12:20:16 PM PDT 24 |
| Finished | Mar 26 12:21:02 PM PDT 24 |
| Peak memory | 143892 kb |
| Host | smart-4d977cfd-a793-4da8-afee-eec8e693fb07 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=888190356 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.888190356 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.812184851 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 4629540000 ps |
| CPU time | 19.2 seconds |
| Started | Mar 26 12:20:20 PM PDT 24 |
| Finished | Mar 26 12:20:56 PM PDT 24 |
| Peak memory | 142628 kb |
| Host | smart-d17fcfcd-ff24-4951-bdd6-4eb9b4da88b1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=812184851 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.812184851 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.2070421906 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 9544280000 ps |
| CPU time | 36.21 seconds |
| Started | Mar 26 12:20:20 PM PDT 24 |
| Finished | Mar 26 12:21:28 PM PDT 24 |
| Peak memory | 143096 kb |
| Host | smart-20348640-9bcc-48c4-bd09-b1e0f8dcde98 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2070421906 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.2070421906 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.3324958001 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 14612780000 ps |
| CPU time | 52.58 seconds |
| Started | Mar 26 12:20:20 PM PDT 24 |
| Finished | Mar 26 12:21:58 PM PDT 24 |
| Peak memory | 142940 kb |
| Host | smart-d085b0f4-045f-4847-a9f9-79c3f378a19f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3324958001 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.3324958001 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.1714924959 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 13467640000 ps |
| CPU time | 48.21 seconds |
| Started | Mar 26 12:20:18 PM PDT 24 |
| Finished | Mar 26 12:21:49 PM PDT 24 |
| Peak memory | 145212 kb |
| Host | smart-3099a72d-ea9a-42c9-bbc4-e2d8733a79cf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1714924959 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.1714924959 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |