| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/0.prim_present_test.2597816142 | ||
| Name |
|---|
| /workspace/coverage/default/1.prim_present_test.4291544043 |
| /workspace/coverage/default/10.prim_present_test.3210030345 |
| /workspace/coverage/default/11.prim_present_test.1517188438 |
| /workspace/coverage/default/12.prim_present_test.8623242 |
| /workspace/coverage/default/13.prim_present_test.3568566796 |
| /workspace/coverage/default/14.prim_present_test.1513140681 |
| /workspace/coverage/default/15.prim_present_test.406151857 |
| /workspace/coverage/default/16.prim_present_test.2582858544 |
| /workspace/coverage/default/17.prim_present_test.1730535505 |
| /workspace/coverage/default/18.prim_present_test.3308831389 |
| /workspace/coverage/default/19.prim_present_test.1429186258 |
| /workspace/coverage/default/2.prim_present_test.1939282202 |
| /workspace/coverage/default/20.prim_present_test.3792122069 |
| /workspace/coverage/default/21.prim_present_test.457408971 |
| /workspace/coverage/default/22.prim_present_test.4182270990 |
| /workspace/coverage/default/23.prim_present_test.1656442550 |
| /workspace/coverage/default/24.prim_present_test.2484805742 |
| /workspace/coverage/default/25.prim_present_test.2642192125 |
| /workspace/coverage/default/26.prim_present_test.2951100467 |
| /workspace/coverage/default/27.prim_present_test.1730177050 |
| /workspace/coverage/default/28.prim_present_test.245774745 |
| /workspace/coverage/default/29.prim_present_test.2010385644 |
| /workspace/coverage/default/3.prim_present_test.996400198 |
| /workspace/coverage/default/30.prim_present_test.2996749655 |
| /workspace/coverage/default/31.prim_present_test.4037385996 |
| /workspace/coverage/default/32.prim_present_test.3679844181 |
| /workspace/coverage/default/33.prim_present_test.3225375344 |
| /workspace/coverage/default/34.prim_present_test.3228317168 |
| /workspace/coverage/default/35.prim_present_test.2895533000 |
| /workspace/coverage/default/36.prim_present_test.1839761666 |
| /workspace/coverage/default/37.prim_present_test.2548811024 |
| /workspace/coverage/default/38.prim_present_test.3769421232 |
| /workspace/coverage/default/39.prim_present_test.2323171253 |
| /workspace/coverage/default/4.prim_present_test.3748185637 |
| /workspace/coverage/default/40.prim_present_test.2431751682 |
| /workspace/coverage/default/41.prim_present_test.2973572957 |
| /workspace/coverage/default/42.prim_present_test.273556179 |
| /workspace/coverage/default/43.prim_present_test.176978928 |
| /workspace/coverage/default/44.prim_present_test.3554274547 |
| /workspace/coverage/default/45.prim_present_test.3036278724 |
| /workspace/coverage/default/46.prim_present_test.3611042629 |
| /workspace/coverage/default/47.prim_present_test.625686281 |
| /workspace/coverage/default/48.prim_present_test.2813741090 |
| /workspace/coverage/default/49.prim_present_test.935878069 |
| /workspace/coverage/default/5.prim_present_test.2172005087 |
| /workspace/coverage/default/6.prim_present_test.4132836320 |
| /workspace/coverage/default/7.prim_present_test.323146546 |
| /workspace/coverage/default/8.prim_present_test.455106885 |
| /workspace/coverage/default/9.prim_present_test.4028289565 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/19.prim_present_test.1429186258 | Mar 28 12:29:28 PM PDT 24 | Mar 28 12:30:39 PM PDT 24 | 11072580000 ps | ||
| T2 | /workspace/coverage/default/38.prim_present_test.3769421232 | Mar 28 12:29:25 PM PDT 24 | Mar 28 12:30:45 PM PDT 24 | 12410540000 ps | ||
| T3 | /workspace/coverage/default/15.prim_present_test.406151857 | Mar 28 12:28:59 PM PDT 24 | Mar 28 12:29:34 PM PDT 24 | 5734380000 ps | ||
| T4 | /workspace/coverage/default/23.prim_present_test.1656442550 | Mar 28 12:29:10 PM PDT 24 | Mar 28 12:30:26 PM PDT 24 | 13823520000 ps | ||
| T5 | /workspace/coverage/default/42.prim_present_test.273556179 | Mar 28 12:29:15 PM PDT 24 | Mar 28 12:29:39 PM PDT 24 | 3821680000 ps | ||
| T6 | /workspace/coverage/default/33.prim_present_test.3225375344 | Mar 28 12:28:51 PM PDT 24 | Mar 28 12:30:13 PM PDT 24 | 13966740000 ps | ||
| T7 | /workspace/coverage/default/0.prim_present_test.2597816142 | Mar 28 12:29:10 PM PDT 24 | Mar 28 12:30:14 PM PDT 24 | 8490900000 ps | ||
| T8 | /workspace/coverage/default/31.prim_present_test.4037385996 | Mar 28 12:29:27 PM PDT 24 | Mar 28 12:30:55 PM PDT 24 | 14029980000 ps | ||
| T9 | /workspace/coverage/default/11.prim_present_test.1517188438 | Mar 28 12:28:57 PM PDT 24 | Mar 28 12:29:19 PM PDT 24 | 3560040000 ps | ||
| T10 | /workspace/coverage/default/32.prim_present_test.3679844181 | Mar 28 12:29:01 PM PDT 24 | Mar 28 12:29:49 PM PDT 24 | 8004200000 ps | ||
| T11 | /workspace/coverage/default/14.prim_present_test.1513140681 | Mar 28 12:29:19 PM PDT 24 | Mar 28 12:29:51 PM PDT 24 | 5648820000 ps | ||
| T12 | /workspace/coverage/default/1.prim_present_test.4291544043 | Mar 28 12:29:13 PM PDT 24 | Mar 28 12:30:00 PM PDT 24 | 7605540000 ps | ||
| T13 | /workspace/coverage/default/3.prim_present_test.996400198 | Mar 28 12:29:17 PM PDT 24 | Mar 28 12:30:29 PM PDT 24 | 11404900000 ps | ||
| T14 | /workspace/coverage/default/26.prim_present_test.2951100467 | Mar 28 12:29:31 PM PDT 24 | Mar 28 12:30:03 PM PDT 24 | 5366720000 ps | ||
| T15 | /workspace/coverage/default/46.prim_present_test.3611042629 | Mar 28 12:28:55 PM PDT 24 | Mar 28 12:29:30 PM PDT 24 | 4527860000 ps | ||
| T16 | /workspace/coverage/default/12.prim_present_test.8623242 | Mar 28 12:28:58 PM PDT 24 | Mar 28 12:29:55 PM PDT 24 | 9085480000 ps | ||
| T17 | /workspace/coverage/default/30.prim_present_test.2996749655 | Mar 28 12:29:23 PM PDT 24 | Mar 28 12:29:46 PM PDT 24 | 3299640000 ps | ||
| T18 | /workspace/coverage/default/7.prim_present_test.323146546 | Mar 28 12:29:00 PM PDT 24 | Mar 28 12:29:40 PM PDT 24 | 6505040000 ps | ||
| T19 | /workspace/coverage/default/8.prim_present_test.455106885 | Mar 28 12:28:57 PM PDT 24 | Mar 28 12:29:52 PM PDT 24 | 9732760000 ps | ||
| T20 | /workspace/coverage/default/35.prim_present_test.2895533000 | Mar 28 12:28:57 PM PDT 24 | Mar 28 12:29:45 PM PDT 24 | 6292380000 ps | ||
| T21 | /workspace/coverage/default/39.prim_present_test.2323171253 | Mar 28 12:29:19 PM PDT 24 | Mar 28 12:29:55 PM PDT 24 | 4772140000 ps | ||
| T22 | /workspace/coverage/default/10.prim_present_test.3210030345 | Mar 28 12:29:11 PM PDT 24 | Mar 28 12:29:43 PM PDT 24 | 4972400000 ps | ||
| T23 | /workspace/coverage/default/5.prim_present_test.2172005087 | Mar 28 12:29:08 PM PDT 24 | Mar 28 12:29:36 PM PDT 24 | 4804380000 ps | ||
| T24 | /workspace/coverage/default/44.prim_present_test.3554274547 | Mar 28 12:29:27 PM PDT 24 | Mar 28 12:30:04 PM PDT 24 | 4569400000 ps | ||
| T25 | /workspace/coverage/default/27.prim_present_test.1730177050 | Mar 28 12:28:54 PM PDT 24 | Mar 28 12:30:20 PM PDT 24 | 12439060000 ps | ||
| T26 | /workspace/coverage/default/40.prim_present_test.2431751682 | Mar 28 12:28:57 PM PDT 24 | Mar 28 12:30:01 PM PDT 24 | 9512660000 ps | ||
| T27 | /workspace/coverage/default/9.prim_present_test.4028289565 | Mar 28 12:28:58 PM PDT 24 | Mar 28 12:29:52 PM PDT 24 | 9091680000 ps | ||
| T28 | /workspace/coverage/default/21.prim_present_test.457408971 | Mar 28 12:29:15 PM PDT 24 | Mar 28 12:29:33 PM PDT 24 | 3254380000 ps | ||
| T29 | /workspace/coverage/default/28.prim_present_test.245774745 | Mar 28 12:29:17 PM PDT 24 | Mar 28 12:29:38 PM PDT 24 | 3290960000 ps | ||
| T30 | /workspace/coverage/default/34.prim_present_test.3228317168 | Mar 28 12:28:58 PM PDT 24 | Mar 28 12:29:54 PM PDT 24 | 9628600000 ps | ||
| T31 | /workspace/coverage/default/47.prim_present_test.625686281 | Mar 28 12:29:23 PM PDT 24 | Mar 28 12:29:49 PM PDT 24 | 3979160000 ps | ||
| T32 | /workspace/coverage/default/49.prim_present_test.935878069 | Mar 28 12:29:19 PM PDT 24 | Mar 28 12:30:18 PM PDT 24 | 7703500000 ps | ||
| T33 | /workspace/coverage/default/13.prim_present_test.3568566796 | Mar 28 12:28:58 PM PDT 24 | Mar 28 12:30:00 PM PDT 24 | 9892720000 ps | ||
| T34 | /workspace/coverage/default/29.prim_present_test.2010385644 | Mar 28 12:29:21 PM PDT 24 | Mar 28 12:30:24 PM PDT 24 | 10088640000 ps | ||
| T35 | /workspace/coverage/default/2.prim_present_test.1939282202 | Mar 28 12:29:04 PM PDT 24 | Mar 28 12:29:28 PM PDT 24 | 4185620000 ps | ||
| T36 | /workspace/coverage/default/41.prim_present_test.2973572957 | Mar 28 12:29:18 PM PDT 24 | Mar 28 12:30:24 PM PDT 24 | 9800960000 ps | ||
| T37 | /workspace/coverage/default/37.prim_present_test.2548811024 | Mar 28 12:28:52 PM PDT 24 | Mar 28 12:30:12 PM PDT 24 | 10509620000 ps | ||
| T38 | /workspace/coverage/default/22.prim_present_test.4182270990 | Mar 28 12:28:54 PM PDT 24 | Mar 28 12:30:22 PM PDT 24 | 15000280000 ps | ||
| T39 | /workspace/coverage/default/25.prim_present_test.2642192125 | Mar 28 12:28:59 PM PDT 24 | Mar 28 12:30:02 PM PDT 24 | 10782420000 ps | ||
| T40 | /workspace/coverage/default/43.prim_present_test.176978928 | Mar 28 12:28:54 PM PDT 24 | Mar 28 12:29:58 PM PDT 24 | 10495980000 ps | ||
| T41 | /workspace/coverage/default/24.prim_present_test.2484805742 | Mar 28 12:28:55 PM PDT 24 | Mar 28 12:30:14 PM PDT 24 | 11088080000 ps | ||
| T42 | /workspace/coverage/default/6.prim_present_test.4132836320 | Mar 28 12:29:31 PM PDT 24 | Mar 28 12:30:51 PM PDT 24 | 13791900000 ps | ||
| T43 | /workspace/coverage/default/4.prim_present_test.3748185637 | Mar 28 12:28:59 PM PDT 24 | Mar 28 12:30:01 PM PDT 24 | 10092360000 ps | ||
| T44 | /workspace/coverage/default/17.prim_present_test.1730535505 | Mar 28 12:28:56 PM PDT 24 | Mar 28 12:30:12 PM PDT 24 | 11250520000 ps | ||
| T45 | /workspace/coverage/default/36.prim_present_test.1839761666 | Mar 28 12:28:57 PM PDT 24 | Mar 28 12:30:16 PM PDT 24 | 11990800000 ps | ||
| T46 | /workspace/coverage/default/45.prim_present_test.3036278724 | Mar 28 12:28:57 PM PDT 24 | Mar 28 12:29:38 PM PDT 24 | 5561400000 ps | ||
| T47 | /workspace/coverage/default/16.prim_present_test.2582858544 | Mar 28 12:29:27 PM PDT 24 | Mar 28 12:29:59 PM PDT 24 | 4782680000 ps | ||
| T48 | /workspace/coverage/default/20.prim_present_test.3792122069 | Mar 28 12:28:56 PM PDT 24 | Mar 28 12:29:19 PM PDT 24 | 4232740000 ps | ||
| T49 | /workspace/coverage/default/48.prim_present_test.2813741090 | Mar 28 12:28:55 PM PDT 24 | Mar 28 12:30:26 PM PDT 24 | 14090120000 ps | ||
| T50 | /workspace/coverage/default/18.prim_present_test.3308831389 | Mar 28 12:28:56 PM PDT 24 | Mar 28 12:29:52 PM PDT 24 | 9164840000 ps |
| Test location | /workspace/coverage/default/0.prim_present_test.2597816142 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 8490900000 ps |
| CPU time | 32.82 seconds |
| Started | Mar 28 12:29:10 PM PDT 24 |
| Finished | Mar 28 12:30:14 PM PDT 24 |
| Peak memory | 144056 kb |
| Host | smart-f9b1619d-9e38-4cc3-8c66-eb309c07fa7d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2597816142 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.2597816142 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/1.prim_present_test.4291544043 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 7605540000 ps |
| CPU time | 24.96 seconds |
| Started | Mar 28 12:29:13 PM PDT 24 |
| Finished | Mar 28 12:30:00 PM PDT 24 |
| Peak memory | 145148 kb |
| Host | smart-2bb70189-31b0-48fb-bc84-6854d7e487a9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4291544043 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.4291544043 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/10.prim_present_test.3210030345 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 4972400000 ps |
| CPU time | 17.09 seconds |
| Started | Mar 28 12:29:11 PM PDT 24 |
| Finished | Mar 28 12:29:43 PM PDT 24 |
| Peak memory | 145040 kb |
| Host | smart-f10613a5-fd15-4b31-8228-2071c9656a32 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3210030345 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.3210030345 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/11.prim_present_test.1517188438 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 3560040000 ps |
| CPU time | 11.44 seconds |
| Started | Mar 28 12:28:57 PM PDT 24 |
| Finished | Mar 28 12:29:19 PM PDT 24 |
| Peak memory | 143676 kb |
| Host | smart-fab5ccb8-c96d-4d33-878c-5c2ce918f69e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1517188438 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.1517188438 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.8623242 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 9085480000 ps |
| CPU time | 30.69 seconds |
| Started | Mar 28 12:28:58 PM PDT 24 |
| Finished | Mar 28 12:29:55 PM PDT 24 |
| Peak memory | 144172 kb |
| Host | smart-4a7523f7-2aab-456d-bb97-5a04bdd1235f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=8623242 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.8623242 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.3568566796 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 9892720000 ps |
| CPU time | 33.06 seconds |
| Started | Mar 28 12:28:58 PM PDT 24 |
| Finished | Mar 28 12:30:00 PM PDT 24 |
| Peak memory | 144644 kb |
| Host | smart-2277e332-fb67-46e8-8ba4-0fe5ce6c6311 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3568566796 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.3568566796 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.1513140681 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 5648820000 ps |
| CPU time | 17.52 seconds |
| Started | Mar 28 12:29:19 PM PDT 24 |
| Finished | Mar 28 12:29:51 PM PDT 24 |
| Peak memory | 144888 kb |
| Host | smart-3db0e240-ce3c-4645-9a2f-1efff34d6fb8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1513140681 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.1513140681 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.406151857 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 5734380000 ps |
| CPU time | 18.81 seconds |
| Started | Mar 28 12:28:59 PM PDT 24 |
| Finished | Mar 28 12:29:34 PM PDT 24 |
| Peak memory | 144644 kb |
| Host | smart-dcff51a9-6904-4a24-a903-2dde72f3338a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=406151857 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.406151857 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.2582858544 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 4782680000 ps |
| CPU time | 16.57 seconds |
| Started | Mar 28 12:29:27 PM PDT 24 |
| Finished | Mar 28 12:29:59 PM PDT 24 |
| Peak memory | 143580 kb |
| Host | smart-d2fe7862-7e53-44a9-9f00-9de8585f0c71 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2582858544 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.2582858544 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.1730535505 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 11250520000 ps |
| CPU time | 39.93 seconds |
| Started | Mar 28 12:28:56 PM PDT 24 |
| Finished | Mar 28 12:30:12 PM PDT 24 |
| Peak memory | 143980 kb |
| Host | smart-3f91215f-4e46-4870-b6ef-2d85bb30f811 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1730535505 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.1730535505 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.3308831389 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 9164840000 ps |
| CPU time | 29.26 seconds |
| Started | Mar 28 12:28:56 PM PDT 24 |
| Finished | Mar 28 12:29:52 PM PDT 24 |
| Peak memory | 144628 kb |
| Host | smart-ee4561dc-1d3b-4e47-8065-cf159bc229ad |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3308831389 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.3308831389 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.1429186258 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 11072580000 ps |
| CPU time | 37.45 seconds |
| Started | Mar 28 12:29:28 PM PDT 24 |
| Finished | Mar 28 12:30:39 PM PDT 24 |
| Peak memory | 144028 kb |
| Host | smart-d591f74e-e49f-401e-925f-688c2e1a5e50 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1429186258 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.1429186258 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.1939282202 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 4185620000 ps |
| CPU time | 12.71 seconds |
| Started | Mar 28 12:29:04 PM PDT 24 |
| Finished | Mar 28 12:29:28 PM PDT 24 |
| Peak memory | 144488 kb |
| Host | smart-e64f8bfa-7008-405f-a484-593fbfd55b3a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1939282202 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.1939282202 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.3792122069 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 4232740000 ps |
| CPU time | 12.34 seconds |
| Started | Mar 28 12:28:56 PM PDT 24 |
| Finished | Mar 28 12:29:19 PM PDT 24 |
| Peak memory | 144868 kb |
| Host | smart-ea3130ba-daff-4ffd-9e10-1bffa6dc63c3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3792122069 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.3792122069 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.457408971 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 3254380000 ps |
| CPU time | 9.56 seconds |
| Started | Mar 28 12:29:15 PM PDT 24 |
| Finished | Mar 28 12:29:33 PM PDT 24 |
| Peak memory | 144868 kb |
| Host | smart-ace61719-fcb7-4cf0-8b70-842e325061e7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=457408971 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.457408971 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.4182270990 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 15000280000 ps |
| CPU time | 46.94 seconds |
| Started | Mar 28 12:28:54 PM PDT 24 |
| Finished | Mar 28 12:30:22 PM PDT 24 |
| Peak memory | 144028 kb |
| Host | smart-a1521395-4df2-44a9-9107-c9e91bcc9cac |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4182270990 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.4182270990 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.1656442550 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 13823520000 ps |
| CPU time | 40.71 seconds |
| Started | Mar 28 12:29:10 PM PDT 24 |
| Finished | Mar 28 12:30:26 PM PDT 24 |
| Peak memory | 144024 kb |
| Host | smart-88db8c9d-4e2e-400f-b709-7e6a6c00a603 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1656442550 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.1656442550 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.2484805742 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 11088080000 ps |
| CPU time | 41.87 seconds |
| Started | Mar 28 12:28:55 PM PDT 24 |
| Finished | Mar 28 12:30:14 PM PDT 24 |
| Peak memory | 144584 kb |
| Host | smart-31597c57-8458-4d5a-bcd5-544a42a32685 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2484805742 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.2484805742 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.2642192125 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 10782420000 ps |
| CPU time | 32.96 seconds |
| Started | Mar 28 12:28:59 PM PDT 24 |
| Finished | Mar 28 12:30:02 PM PDT 24 |
| Peak memory | 144060 kb |
| Host | smart-076fc7cc-7661-42e1-adbb-d0b0e175cc38 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2642192125 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.2642192125 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.2951100467 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 5366720000 ps |
| CPU time | 17.18 seconds |
| Started | Mar 28 12:29:31 PM PDT 24 |
| Finished | Mar 28 12:30:03 PM PDT 24 |
| Peak memory | 144688 kb |
| Host | smart-ab45ae75-f712-4939-8f88-85f099ae1117 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2951100467 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.2951100467 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.1730177050 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 12439060000 ps |
| CPU time | 44.09 seconds |
| Started | Mar 28 12:28:54 PM PDT 24 |
| Finished | Mar 28 12:30:20 PM PDT 24 |
| Peak memory | 144028 kb |
| Host | smart-40b24e98-11c1-4022-a401-c375356edd77 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1730177050 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.1730177050 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.245774745 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 3290960000 ps |
| CPU time | 11.05 seconds |
| Started | Mar 28 12:29:17 PM PDT 24 |
| Finished | Mar 28 12:29:38 PM PDT 24 |
| Peak memory | 144488 kb |
| Host | smart-b0d2ed13-4593-4704-97cf-dddad77dd694 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=245774745 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.245774745 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.2010385644 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 10088640000 ps |
| CPU time | 33.52 seconds |
| Started | Mar 28 12:29:21 PM PDT 24 |
| Finished | Mar 28 12:30:24 PM PDT 24 |
| Peak memory | 144688 kb |
| Host | smart-86c3c32b-a546-47de-8f04-f0a0bfb180db |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2010385644 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.2010385644 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.996400198 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 11404900000 ps |
| CPU time | 38.53 seconds |
| Started | Mar 28 12:29:17 PM PDT 24 |
| Finished | Mar 28 12:30:29 PM PDT 24 |
| Peak memory | 145024 kb |
| Host | smart-86cf903e-27a5-42ef-a817-766f865b8627 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=996400198 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.996400198 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.2996749655 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 3299640000 ps |
| CPU time | 12.19 seconds |
| Started | Mar 28 12:29:23 PM PDT 24 |
| Finished | Mar 28 12:29:46 PM PDT 24 |
| Peak memory | 143912 kb |
| Host | smart-646c90c3-5694-4d87-9d7c-d47c160e52cf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2996749655 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.2996749655 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.4037385996 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 14029980000 ps |
| CPU time | 46.66 seconds |
| Started | Mar 28 12:29:27 PM PDT 24 |
| Finished | Mar 28 12:30:55 PM PDT 24 |
| Peak memory | 143608 kb |
| Host | smart-42cc09a5-779d-45f2-8488-7a3d100989fa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4037385996 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.4037385996 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.3679844181 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 8004200000 ps |
| CPU time | 25.7 seconds |
| Started | Mar 28 12:29:01 PM PDT 24 |
| Finished | Mar 28 12:29:49 PM PDT 24 |
| Peak memory | 145040 kb |
| Host | smart-1b8451ea-6f6f-4d52-b519-06882f8c9f2e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3679844181 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.3679844181 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.3225375344 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 13966740000 ps |
| CPU time | 43.8 seconds |
| Started | Mar 28 12:28:51 PM PDT 24 |
| Finished | Mar 28 12:30:13 PM PDT 24 |
| Peak memory | 145160 kb |
| Host | smart-c19a358d-df67-471b-9334-636ecf5a9275 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3225375344 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.3225375344 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.3228317168 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 9628600000 ps |
| CPU time | 30.13 seconds |
| Started | Mar 28 12:28:58 PM PDT 24 |
| Finished | Mar 28 12:29:54 PM PDT 24 |
| Peak memory | 144888 kb |
| Host | smart-32849a3f-c4e8-47ca-bdb5-9dd878277db9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3228317168 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.3228317168 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.2895533000 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 6292380000 ps |
| CPU time | 25.32 seconds |
| Started | Mar 28 12:28:57 PM PDT 24 |
| Finished | Mar 28 12:29:45 PM PDT 24 |
| Peak memory | 142972 kb |
| Host | smart-23722c5c-53f7-40d9-ad5c-1f6315115eed |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2895533000 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.2895533000 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.1839761666 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 11990800000 ps |
| CPU time | 41.23 seconds |
| Started | Mar 28 12:28:57 PM PDT 24 |
| Finished | Mar 28 12:30:16 PM PDT 24 |
| Peak memory | 143476 kb |
| Host | smart-667f4afc-6451-423c-9b3b-4880826d6437 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1839761666 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.1839761666 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.2548811024 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 10509620000 ps |
| CPU time | 37.03 seconds |
| Started | Mar 28 12:28:52 PM PDT 24 |
| Finished | Mar 28 12:30:12 PM PDT 24 |
| Peak memory | 144020 kb |
| Host | smart-9c4b5f84-07ab-4266-9df5-43c3f7b4ec58 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2548811024 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.2548811024 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.3769421232 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 12410540000 ps |
| CPU time | 41.71 seconds |
| Started | Mar 28 12:29:25 PM PDT 24 |
| Finished | Mar 28 12:30:45 PM PDT 24 |
| Peak memory | 144652 kb |
| Host | smart-3a20e881-9ece-4a26-ab10-2ae1ad545e85 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3769421232 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.3769421232 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.2323171253 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 4772140000 ps |
| CPU time | 19.16 seconds |
| Started | Mar 28 12:29:19 PM PDT 24 |
| Finished | Mar 28 12:29:55 PM PDT 24 |
| Peak memory | 144656 kb |
| Host | smart-40a5c256-4d3a-4d34-ae5f-d66d9714821d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2323171253 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.2323171253 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.3748185637 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 10092360000 ps |
| CPU time | 33.34 seconds |
| Started | Mar 28 12:28:59 PM PDT 24 |
| Finished | Mar 28 12:30:01 PM PDT 24 |
| Peak memory | 145152 kb |
| Host | smart-14623241-a3aa-4bde-a75a-37946ebd53ba |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3748185637 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.3748185637 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.2431751682 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 9512660000 ps |
| CPU time | 34.42 seconds |
| Started | Mar 28 12:28:57 PM PDT 24 |
| Finished | Mar 28 12:30:01 PM PDT 24 |
| Peak memory | 145016 kb |
| Host | smart-8873a794-457d-4eae-b4b1-baeeb074c8ff |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2431751682 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.2431751682 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.2973572957 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 9800960000 ps |
| CPU time | 34.73 seconds |
| Started | Mar 28 12:29:18 PM PDT 24 |
| Finished | Mar 28 12:30:24 PM PDT 24 |
| Peak memory | 144060 kb |
| Host | smart-dcc04b63-d4a3-4588-99d0-3e8c959a5943 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2973572957 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.2973572957 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.273556179 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 3821680000 ps |
| CPU time | 12.35 seconds |
| Started | Mar 28 12:29:15 PM PDT 24 |
| Finished | Mar 28 12:29:39 PM PDT 24 |
| Peak memory | 144484 kb |
| Host | smart-e70d1f2a-b708-44f3-bb8b-accbcf2b7897 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=273556179 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.273556179 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.176978928 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 10495980000 ps |
| CPU time | 33.98 seconds |
| Started | Mar 28 12:28:54 PM PDT 24 |
| Finished | Mar 28 12:29:58 PM PDT 24 |
| Peak memory | 144028 kb |
| Host | smart-fe407773-970f-400b-8dc9-2684107b03f4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=176978928 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.176978928 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.3554274547 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 4569400000 ps |
| CPU time | 18.98 seconds |
| Started | Mar 28 12:29:27 PM PDT 24 |
| Finished | Mar 28 12:30:04 PM PDT 24 |
| Peak memory | 144688 kb |
| Host | smart-364441fb-ea71-4bcc-bacc-decaf8ba263f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3554274547 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.3554274547 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.3036278724 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 5561400000 ps |
| CPU time | 21.33 seconds |
| Started | Mar 28 12:28:57 PM PDT 24 |
| Finished | Mar 28 12:29:38 PM PDT 24 |
| Peak memory | 144860 kb |
| Host | smart-e053a90e-aaab-484d-9fc7-9df3f2411a3a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3036278724 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.3036278724 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.3611042629 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 4527860000 ps |
| CPU time | 18.85 seconds |
| Started | Mar 28 12:28:55 PM PDT 24 |
| Finished | Mar 28 12:29:30 PM PDT 24 |
| Peak memory | 143224 kb |
| Host | smart-62d765b7-e70f-4342-a154-8b23c5c5686e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3611042629 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.3611042629 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.625686281 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 3979160000 ps |
| CPU time | 13.67 seconds |
| Started | Mar 28 12:29:23 PM PDT 24 |
| Finished | Mar 28 12:29:49 PM PDT 24 |
| Peak memory | 143908 kb |
| Host | smart-acfb7362-e766-4ca4-b391-a5ed49363f3b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=625686281 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.625686281 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.2813741090 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 14090120000 ps |
| CPU time | 48.59 seconds |
| Started | Mar 28 12:28:55 PM PDT 24 |
| Finished | Mar 28 12:30:26 PM PDT 24 |
| Peak memory | 143044 kb |
| Host | smart-ebc15ae0-a95c-4a53-a29d-ed339195dd2a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2813741090 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.2813741090 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.935878069 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 7703500000 ps |
| CPU time | 31.01 seconds |
| Started | Mar 28 12:29:19 PM PDT 24 |
| Finished | Mar 28 12:30:18 PM PDT 24 |
| Peak memory | 144684 kb |
| Host | smart-0bdc4600-e9eb-4e6d-ab4c-6127259a33c9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=935878069 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.935878069 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.2172005087 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 4804380000 ps |
| CPU time | 15.29 seconds |
| Started | Mar 28 12:29:08 PM PDT 24 |
| Finished | Mar 28 12:29:36 PM PDT 24 |
| Peak memory | 145068 kb |
| Host | smart-afd505a0-6ac1-4350-b7ec-a4aee91c242a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2172005087 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.2172005087 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.4132836320 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 13791900000 ps |
| CPU time | 43.75 seconds |
| Started | Mar 28 12:29:31 PM PDT 24 |
| Finished | Mar 28 12:30:51 PM PDT 24 |
| Peak memory | 145068 kb |
| Host | smart-37136f3a-58be-4b65-ad43-6449bd2ce82b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4132836320 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.4132836320 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.323146546 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 6505040000 ps |
| CPU time | 21.61 seconds |
| Started | Mar 28 12:29:00 PM PDT 24 |
| Finished | Mar 28 12:29:40 PM PDT 24 |
| Peak memory | 145152 kb |
| Host | smart-7e23839e-3880-4e98-94a8-08fd47c32327 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=323146546 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.323146546 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.455106885 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 9732760000 ps |
| CPU time | 29.57 seconds |
| Started | Mar 28 12:28:57 PM PDT 24 |
| Finished | Mar 28 12:29:52 PM PDT 24 |
| Peak memory | 144604 kb |
| Host | smart-7eda0e9f-1530-46c9-997c-a00264eac53b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=455106885 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.455106885 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.4028289565 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 9091680000 ps |
| CPU time | 29.04 seconds |
| Started | Mar 28 12:28:58 PM PDT 24 |
| Finished | Mar 28 12:29:52 PM PDT 24 |
| Peak memory | 144524 kb |
| Host | smart-023b5cb1-596c-457d-aa8c-88972cb67c1a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4028289565 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.4028289565 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |