| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/16.prim_present_test.3766368192 | ||
| Name |
|---|
| /workspace/coverage/default/0.prim_present_test.3018754864 |
| /workspace/coverage/default/1.prim_present_test.2819550041 |
| /workspace/coverage/default/10.prim_present_test.1686653029 |
| /workspace/coverage/default/11.prim_present_test.690693069 |
| /workspace/coverage/default/12.prim_present_test.96651527 |
| /workspace/coverage/default/13.prim_present_test.1023828683 |
| /workspace/coverage/default/14.prim_present_test.3639708606 |
| /workspace/coverage/default/15.prim_present_test.2789797541 |
| /workspace/coverage/default/17.prim_present_test.547015691 |
| /workspace/coverage/default/18.prim_present_test.1704486582 |
| /workspace/coverage/default/19.prim_present_test.793701918 |
| /workspace/coverage/default/2.prim_present_test.4015414391 |
| /workspace/coverage/default/20.prim_present_test.1786976870 |
| /workspace/coverage/default/21.prim_present_test.2228745436 |
| /workspace/coverage/default/22.prim_present_test.3747479548 |
| /workspace/coverage/default/23.prim_present_test.4106099603 |
| /workspace/coverage/default/24.prim_present_test.888801898 |
| /workspace/coverage/default/25.prim_present_test.248611129 |
| /workspace/coverage/default/26.prim_present_test.412198908 |
| /workspace/coverage/default/27.prim_present_test.2800357284 |
| /workspace/coverage/default/28.prim_present_test.3715478148 |
| /workspace/coverage/default/29.prim_present_test.2956694849 |
| /workspace/coverage/default/3.prim_present_test.4197726338 |
| /workspace/coverage/default/30.prim_present_test.2244214306 |
| /workspace/coverage/default/31.prim_present_test.23170877 |
| /workspace/coverage/default/32.prim_present_test.572223558 |
| /workspace/coverage/default/33.prim_present_test.1177671558 |
| /workspace/coverage/default/34.prim_present_test.1259873289 |
| /workspace/coverage/default/35.prim_present_test.20742852 |
| /workspace/coverage/default/36.prim_present_test.1644509802 |
| /workspace/coverage/default/37.prim_present_test.1056878633 |
| /workspace/coverage/default/38.prim_present_test.1478236494 |
| /workspace/coverage/default/39.prim_present_test.2905564281 |
| /workspace/coverage/default/4.prim_present_test.3956437598 |
| /workspace/coverage/default/40.prim_present_test.2929600353 |
| /workspace/coverage/default/41.prim_present_test.661809982 |
| /workspace/coverage/default/42.prim_present_test.1268334251 |
| /workspace/coverage/default/43.prim_present_test.1501573888 |
| /workspace/coverage/default/44.prim_present_test.3699620848 |
| /workspace/coverage/default/45.prim_present_test.1104271177 |
| /workspace/coverage/default/46.prim_present_test.2078501032 |
| /workspace/coverage/default/47.prim_present_test.2721808690 |
| /workspace/coverage/default/48.prim_present_test.325669270 |
| /workspace/coverage/default/49.prim_present_test.2445807542 |
| /workspace/coverage/default/5.prim_present_test.2528015633 |
| /workspace/coverage/default/6.prim_present_test.3619782816 |
| /workspace/coverage/default/7.prim_present_test.2228216996 |
| /workspace/coverage/default/8.prim_present_test.3050939761 |
| /workspace/coverage/default/9.prim_present_test.2368380228 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/2.prim_present_test.4015414391 | Mar 31 12:37:14 PM PDT 24 | Mar 31 12:37:57 PM PDT 24 | 5643860000 ps | ||
| T2 | /workspace/coverage/default/4.prim_present_test.3956437598 | Mar 31 12:36:48 PM PDT 24 | Mar 31 12:38:38 PM PDT 24 | 13483760000 ps | ||
| T3 | /workspace/coverage/default/41.prim_present_test.661809982 | Mar 31 12:37:12 PM PDT 24 | Mar 31 12:37:55 PM PDT 24 | 6097700000 ps | ||
| T4 | /workspace/coverage/default/34.prim_present_test.1259873289 | Mar 31 12:36:57 PM PDT 24 | Mar 31 12:37:49 PM PDT 24 | 7609880000 ps | ||
| T5 | /workspace/coverage/default/20.prim_present_test.1786976870 | Mar 31 12:36:55 PM PDT 24 | Mar 31 12:37:31 PM PDT 24 | 5477700000 ps | ||
| T6 | /workspace/coverage/default/43.prim_present_test.1501573888 | Mar 31 12:37:03 PM PDT 24 | Mar 31 12:37:53 PM PDT 24 | 7459840000 ps | ||
| T7 | /workspace/coverage/default/16.prim_present_test.3766368192 | Mar 31 12:36:57 PM PDT 24 | Mar 31 12:37:41 PM PDT 24 | 6390340000 ps | ||
| T8 | /workspace/coverage/default/35.prim_present_test.20742852 | Mar 31 12:36:55 PM PDT 24 | Mar 31 12:38:05 PM PDT 24 | 9734620000 ps | ||
| T9 | /workspace/coverage/default/6.prim_present_test.3619782816 | Mar 31 12:36:56 PM PDT 24 | Mar 31 12:38:34 PM PDT 24 | 14628280000 ps | ||
| T10 | /workspace/coverage/default/21.prim_present_test.2228745436 | Mar 31 12:36:52 PM PDT 24 | Mar 31 12:38:15 PM PDT 24 | 12574220000 ps | ||
| T11 | /workspace/coverage/default/24.prim_present_test.888801898 | Mar 31 12:36:55 PM PDT 24 | Mar 31 12:37:53 PM PDT 24 | 8681860000 ps | ||
| T12 | /workspace/coverage/default/33.prim_present_test.1177671558 | Mar 31 12:37:21 PM PDT 24 | Mar 31 12:38:41 PM PDT 24 | 12467580000 ps | ||
| T13 | /workspace/coverage/default/37.prim_present_test.1056878633 | Mar 31 12:36:54 PM PDT 24 | Mar 31 12:37:48 PM PDT 24 | 8319160000 ps | ||
| T14 | /workspace/coverage/default/36.prim_present_test.1644509802 | Mar 31 12:36:57 PM PDT 24 | Mar 31 12:38:20 PM PDT 24 | 13053480000 ps | ||
| T15 | /workspace/coverage/default/40.prim_present_test.2929600353 | Mar 31 12:37:03 PM PDT 24 | Mar 31 12:38:06 PM PDT 24 | 10069420000 ps | ||
| T16 | /workspace/coverage/default/0.prim_present_test.3018754864 | Mar 31 12:36:48 PM PDT 24 | Mar 31 12:38:44 PM PDT 24 | 14193040000 ps | ||
| T17 | /workspace/coverage/default/32.prim_present_test.572223558 | Mar 31 12:36:52 PM PDT 24 | Mar 31 12:38:45 PM PDT 24 | 14286040000 ps | ||
| T18 | /workspace/coverage/default/18.prim_present_test.1704486582 | Mar 31 12:36:56 PM PDT 24 | Mar 31 12:38:28 PM PDT 24 | 13255600000 ps | ||
| T19 | /workspace/coverage/default/38.prim_present_test.1478236494 | Mar 31 12:36:58 PM PDT 24 | Mar 31 12:38:30 PM PDT 24 | 13517240000 ps | ||
| T20 | /workspace/coverage/default/8.prim_present_test.3050939761 | Mar 31 12:37:08 PM PDT 24 | Mar 31 12:38:10 PM PDT 24 | 9683160000 ps | ||
| T21 | /workspace/coverage/default/29.prim_present_test.2956694849 | Mar 31 12:36:57 PM PDT 24 | Mar 31 12:37:52 PM PDT 24 | 7660100000 ps | ||
| T22 | /workspace/coverage/default/9.prim_present_test.2368380228 | Mar 31 12:37:10 PM PDT 24 | Mar 31 12:38:22 PM PDT 24 | 10190940000 ps | ||
| T23 | /workspace/coverage/default/48.prim_present_test.325669270 | Mar 31 12:37:04 PM PDT 24 | Mar 31 12:38:39 PM PDT 24 | 14315800000 ps | ||
| T24 | /workspace/coverage/default/7.prim_present_test.2228216996 | Mar 31 12:37:01 PM PDT 24 | Mar 31 12:38:10 PM PDT 24 | 10463120000 ps | ||
| T25 | /workspace/coverage/default/17.prim_present_test.547015691 | Mar 31 12:36:50 PM PDT 24 | Mar 31 12:38:11 PM PDT 24 | 13201660000 ps | ||
| T26 | /workspace/coverage/default/31.prim_present_test.23170877 | Mar 31 12:36:57 PM PDT 24 | Mar 31 12:37:31 PM PDT 24 | 4598540000 ps | ||
| T27 | /workspace/coverage/default/49.prim_present_test.2445807542 | Mar 31 12:37:28 PM PDT 24 | Mar 31 12:38:06 PM PDT 24 | 5929060000 ps | ||
| T28 | /workspace/coverage/default/22.prim_present_test.3747479548 | Mar 31 12:36:56 PM PDT 24 | Mar 31 12:38:12 PM PDT 24 | 10450720000 ps | ||
| T29 | /workspace/coverage/default/46.prim_present_test.2078501032 | Mar 31 12:37:04 PM PDT 24 | Mar 31 12:37:55 PM PDT 24 | 7355060000 ps | ||
| T30 | /workspace/coverage/default/12.prim_present_test.96651527 | Mar 31 12:36:46 PM PDT 24 | Mar 31 12:38:17 PM PDT 24 | 14124220000 ps | ||
| T31 | /workspace/coverage/default/39.prim_present_test.2905564281 | Mar 31 12:37:03 PM PDT 24 | Mar 31 12:37:35 PM PDT 24 | 4969920000 ps | ||
| T32 | /workspace/coverage/default/19.prim_present_test.793701918 | Mar 31 12:36:54 PM PDT 24 | Mar 31 12:38:20 PM PDT 24 | 14671680000 ps | ||
| T33 | /workspace/coverage/default/5.prim_present_test.2528015633 | Mar 31 12:36:51 PM PDT 24 | Mar 31 12:37:55 PM PDT 24 | 10402980000 ps | ||
| T34 | /workspace/coverage/default/1.prim_present_test.2819550041 | Mar 31 12:36:58 PM PDT 24 | Mar 31 12:38:23 PM PDT 24 | 15366080000 ps | ||
| T35 | /workspace/coverage/default/13.prim_present_test.1023828683 | Mar 31 12:36:46 PM PDT 24 | Mar 31 12:37:38 PM PDT 24 | 7935380000 ps | ||
| T36 | /workspace/coverage/default/27.prim_present_test.2800357284 | Mar 31 12:36:56 PM PDT 24 | Mar 31 12:37:42 PM PDT 24 | 6892540000 ps | ||
| T37 | /workspace/coverage/default/11.prim_present_test.690693069 | Mar 31 12:37:11 PM PDT 24 | Mar 31 12:37:36 PM PDT 24 | 3140300000 ps | ||
| T38 | /workspace/coverage/default/30.prim_present_test.2244214306 | Mar 31 12:36:55 PM PDT 24 | Mar 31 12:37:17 PM PDT 24 | 3134100000 ps | ||
| T39 | /workspace/coverage/default/26.prim_present_test.412198908 | Mar 31 12:36:56 PM PDT 24 | Mar 31 12:38:23 PM PDT 24 | 13334340000 ps | ||
| T40 | /workspace/coverage/default/10.prim_present_test.1686653029 | Mar 31 12:36:51 PM PDT 24 | Mar 31 12:37:49 PM PDT 24 | 9108420000 ps | ||
| T41 | /workspace/coverage/default/45.prim_present_test.1104271177 | Mar 31 12:37:04 PM PDT 24 | Mar 31 12:38:59 PM PDT 24 | 14699580000 ps | ||
| T42 | /workspace/coverage/default/47.prim_present_test.2721808690 | Mar 31 12:37:06 PM PDT 24 | Mar 31 12:38:41 PM PDT 24 | 14555120000 ps | ||
| T43 | /workspace/coverage/default/3.prim_present_test.4197726338 | Mar 31 12:37:16 PM PDT 24 | Mar 31 12:38:40 PM PDT 24 | 13630080000 ps | ||
| T44 | /workspace/coverage/default/15.prim_present_test.2789797541 | Mar 31 12:37:01 PM PDT 24 | Mar 31 12:37:41 PM PDT 24 | 5428720000 ps | ||
| T45 | /workspace/coverage/default/42.prim_present_test.1268334251 | Mar 31 12:37:22 PM PDT 24 | Mar 31 12:38:55 PM PDT 24 | 14638820000 ps | ||
| T46 | /workspace/coverage/default/28.prim_present_test.3715478148 | Mar 31 12:36:56 PM PDT 24 | Mar 31 12:38:05 PM PDT 24 | 12513460000 ps | ||
| T47 | /workspace/coverage/default/14.prim_present_test.3639708606 | Mar 31 12:36:56 PM PDT 24 | Mar 31 12:38:06 PM PDT 24 | 9682540000 ps | ||
| T48 | /workspace/coverage/default/44.prim_present_test.3699620848 | Mar 31 12:37:22 PM PDT 24 | Mar 31 12:38:08 PM PDT 24 | 7745040000 ps | ||
| T49 | /workspace/coverage/default/25.prim_present_test.248611129 | Mar 31 12:36:56 PM PDT 24 | Mar 31 12:38:20 PM PDT 24 | 11777520000 ps | ||
| T50 | /workspace/coverage/default/23.prim_present_test.4106099603 | Mar 31 12:37:14 PM PDT 24 | Mar 31 12:38:50 PM PDT 24 | 14734300000 ps |
| Test location | /workspace/coverage/default/16.prim_present_test.3766368192 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 6390340000 ps |
| CPU time | 22.77 seconds |
| Started | Mar 31 12:36:57 PM PDT 24 |
| Finished | Mar 31 12:37:41 PM PDT 24 |
| Peak memory | 145132 kb |
| Host | smart-8576e2c6-2c05-4488-8b08-2c4443044c56 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3766368192 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.3766368192 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/0.prim_present_test.3018754864 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 14193040000 ps |
| CPU time | 58.34 seconds |
| Started | Mar 31 12:36:48 PM PDT 24 |
| Finished | Mar 31 12:38:44 PM PDT 24 |
| Peak memory | 145128 kb |
| Host | smart-bcb10053-cd61-432e-8ac9-4fff6d3c26d0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3018754864 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.3018754864 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/1.prim_present_test.2819550041 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 15366080000 ps |
| CPU time | 46.12 seconds |
| Started | Mar 31 12:36:58 PM PDT 24 |
| Finished | Mar 31 12:38:23 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-4472c6a0-149f-4bd0-97fc-08fc8847b506 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2819550041 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.2819550041 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/10.prim_present_test.1686653029 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 9108420000 ps |
| CPU time | 31.47 seconds |
| Started | Mar 31 12:36:51 PM PDT 24 |
| Finished | Mar 31 12:37:49 PM PDT 24 |
| Peak memory | 145128 kb |
| Host | smart-90d92b29-ed34-481d-a122-656e0380522d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1686653029 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.1686653029 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/11.prim_present_test.690693069 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 3140300000 ps |
| CPU time | 13.34 seconds |
| Started | Mar 31 12:37:11 PM PDT 24 |
| Finished | Mar 31 12:37:36 PM PDT 24 |
| Peak memory | 144916 kb |
| Host | smart-65192baf-7448-4397-ac28-2d826ecedb0a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=690693069 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.690693069 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.96651527 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 14124220000 ps |
| CPU time | 48.96 seconds |
| Started | Mar 31 12:36:46 PM PDT 24 |
| Finished | Mar 31 12:38:17 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-e6e61999-96be-4cde-a12d-0f11be584e9d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=96651527 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.96651527 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.1023828683 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 7935380000 ps |
| CPU time | 27.69 seconds |
| Started | Mar 31 12:36:46 PM PDT 24 |
| Finished | Mar 31 12:37:38 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-b324f544-b0d7-4768-9421-065630bcec4d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1023828683 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.1023828683 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.3639708606 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 9682540000 ps |
| CPU time | 36.67 seconds |
| Started | Mar 31 12:36:56 PM PDT 24 |
| Finished | Mar 31 12:38:06 PM PDT 24 |
| Peak memory | 145124 kb |
| Host | smart-1d910a43-d820-48a5-b839-18e7731156c0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3639708606 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.3639708606 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.2789797541 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 5428720000 ps |
| CPU time | 21.52 seconds |
| Started | Mar 31 12:37:01 PM PDT 24 |
| Finished | Mar 31 12:37:41 PM PDT 24 |
| Peak memory | 145064 kb |
| Host | smart-3edd3c6d-6f68-458d-817a-aab4ef29359c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2789797541 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.2789797541 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.547015691 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 13201660000 ps |
| CPU time | 43.85 seconds |
| Started | Mar 31 12:36:50 PM PDT 24 |
| Finished | Mar 31 12:38:11 PM PDT 24 |
| Peak memory | 145152 kb |
| Host | smart-d37d9b24-914a-41dd-8560-869c0647bebb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=547015691 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.547015691 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.1704486582 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 13255600000 ps |
| CPU time | 48.42 seconds |
| Started | Mar 31 12:36:56 PM PDT 24 |
| Finished | Mar 31 12:38:28 PM PDT 24 |
| Peak memory | 145124 kb |
| Host | smart-3742e079-ad3c-4ca9-9bc1-7c80327b9898 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1704486582 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.1704486582 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.793701918 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 14671680000 ps |
| CPU time | 46.91 seconds |
| Started | Mar 31 12:36:54 PM PDT 24 |
| Finished | Mar 31 12:38:20 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-20d263d7-4c33-4f29-8069-c478624733ea |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=793701918 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.793701918 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.4015414391 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 5643860000 ps |
| CPU time | 22.03 seconds |
| Started | Mar 31 12:37:14 PM PDT 24 |
| Finished | Mar 31 12:37:57 PM PDT 24 |
| Peak memory | 145080 kb |
| Host | smart-5cd4a442-8977-4fc7-85e4-54ac80a472b3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4015414391 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.4015414391 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.1786976870 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 5477700000 ps |
| CPU time | 19.05 seconds |
| Started | Mar 31 12:36:55 PM PDT 24 |
| Finished | Mar 31 12:37:31 PM PDT 24 |
| Peak memory | 145124 kb |
| Host | smart-2c4f0d7e-4169-4bc7-b0ca-34c9bf3b76ea |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1786976870 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.1786976870 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.2228745436 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 12574220000 ps |
| CPU time | 44.78 seconds |
| Started | Mar 31 12:36:52 PM PDT 24 |
| Finished | Mar 31 12:38:15 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-c4fd82b9-5ceb-4b37-82c4-d2d210cc302a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2228745436 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.2228745436 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.3747479548 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 10450720000 ps |
| CPU time | 39.4 seconds |
| Started | Mar 31 12:36:56 PM PDT 24 |
| Finished | Mar 31 12:38:12 PM PDT 24 |
| Peak memory | 145124 kb |
| Host | smart-63c166d3-d760-426b-b538-36d7430948fc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3747479548 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.3747479548 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.4106099603 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 14734300000 ps |
| CPU time | 50.76 seconds |
| Started | Mar 31 12:37:14 PM PDT 24 |
| Finished | Mar 31 12:38:50 PM PDT 24 |
| Peak memory | 145148 kb |
| Host | smart-4cede7b1-167e-482d-bb98-7b140fd0be74 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4106099603 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.4106099603 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.888801898 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 8681860000 ps |
| CPU time | 30.62 seconds |
| Started | Mar 31 12:36:55 PM PDT 24 |
| Finished | Mar 31 12:37:53 PM PDT 24 |
| Peak memory | 145196 kb |
| Host | smart-a45bb04c-1309-4a54-bd09-85a3389130f7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=888801898 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.888801898 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.248611129 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 11777520000 ps |
| CPU time | 44.49 seconds |
| Started | Mar 31 12:36:56 PM PDT 24 |
| Finished | Mar 31 12:38:20 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-85074567-b998-45e8-921e-7cf48b7632f1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=248611129 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.248611129 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.412198908 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 13334340000 ps |
| CPU time | 46.13 seconds |
| Started | Mar 31 12:36:56 PM PDT 24 |
| Finished | Mar 31 12:38:23 PM PDT 24 |
| Peak memory | 145196 kb |
| Host | smart-f77324ff-c02d-424b-b8a4-b20dbed611a6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=412198908 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.412198908 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.2800357284 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 6892540000 ps |
| CPU time | 24.08 seconds |
| Started | Mar 31 12:36:56 PM PDT 24 |
| Finished | Mar 31 12:37:42 PM PDT 24 |
| Peak memory | 145200 kb |
| Host | smart-a610a077-3c52-4e69-b3d5-259d3281f973 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2800357284 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.2800357284 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.3715478148 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 12513460000 ps |
| CPU time | 38.54 seconds |
| Started | Mar 31 12:36:56 PM PDT 24 |
| Finished | Mar 31 12:38:05 PM PDT 24 |
| Peak memory | 145200 kb |
| Host | smart-682bfffd-0506-4ea5-8faa-9b2736dabf2a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3715478148 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.3715478148 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.2956694849 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 7660100000 ps |
| CPU time | 29.19 seconds |
| Started | Mar 31 12:36:57 PM PDT 24 |
| Finished | Mar 31 12:37:52 PM PDT 24 |
| Peak memory | 145084 kb |
| Host | smart-24b1d80b-a295-4e00-98c6-e6c0b4f9f735 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2956694849 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.2956694849 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.4197726338 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 13630080000 ps |
| CPU time | 44.46 seconds |
| Started | Mar 31 12:37:16 PM PDT 24 |
| Finished | Mar 31 12:38:40 PM PDT 24 |
| Peak memory | 145076 kb |
| Host | smart-6f3fe185-6621-439e-a86d-e353b2c7269f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4197726338 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.4197726338 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.2244214306 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 3134100000 ps |
| CPU time | 11.44 seconds |
| Started | Mar 31 12:36:55 PM PDT 24 |
| Finished | Mar 31 12:37:17 PM PDT 24 |
| Peak memory | 144976 kb |
| Host | smart-824edf62-e57e-47d8-9b0b-b02ce21b75d4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2244214306 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.2244214306 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.23170877 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 4598540000 ps |
| CPU time | 18.07 seconds |
| Started | Mar 31 12:36:57 PM PDT 24 |
| Finished | Mar 31 12:37:31 PM PDT 24 |
| Peak memory | 145164 kb |
| Host | smart-b778ee0c-6683-49f7-92a6-b874fb66a75e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=23170877 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.23170877 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.572223558 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 14286040000 ps |
| CPU time | 57.25 seconds |
| Started | Mar 31 12:36:52 PM PDT 24 |
| Finished | Mar 31 12:38:45 PM PDT 24 |
| Peak memory | 145092 kb |
| Host | smart-e2894fa2-3872-4d87-bd90-92c902613172 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=572223558 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.572223558 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.1177671558 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 12467580000 ps |
| CPU time | 42.71 seconds |
| Started | Mar 31 12:37:21 PM PDT 24 |
| Finished | Mar 31 12:38:41 PM PDT 24 |
| Peak memory | 145092 kb |
| Host | smart-ce321a23-153d-42f8-80f2-1b4e24e75fd2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1177671558 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.1177671558 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.1259873289 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 7609880000 ps |
| CPU time | 27.81 seconds |
| Started | Mar 31 12:36:57 PM PDT 24 |
| Finished | Mar 31 12:37:49 PM PDT 24 |
| Peak memory | 145072 kb |
| Host | smart-17d8e28f-8507-48fd-aa25-b75d3cf9c792 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1259873289 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.1259873289 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.20742852 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 9734620000 ps |
| CPU time | 36.31 seconds |
| Started | Mar 31 12:36:55 PM PDT 24 |
| Finished | Mar 31 12:38:05 PM PDT 24 |
| Peak memory | 145092 kb |
| Host | smart-c3e40fba-8b02-423a-8ba4-968c44b63800 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=20742852 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.20742852 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.1644509802 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 13053480000 ps |
| CPU time | 44.75 seconds |
| Started | Mar 31 12:36:57 PM PDT 24 |
| Finished | Mar 31 12:38:20 PM PDT 24 |
| Peak memory | 145200 kb |
| Host | smart-4a3c1568-1f46-4311-8ea4-5af5ef77d4cc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1644509802 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.1644509802 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.1056878633 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 8319160000 ps |
| CPU time | 28.92 seconds |
| Started | Mar 31 12:36:54 PM PDT 24 |
| Finished | Mar 31 12:37:48 PM PDT 24 |
| Peak memory | 145100 kb |
| Host | smart-a14b9d0b-4420-4157-a9b0-0b6323c26bfc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1056878633 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.1056878633 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.1478236494 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 13517240000 ps |
| CPU time | 48.89 seconds |
| Started | Mar 31 12:36:58 PM PDT 24 |
| Finished | Mar 31 12:38:30 PM PDT 24 |
| Peak memory | 145084 kb |
| Host | smart-2ec8b817-23ce-4dd5-81b4-092dc8555b2e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1478236494 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.1478236494 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.2905564281 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 4969920000 ps |
| CPU time | 17.05 seconds |
| Started | Mar 31 12:37:03 PM PDT 24 |
| Finished | Mar 31 12:37:35 PM PDT 24 |
| Peak memory | 145164 kb |
| Host | smart-a813562b-7345-4448-b67a-f1c1b2407a33 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2905564281 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.2905564281 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.3956437598 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 13483760000 ps |
| CPU time | 55.11 seconds |
| Started | Mar 31 12:36:48 PM PDT 24 |
| Finished | Mar 31 12:38:38 PM PDT 24 |
| Peak memory | 145128 kb |
| Host | smart-a5002e31-b160-46aa-81ae-0e746640ab7f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3956437598 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.3956437598 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.2929600353 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 10069420000 ps |
| CPU time | 34.31 seconds |
| Started | Mar 31 12:37:03 PM PDT 24 |
| Finished | Mar 31 12:38:06 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-6cfaac3a-25d8-4675-ad76-27ecf0250845 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2929600353 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.2929600353 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.661809982 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 6097700000 ps |
| CPU time | 22.41 seconds |
| Started | Mar 31 12:37:12 PM PDT 24 |
| Finished | Mar 31 12:37:55 PM PDT 24 |
| Peak memory | 145080 kb |
| Host | smart-a8e05902-3c91-4542-b736-66eb1b74638b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=661809982 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.661809982 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.1268334251 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 14638820000 ps |
| CPU time | 47.02 seconds |
| Started | Mar 31 12:37:22 PM PDT 24 |
| Finished | Mar 31 12:38:55 PM PDT 24 |
| Peak memory | 145096 kb |
| Host | smart-d3a793e4-e274-4304-ad89-e9fd815aa13a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1268334251 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.1268334251 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.1501573888 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 7459840000 ps |
| CPU time | 26.73 seconds |
| Started | Mar 31 12:37:03 PM PDT 24 |
| Finished | Mar 31 12:37:53 PM PDT 24 |
| Peak memory | 145200 kb |
| Host | smart-6426ad30-3dee-4b5a-b1ec-73ab37ed0fb2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1501573888 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.1501573888 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.3699620848 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 7745040000 ps |
| CPU time | 24.21 seconds |
| Started | Mar 31 12:37:22 PM PDT 24 |
| Finished | Mar 31 12:38:08 PM PDT 24 |
| Peak memory | 145160 kb |
| Host | smart-2e682c7b-a65e-44bd-9761-8dd25c30674e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3699620848 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.3699620848 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.1104271177 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 14699580000 ps |
| CPU time | 58.11 seconds |
| Started | Mar 31 12:37:04 PM PDT 24 |
| Finished | Mar 31 12:38:59 PM PDT 24 |
| Peak memory | 145132 kb |
| Host | smart-c858ccd5-a45d-442f-b7a6-a392ba00c675 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1104271177 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.1104271177 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.2078501032 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 7355060000 ps |
| CPU time | 27.09 seconds |
| Started | Mar 31 12:37:04 PM PDT 24 |
| Finished | Mar 31 12:37:55 PM PDT 24 |
| Peak memory | 145200 kb |
| Host | smart-b452c646-4ae0-4194-8075-0ab6f74f87b2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2078501032 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.2078501032 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.2721808690 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 14555120000 ps |
| CPU time | 50.18 seconds |
| Started | Mar 31 12:37:06 PM PDT 24 |
| Finished | Mar 31 12:38:41 PM PDT 24 |
| Peak memory | 145112 kb |
| Host | smart-0af485a5-5273-40fd-8c67-abd2ebf35fc0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2721808690 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.2721808690 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.325669270 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 14315800000 ps |
| CPU time | 50.83 seconds |
| Started | Mar 31 12:37:04 PM PDT 24 |
| Finished | Mar 31 12:38:39 PM PDT 24 |
| Peak memory | 145200 kb |
| Host | smart-8367e98a-1a7d-4acc-a496-10c2987fc7ae |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=325669270 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.325669270 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.2445807542 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 5929060000 ps |
| CPU time | 20.37 seconds |
| Started | Mar 31 12:37:28 PM PDT 24 |
| Finished | Mar 31 12:38:06 PM PDT 24 |
| Peak memory | 145096 kb |
| Host | smart-6ae22be5-8c4c-48ca-854b-72741fb04c74 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2445807542 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.2445807542 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.2528015633 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 10402980000 ps |
| CPU time | 34.01 seconds |
| Started | Mar 31 12:36:51 PM PDT 24 |
| Finished | Mar 31 12:37:55 PM PDT 24 |
| Peak memory | 145092 kb |
| Host | smart-34d8a5f5-9dc9-41af-92cc-f6b6defc7958 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2528015633 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.2528015633 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.3619782816 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 14628280000 ps |
| CPU time | 51.79 seconds |
| Started | Mar 31 12:36:56 PM PDT 24 |
| Finished | Mar 31 12:38:34 PM PDT 24 |
| Peak memory | 145120 kb |
| Host | smart-4c091007-61bc-42a4-99d3-9d377d1a1463 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3619782816 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.3619782816 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.2228216996 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 10463120000 ps |
| CPU time | 36.91 seconds |
| Started | Mar 31 12:37:01 PM PDT 24 |
| Finished | Mar 31 12:38:10 PM PDT 24 |
| Peak memory | 145112 kb |
| Host | smart-0ab345e8-c6da-4886-a0e5-0d7cf5365e60 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2228216996 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.2228216996 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.3050939761 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 9683160000 ps |
| CPU time | 33.4 seconds |
| Started | Mar 31 12:37:08 PM PDT 24 |
| Finished | Mar 31 12:38:10 PM PDT 24 |
| Peak memory | 145064 kb |
| Host | smart-b9b592ba-b487-4182-b14a-5b85cc13a65a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3050939761 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.3050939761 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.2368380228 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 10190940000 ps |
| CPU time | 37.75 seconds |
| Started | Mar 31 12:37:10 PM PDT 24 |
| Finished | Mar 31 12:38:22 PM PDT 24 |
| Peak memory | 145116 kb |
| Host | smart-98c43afc-a7f3-4820-9aad-5ecbe9018d33 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2368380228 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.2368380228 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |