| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/2.prim_present_test.1329823498 | ||
| Name |
|---|
| /workspace/coverage/default/0.prim_present_test.1714985330 |
| /workspace/coverage/default/1.prim_present_test.405315366 |
| /workspace/coverage/default/10.prim_present_test.2010010495 |
| /workspace/coverage/default/11.prim_present_test.1342633457 |
| /workspace/coverage/default/12.prim_present_test.1731634023 |
| /workspace/coverage/default/13.prim_present_test.499031901 |
| /workspace/coverage/default/14.prim_present_test.3820002033 |
| /workspace/coverage/default/15.prim_present_test.110455558 |
| /workspace/coverage/default/16.prim_present_test.3846008960 |
| /workspace/coverage/default/17.prim_present_test.3577289877 |
| /workspace/coverage/default/18.prim_present_test.2228104610 |
| /workspace/coverage/default/19.prim_present_test.2955881558 |
| /workspace/coverage/default/20.prim_present_test.1892050308 |
| /workspace/coverage/default/21.prim_present_test.1083448181 |
| /workspace/coverage/default/22.prim_present_test.2019272932 |
| /workspace/coverage/default/23.prim_present_test.3579052038 |
| /workspace/coverage/default/24.prim_present_test.1848863208 |
| /workspace/coverage/default/25.prim_present_test.170098708 |
| /workspace/coverage/default/26.prim_present_test.4019211860 |
| /workspace/coverage/default/27.prim_present_test.4253540732 |
| /workspace/coverage/default/28.prim_present_test.1744512072 |
| /workspace/coverage/default/29.prim_present_test.3235597525 |
| /workspace/coverage/default/3.prim_present_test.338947135 |
| /workspace/coverage/default/30.prim_present_test.3264698583 |
| /workspace/coverage/default/31.prim_present_test.3264589805 |
| /workspace/coverage/default/32.prim_present_test.848382083 |
| /workspace/coverage/default/33.prim_present_test.130924697 |
| /workspace/coverage/default/34.prim_present_test.909242650 |
| /workspace/coverage/default/35.prim_present_test.1063367848 |
| /workspace/coverage/default/36.prim_present_test.1780616018 |
| /workspace/coverage/default/37.prim_present_test.914177048 |
| /workspace/coverage/default/38.prim_present_test.1764452138 |
| /workspace/coverage/default/39.prim_present_test.140019459 |
| /workspace/coverage/default/4.prim_present_test.1899707606 |
| /workspace/coverage/default/40.prim_present_test.1006556266 |
| /workspace/coverage/default/41.prim_present_test.3226916002 |
| /workspace/coverage/default/42.prim_present_test.2620683882 |
| /workspace/coverage/default/43.prim_present_test.2793503568 |
| /workspace/coverage/default/44.prim_present_test.3162182899 |
| /workspace/coverage/default/45.prim_present_test.1548180276 |
| /workspace/coverage/default/46.prim_present_test.3807164963 |
| /workspace/coverage/default/47.prim_present_test.1293782850 |
| /workspace/coverage/default/48.prim_present_test.1693843190 |
| /workspace/coverage/default/49.prim_present_test.2992670891 |
| /workspace/coverage/default/5.prim_present_test.2534114704 |
| /workspace/coverage/default/6.prim_present_test.4052562233 |
| /workspace/coverage/default/7.prim_present_test.2314553024 |
| /workspace/coverage/default/8.prim_present_test.1993612201 |
| /workspace/coverage/default/9.prim_present_test.4267974290 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/25.prim_present_test.170098708 | Apr 02 12:20:52 PM PDT 24 | Apr 02 12:21:25 PM PDT 24 | 4258780000 ps | ||
| T2 | /workspace/coverage/default/7.prim_present_test.2314553024 | Apr 02 12:22:16 PM PDT 24 | Apr 02 12:22:51 PM PDT 24 | 4426800000 ps | ||
| T3 | /workspace/coverage/default/8.prim_present_test.1993612201 | Apr 02 12:22:28 PM PDT 24 | Apr 02 12:23:59 PM PDT 24 | 13449040000 ps | ||
| T4 | /workspace/coverage/default/41.prim_present_test.3226916002 | Apr 02 12:19:11 PM PDT 24 | Apr 02 12:20:32 PM PDT 24 | 9550480000 ps | ||
| T5 | /workspace/coverage/default/30.prim_present_test.3264698583 | Apr 02 12:22:53 PM PDT 24 | Apr 02 12:24:20 PM PDT 24 | 13343020000 ps | ||
| T6 | /workspace/coverage/default/32.prim_present_test.848382083 | Apr 02 12:23:04 PM PDT 24 | Apr 02 12:24:41 PM PDT 24 | 14077100000 ps | ||
| T7 | /workspace/coverage/default/2.prim_present_test.1329823498 | Apr 02 12:22:20 PM PDT 24 | Apr 02 12:24:02 PM PDT 24 | 14482580000 ps | ||
| T8 | /workspace/coverage/default/26.prim_present_test.4019211860 | Apr 02 12:22:41 PM PDT 24 | Apr 02 12:23:48 PM PDT 24 | 10659040000 ps | ||
| T9 | /workspace/coverage/default/4.prim_present_test.1899707606 | Apr 02 12:20:35 PM PDT 24 | Apr 02 12:21:15 PM PDT 24 | 5452280000 ps | ||
| T10 | /workspace/coverage/default/22.prim_present_test.2019272932 | Apr 02 12:22:48 PM PDT 24 | Apr 02 12:23:15 PM PDT 24 | 3297160000 ps | ||
| T11 | /workspace/coverage/default/40.prim_present_test.1006556266 | Apr 02 12:21:23 PM PDT 24 | Apr 02 12:22:45 PM PDT 24 | 10860540000 ps | ||
| T12 | /workspace/coverage/default/49.prim_present_test.2992670891 | Apr 02 12:22:22 PM PDT 24 | Apr 02 12:23:51 PM PDT 24 | 13026820000 ps | ||
| T13 | /workspace/coverage/default/47.prim_present_test.1293782850 | Apr 02 12:20:58 PM PDT 24 | Apr 02 12:21:53 PM PDT 24 | 7872760000 ps | ||
| T14 | /workspace/coverage/default/13.prim_present_test.499031901 | Apr 02 12:20:01 PM PDT 24 | Apr 02 12:21:44 PM PDT 24 | 14937660000 ps | ||
| T15 | /workspace/coverage/default/35.prim_present_test.1063367848 | Apr 02 12:18:57 PM PDT 24 | Apr 02 12:20:17 PM PDT 24 | 9965880000 ps | ||
| T16 | /workspace/coverage/default/44.prim_present_test.3162182899 | Apr 02 12:19:04 PM PDT 24 | Apr 02 12:19:31 PM PDT 24 | 3599720000 ps | ||
| T17 | /workspace/coverage/default/48.prim_present_test.1693843190 | Apr 02 12:22:30 PM PDT 24 | Apr 02 12:23:29 PM PDT 24 | 8203220000 ps | ||
| T18 | /workspace/coverage/default/15.prim_present_test.110455558 | Apr 02 12:22:16 PM PDT 24 | Apr 02 12:23:09 PM PDT 24 | 6882000000 ps | ||
| T19 | /workspace/coverage/default/27.prim_present_test.4253540732 | Apr 02 12:22:29 PM PDT 24 | Apr 02 12:23:20 PM PDT 24 | 7172780000 ps | ||
| T20 | /workspace/coverage/default/6.prim_present_test.4052562233 | Apr 02 12:18:21 PM PDT 24 | Apr 02 12:19:40 PM PDT 24 | 12282820000 ps | ||
| T21 | /workspace/coverage/default/10.prim_present_test.2010010495 | Apr 02 12:22:15 PM PDT 24 | Apr 02 12:22:34 PM PDT 24 | 3124800000 ps | ||
| T22 | /workspace/coverage/default/37.prim_present_test.914177048 | Apr 02 12:19:07 PM PDT 24 | Apr 02 12:19:45 PM PDT 24 | 4718200000 ps | ||
| T23 | /workspace/coverage/default/12.prim_present_test.1731634023 | Apr 02 12:22:16 PM PDT 24 | Apr 02 12:24:11 PM PDT 24 | 15204260000 ps | ||
| T24 | /workspace/coverage/default/36.prim_present_test.1780616018 | Apr 02 12:18:43 PM PDT 24 | Apr 02 12:19:35 PM PDT 24 | 9773060000 ps | ||
| T25 | /workspace/coverage/default/19.prim_present_test.2955881558 | Apr 02 12:22:56 PM PDT 24 | Apr 02 12:23:36 PM PDT 24 | 5965640000 ps | ||
| T26 | /workspace/coverage/default/1.prim_present_test.405315366 | Apr 02 12:22:14 PM PDT 24 | Apr 02 12:22:33 PM PDT 24 | 3646840000 ps | ||
| T27 | /workspace/coverage/default/16.prim_present_test.3846008960 | Apr 02 12:22:48 PM PDT 24 | Apr 02 12:23:24 PM PDT 24 | 4612800000 ps | ||
| T28 | /workspace/coverage/default/39.prim_present_test.140019459 | Apr 02 12:19:17 PM PDT 24 | Apr 02 12:20:38 PM PDT 24 | 10402360000 ps | ||
| T29 | /workspace/coverage/default/29.prim_present_test.3235597525 | Apr 02 12:23:02 PM PDT 24 | Apr 02 12:23:52 PM PDT 24 | 6955780000 ps | ||
| T30 | /workspace/coverage/default/11.prim_present_test.1342633457 | Apr 02 12:21:09 PM PDT 24 | Apr 02 12:22:25 PM PDT 24 | 9894580000 ps | ||
| T31 | /workspace/coverage/default/20.prim_present_test.1892050308 | Apr 02 12:20:02 PM PDT 24 | Apr 02 12:21:01 PM PDT 24 | 6761100000 ps | ||
| T32 | /workspace/coverage/default/31.prim_present_test.3264589805 | Apr 02 12:23:04 PM PDT 24 | Apr 02 12:23:35 PM PDT 24 | 4086420000 ps | ||
| T33 | /workspace/coverage/default/9.prim_present_test.4267974290 | Apr 02 12:22:28 PM PDT 24 | Apr 02 12:23:18 PM PDT 24 | 7348860000 ps | ||
| T34 | /workspace/coverage/default/0.prim_present_test.1714985330 | Apr 02 12:22:31 PM PDT 24 | Apr 02 12:22:57 PM PDT 24 | 3366600000 ps | ||
| T35 | /workspace/coverage/default/14.prim_present_test.3820002033 | Apr 02 12:19:28 PM PDT 24 | Apr 02 12:20:32 PM PDT 24 | 7776040000 ps | ||
| T36 | /workspace/coverage/default/24.prim_present_test.1848863208 | Apr 02 12:22:42 PM PDT 24 | Apr 02 12:23:34 PM PDT 24 | 7813860000 ps | ||
| T37 | /workspace/coverage/default/5.prim_present_test.2534114704 | Apr 02 12:22:56 PM PDT 24 | Apr 02 12:23:47 PM PDT 24 | 8909400000 ps | ||
| T38 | /workspace/coverage/default/23.prim_present_test.3579052038 | Apr 02 12:22:48 PM PDT 24 | Apr 02 12:24:11 PM PDT 24 | 11231300000 ps | ||
| T39 | /workspace/coverage/default/38.prim_present_test.1764452138 | Apr 02 12:19:17 PM PDT 24 | Apr 02 12:19:56 PM PDT 24 | 4826700000 ps | ||
| T40 | /workspace/coverage/default/28.prim_present_test.1744512072 | Apr 02 12:22:53 PM PDT 24 | Apr 02 12:23:38 PM PDT 24 | 6606100000 ps | ||
| T41 | /workspace/coverage/default/43.prim_present_test.2793503568 | Apr 02 12:19:17 PM PDT 24 | Apr 02 12:20:32 PM PDT 24 | 10407940000 ps | ||
| T42 | /workspace/coverage/default/21.prim_present_test.1083448181 | Apr 02 12:22:48 PM PDT 24 | Apr 02 12:24:32 PM PDT 24 | 14296580000 ps | ||
| T43 | /workspace/coverage/default/33.prim_present_test.130924697 | Apr 02 12:23:04 PM PDT 24 | Apr 02 12:24:49 PM PDT 24 | 15159620000 ps | ||
| T44 | /workspace/coverage/default/46.prim_present_test.3807164963 | Apr 02 12:22:18 PM PDT 24 | Apr 02 12:24:07 PM PDT 24 | 15109400000 ps | ||
| T45 | /workspace/coverage/default/34.prim_present_test.909242650 | Apr 02 12:23:02 PM PDT 24 | Apr 02 12:24:24 PM PDT 24 | 11623760000 ps | ||
| T46 | /workspace/coverage/default/42.prim_present_test.2620683882 | Apr 02 12:19:09 PM PDT 24 | Apr 02 12:19:59 PM PDT 24 | 5988580000 ps | ||
| T47 | /workspace/coverage/default/17.prim_present_test.3577289877 | Apr 02 12:22:56 PM PDT 24 | Apr 02 12:24:18 PM PDT 24 | 12857560000 ps | ||
| T48 | /workspace/coverage/default/45.prim_present_test.1548180276 | Apr 02 12:22:31 PM PDT 24 | Apr 02 12:24:07 PM PDT 24 | 14100660000 ps | ||
| T49 | /workspace/coverage/default/3.prim_present_test.338947135 | Apr 02 12:22:21 PM PDT 24 | Apr 02 12:23:56 PM PDT 24 | 14251940000 ps | ||
| T50 | /workspace/coverage/default/18.prim_present_test.2228104610 | Apr 02 12:22:56 PM PDT 24 | Apr 02 12:23:40 PM PDT 24 | 6866500000 ps |
| Test location | /workspace/coverage/default/2.prim_present_test.1329823498 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 14482580000 ps |
| CPU time | 53.17 seconds |
| Started | Apr 02 12:22:20 PM PDT 24 |
| Finished | Apr 02 12:24:02 PM PDT 24 |
| Peak memory | 144768 kb |
| Host | smart-e8a6e136-df83-4bb8-99a0-99be5f7a9789 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1329823498 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.1329823498 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/0.prim_present_test.1714985330 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 3366600000 ps |
| CPU time | 13.64 seconds |
| Started | Apr 02 12:22:31 PM PDT 24 |
| Finished | Apr 02 12:22:57 PM PDT 24 |
| Peak memory | 144824 kb |
| Host | smart-9a65bb27-aaaa-4750-bffe-d34bd234fe31 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1714985330 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.1714985330 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/1.prim_present_test.405315366 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 3646840000 ps |
| CPU time | 10.61 seconds |
| Started | Apr 02 12:22:14 PM PDT 24 |
| Finished | Apr 02 12:22:33 PM PDT 24 |
| Peak memory | 143760 kb |
| Host | smart-a9e6dd41-4ad9-45fe-8bd7-d470707a5314 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=405315366 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.405315366 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/10.prim_present_test.2010010495 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 3124800000 ps |
| CPU time | 9.91 seconds |
| Started | Apr 02 12:22:15 PM PDT 24 |
| Finished | Apr 02 12:22:34 PM PDT 24 |
| Peak memory | 143872 kb |
| Host | smart-25ee9c02-34a0-49f6-9fc4-984789ea3e14 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2010010495 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.2010010495 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/11.prim_present_test.1342633457 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 9894580000 ps |
| CPU time | 39.53 seconds |
| Started | Apr 02 12:21:09 PM PDT 24 |
| Finished | Apr 02 12:22:25 PM PDT 24 |
| Peak memory | 145152 kb |
| Host | smart-c6eceb41-88c7-484f-918a-fc3f71d6d54a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1342633457 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.1342633457 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.1731634023 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 15204260000 ps |
| CPU time | 59.91 seconds |
| Started | Apr 02 12:22:16 PM PDT 24 |
| Finished | Apr 02 12:24:11 PM PDT 24 |
| Peak memory | 142908 kb |
| Host | smart-32138f90-0255-49fe-9970-590ab9bb0d97 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1731634023 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.1731634023 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.499031901 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 14937660000 ps |
| CPU time | 54.52 seconds |
| Started | Apr 02 12:20:01 PM PDT 24 |
| Finished | Apr 02 12:21:44 PM PDT 24 |
| Peak memory | 145020 kb |
| Host | smart-7795d777-3c5b-461b-ad6d-9e5c3823fb10 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=499031901 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.499031901 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.3820002033 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 7776040000 ps |
| CPU time | 32.83 seconds |
| Started | Apr 02 12:19:28 PM PDT 24 |
| Finished | Apr 02 12:20:32 PM PDT 24 |
| Peak memory | 145148 kb |
| Host | smart-dd79d7fd-6919-455b-9838-34f97782d5b5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3820002033 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.3820002033 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.110455558 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 6882000000 ps |
| CPU time | 27.5 seconds |
| Started | Apr 02 12:22:16 PM PDT 24 |
| Finished | Apr 02 12:23:09 PM PDT 24 |
| Peak memory | 142800 kb |
| Host | smart-50209fd1-8f59-427a-a984-02fba38231d5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=110455558 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.110455558 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.3846008960 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 4612800000 ps |
| CPU time | 18.57 seconds |
| Started | Apr 02 12:22:48 PM PDT 24 |
| Finished | Apr 02 12:23:24 PM PDT 24 |
| Peak memory | 142968 kb |
| Host | smart-70dce929-380c-463b-97f0-599fc193ecd4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3846008960 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.3846008960 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.3577289877 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 12857560000 ps |
| CPU time | 43.72 seconds |
| Started | Apr 02 12:22:56 PM PDT 24 |
| Finished | Apr 02 12:24:18 PM PDT 24 |
| Peak memory | 144776 kb |
| Host | smart-0bbb25d9-4e02-4886-88ca-b59ed9aa4f28 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3577289877 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.3577289877 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.2228104610 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 6866500000 ps |
| CPU time | 23.78 seconds |
| Started | Apr 02 12:22:56 PM PDT 24 |
| Finished | Apr 02 12:23:40 PM PDT 24 |
| Peak memory | 144776 kb |
| Host | smart-11fd28e1-c11d-4bb6-9e5d-28e33dbcafe6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2228104610 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.2228104610 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.2955881558 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 5965640000 ps |
| CPU time | 21.7 seconds |
| Started | Apr 02 12:22:56 PM PDT 24 |
| Finished | Apr 02 12:23:36 PM PDT 24 |
| Peak memory | 144776 kb |
| Host | smart-15ee5e16-4b1d-4e2b-aacd-1677f7f3e155 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2955881558 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.2955881558 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.1892050308 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 6761100000 ps |
| CPU time | 30.34 seconds |
| Started | Apr 02 12:20:02 PM PDT 24 |
| Finished | Apr 02 12:21:01 PM PDT 24 |
| Peak memory | 145160 kb |
| Host | smart-501d2560-5b00-4638-b7a2-9c617502fbea |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1892050308 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.1892050308 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.1083448181 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 14296580000 ps |
| CPU time | 54.33 seconds |
| Started | Apr 02 12:22:48 PM PDT 24 |
| Finished | Apr 02 12:24:32 PM PDT 24 |
| Peak memory | 142664 kb |
| Host | smart-af4c09a7-c538-4322-ba0a-a7e2958cbcfd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1083448181 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.1083448181 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.2019272932 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 3297160000 ps |
| CPU time | 13.92 seconds |
| Started | Apr 02 12:22:48 PM PDT 24 |
| Finished | Apr 02 12:23:15 PM PDT 24 |
| Peak memory | 142704 kb |
| Host | smart-9c71c61a-c519-4e0a-9b64-0749940000b9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2019272932 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.2019272932 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.3579052038 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 11231300000 ps |
| CPU time | 43.14 seconds |
| Started | Apr 02 12:22:48 PM PDT 24 |
| Finished | Apr 02 12:24:11 PM PDT 24 |
| Peak memory | 142712 kb |
| Host | smart-6ece460a-db21-4827-9351-cdcad8d06d47 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3579052038 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.3579052038 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.1848863208 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 7813860000 ps |
| CPU time | 28.07 seconds |
| Started | Apr 02 12:22:42 PM PDT 24 |
| Finished | Apr 02 12:23:34 PM PDT 24 |
| Peak memory | 144868 kb |
| Host | smart-52cb5ba2-c74c-4468-bb6c-b173cb5041a9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1848863208 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.1848863208 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.170098708 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 4258780000 ps |
| CPU time | 17.59 seconds |
| Started | Apr 02 12:20:52 PM PDT 24 |
| Finished | Apr 02 12:21:25 PM PDT 24 |
| Peak memory | 144988 kb |
| Host | smart-d5a9bdc0-0738-4c42-bcc8-001b3fce2e3e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=170098708 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.170098708 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.4019211860 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 10659040000 ps |
| CPU time | 36.31 seconds |
| Started | Apr 02 12:22:41 PM PDT 24 |
| Finished | Apr 02 12:23:48 PM PDT 24 |
| Peak memory | 144928 kb |
| Host | smart-cccc91a2-ec5e-4065-b11f-cccf3c1de582 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4019211860 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.4019211860 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.4253540732 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 7172780000 ps |
| CPU time | 27.15 seconds |
| Started | Apr 02 12:22:29 PM PDT 24 |
| Finished | Apr 02 12:23:20 PM PDT 24 |
| Peak memory | 143136 kb |
| Host | smart-d31f6223-f523-4ff7-bf8d-f8a2aff14df3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4253540732 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.4253540732 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.1744512072 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 6606100000 ps |
| CPU time | 23.86 seconds |
| Started | Apr 02 12:22:53 PM PDT 24 |
| Finished | Apr 02 12:23:38 PM PDT 24 |
| Peak memory | 143788 kb |
| Host | smart-272dadfe-236a-42ef-b8a5-089694cda152 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1744512072 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.1744512072 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.3235597525 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 6955780000 ps |
| CPU time | 26.03 seconds |
| Started | Apr 02 12:23:02 PM PDT 24 |
| Finished | Apr 02 12:23:52 PM PDT 24 |
| Peak memory | 144656 kb |
| Host | smart-6da8a895-d2ce-4f8d-ac06-8bac4b22726d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3235597525 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.3235597525 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.338947135 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 14251940000 ps |
| CPU time | 50.69 seconds |
| Started | Apr 02 12:22:21 PM PDT 24 |
| Finished | Apr 02 12:23:56 PM PDT 24 |
| Peak memory | 144564 kb |
| Host | smart-10cb99e5-c809-4c58-b694-40a4b922eff1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=338947135 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.338947135 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.3264698583 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 13343020000 ps |
| CPU time | 46.9 seconds |
| Started | Apr 02 12:22:53 PM PDT 24 |
| Finished | Apr 02 12:24:20 PM PDT 24 |
| Peak memory | 143756 kb |
| Host | smart-fdf49804-a950-4295-a0a7-34898914042c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3264698583 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.3264698583 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.3264589805 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 4086420000 ps |
| CPU time | 16.42 seconds |
| Started | Apr 02 12:23:04 PM PDT 24 |
| Finished | Apr 02 12:23:35 PM PDT 24 |
| Peak memory | 145152 kb |
| Host | smart-ac4a9c3f-2187-433c-9b29-d99a6f24268c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3264589805 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.3264589805 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.848382083 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 14077100000 ps |
| CPU time | 50.87 seconds |
| Started | Apr 02 12:23:04 PM PDT 24 |
| Finished | Apr 02 12:24:41 PM PDT 24 |
| Peak memory | 144720 kb |
| Host | smart-f8f9469f-39bc-499b-a0bb-35b11e5fdc1f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=848382083 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.848382083 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.130924697 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 15159620000 ps |
| CPU time | 54.78 seconds |
| Started | Apr 02 12:23:04 PM PDT 24 |
| Finished | Apr 02 12:24:49 PM PDT 24 |
| Peak memory | 144720 kb |
| Host | smart-6ab2af0d-42d3-4846-8c17-b48f69a33457 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=130924697 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.130924697 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.909242650 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 11623760000 ps |
| CPU time | 43.13 seconds |
| Started | Apr 02 12:23:02 PM PDT 24 |
| Finished | Apr 02 12:24:24 PM PDT 24 |
| Peak memory | 144632 kb |
| Host | smart-8e11e62f-4eb7-4c99-bf96-9b2ab24a3b0b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=909242650 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.909242650 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.1063367848 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 9965880000 ps |
| CPU time | 41.48 seconds |
| Started | Apr 02 12:18:57 PM PDT 24 |
| Finished | Apr 02 12:20:17 PM PDT 24 |
| Peak memory | 145144 kb |
| Host | smart-9f6e29e5-53a7-45a9-b8d0-9b7abe73bcf3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1063367848 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.1063367848 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.1780616018 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 9773060000 ps |
| CPU time | 28.42 seconds |
| Started | Apr 02 12:18:43 PM PDT 24 |
| Finished | Apr 02 12:19:35 PM PDT 24 |
| Peak memory | 145264 kb |
| Host | smart-bc3ff74e-8ae9-4233-92b0-b66f3304b5b0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1780616018 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.1780616018 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.914177048 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 4718200000 ps |
| CPU time | 19.66 seconds |
| Started | Apr 02 12:19:07 PM PDT 24 |
| Finished | Apr 02 12:19:45 PM PDT 24 |
| Peak memory | 145144 kb |
| Host | smart-d28a4cac-f2a1-418c-94f9-01d22430dd23 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=914177048 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.914177048 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.1764452138 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 4826700000 ps |
| CPU time | 20.34 seconds |
| Started | Apr 02 12:19:17 PM PDT 24 |
| Finished | Apr 02 12:19:56 PM PDT 24 |
| Peak memory | 145144 kb |
| Host | smart-ac86cce9-a423-41e0-9158-22aa800c6cca |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1764452138 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.1764452138 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.140019459 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 10402360000 ps |
| CPU time | 42.62 seconds |
| Started | Apr 02 12:19:17 PM PDT 24 |
| Finished | Apr 02 12:20:38 PM PDT 24 |
| Peak memory | 145144 kb |
| Host | smart-a820a3db-33ea-4da1-aa82-a783c855ded0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=140019459 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.140019459 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.1899707606 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 5452280000 ps |
| CPU time | 21.26 seconds |
| Started | Apr 02 12:20:35 PM PDT 24 |
| Finished | Apr 02 12:21:15 PM PDT 24 |
| Peak memory | 145148 kb |
| Host | smart-b0b47c58-0278-410c-8e56-6f5a8c188704 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1899707606 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.1899707606 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.1006556266 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 10860540000 ps |
| CPU time | 43.86 seconds |
| Started | Apr 02 12:21:23 PM PDT 24 |
| Finished | Apr 02 12:22:45 PM PDT 24 |
| Peak memory | 145148 kb |
| Host | smart-7bcbacfc-5c20-446a-88a3-369be15b3329 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1006556266 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.1006556266 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.3226916002 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 9550480000 ps |
| CPU time | 41.74 seconds |
| Started | Apr 02 12:19:11 PM PDT 24 |
| Finished | Apr 02 12:20:32 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-5c7378dd-2f0f-4d5c-9639-4a2a0fccdf6b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3226916002 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.3226916002 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.2620683882 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 5988580000 ps |
| CPU time | 25.75 seconds |
| Started | Apr 02 12:19:09 PM PDT 24 |
| Finished | Apr 02 12:19:59 PM PDT 24 |
| Peak memory | 145136 kb |
| Host | smart-990f85c8-6a19-4916-9a58-530860e3e8d7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2620683882 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.2620683882 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.2793503568 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 10407940000 ps |
| CPU time | 39.84 seconds |
| Started | Apr 02 12:19:17 PM PDT 24 |
| Finished | Apr 02 12:20:32 PM PDT 24 |
| Peak memory | 145152 kb |
| Host | smart-79976d4b-48da-429b-88de-f358f1785b17 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2793503568 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.2793503568 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.3162182899 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 3599720000 ps |
| CPU time | 13.77 seconds |
| Started | Apr 02 12:19:04 PM PDT 24 |
| Finished | Apr 02 12:19:31 PM PDT 24 |
| Peak memory | 144976 kb |
| Host | smart-dfb79cef-71eb-46fc-9f04-2408aeb064a2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3162182899 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.3162182899 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.1548180276 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 14100660000 ps |
| CPU time | 50.99 seconds |
| Started | Apr 02 12:22:31 PM PDT 24 |
| Finished | Apr 02 12:24:07 PM PDT 24 |
| Peak memory | 144968 kb |
| Host | smart-7bf0234c-d4d2-4b5f-8e44-9d1005e3786a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1548180276 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.1548180276 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.3807164963 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 15109400000 ps |
| CPU time | 56 seconds |
| Started | Apr 02 12:22:18 PM PDT 24 |
| Finished | Apr 02 12:24:07 PM PDT 24 |
| Peak memory | 143100 kb |
| Host | smart-06f9a9c3-6a9a-4f38-8650-f1042da858e5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3807164963 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.3807164963 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.1293782850 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 7872760000 ps |
| CPU time | 28.95 seconds |
| Started | Apr 02 12:20:58 PM PDT 24 |
| Finished | Apr 02 12:21:53 PM PDT 24 |
| Peak memory | 145012 kb |
| Host | smart-b7548740-9424-4d25-896b-ba33d4bee184 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1293782850 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.1293782850 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.1693843190 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 8203220000 ps |
| CPU time | 31.17 seconds |
| Started | Apr 02 12:22:30 PM PDT 24 |
| Finished | Apr 02 12:23:29 PM PDT 24 |
| Peak memory | 144972 kb |
| Host | smart-17139c8e-225d-463e-9d56-847d43373449 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1693843190 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.1693843190 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.2992670891 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 13026820000 ps |
| CPU time | 47.19 seconds |
| Started | Apr 02 12:22:22 PM PDT 24 |
| Finished | Apr 02 12:23:51 PM PDT 24 |
| Peak memory | 144828 kb |
| Host | smart-d8e3bc1f-16a4-4cd4-afc5-fa8928cf802e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2992670891 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.2992670891 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.2534114704 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 8909400000 ps |
| CPU time | 27.8 seconds |
| Started | Apr 02 12:22:56 PM PDT 24 |
| Finished | Apr 02 12:23:47 PM PDT 24 |
| Peak memory | 144492 kb |
| Host | smart-fdcb9305-8c4e-45bd-b862-12c6af19f633 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2534114704 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.2534114704 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.4052562233 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 12282820000 ps |
| CPU time | 42.3 seconds |
| Started | Apr 02 12:18:21 PM PDT 24 |
| Finished | Apr 02 12:19:40 PM PDT 24 |
| Peak memory | 144964 kb |
| Host | smart-bd52ac3c-7c53-4756-b18a-0973ab23e338 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4052562233 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.4052562233 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.2314553024 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 4426800000 ps |
| CPU time | 17.79 seconds |
| Started | Apr 02 12:22:16 PM PDT 24 |
| Finished | Apr 02 12:22:51 PM PDT 24 |
| Peak memory | 143276 kb |
| Host | smart-c02ba925-f693-4033-aecf-b9e65c1a4d6a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2314553024 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.2314553024 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.1993612201 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 13449040000 ps |
| CPU time | 48.85 seconds |
| Started | Apr 02 12:22:28 PM PDT 24 |
| Finished | Apr 02 12:23:59 PM PDT 24 |
| Peak memory | 144740 kb |
| Host | smart-424193f0-1175-40c3-a7cf-1a13c58b70d9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1993612201 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.1993612201 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.4267974290 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 7348860000 ps |
| CPU time | 26.25 seconds |
| Started | Apr 02 12:22:28 PM PDT 24 |
| Finished | Apr 02 12:23:18 PM PDT 24 |
| Peak memory | 144744 kb |
| Host | smart-f5687fdf-4f6a-4af0-90fb-296f0897644e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4267974290 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.4267974290 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |