| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/0.prim_present_test.3456289398 | ||
| Name |
|---|
| /workspace/coverage/default/1.prim_present_test.3022809677 |
| /workspace/coverage/default/10.prim_present_test.691281313 |
| /workspace/coverage/default/11.prim_present_test.1716827854 |
| /workspace/coverage/default/12.prim_present_test.1618383545 |
| /workspace/coverage/default/13.prim_present_test.822629561 |
| /workspace/coverage/default/14.prim_present_test.2608818061 |
| /workspace/coverage/default/15.prim_present_test.373460743 |
| /workspace/coverage/default/16.prim_present_test.1371463792 |
| /workspace/coverage/default/17.prim_present_test.1770971808 |
| /workspace/coverage/default/18.prim_present_test.323477562 |
| /workspace/coverage/default/19.prim_present_test.3082033257 |
| /workspace/coverage/default/2.prim_present_test.231898233 |
| /workspace/coverage/default/20.prim_present_test.1151658709 |
| /workspace/coverage/default/21.prim_present_test.1898327317 |
| /workspace/coverage/default/22.prim_present_test.3383936933 |
| /workspace/coverage/default/23.prim_present_test.3257196680 |
| /workspace/coverage/default/24.prim_present_test.2343520019 |
| /workspace/coverage/default/25.prim_present_test.1150069745 |
| /workspace/coverage/default/26.prim_present_test.3291289854 |
| /workspace/coverage/default/27.prim_present_test.420429170 |
| /workspace/coverage/default/28.prim_present_test.3303213662 |
| /workspace/coverage/default/29.prim_present_test.3674673340 |
| /workspace/coverage/default/3.prim_present_test.779057631 |
| /workspace/coverage/default/30.prim_present_test.1341170464 |
| /workspace/coverage/default/31.prim_present_test.2117479233 |
| /workspace/coverage/default/32.prim_present_test.1118215419 |
| /workspace/coverage/default/33.prim_present_test.3566013694 |
| /workspace/coverage/default/34.prim_present_test.621683874 |
| /workspace/coverage/default/35.prim_present_test.3273525874 |
| /workspace/coverage/default/36.prim_present_test.426827774 |
| /workspace/coverage/default/37.prim_present_test.1063228520 |
| /workspace/coverage/default/38.prim_present_test.2739653142 |
| /workspace/coverage/default/39.prim_present_test.309578191 |
| /workspace/coverage/default/4.prim_present_test.1716764352 |
| /workspace/coverage/default/40.prim_present_test.526031264 |
| /workspace/coverage/default/41.prim_present_test.1420485411 |
| /workspace/coverage/default/42.prim_present_test.97676222 |
| /workspace/coverage/default/43.prim_present_test.4222617092 |
| /workspace/coverage/default/44.prim_present_test.947585617 |
| /workspace/coverage/default/45.prim_present_test.1310625086 |
| /workspace/coverage/default/46.prim_present_test.3398887020 |
| /workspace/coverage/default/47.prim_present_test.2488564718 |
| /workspace/coverage/default/48.prim_present_test.1926913057 |
| /workspace/coverage/default/49.prim_present_test.1432542783 |
| /workspace/coverage/default/5.prim_present_test.974290526 |
| /workspace/coverage/default/6.prim_present_test.340155657 |
| /workspace/coverage/default/7.prim_present_test.1809659168 |
| /workspace/coverage/default/8.prim_present_test.3683026986 |
| /workspace/coverage/default/9.prim_present_test.2437981275 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/2.prim_present_test.231898233 | Apr 04 02:03:51 PM PDT 24 | Apr 04 02:04:59 PM PDT 24 | 10938660000 ps | ||
| T2 | /workspace/coverage/default/16.prim_present_test.1371463792 | Apr 04 02:03:55 PM PDT 24 | Apr 04 02:05:42 PM PDT 24 | 14307120000 ps | ||
| T3 | /workspace/coverage/default/3.prim_present_test.779057631 | Apr 04 02:03:53 PM PDT 24 | Apr 04 02:05:01 PM PDT 24 | 12254920000 ps | ||
| T4 | /workspace/coverage/default/47.prim_present_test.2488564718 | Apr 04 02:04:04 PM PDT 24 | Apr 04 02:05:31 PM PDT 24 | 13751600000 ps | ||
| T5 | /workspace/coverage/default/21.prim_present_test.1898327317 | Apr 04 02:03:54 PM PDT 24 | Apr 04 02:04:42 PM PDT 24 | 5651300000 ps | ||
| T6 | /workspace/coverage/default/40.prim_present_test.526031264 | Apr 04 02:03:58 PM PDT 24 | Apr 04 02:04:50 PM PDT 24 | 7900040000 ps | ||
| T7 | /workspace/coverage/default/20.prim_present_test.1151658709 | Apr 04 02:03:51 PM PDT 24 | Apr 04 02:05:06 PM PDT 24 | 12157580000 ps | ||
| T8 | /workspace/coverage/default/10.prim_present_test.691281313 | Apr 04 02:03:52 PM PDT 24 | Apr 04 02:04:29 PM PDT 24 | 4772760000 ps | ||
| T9 | /workspace/coverage/default/13.prim_present_test.822629561 | Apr 04 02:03:51 PM PDT 24 | Apr 04 02:05:10 PM PDT 24 | 12694500000 ps | ||
| T10 | /workspace/coverage/default/0.prim_present_test.3456289398 | Apr 04 02:03:56 PM PDT 24 | Apr 04 02:04:27 PM PDT 24 | 6081580000 ps | ||
| T11 | /workspace/coverage/default/38.prim_present_test.2739653142 | Apr 04 02:04:00 PM PDT 24 | Apr 04 02:04:37 PM PDT 24 | 6619120000 ps | ||
| T12 | /workspace/coverage/default/15.prim_present_test.373460743 | Apr 04 02:03:53 PM PDT 24 | Apr 04 02:05:06 PM PDT 24 | 12979700000 ps | ||
| T13 | /workspace/coverage/default/49.prim_present_test.1432542783 | Apr 04 02:04:00 PM PDT 24 | Apr 04 02:04:53 PM PDT 24 | 6459780000 ps | ||
| T14 | /workspace/coverage/default/35.prim_present_test.3273525874 | Apr 04 02:03:58 PM PDT 24 | Apr 04 02:05:01 PM PDT 24 | 9231800000 ps | ||
| T15 | /workspace/coverage/default/37.prim_present_test.1063228520 | Apr 04 02:04:01 PM PDT 24 | Apr 04 02:04:45 PM PDT 24 | 5527300000 ps | ||
| T16 | /workspace/coverage/default/33.prim_present_test.3566013694 | Apr 04 02:04:00 PM PDT 24 | Apr 04 02:05:10 PM PDT 24 | 13427960000 ps | ||
| T17 | /workspace/coverage/default/28.prim_present_test.3303213662 | Apr 04 02:04:01 PM PDT 24 | Apr 04 02:05:06 PM PDT 24 | 9743920000 ps | ||
| T18 | /workspace/coverage/default/45.prim_present_test.1310625086 | Apr 04 02:04:01 PM PDT 24 | Apr 04 02:05:13 PM PDT 24 | 10986400000 ps | ||
| T19 | /workspace/coverage/default/39.prim_present_test.309578191 | Apr 04 02:04:00 PM PDT 24 | Apr 04 02:05:13 PM PDT 24 | 13532120000 ps | ||
| T20 | /workspace/coverage/default/7.prim_present_test.1809659168 | Apr 04 02:03:52 PM PDT 24 | Apr 04 02:04:52 PM PDT 24 | 7638400000 ps | ||
| T21 | /workspace/coverage/default/41.prim_present_test.1420485411 | Apr 04 02:04:01 PM PDT 24 | Apr 04 02:05:38 PM PDT 24 | 12288400000 ps | ||
| T22 | /workspace/coverage/default/44.prim_present_test.947585617 | Apr 04 02:04:01 PM PDT 24 | Apr 04 02:04:45 PM PDT 24 | 6505660000 ps | ||
| T23 | /workspace/coverage/default/24.prim_present_test.2343520019 | Apr 04 02:03:57 PM PDT 24 | Apr 04 02:05:19 PM PDT 24 | 13072700000 ps | ||
| T24 | /workspace/coverage/default/5.prim_present_test.974290526 | Apr 04 02:03:52 PM PDT 24 | Apr 04 02:05:36 PM PDT 24 | 15428080000 ps | ||
| T25 | /workspace/coverage/default/17.prim_present_test.1770971808 | Apr 04 02:03:57 PM PDT 24 | Apr 04 02:05:40 PM PDT 24 | 14103760000 ps | ||
| T26 | /workspace/coverage/default/11.prim_present_test.1716827854 | Apr 04 02:03:57 PM PDT 24 | Apr 04 02:05:35 PM PDT 24 | 13584820000 ps | ||
| T27 | /workspace/coverage/default/43.prim_present_test.4222617092 | Apr 04 02:03:58 PM PDT 24 | Apr 04 02:05:28 PM PDT 24 | 12434720000 ps | ||
| T28 | /workspace/coverage/default/48.prim_present_test.1926913057 | Apr 04 02:04:00 PM PDT 24 | Apr 04 02:05:36 PM PDT 24 | 12006920000 ps | ||
| T29 | /workspace/coverage/default/25.prim_present_test.1150069745 | Apr 04 02:03:56 PM PDT 24 | Apr 04 02:04:57 PM PDT 24 | 8354500000 ps | ||
| T30 | /workspace/coverage/default/36.prim_present_test.426827774 | Apr 04 02:03:58 PM PDT 24 | Apr 04 02:04:56 PM PDT 24 | 8450600000 ps | ||
| T31 | /workspace/coverage/default/12.prim_present_test.1618383545 | Apr 04 02:03:54 PM PDT 24 | Apr 04 02:04:19 PM PDT 24 | 3193620000 ps | ||
| T32 | /workspace/coverage/default/14.prim_present_test.2608818061 | Apr 04 02:03:53 PM PDT 24 | Apr 04 02:04:48 PM PDT 24 | 8306140000 ps | ||
| T33 | /workspace/coverage/default/34.prim_present_test.621683874 | Apr 04 02:03:57 PM PDT 24 | Apr 04 02:04:29 PM PDT 24 | 5810640000 ps | ||
| T34 | /workspace/coverage/default/9.prim_present_test.2437981275 | Apr 04 02:03:54 PM PDT 24 | Apr 04 02:05:13 PM PDT 24 | 13011940000 ps | ||
| T35 | /workspace/coverage/default/46.prim_present_test.3398887020 | Apr 04 02:03:59 PM PDT 24 | Apr 04 02:05:14 PM PDT 24 | 11148840000 ps | ||
| T36 | /workspace/coverage/default/18.prim_present_test.323477562 | Apr 04 02:03:54 PM PDT 24 | Apr 04 02:04:59 PM PDT 24 | 11609500000 ps | ||
| T37 | /workspace/coverage/default/30.prim_present_test.1341170464 | Apr 04 02:03:59 PM PDT 24 | Apr 04 02:04:54 PM PDT 24 | 9079280000 ps | ||
| T38 | /workspace/coverage/default/31.prim_present_test.2117479233 | Apr 04 02:04:01 PM PDT 24 | Apr 04 02:05:19 PM PDT 24 | 13602180000 ps | ||
| T39 | /workspace/coverage/default/4.prim_present_test.1716764352 | Apr 04 02:03:51 PM PDT 24 | Apr 04 02:04:53 PM PDT 24 | 8102780000 ps | ||
| T40 | /workspace/coverage/default/22.prim_present_test.3383936933 | Apr 04 02:03:52 PM PDT 24 | Apr 04 02:04:38 PM PDT 24 | 7529900000 ps | ||
| T41 | /workspace/coverage/default/27.prim_present_test.420429170 | Apr 04 02:04:00 PM PDT 24 | Apr 04 02:05:29 PM PDT 24 | 15033760000 ps | ||
| T42 | /workspace/coverage/default/42.prim_present_test.97676222 | Apr 04 02:04:00 PM PDT 24 | Apr 04 02:05:24 PM PDT 24 | 14205440000 ps | ||
| T43 | /workspace/coverage/default/8.prim_present_test.3683026986 | Apr 04 02:03:52 PM PDT 24 | Apr 04 02:05:20 PM PDT 24 | 12888560000 ps | ||
| T44 | /workspace/coverage/default/1.prim_present_test.3022809677 | Apr 04 02:03:52 PM PDT 24 | Apr 04 02:05:13 PM PDT 24 | 14491260000 ps | ||
| T45 | /workspace/coverage/default/29.prim_present_test.3674673340 | Apr 04 02:03:57 PM PDT 24 | Apr 04 02:04:52 PM PDT 24 | 8503300000 ps | ||
| T46 | /workspace/coverage/default/23.prim_present_test.3257196680 | Apr 04 02:03:52 PM PDT 24 | Apr 04 02:04:27 PM PDT 24 | 5931540000 ps | ||
| T47 | /workspace/coverage/default/19.prim_present_test.3082033257 | Apr 04 02:03:53 PM PDT 24 | Apr 04 02:04:14 PM PDT 24 | 4209800000 ps | ||
| T48 | /workspace/coverage/default/32.prim_present_test.1118215419 | Apr 04 02:04:00 PM PDT 24 | Apr 04 02:04:29 PM PDT 24 | 3796880000 ps | ||
| T49 | /workspace/coverage/default/26.prim_present_test.3291289854 | Apr 04 02:04:00 PM PDT 24 | Apr 04 02:04:49 PM PDT 24 | 7227960000 ps | ||
| T50 | /workspace/coverage/default/6.prim_present_test.340155657 | Apr 04 02:03:55 PM PDT 24 | Apr 04 02:05:47 PM PDT 24 | 15196820000 ps |
| Test location | /workspace/coverage/default/0.prim_present_test.3456289398 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 6081580000 ps |
| CPU time | 16.93 seconds |
| Started | Apr 04 02:03:56 PM PDT 24 |
| Finished | Apr 04 02:04:27 PM PDT 24 |
| Peak memory | 145120 kb |
| Host | smart-38efc6b3-233d-42c8-abfb-9c54d65f523b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3456289398 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.3456289398 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/1.prim_present_test.3022809677 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 14491260000 ps |
| CPU time | 43.41 seconds |
| Started | Apr 04 02:03:52 PM PDT 24 |
| Finished | Apr 04 02:05:13 PM PDT 24 |
| Peak memory | 145120 kb |
| Host | smart-6ed9e041-6dd9-42e2-b7e2-ea5a8c3dc81e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3022809677 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.3022809677 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/10.prim_present_test.691281313 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 4772760000 ps |
| CPU time | 18.39 seconds |
| Started | Apr 04 02:03:52 PM PDT 24 |
| Finished | Apr 04 02:04:29 PM PDT 24 |
| Peak memory | 145200 kb |
| Host | smart-202f5feb-121d-4f62-bd61-aa617e893b00 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=691281313 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.691281313 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/11.prim_present_test.1716827854 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 13584820000 ps |
| CPU time | 51.59 seconds |
| Started | Apr 04 02:03:57 PM PDT 24 |
| Finished | Apr 04 02:05:35 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-2c32c938-f162-48ab-a54f-f0a550f44da7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1716827854 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.1716827854 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.1618383545 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 3193620000 ps |
| CPU time | 12.5 seconds |
| Started | Apr 04 02:03:54 PM PDT 24 |
| Finished | Apr 04 02:04:19 PM PDT 24 |
| Peak memory | 145020 kb |
| Host | smart-3032fca2-6238-4ec9-b61b-f0c385e3b9d8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1618383545 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.1618383545 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.822629561 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 12694500000 ps |
| CPU time | 42.11 seconds |
| Started | Apr 04 02:03:51 PM PDT 24 |
| Finished | Apr 04 02:05:10 PM PDT 24 |
| Peak memory | 145048 kb |
| Host | smart-7d69a829-3317-4a66-844c-4ccd653776e3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=822629561 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.822629561 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.2608818061 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 8306140000 ps |
| CPU time | 28.77 seconds |
| Started | Apr 04 02:03:53 PM PDT 24 |
| Finished | Apr 04 02:04:48 PM PDT 24 |
| Peak memory | 145164 kb |
| Host | smart-5b35acfe-7034-47ea-9adf-cf61f48c6cd3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2608818061 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.2608818061 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.373460743 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 12979700000 ps |
| CPU time | 39.09 seconds |
| Started | Apr 04 02:03:53 PM PDT 24 |
| Finished | Apr 04 02:05:06 PM PDT 24 |
| Peak memory | 145208 kb |
| Host | smart-6cbc540f-7878-458c-87f9-404db06250dd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=373460743 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.373460743 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.1371463792 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 14307120000 ps |
| CPU time | 54.9 seconds |
| Started | Apr 04 02:03:55 PM PDT 24 |
| Finished | Apr 04 02:05:42 PM PDT 24 |
| Peak memory | 145164 kb |
| Host | smart-85cc01d7-945c-4279-b110-4dc9d6ad828b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1371463792 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.1371463792 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.1770971808 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 14103760000 ps |
| CPU time | 53.94 seconds |
| Started | Apr 04 02:03:57 PM PDT 24 |
| Finished | Apr 04 02:05:40 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-5564ab44-0f0b-4031-969f-6ab75961cd30 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1770971808 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.1770971808 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.323477562 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 11609500000 ps |
| CPU time | 35.2 seconds |
| Started | Apr 04 02:03:54 PM PDT 24 |
| Finished | Apr 04 02:04:59 PM PDT 24 |
| Peak memory | 145164 kb |
| Host | smart-6a9abbc0-a33d-4a21-8203-4ca58d5b106a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=323477562 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.323477562 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.3082033257 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 4209800000 ps |
| CPU time | 11.98 seconds |
| Started | Apr 04 02:03:53 PM PDT 24 |
| Finished | Apr 04 02:04:14 PM PDT 24 |
| Peak memory | 144984 kb |
| Host | smart-35522d08-9952-480d-bab8-828d66fac3ed |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3082033257 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.3082033257 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.231898233 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 10938660000 ps |
| CPU time | 37.46 seconds |
| Started | Apr 04 02:03:51 PM PDT 24 |
| Finished | Apr 04 02:04:59 PM PDT 24 |
| Peak memory | 145096 kb |
| Host | smart-892d25fb-ec1a-4c96-a727-8cef9bda833f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=231898233 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.231898233 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.1151658709 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 12157580000 ps |
| CPU time | 40.25 seconds |
| Started | Apr 04 02:03:51 PM PDT 24 |
| Finished | Apr 04 02:05:06 PM PDT 24 |
| Peak memory | 145076 kb |
| Host | smart-3a24fe48-35c9-4b28-9889-fbc35b149348 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1151658709 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.1151658709 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.1898327317 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 5651300000 ps |
| CPU time | 25.74 seconds |
| Started | Apr 04 02:03:54 PM PDT 24 |
| Finished | Apr 04 02:04:42 PM PDT 24 |
| Peak memory | 145140 kb |
| Host | smart-f2812bc2-0841-48a0-9e66-c769b687ddc4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1898327317 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.1898327317 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.3383936933 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 7529900000 ps |
| CPU time | 24.21 seconds |
| Started | Apr 04 02:03:52 PM PDT 24 |
| Finished | Apr 04 02:04:38 PM PDT 24 |
| Peak memory | 145256 kb |
| Host | smart-047877a6-7258-4dd7-82bc-1d75ee922a5c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3383936933 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.3383936933 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.3257196680 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 5931540000 ps |
| CPU time | 18.75 seconds |
| Started | Apr 04 02:03:52 PM PDT 24 |
| Finished | Apr 04 02:04:27 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-2ac8439d-1b0f-4495-867d-119cb2834c3e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3257196680 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.3257196680 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.2343520019 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 13072700000 ps |
| CPU time | 42.12 seconds |
| Started | Apr 04 02:03:57 PM PDT 24 |
| Finished | Apr 04 02:05:19 PM PDT 24 |
| Peak memory | 145152 kb |
| Host | smart-993bc600-2611-44c4-8b3c-6f6d721da60e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2343520019 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.2343520019 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.1150069745 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 8354500000 ps |
| CPU time | 30.34 seconds |
| Started | Apr 04 02:03:56 PM PDT 24 |
| Finished | Apr 04 02:04:57 PM PDT 24 |
| Peak memory | 145204 kb |
| Host | smart-183af51c-5b5d-499a-be5a-9608215d0af6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1150069745 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.1150069745 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.3291289854 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 7227960000 ps |
| CPU time | 26.14 seconds |
| Started | Apr 04 02:04:00 PM PDT 24 |
| Finished | Apr 04 02:04:49 PM PDT 24 |
| Peak memory | 145088 kb |
| Host | smart-eeb538fa-5e39-4a14-9b6d-3068eef59336 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3291289854 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.3291289854 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.420429170 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 15033760000 ps |
| CPU time | 47.28 seconds |
| Started | Apr 04 02:04:00 PM PDT 24 |
| Finished | Apr 04 02:05:29 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-e0a3d43f-a1a3-41f3-925a-055c576acc97 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=420429170 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.420429170 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.3303213662 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 9743920000 ps |
| CPU time | 33.21 seconds |
| Started | Apr 04 02:04:01 PM PDT 24 |
| Finished | Apr 04 02:05:06 PM PDT 24 |
| Peak memory | 145164 kb |
| Host | smart-77a8f605-10d7-41fc-a1a5-b873f0c23bd6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3303213662 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.3303213662 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.3674673340 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 8503300000 ps |
| CPU time | 28.09 seconds |
| Started | Apr 04 02:03:57 PM PDT 24 |
| Finished | Apr 04 02:04:52 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-3019bab9-1a0e-40bd-92d0-0329fff86f02 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3674673340 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.3674673340 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.779057631 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 12254920000 ps |
| CPU time | 36.61 seconds |
| Started | Apr 04 02:03:53 PM PDT 24 |
| Finished | Apr 04 02:05:01 PM PDT 24 |
| Peak memory | 145164 kb |
| Host | smart-597cc840-30b6-4378-9d78-8fa1b6c3ff51 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=779057631 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.779057631 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.1341170464 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 9079280000 ps |
| CPU time | 29.13 seconds |
| Started | Apr 04 02:03:59 PM PDT 24 |
| Finished | Apr 04 02:04:54 PM PDT 24 |
| Peak memory | 145088 kb |
| Host | smart-5d681f83-28fa-4d4b-8bee-459ad4e3f4b7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1341170464 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.1341170464 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.2117479233 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 13602180000 ps |
| CPU time | 41.91 seconds |
| Started | Apr 04 02:04:01 PM PDT 24 |
| Finished | Apr 04 02:05:19 PM PDT 24 |
| Peak memory | 145140 kb |
| Host | smart-674c6f01-a18b-4749-9db1-e265456e8b6d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2117479233 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.2117479233 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.1118215419 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 3796880000 ps |
| CPU time | 14.65 seconds |
| Started | Apr 04 02:04:00 PM PDT 24 |
| Finished | Apr 04 02:04:29 PM PDT 24 |
| Peak memory | 144940 kb |
| Host | smart-eb5c3f97-6996-4937-a33e-d48b86a51cc5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1118215419 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.1118215419 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.3566013694 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 13427960000 ps |
| CPU time | 38.21 seconds |
| Started | Apr 04 02:04:00 PM PDT 24 |
| Finished | Apr 04 02:05:10 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-7ba6b8ae-eccf-4ae0-b3b1-21c062e04b58 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3566013694 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.3566013694 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.621683874 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 5810640000 ps |
| CPU time | 16.45 seconds |
| Started | Apr 04 02:03:57 PM PDT 24 |
| Finished | Apr 04 02:04:29 PM PDT 24 |
| Peak memory | 145088 kb |
| Host | smart-ba3c1edd-9cc0-4b9d-a30e-2cc8874c1373 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=621683874 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.621683874 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.3273525874 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 9231800000 ps |
| CPU time | 32.99 seconds |
| Started | Apr 04 02:03:58 PM PDT 24 |
| Finished | Apr 04 02:05:01 PM PDT 24 |
| Peak memory | 145196 kb |
| Host | smart-34721587-2ab7-4520-9d46-c8126e01c9b4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3273525874 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.3273525874 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.426827774 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 8450600000 ps |
| CPU time | 29.71 seconds |
| Started | Apr 04 02:03:58 PM PDT 24 |
| Finished | Apr 04 02:04:56 PM PDT 24 |
| Peak memory | 145160 kb |
| Host | smart-3988f513-adfa-47e5-bb17-66fdf17240d6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=426827774 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.426827774 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.1063228520 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 5527300000 ps |
| CPU time | 22.6 seconds |
| Started | Apr 04 02:04:01 PM PDT 24 |
| Finished | Apr 04 02:04:45 PM PDT 24 |
| Peak memory | 145164 kb |
| Host | smart-15c49d81-7f7d-4ba8-be8b-273ee19cd5a4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1063228520 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.1063228520 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.2739653142 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 6619120000 ps |
| CPU time | 20.04 seconds |
| Started | Apr 04 02:04:00 PM PDT 24 |
| Finished | Apr 04 02:04:37 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-939f367e-19d1-47a6-9aaa-86cac2e01ff7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2739653142 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.2739653142 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.309578191 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 13532120000 ps |
| CPU time | 39.81 seconds |
| Started | Apr 04 02:04:00 PM PDT 24 |
| Finished | Apr 04 02:05:13 PM PDT 24 |
| Peak memory | 145200 kb |
| Host | smart-a1ad0b45-e531-447e-a280-e616348884a9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=309578191 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.309578191 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.1716764352 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 8102780000 ps |
| CPU time | 30.18 seconds |
| Started | Apr 04 02:03:51 PM PDT 24 |
| Finished | Apr 04 02:04:53 PM PDT 24 |
| Peak memory | 145160 kb |
| Host | smart-6b559357-6280-42f2-a474-3c6c746bf69c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1716764352 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.1716764352 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.526031264 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 7900040000 ps |
| CPU time | 27.02 seconds |
| Started | Apr 04 02:03:58 PM PDT 24 |
| Finished | Apr 04 02:04:50 PM PDT 24 |
| Peak memory | 145152 kb |
| Host | smart-25781da3-8a3f-47ed-b6bd-206cd534f713 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=526031264 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.526031264 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.1420485411 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 12288400000 ps |
| CPU time | 47.94 seconds |
| Started | Apr 04 02:04:01 PM PDT 24 |
| Finished | Apr 04 02:05:38 PM PDT 24 |
| Peak memory | 145112 kb |
| Host | smart-cfc9e76f-6730-4275-a7a1-e25a42ff17de |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1420485411 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.1420485411 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.97676222 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 14205440000 ps |
| CPU time | 44.85 seconds |
| Started | Apr 04 02:04:00 PM PDT 24 |
| Finished | Apr 04 02:05:24 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-641cc983-dfca-49b2-aa20-ae5a7f80fb97 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=97676222 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.97676222 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.4222617092 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 12434720000 ps |
| CPU time | 45.28 seconds |
| Started | Apr 04 02:03:58 PM PDT 24 |
| Finished | Apr 04 02:05:28 PM PDT 24 |
| Peak memory | 145164 kb |
| Host | smart-16eb3fd9-339a-4489-ace7-fb33dbd4e200 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4222617092 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.4222617092 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.947585617 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 6505660000 ps |
| CPU time | 22.52 seconds |
| Started | Apr 04 02:04:01 PM PDT 24 |
| Finished | Apr 04 02:04:45 PM PDT 24 |
| Peak memory | 145164 kb |
| Host | smart-b1706383-f79a-45a5-add4-3809636882b9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=947585617 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.947585617 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.1310625086 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 10986400000 ps |
| CPU time | 37.24 seconds |
| Started | Apr 04 02:04:01 PM PDT 24 |
| Finished | Apr 04 02:05:13 PM PDT 24 |
| Peak memory | 145160 kb |
| Host | smart-f7398e12-9fd3-442b-a6f9-928ee8954901 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1310625086 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.1310625086 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.3398887020 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 11148840000 ps |
| CPU time | 40.06 seconds |
| Started | Apr 04 02:03:59 PM PDT 24 |
| Finished | Apr 04 02:05:14 PM PDT 24 |
| Peak memory | 145156 kb |
| Host | smart-85151e3b-ee7f-4949-9eed-0b2b41275955 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3398887020 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.3398887020 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.2488564718 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 13751600000 ps |
| CPU time | 46.34 seconds |
| Started | Apr 04 02:04:04 PM PDT 24 |
| Finished | Apr 04 02:05:31 PM PDT 24 |
| Peak memory | 145128 kb |
| Host | smart-ce66cc82-d224-4e6f-b66c-50e982b3c2d1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2488564718 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.2488564718 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.1926913057 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 12006920000 ps |
| CPU time | 47 seconds |
| Started | Apr 04 02:04:00 PM PDT 24 |
| Finished | Apr 04 02:05:36 PM PDT 24 |
| Peak memory | 145112 kb |
| Host | smart-93183f74-a620-4da1-a5f5-0e60ba9209b5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1926913057 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.1926913057 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.1432542783 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 6459780000 ps |
| CPU time | 26.01 seconds |
| Started | Apr 04 02:04:00 PM PDT 24 |
| Finished | Apr 04 02:04:53 PM PDT 24 |
| Peak memory | 145112 kb |
| Host | smart-12d77ef5-32d6-4224-88fe-44639e138f7e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1432542783 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.1432542783 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.974290526 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 15428080000 ps |
| CPU time | 54.29 seconds |
| Started | Apr 04 02:03:52 PM PDT 24 |
| Finished | Apr 04 02:05:36 PM PDT 24 |
| Peak memory | 145132 kb |
| Host | smart-c49ebc11-23c0-47a2-b75d-2697e0f793de |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=974290526 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.974290526 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.340155657 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 15196820000 ps |
| CPU time | 58.29 seconds |
| Started | Apr 04 02:03:55 PM PDT 24 |
| Finished | Apr 04 02:05:47 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-ee043b12-b7c6-4f8e-8374-7dc53d22e3f9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=340155657 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.340155657 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.1809659168 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 7638400000 ps |
| CPU time | 32.15 seconds |
| Started | Apr 04 02:03:52 PM PDT 24 |
| Finished | Apr 04 02:04:52 PM PDT 24 |
| Peak memory | 145144 kb |
| Host | smart-a5bb4d95-117d-4074-aa82-153efeb0d196 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1809659168 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.1809659168 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.3683026986 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 12888560000 ps |
| CPU time | 46 seconds |
| Started | Apr 04 02:03:52 PM PDT 24 |
| Finished | Apr 04 02:05:20 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-1a8ab2b0-95f6-459f-86b3-a24639d93e95 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3683026986 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.3683026986 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.2437981275 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 13011940000 ps |
| CPU time | 42.26 seconds |
| Started | Apr 04 02:03:54 PM PDT 24 |
| Finished | Apr 04 02:05:13 PM PDT 24 |
| Peak memory | 145152 kb |
| Host | smart-23c11676-0253-4726-926f-e9cfa31e6ffc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2437981275 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.2437981275 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |