| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/14.prim_present_test.48151768 | ||
| Name |
|---|
| /workspace/coverage/default/0.prim_present_test.3854736718 |
| /workspace/coverage/default/1.prim_present_test.1091175581 |
| /workspace/coverage/default/10.prim_present_test.3037152330 |
| /workspace/coverage/default/11.prim_present_test.821389234 |
| /workspace/coverage/default/12.prim_present_test.3377174856 |
| /workspace/coverage/default/13.prim_present_test.334684252 |
| /workspace/coverage/default/15.prim_present_test.916911409 |
| /workspace/coverage/default/16.prim_present_test.1302719357 |
| /workspace/coverage/default/17.prim_present_test.3584434967 |
| /workspace/coverage/default/18.prim_present_test.1484352296 |
| /workspace/coverage/default/19.prim_present_test.1375873300 |
| /workspace/coverage/default/2.prim_present_test.3072350714 |
| /workspace/coverage/default/20.prim_present_test.1085846472 |
| /workspace/coverage/default/21.prim_present_test.1362906901 |
| /workspace/coverage/default/22.prim_present_test.185726660 |
| /workspace/coverage/default/23.prim_present_test.3543855601 |
| /workspace/coverage/default/24.prim_present_test.2695806223 |
| /workspace/coverage/default/25.prim_present_test.1740161052 |
| /workspace/coverage/default/26.prim_present_test.3199403849 |
| /workspace/coverage/default/27.prim_present_test.3310920325 |
| /workspace/coverage/default/28.prim_present_test.3241306441 |
| /workspace/coverage/default/29.prim_present_test.2473996923 |
| /workspace/coverage/default/3.prim_present_test.720281203 |
| /workspace/coverage/default/30.prim_present_test.566218666 |
| /workspace/coverage/default/31.prim_present_test.4205352839 |
| /workspace/coverage/default/32.prim_present_test.1199765961 |
| /workspace/coverage/default/33.prim_present_test.2984869412 |
| /workspace/coverage/default/34.prim_present_test.2982841239 |
| /workspace/coverage/default/35.prim_present_test.4274979666 |
| /workspace/coverage/default/36.prim_present_test.2734512683 |
| /workspace/coverage/default/37.prim_present_test.3017770508 |
| /workspace/coverage/default/38.prim_present_test.1085145330 |
| /workspace/coverage/default/39.prim_present_test.1072401440 |
| /workspace/coverage/default/4.prim_present_test.2821209145 |
| /workspace/coverage/default/40.prim_present_test.116038203 |
| /workspace/coverage/default/41.prim_present_test.806972468 |
| /workspace/coverage/default/42.prim_present_test.2856050703 |
| /workspace/coverage/default/43.prim_present_test.2711632806 |
| /workspace/coverage/default/44.prim_present_test.2781196095 |
| /workspace/coverage/default/45.prim_present_test.609893852 |
| /workspace/coverage/default/46.prim_present_test.2236566541 |
| /workspace/coverage/default/47.prim_present_test.1327139558 |
| /workspace/coverage/default/48.prim_present_test.2438304511 |
| /workspace/coverage/default/49.prim_present_test.3950656198 |
| /workspace/coverage/default/5.prim_present_test.620632412 |
| /workspace/coverage/default/6.prim_present_test.1151473715 |
| /workspace/coverage/default/7.prim_present_test.2715881894 |
| /workspace/coverage/default/8.prim_present_test.3473924698 |
| /workspace/coverage/default/9.prim_present_test.2660513856 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/26.prim_present_test.3199403849 | Apr 15 12:16:33 PM PDT 24 | Apr 15 12:17:10 PM PDT 24 | 4860800000 ps | ||
| T2 | /workspace/coverage/default/27.prim_present_test.3310920325 | Apr 15 12:19:13 PM PDT 24 | Apr 15 12:20:24 PM PDT 24 | 11931280000 ps | ||
| T3 | /workspace/coverage/default/30.prim_present_test.566218666 | Apr 15 12:19:07 PM PDT 24 | Apr 15 12:19:40 PM PDT 24 | 5403300000 ps | ||
| T4 | /workspace/coverage/default/37.prim_present_test.3017770508 | Apr 15 12:19:41 PM PDT 24 | Apr 15 12:20:23 PM PDT 24 | 5945180000 ps | ||
| T5 | /workspace/coverage/default/29.prim_present_test.2473996923 | Apr 15 12:19:03 PM PDT 24 | Apr 15 12:20:20 PM PDT 24 | 13483140000 ps | ||
| T6 | /workspace/coverage/default/45.prim_present_test.609893852 | Apr 15 12:19:16 PM PDT 24 | Apr 15 12:19:53 PM PDT 24 | 5555200000 ps | ||
| T7 | /workspace/coverage/default/33.prim_present_test.2984869412 | Apr 15 12:19:13 PM PDT 24 | Apr 15 12:20:29 PM PDT 24 | 13369060000 ps | ||
| T8 | /workspace/coverage/default/6.prim_present_test.1151473715 | Apr 15 12:13:57 PM PDT 24 | Apr 15 12:15:44 PM PDT 24 | 14019440000 ps | ||
| T9 | /workspace/coverage/default/4.prim_present_test.2821209145 | Apr 15 12:20:18 PM PDT 24 | Apr 15 12:21:30 PM PDT 24 | 12765180000 ps | ||
| T10 | /workspace/coverage/default/14.prim_present_test.48151768 | Apr 15 12:18:48 PM PDT 24 | Apr 15 12:19:21 PM PDT 24 | 4303420000 ps | ||
| T11 | /workspace/coverage/default/38.prim_present_test.1085145330 | Apr 15 12:14:49 PM PDT 24 | Apr 15 12:15:37 PM PDT 24 | 7341420000 ps | ||
| T12 | /workspace/coverage/default/18.prim_present_test.1484352296 | Apr 15 12:16:33 PM PDT 24 | Apr 15 12:18:01 PM PDT 24 | 12413020000 ps | ||
| T13 | /workspace/coverage/default/24.prim_present_test.2695806223 | Apr 15 12:16:51 PM PDT 24 | Apr 15 12:18:03 PM PDT 24 | 10918820000 ps | ||
| T14 | /workspace/coverage/default/23.prim_present_test.3543855601 | Apr 15 12:16:39 PM PDT 24 | Apr 15 12:17:23 PM PDT 24 | 5363000000 ps | ||
| T15 | /workspace/coverage/default/35.prim_present_test.4274979666 | Apr 15 12:19:08 PM PDT 24 | Apr 15 12:20:11 PM PDT 24 | 11286480000 ps | ||
| T16 | /workspace/coverage/default/5.prim_present_test.620632412 | Apr 15 12:20:19 PM PDT 24 | Apr 15 12:20:49 PM PDT 24 | 4598540000 ps | ||
| T17 | /workspace/coverage/default/8.prim_present_test.3473924698 | Apr 15 12:19:22 PM PDT 24 | Apr 15 12:20:02 PM PDT 24 | 6171480000 ps | ||
| T18 | /workspace/coverage/default/40.prim_present_test.116038203 | Apr 15 12:19:46 PM PDT 24 | Apr 15 12:20:10 PM PDT 24 | 3715040000 ps | ||
| T19 | /workspace/coverage/default/39.prim_present_test.1072401440 | Apr 15 12:19:16 PM PDT 24 | Apr 15 12:19:58 PM PDT 24 | 6723280000 ps | ||
| T20 | /workspace/coverage/default/43.prim_present_test.2711632806 | Apr 15 12:18:40 PM PDT 24 | Apr 15 12:19:24 PM PDT 24 | 6212400000 ps | ||
| T21 | /workspace/coverage/default/46.prim_present_test.2236566541 | Apr 15 12:16:23 PM PDT 24 | Apr 15 12:17:57 PM PDT 24 | 13155780000 ps | ||
| T22 | /workspace/coverage/default/3.prim_present_test.720281203 | Apr 15 12:16:04 PM PDT 24 | Apr 15 12:17:41 PM PDT 24 | 12037300000 ps | ||
| T23 | /workspace/coverage/default/44.prim_present_test.2781196095 | Apr 15 12:14:46 PM PDT 24 | Apr 15 12:15:13 PM PDT 24 | 4445400000 ps | ||
| T24 | /workspace/coverage/default/10.prim_present_test.3037152330 | Apr 15 12:16:33 PM PDT 24 | Apr 15 12:17:36 PM PDT 24 | 8580800000 ps | ||
| T25 | /workspace/coverage/default/31.prim_present_test.4205352839 | Apr 15 12:18:21 PM PDT 24 | Apr 15 12:18:58 PM PDT 24 | 4801900000 ps | ||
| T26 | /workspace/coverage/default/9.prim_present_test.2660513856 | Apr 15 12:16:40 PM PDT 24 | Apr 15 12:18:35 PM PDT 24 | 14291000000 ps | ||
| T27 | /workspace/coverage/default/36.prim_present_test.2734512683 | Apr 15 12:19:16 PM PDT 24 | Apr 15 12:20:09 PM PDT 24 | 8688680000 ps | ||
| T28 | /workspace/coverage/default/20.prim_present_test.1085846472 | Apr 15 12:18:58 PM PDT 24 | Apr 15 12:20:08 PM PDT 24 | 11264780000 ps | ||
| T29 | /workspace/coverage/default/13.prim_present_test.334684252 | Apr 15 12:18:48 PM PDT 24 | Apr 15 12:19:22 PM PDT 24 | 4560720000 ps | ||
| T30 | /workspace/coverage/default/21.prim_present_test.1362906901 | Apr 15 12:16:43 PM PDT 24 | Apr 15 12:17:22 PM PDT 24 | 5318360000 ps | ||
| T31 | /workspace/coverage/default/47.prim_present_test.1327139558 | Apr 15 12:19:06 PM PDT 24 | Apr 15 12:19:55 PM PDT 24 | 7549120000 ps | ||
| T32 | /workspace/coverage/default/34.prim_present_test.2982841239 | Apr 15 12:19:45 PM PDT 24 | Apr 15 12:20:54 PM PDT 24 | 10596420000 ps | ||
| T33 | /workspace/coverage/default/1.prim_present_test.1091175581 | Apr 15 12:19:19 PM PDT 24 | Apr 15 12:19:49 PM PDT 24 | 3928320000 ps | ||
| T34 | /workspace/coverage/default/28.prim_present_test.3241306441 | Apr 15 12:19:07 PM PDT 24 | Apr 15 12:19:46 PM PDT 24 | 6457300000 ps | ||
| T35 | /workspace/coverage/default/22.prim_present_test.185726660 | Apr 15 12:18:57 PM PDT 24 | Apr 15 12:20:16 PM PDT 24 | 12990860000 ps | ||
| T36 | /workspace/coverage/default/7.prim_present_test.2715881894 | Apr 15 12:19:19 PM PDT 24 | Apr 15 12:20:46 PM PDT 24 | 13537700000 ps | ||
| T37 | /workspace/coverage/default/11.prim_present_test.821389234 | Apr 15 12:18:58 PM PDT 24 | Apr 15 12:19:36 PM PDT 24 | 5843500000 ps | ||
| T38 | /workspace/coverage/default/32.prim_present_test.1199765961 | Apr 15 12:19:34 PM PDT 24 | Apr 15 12:20:21 PM PDT 24 | 7353820000 ps | ||
| T39 | /workspace/coverage/default/41.prim_present_test.806972468 | Apr 15 12:14:52 PM PDT 24 | Apr 15 12:15:47 PM PDT 24 | 8520660000 ps | ||
| T40 | /workspace/coverage/default/19.prim_present_test.1375873300 | Apr 15 12:19:07 PM PDT 24 | Apr 15 12:19:29 PM PDT 24 | 3522840000 ps | ||
| T41 | /workspace/coverage/default/17.prim_present_test.3584434967 | Apr 15 12:15:31 PM PDT 24 | Apr 15 12:17:02 PM PDT 24 | 12710000000 ps | ||
| T42 | /workspace/coverage/default/12.prim_present_test.3377174856 | Apr 15 12:16:33 PM PDT 24 | Apr 15 12:18:17 PM PDT 24 | 14459640000 ps | ||
| T43 | /workspace/coverage/default/25.prim_present_test.1740161052 | Apr 15 12:17:23 PM PDT 24 | Apr 15 12:17:47 PM PDT 24 | 3399460000 ps | ||
| T44 | /workspace/coverage/default/16.prim_present_test.1302719357 | Apr 15 12:18:48 PM PDT 24 | Apr 15 12:19:49 PM PDT 24 | 8776720000 ps | ||
| T45 | /workspace/coverage/default/49.prim_present_test.3950656198 | Apr 15 12:19:16 PM PDT 24 | Apr 15 12:19:48 PM PDT 24 | 4920940000 ps | ||
| T46 | /workspace/coverage/default/48.prim_present_test.2438304511 | Apr 15 12:18:41 PM PDT 24 | Apr 15 12:19:13 PM PDT 24 | 4674180000 ps | ||
| T47 | /workspace/coverage/default/15.prim_present_test.916911409 | Apr 15 12:18:48 PM PDT 24 | Apr 15 12:19:35 PM PDT 24 | 6314080000 ps | ||
| T48 | /workspace/coverage/default/42.prim_present_test.2856050703 | Apr 15 12:16:24 PM PDT 24 | Apr 15 12:17:29 PM PDT 24 | 8937300000 ps | ||
| T49 | /workspace/coverage/default/0.prim_present_test.3854736718 | Apr 15 12:13:57 PM PDT 24 | Apr 15 12:15:02 PM PDT 24 | 8311720000 ps | ||
| T50 | /workspace/coverage/default/2.prim_present_test.3072350714 | Apr 15 12:13:56 PM PDT 24 | Apr 15 12:15:46 PM PDT 24 | 14303400000 ps |
| Test location | /workspace/coverage/default/14.prim_present_test.48151768 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 4303420000 ps |
| CPU time | 16.74 seconds |
| Started | Apr 15 12:18:48 PM PDT 24 |
| Finished | Apr 15 12:19:21 PM PDT 24 |
| Peak memory | 144552 kb |
| Host | smart-d3700f4b-129b-4aa1-bd83-c493168f59c9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=48151768 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.48151768 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/0.prim_present_test.3854736718 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 8311720000 ps |
| CPU time | 33.15 seconds |
| Started | Apr 15 12:13:57 PM PDT 24 |
| Finished | Apr 15 12:15:02 PM PDT 24 |
| Peak memory | 144684 kb |
| Host | smart-5585a506-422e-41dc-9f09-e9b97b0cb730 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3854736718 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.3854736718 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/1.prim_present_test.1091175581 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 3928320000 ps |
| CPU time | 15.74 seconds |
| Started | Apr 15 12:19:19 PM PDT 24 |
| Finished | Apr 15 12:19:49 PM PDT 24 |
| Peak memory | 144548 kb |
| Host | smart-1caaf39e-fc22-4aac-aa0c-5a9a00baa5b7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1091175581 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.1091175581 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/10.prim_present_test.3037152330 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 8580800000 ps |
| CPU time | 33.67 seconds |
| Started | Apr 15 12:16:33 PM PDT 24 |
| Finished | Apr 15 12:17:36 PM PDT 24 |
| Peak memory | 144936 kb |
| Host | smart-449e2261-bb7e-4f3b-92b1-70e02b242617 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3037152330 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.3037152330 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/11.prim_present_test.821389234 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 5843500000 ps |
| CPU time | 20.52 seconds |
| Started | Apr 15 12:18:58 PM PDT 24 |
| Finished | Apr 15 12:19:36 PM PDT 24 |
| Peak memory | 144648 kb |
| Host | smart-a6a5880c-6ff8-4473-aba5-1b0dd20bcf7f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=821389234 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.821389234 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.3377174856 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 14459640000 ps |
| CPU time | 55.53 seconds |
| Started | Apr 15 12:16:33 PM PDT 24 |
| Finished | Apr 15 12:18:17 PM PDT 24 |
| Peak memory | 145016 kb |
| Host | smart-111f9f33-7a80-4626-b514-2f5341c00dc0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3377174856 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.3377174856 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.334684252 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 4560720000 ps |
| CPU time | 17.7 seconds |
| Started | Apr 15 12:18:48 PM PDT 24 |
| Finished | Apr 15 12:19:22 PM PDT 24 |
| Peak memory | 142468 kb |
| Host | smart-f03aa196-377c-44b5-9f4a-434b3586ab00 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=334684252 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.334684252 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.916911409 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 6314080000 ps |
| CPU time | 24.9 seconds |
| Started | Apr 15 12:18:48 PM PDT 24 |
| Finished | Apr 15 12:19:35 PM PDT 24 |
| Peak memory | 143244 kb |
| Host | smart-f20cada0-bb2b-48cc-899f-2e67a1bf0197 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=916911409 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.916911409 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.1302719357 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 8776720000 ps |
| CPU time | 32.44 seconds |
| Started | Apr 15 12:18:48 PM PDT 24 |
| Finished | Apr 15 12:19:49 PM PDT 24 |
| Peak memory | 142664 kb |
| Host | smart-72e0ca49-6496-480c-a9f5-8dd50752cb98 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1302719357 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.1302719357 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.3584434967 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 12710000000 ps |
| CPU time | 48.14 seconds |
| Started | Apr 15 12:15:31 PM PDT 24 |
| Finished | Apr 15 12:17:02 PM PDT 24 |
| Peak memory | 144996 kb |
| Host | smart-bd816b00-2200-43d1-8487-7747edf1e272 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3584434967 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.3584434967 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.1484352296 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 12413020000 ps |
| CPU time | 46.91 seconds |
| Started | Apr 15 12:16:33 PM PDT 24 |
| Finished | Apr 15 12:18:01 PM PDT 24 |
| Peak memory | 145016 kb |
| Host | smart-da3e130b-2bfc-4711-b882-6acf453010db |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1484352296 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.1484352296 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.1375873300 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 3522840000 ps |
| CPU time | 11.37 seconds |
| Started | Apr 15 12:19:07 PM PDT 24 |
| Finished | Apr 15 12:19:29 PM PDT 24 |
| Peak memory | 142780 kb |
| Host | smart-e0138edf-faba-44f3-9e96-e141271fd769 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1375873300 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.1375873300 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.3072350714 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 14303400000 ps |
| CPU time | 56.82 seconds |
| Started | Apr 15 12:13:56 PM PDT 24 |
| Finished | Apr 15 12:15:46 PM PDT 24 |
| Peak memory | 143100 kb |
| Host | smart-32b5520b-5812-43b3-939c-17bff7b03dbc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3072350714 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.3072350714 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.1085846472 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 11264780000 ps |
| CPU time | 37.69 seconds |
| Started | Apr 15 12:18:58 PM PDT 24 |
| Finished | Apr 15 12:20:08 PM PDT 24 |
| Peak memory | 144660 kb |
| Host | smart-3ac8bfa4-3d03-4e2f-9d8a-c824a414aaeb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1085846472 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.1085846472 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.1362906901 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 5318360000 ps |
| CPU time | 20.57 seconds |
| Started | Apr 15 12:16:43 PM PDT 24 |
| Finished | Apr 15 12:17:22 PM PDT 24 |
| Peak memory | 145032 kb |
| Host | smart-b7fff95c-ba9f-47a2-8e49-9364a3c05cd8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1362906901 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.1362906901 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.185726660 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 12990860000 ps |
| CPU time | 42.25 seconds |
| Started | Apr 15 12:18:57 PM PDT 24 |
| Finished | Apr 15 12:20:16 PM PDT 24 |
| Peak memory | 143684 kb |
| Host | smart-1b5dc840-33eb-4e21-9d97-be980d2e97ed |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=185726660 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.185726660 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.3543855601 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 5363000000 ps |
| CPU time | 22.6 seconds |
| Started | Apr 15 12:16:39 PM PDT 24 |
| Finished | Apr 15 12:17:23 PM PDT 24 |
| Peak memory | 145060 kb |
| Host | smart-ec89673e-efdd-4a4c-a79f-36f6b3125e06 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3543855601 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.3543855601 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.2695806223 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 10918820000 ps |
| CPU time | 38.35 seconds |
| Started | Apr 15 12:16:51 PM PDT 24 |
| Finished | Apr 15 12:18:03 PM PDT 24 |
| Peak memory | 144892 kb |
| Host | smart-5970afe0-0623-4e1d-b1e6-a92cbceef265 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2695806223 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.2695806223 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.1740161052 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 3399460000 ps |
| CPU time | 12.9 seconds |
| Started | Apr 15 12:17:23 PM PDT 24 |
| Finished | Apr 15 12:17:47 PM PDT 24 |
| Peak memory | 144868 kb |
| Host | smart-d11d1c99-c516-42e2-a8ae-04f5c29b22f1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1740161052 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.1740161052 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.3199403849 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 4860800000 ps |
| CPU time | 19.44 seconds |
| Started | Apr 15 12:16:33 PM PDT 24 |
| Finished | Apr 15 12:17:10 PM PDT 24 |
| Peak memory | 145024 kb |
| Host | smart-10e3caba-0b40-49e5-8651-3ba0e85245cb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3199403849 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.3199403849 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.3310920325 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 11931280000 ps |
| CPU time | 38.01 seconds |
| Started | Apr 15 12:19:13 PM PDT 24 |
| Finished | Apr 15 12:20:24 PM PDT 24 |
| Peak memory | 144660 kb |
| Host | smart-cb993769-aacc-4702-9fd9-025e4b5640f3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3310920325 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.3310920325 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.3241306441 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 6457300000 ps |
| CPU time | 20.67 seconds |
| Started | Apr 15 12:19:07 PM PDT 24 |
| Finished | Apr 15 12:19:46 PM PDT 24 |
| Peak memory | 143832 kb |
| Host | smart-4ff01dd7-98c8-4ff5-9b0b-67402f9c770a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3241306441 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.3241306441 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.2473996923 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 13483140000 ps |
| CPU time | 40.91 seconds |
| Started | Apr 15 12:19:03 PM PDT 24 |
| Finished | Apr 15 12:20:20 PM PDT 24 |
| Peak memory | 143904 kb |
| Host | smart-ce031437-d996-4687-80aa-3fed7b52a50f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2473996923 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.2473996923 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.720281203 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 12037300000 ps |
| CPU time | 49.79 seconds |
| Started | Apr 15 12:16:04 PM PDT 24 |
| Finished | Apr 15 12:17:41 PM PDT 24 |
| Peak memory | 144860 kb |
| Host | smart-fd0666f2-f758-4ef5-91cf-5adfb5e5e764 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=720281203 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.720281203 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.566218666 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 5403300000 ps |
| CPU time | 17.46 seconds |
| Started | Apr 15 12:19:07 PM PDT 24 |
| Finished | Apr 15 12:19:40 PM PDT 24 |
| Peak memory | 144284 kb |
| Host | smart-d4676d31-8dc6-46b6-96d7-28e7fe34cf25 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=566218666 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.566218666 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.4205352839 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 4801900000 ps |
| CPU time | 19.32 seconds |
| Started | Apr 15 12:18:21 PM PDT 24 |
| Finished | Apr 15 12:18:58 PM PDT 24 |
| Peak memory | 145056 kb |
| Host | smart-0e6b3661-18b9-4dce-9938-32b74f91e50c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4205352839 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.4205352839 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.1199765961 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 7353820000 ps |
| CPU time | 24.71 seconds |
| Started | Apr 15 12:19:34 PM PDT 24 |
| Finished | Apr 15 12:20:21 PM PDT 24 |
| Peak memory | 143828 kb |
| Host | smart-637bee6b-dd1c-4ef8-8dcd-df58963ce1b8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1199765961 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.1199765961 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.2984869412 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 13369060000 ps |
| CPU time | 41.28 seconds |
| Started | Apr 15 12:19:13 PM PDT 24 |
| Finished | Apr 15 12:20:29 PM PDT 24 |
| Peak memory | 144096 kb |
| Host | smart-4af1de06-be9a-43fd-b303-402aaf206e76 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2984869412 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.2984869412 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.2982841239 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 10596420000 ps |
| CPU time | 36.84 seconds |
| Started | Apr 15 12:19:45 PM PDT 24 |
| Finished | Apr 15 12:20:54 PM PDT 24 |
| Peak memory | 144932 kb |
| Host | smart-db05c6ee-97f1-4c9d-8629-24d869bcfb71 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2982841239 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.2982841239 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.4274979666 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 11286480000 ps |
| CPU time | 34.39 seconds |
| Started | Apr 15 12:19:08 PM PDT 24 |
| Finished | Apr 15 12:20:11 PM PDT 24 |
| Peak memory | 144572 kb |
| Host | smart-5ba1304e-37cf-4465-88c4-2821975931bc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4274979666 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.4274979666 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.2734512683 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 8688680000 ps |
| CPU time | 28.61 seconds |
| Started | Apr 15 12:19:16 PM PDT 24 |
| Finished | Apr 15 12:20:09 PM PDT 24 |
| Peak memory | 144828 kb |
| Host | smart-5b538a5f-b5b0-4e25-bb8c-5429c10763c8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2734512683 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.2734512683 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.3017770508 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 5945180000 ps |
| CPU time | 22 seconds |
| Started | Apr 15 12:19:41 PM PDT 24 |
| Finished | Apr 15 12:20:23 PM PDT 24 |
| Peak memory | 142876 kb |
| Host | smart-e1760d0f-4860-46b9-b809-c4ef5a1fb07f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3017770508 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.3017770508 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.1085145330 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 7341420000 ps |
| CPU time | 25.93 seconds |
| Started | Apr 15 12:14:49 PM PDT 24 |
| Finished | Apr 15 12:15:37 PM PDT 24 |
| Peak memory | 144980 kb |
| Host | smart-849680e9-b79f-41f3-89b2-9486952985f6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1085145330 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.1085145330 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.1072401440 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 6723280000 ps |
| CPU time | 22.79 seconds |
| Started | Apr 15 12:19:16 PM PDT 24 |
| Finished | Apr 15 12:19:58 PM PDT 24 |
| Peak memory | 144880 kb |
| Host | smart-14b1610a-a8a9-4cab-a7e9-48a9fb5939dd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1072401440 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.1072401440 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.2821209145 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 12765180000 ps |
| CPU time | 38.54 seconds |
| Started | Apr 15 12:20:18 PM PDT 24 |
| Finished | Apr 15 12:21:30 PM PDT 24 |
| Peak memory | 144688 kb |
| Host | smart-d19f152b-5198-447b-84b3-8acb312f4efa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2821209145 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.2821209145 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.116038203 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 3715040000 ps |
| CPU time | 13.02 seconds |
| Started | Apr 15 12:19:46 PM PDT 24 |
| Finished | Apr 15 12:20:10 PM PDT 24 |
| Peak memory | 144784 kb |
| Host | smart-3c7c8eea-baab-422f-aa8e-3a9250bd5af2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=116038203 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.116038203 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.806972468 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 8520660000 ps |
| CPU time | 29.48 seconds |
| Started | Apr 15 12:14:52 PM PDT 24 |
| Finished | Apr 15 12:15:47 PM PDT 24 |
| Peak memory | 145300 kb |
| Host | smart-892f525a-3c15-4bb0-bb3b-66352888d631 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=806972468 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.806972468 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.2856050703 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 8937300000 ps |
| CPU time | 34.1 seconds |
| Started | Apr 15 12:16:24 PM PDT 24 |
| Finished | Apr 15 12:17:29 PM PDT 24 |
| Peak memory | 145012 kb |
| Host | smart-aba7637e-eba3-4fbf-8568-7db1593a0293 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2856050703 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.2856050703 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.2711632806 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 6212400000 ps |
| CPU time | 23.14 seconds |
| Started | Apr 15 12:18:40 PM PDT 24 |
| Finished | Apr 15 12:19:24 PM PDT 24 |
| Peak memory | 142804 kb |
| Host | smart-defc4a11-09b5-482c-82a2-e4295f157f3d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2711632806 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.2711632806 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.2781196095 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 4445400000 ps |
| CPU time | 14.68 seconds |
| Started | Apr 15 12:14:46 PM PDT 24 |
| Finished | Apr 15 12:15:13 PM PDT 24 |
| Peak memory | 144872 kb |
| Host | smart-eb7d284b-639d-4585-b839-a6b656f6b7f9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2781196095 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.2781196095 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.609893852 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 5555200000 ps |
| CPU time | 20.16 seconds |
| Started | Apr 15 12:19:16 PM PDT 24 |
| Finished | Apr 15 12:19:53 PM PDT 24 |
| Peak memory | 144868 kb |
| Host | smart-5dfdd60d-73d3-4dec-b911-2ef4e0be4951 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=609893852 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.609893852 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.2236566541 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 13155780000 ps |
| CPU time | 50.1 seconds |
| Started | Apr 15 12:16:23 PM PDT 24 |
| Finished | Apr 15 12:17:57 PM PDT 24 |
| Peak memory | 145012 kb |
| Host | smart-ac33fde7-b358-4b80-a896-a0c22d69f851 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2236566541 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.2236566541 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.1327139558 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 7549120000 ps |
| CPU time | 25.69 seconds |
| Started | Apr 15 12:19:06 PM PDT 24 |
| Finished | Apr 15 12:19:55 PM PDT 24 |
| Peak memory | 144060 kb |
| Host | smart-9d5d2513-398b-4d66-8fb6-bdb27c694c7a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1327139558 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.1327139558 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.2438304511 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 4674180000 ps |
| CPU time | 17 seconds |
| Started | Apr 15 12:18:41 PM PDT 24 |
| Finished | Apr 15 12:19:13 PM PDT 24 |
| Peak memory | 144536 kb |
| Host | smart-35bd7a54-fccf-4903-b826-e04a996f841b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2438304511 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.2438304511 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.3950656198 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 4920940000 ps |
| CPU time | 17.16 seconds |
| Started | Apr 15 12:19:16 PM PDT 24 |
| Finished | Apr 15 12:19:48 PM PDT 24 |
| Peak memory | 144880 kb |
| Host | smart-2762684f-f5d6-40a0-b74d-021072922a29 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3950656198 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.3950656198 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.620632412 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 4598540000 ps |
| CPU time | 16.2 seconds |
| Started | Apr 15 12:20:19 PM PDT 24 |
| Finished | Apr 15 12:20:49 PM PDT 24 |
| Peak memory | 144744 kb |
| Host | smart-3ae1534d-f1d7-4ae2-9621-02ed1b609e2f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=620632412 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.620632412 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.1151473715 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 14019440000 ps |
| CPU time | 54.54 seconds |
| Started | Apr 15 12:13:57 PM PDT 24 |
| Finished | Apr 15 12:15:44 PM PDT 24 |
| Peak memory | 144692 kb |
| Host | smart-2d4571dc-0eff-4a4a-a7cc-edbb8ed4abaf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1151473715 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.1151473715 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.2715881894 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 13537700000 ps |
| CPU time | 46.01 seconds |
| Started | Apr 15 12:19:19 PM PDT 24 |
| Finished | Apr 15 12:20:46 PM PDT 24 |
| Peak memory | 143648 kb |
| Host | smart-d1efb142-45d6-4d06-ae34-f881ab6216b9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2715881894 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.2715881894 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.3473924698 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 6171480000 ps |
| CPU time | 21.69 seconds |
| Started | Apr 15 12:19:22 PM PDT 24 |
| Finished | Apr 15 12:20:02 PM PDT 24 |
| Peak memory | 144660 kb |
| Host | smart-2256dabf-0224-403d-855f-a5e43ebe4439 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3473924698 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.3473924698 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.2660513856 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 14291000000 ps |
| CPU time | 59.47 seconds |
| Started | Apr 15 12:16:40 PM PDT 24 |
| Finished | Apr 15 12:18:35 PM PDT 24 |
| Peak memory | 145060 kb |
| Host | smart-45f8bb5d-6415-4321-b9a4-f574c52b3160 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2660513856 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.2660513856 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |