| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/0.prim_present_test.2670539435 | ||
| Name |
|---|
| /workspace/coverage/default/1.prim_present_test.474250631 |
| /workspace/coverage/default/10.prim_present_test.22824470 |
| /workspace/coverage/default/11.prim_present_test.390008873 |
| /workspace/coverage/default/12.prim_present_test.4226483579 |
| /workspace/coverage/default/13.prim_present_test.2918090200 |
| /workspace/coverage/default/14.prim_present_test.1701830718 |
| /workspace/coverage/default/15.prim_present_test.2447750487 |
| /workspace/coverage/default/16.prim_present_test.798004123 |
| /workspace/coverage/default/17.prim_present_test.4119572536 |
| /workspace/coverage/default/18.prim_present_test.1281326743 |
| /workspace/coverage/default/19.prim_present_test.4137622270 |
| /workspace/coverage/default/2.prim_present_test.2724282494 |
| /workspace/coverage/default/20.prim_present_test.3534329553 |
| /workspace/coverage/default/21.prim_present_test.3839373907 |
| /workspace/coverage/default/22.prim_present_test.1185563208 |
| /workspace/coverage/default/23.prim_present_test.1954295562 |
| /workspace/coverage/default/24.prim_present_test.3896464161 |
| /workspace/coverage/default/25.prim_present_test.1937706277 |
| /workspace/coverage/default/26.prim_present_test.1193369876 |
| /workspace/coverage/default/27.prim_present_test.2028739286 |
| /workspace/coverage/default/28.prim_present_test.1084247277 |
| /workspace/coverage/default/29.prim_present_test.695578268 |
| /workspace/coverage/default/3.prim_present_test.2817633265 |
| /workspace/coverage/default/30.prim_present_test.3388900054 |
| /workspace/coverage/default/31.prim_present_test.1978614841 |
| /workspace/coverage/default/32.prim_present_test.3750933877 |
| /workspace/coverage/default/33.prim_present_test.2011514906 |
| /workspace/coverage/default/34.prim_present_test.1865390311 |
| /workspace/coverage/default/35.prim_present_test.1109335608 |
| /workspace/coverage/default/36.prim_present_test.3177757015 |
| /workspace/coverage/default/37.prim_present_test.121006023 |
| /workspace/coverage/default/38.prim_present_test.2320640472 |
| /workspace/coverage/default/39.prim_present_test.2150835529 |
| /workspace/coverage/default/4.prim_present_test.1954038896 |
| /workspace/coverage/default/40.prim_present_test.3788546567 |
| /workspace/coverage/default/41.prim_present_test.3108804009 |
| /workspace/coverage/default/42.prim_present_test.4106077206 |
| /workspace/coverage/default/43.prim_present_test.17630420 |
| /workspace/coverage/default/44.prim_present_test.970068384 |
| /workspace/coverage/default/45.prim_present_test.2337033170 |
| /workspace/coverage/default/46.prim_present_test.897262570 |
| /workspace/coverage/default/47.prim_present_test.965652448 |
| /workspace/coverage/default/48.prim_present_test.2034464131 |
| /workspace/coverage/default/49.prim_present_test.2962912558 |
| /workspace/coverage/default/5.prim_present_test.3494410688 |
| /workspace/coverage/default/6.prim_present_test.864031140 |
| /workspace/coverage/default/7.prim_present_test.2632634594 |
| /workspace/coverage/default/8.prim_present_test.2451823463 |
| /workspace/coverage/default/9.prim_present_test.1091303917 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/35.prim_present_test.1109335608 | Apr 16 12:17:44 PM PDT 24 | Apr 16 12:19:24 PM PDT 24 | 11370800000 ps | ||
| T2 | /workspace/coverage/default/24.prim_present_test.3896464161 | Apr 16 12:22:58 PM PDT 24 | Apr 16 12:23:26 PM PDT 24 | 4362320000 ps | ||
| T3 | /workspace/coverage/default/19.prim_present_test.4137622270 | Apr 16 12:20:54 PM PDT 24 | Apr 16 12:22:10 PM PDT 24 | 11767600000 ps | ||
| T4 | /workspace/coverage/default/8.prim_present_test.2451823463 | Apr 16 12:21:19 PM PDT 24 | Apr 16 12:22:48 PM PDT 24 | 12669080000 ps | ||
| T5 | /workspace/coverage/default/12.prim_present_test.4226483579 | Apr 16 12:21:19 PM PDT 24 | Apr 16 12:22:55 PM PDT 24 | 13974180000 ps | ||
| T6 | /workspace/coverage/default/0.prim_present_test.2670539435 | Apr 16 12:21:08 PM PDT 24 | Apr 16 12:22:27 PM PDT 24 | 12189200000 ps | ||
| T7 | /workspace/coverage/default/41.prim_present_test.3108804009 | Apr 16 12:21:44 PM PDT 24 | Apr 16 12:22:42 PM PDT 24 | 8084180000 ps | ||
| T8 | /workspace/coverage/default/28.prim_present_test.1084247277 | Apr 16 12:22:38 PM PDT 24 | Apr 16 12:23:36 PM PDT 24 | 9791040000 ps | ||
| T9 | /workspace/coverage/default/38.prim_present_test.2320640472 | Apr 16 12:16:58 PM PDT 24 | Apr 16 12:17:45 PM PDT 24 | 6014620000 ps | ||
| T10 | /workspace/coverage/default/5.prim_present_test.3494410688 | Apr 16 12:21:26 PM PDT 24 | Apr 16 12:22:16 PM PDT 24 | 7560280000 ps | ||
| T11 | /workspace/coverage/default/25.prim_present_test.1937706277 | Apr 16 12:21:43 PM PDT 24 | Apr 16 12:22:11 PM PDT 24 | 3446580000 ps | ||
| T12 | /workspace/coverage/default/43.prim_present_test.17630420 | Apr 16 12:17:08 PM PDT 24 | Apr 16 12:18:39 PM PDT 24 | 11507200000 ps | ||
| T13 | /workspace/coverage/default/27.prim_present_test.2028739286 | Apr 16 12:21:42 PM PDT 24 | Apr 16 12:23:03 PM PDT 24 | 10934940000 ps | ||
| T14 | /workspace/coverage/default/1.prim_present_test.474250631 | Apr 16 12:18:38 PM PDT 24 | Apr 16 12:20:16 PM PDT 24 | 11037860000 ps | ||
| T15 | /workspace/coverage/default/30.prim_present_test.3388900054 | Apr 16 12:21:01 PM PDT 24 | Apr 16 12:22:22 PM PDT 24 | 13215300000 ps | ||
| T16 | /workspace/coverage/default/34.prim_present_test.1865390311 | Apr 16 12:16:47 PM PDT 24 | Apr 16 12:18:00 PM PDT 24 | 8747580000 ps | ||
| T17 | /workspace/coverage/default/48.prim_present_test.2034464131 | Apr 16 12:21:45 PM PDT 24 | Apr 16 12:22:14 PM PDT 24 | 4047980000 ps | ||
| T18 | /workspace/coverage/default/10.prim_present_test.22824470 | Apr 16 12:22:46 PM PDT 24 | Apr 16 12:23:24 PM PDT 24 | 4948840000 ps | ||
| T19 | /workspace/coverage/default/31.prim_present_test.1978614841 | Apr 16 12:18:31 PM PDT 24 | Apr 16 12:19:41 PM PDT 24 | 9846220000 ps | ||
| T20 | /workspace/coverage/default/37.prim_present_test.121006023 | Apr 16 12:16:32 PM PDT 24 | Apr 16 12:17:42 PM PDT 24 | 8702320000 ps | ||
| T21 | /workspace/coverage/default/4.prim_present_test.1954038896 | Apr 16 12:22:52 PM PDT 24 | Apr 16 12:23:39 PM PDT 24 | 6867740000 ps | ||
| T22 | /workspace/coverage/default/11.prim_present_test.390008873 | Apr 16 12:21:20 PM PDT 24 | Apr 16 12:21:44 PM PDT 24 | 3320720000 ps | ||
| T23 | /workspace/coverage/default/46.prim_present_test.897262570 | Apr 16 12:21:16 PM PDT 24 | Apr 16 12:22:21 PM PDT 24 | 9147480000 ps | ||
| T24 | /workspace/coverage/default/26.prim_present_test.1193369876 | Apr 16 12:22:38 PM PDT 24 | Apr 16 12:23:15 PM PDT 24 | 5792040000 ps | ||
| T25 | /workspace/coverage/default/40.prim_present_test.3788546567 | Apr 16 12:21:45 PM PDT 24 | Apr 16 12:22:57 PM PDT 24 | 10331060000 ps | ||
| T26 | /workspace/coverage/default/16.prim_present_test.798004123 | Apr 16 12:21:19 PM PDT 24 | Apr 16 12:22:51 PM PDT 24 | 14384000000 ps | ||
| T27 | /workspace/coverage/default/29.prim_present_test.695578268 | Apr 16 12:21:01 PM PDT 24 | Apr 16 12:21:56 PM PDT 24 | 8433240000 ps | ||
| T28 | /workspace/coverage/default/39.prim_present_test.2150835529 | Apr 16 12:17:16 PM PDT 24 | Apr 16 12:18:10 PM PDT 24 | 6485200000 ps | ||
| T29 | /workspace/coverage/default/18.prim_present_test.1281326743 | Apr 16 12:20:54 PM PDT 24 | Apr 16 12:22:27 PM PDT 24 | 14627660000 ps | ||
| T30 | /workspace/coverage/default/22.prim_present_test.1185563208 | Apr 16 12:21:43 PM PDT 24 | Apr 16 12:23:10 PM PDT 24 | 11986460000 ps | ||
| T31 | /workspace/coverage/default/23.prim_present_test.1954295562 | Apr 16 12:21:42 PM PDT 24 | Apr 16 12:22:44 PM PDT 24 | 8354500000 ps | ||
| T32 | /workspace/coverage/default/2.prim_present_test.2724282494 | Apr 16 12:21:08 PM PDT 24 | Apr 16 12:21:33 PM PDT 24 | 3407520000 ps | ||
| T33 | /workspace/coverage/default/36.prim_present_test.3177757015 | Apr 16 12:17:05 PM PDT 24 | Apr 16 12:18:28 PM PDT 24 | 9873500000 ps | ||
| T34 | /workspace/coverage/default/17.prim_present_test.4119572536 | Apr 16 12:17:16 PM PDT 24 | Apr 16 12:18:38 PM PDT 24 | 9055100000 ps | ||
| T35 | /workspace/coverage/default/20.prim_present_test.3534329553 | Apr 16 12:19:28 PM PDT 24 | Apr 16 12:20:31 PM PDT 24 | 8476020000 ps | ||
| T36 | /workspace/coverage/default/42.prim_present_test.4106077206 | Apr 16 12:22:24 PM PDT 24 | Apr 16 12:23:31 PM PDT 24 | 12898480000 ps | ||
| T37 | /workspace/coverage/default/15.prim_present_test.2447750487 | Apr 16 12:18:34 PM PDT 24 | Apr 16 12:20:03 PM PDT 24 | 11285860000 ps | ||
| T38 | /workspace/coverage/default/47.prim_present_test.965652448 | Apr 16 12:16:24 PM PDT 24 | Apr 16 12:18:16 PM PDT 24 | 14484440000 ps | ||
| T39 | /workspace/coverage/default/3.prim_present_test.2817633265 | Apr 16 12:20:05 PM PDT 24 | Apr 16 12:21:40 PM PDT 24 | 11305700000 ps | ||
| T40 | /workspace/coverage/default/33.prim_present_test.2011514906 | Apr 16 12:16:57 PM PDT 24 | Apr 16 12:18:04 PM PDT 24 | 10286420000 ps | ||
| T41 | /workspace/coverage/default/9.prim_present_test.1091303917 | Apr 16 12:21:26 PM PDT 24 | Apr 16 12:23:00 PM PDT 24 | 14367880000 ps | ||
| T42 | /workspace/coverage/default/14.prim_present_test.1701830718 | Apr 16 12:21:21 PM PDT 24 | Apr 16 12:22:46 PM PDT 24 | 12874920000 ps | ||
| T43 | /workspace/coverage/default/49.prim_present_test.2962912558 | Apr 16 12:18:16 PM PDT 24 | Apr 16 12:19:46 PM PDT 24 | 13857620000 ps | ||
| T44 | /workspace/coverage/default/32.prim_present_test.3750933877 | Apr 16 12:21:20 PM PDT 24 | Apr 16 12:22:24 PM PDT 24 | 11223240000 ps | ||
| T45 | /workspace/coverage/default/6.prim_present_test.864031140 | Apr 16 12:21:19 PM PDT 24 | Apr 16 12:21:52 PM PDT 24 | 4742380000 ps | ||
| T46 | /workspace/coverage/default/7.prim_present_test.2632634594 | Apr 16 12:21:20 PM PDT 24 | Apr 16 12:23:07 PM PDT 24 | 15128620000 ps | ||
| T47 | /workspace/coverage/default/45.prim_present_test.2337033170 | Apr 16 12:21:43 PM PDT 24 | Apr 16 12:22:44 PM PDT 24 | 7953980000 ps | ||
| T48 | /workspace/coverage/default/21.prim_present_test.3839373907 | Apr 16 12:22:44 PM PDT 24 | Apr 16 12:23:36 PM PDT 24 | 7081640000 ps | ||
| T49 | /workspace/coverage/default/13.prim_present_test.2918090200 | Apr 16 12:18:34 PM PDT 24 | Apr 16 12:20:31 PM PDT 24 | 14617120000 ps | ||
| T50 | /workspace/coverage/default/44.prim_present_test.970068384 | Apr 16 12:19:28 PM PDT 24 | Apr 16 12:21:07 PM PDT 24 | 12497960000 ps |
| Test location | /workspace/coverage/default/0.prim_present_test.2670539435 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 12189200000 ps |
| CPU time | 41.19 seconds |
| Started | Apr 16 12:21:08 PM PDT 24 |
| Finished | Apr 16 12:22:27 PM PDT 24 |
| Peak memory | 143620 kb |
| Host | smart-d39f5dc5-3024-4216-8e08-2f4799795718 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2670539435 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.2670539435 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/1.prim_present_test.474250631 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 11037860000 ps |
| CPU time | 48.7 seconds |
| Started | Apr 16 12:18:38 PM PDT 24 |
| Finished | Apr 16 12:20:16 PM PDT 24 |
| Peak memory | 145020 kb |
| Host | smart-79aa0f77-88e6-4c38-ae23-25da69075e97 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=474250631 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.474250631 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/10.prim_present_test.22824470 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 4948840000 ps |
| CPU time | 18 seconds |
| Started | Apr 16 12:22:46 PM PDT 24 |
| Finished | Apr 16 12:23:24 PM PDT 24 |
| Peak memory | 144620 kb |
| Host | smart-e8882f88-b0b1-44ea-b9fe-c8b5d2926e6b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=22824470 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.22824470 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/11.prim_present_test.390008873 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 3320720000 ps |
| CPU time | 12.37 seconds |
| Started | Apr 16 12:21:20 PM PDT 24 |
| Finished | Apr 16 12:21:44 PM PDT 24 |
| Peak memory | 144540 kb |
| Host | smart-5aed13d7-880c-4ab5-a3dc-3a4b887cc0eb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=390008873 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.390008873 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.4226483579 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 13974180000 ps |
| CPU time | 50.07 seconds |
| Started | Apr 16 12:21:19 PM PDT 24 |
| Finished | Apr 16 12:22:55 PM PDT 24 |
| Peak memory | 143876 kb |
| Host | smart-52beafe4-54bb-4f65-b545-ee83f44f4e8d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4226483579 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.4226483579 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.2918090200 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 14617120000 ps |
| CPU time | 61.14 seconds |
| Started | Apr 16 12:18:34 PM PDT 24 |
| Finished | Apr 16 12:20:31 PM PDT 24 |
| Peak memory | 145064 kb |
| Host | smart-916c1bc4-6a5a-45df-aca7-e37bcbc6b090 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2918090200 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.2918090200 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.1701830718 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 12874920000 ps |
| CPU time | 45.25 seconds |
| Started | Apr 16 12:21:21 PM PDT 24 |
| Finished | Apr 16 12:22:46 PM PDT 24 |
| Peak memory | 144832 kb |
| Host | smart-0092e8a0-0e85-4ef9-90cf-06336ba4f79f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1701830718 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.1701830718 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.2447750487 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 11285860000 ps |
| CPU time | 46.11 seconds |
| Started | Apr 16 12:18:34 PM PDT 24 |
| Finished | Apr 16 12:20:03 PM PDT 24 |
| Peak memory | 145068 kb |
| Host | smart-58c9b463-771e-47be-9fd5-120bc6885cba |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2447750487 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.2447750487 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.798004123 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 14384000000 ps |
| CPU time | 48.52 seconds |
| Started | Apr 16 12:21:19 PM PDT 24 |
| Finished | Apr 16 12:22:51 PM PDT 24 |
| Peak memory | 144688 kb |
| Host | smart-2a64a4f6-a863-42ed-9039-169334ef0f48 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=798004123 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.798004123 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.4119572536 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 9055100000 ps |
| CPU time | 40.99 seconds |
| Started | Apr 16 12:17:16 PM PDT 24 |
| Finished | Apr 16 12:18:38 PM PDT 24 |
| Peak memory | 144884 kb |
| Host | smart-03908b40-7b76-4985-90df-5306fa7ed941 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4119572536 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.4119572536 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.1281326743 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 14627660000 ps |
| CPU time | 49.34 seconds |
| Started | Apr 16 12:20:54 PM PDT 24 |
| Finished | Apr 16 12:22:27 PM PDT 24 |
| Peak memory | 143332 kb |
| Host | smart-c80f683e-43f1-4d40-aa37-0f3ba787435f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1281326743 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.1281326743 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.4137622270 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 11767600000 ps |
| CPU time | 40.31 seconds |
| Started | Apr 16 12:20:54 PM PDT 24 |
| Finished | Apr 16 12:22:10 PM PDT 24 |
| Peak memory | 143408 kb |
| Host | smart-ab7ef314-f57d-4d4e-a352-d612823249f9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4137622270 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.4137622270 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.2724282494 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 3407520000 ps |
| CPU time | 12.08 seconds |
| Started | Apr 16 12:21:08 PM PDT 24 |
| Finished | Apr 16 12:21:33 PM PDT 24 |
| Peak memory | 144524 kb |
| Host | smart-1a941a4d-04ed-4f8c-845b-a6f0bc0c9629 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2724282494 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.2724282494 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.3534329553 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 8476020000 ps |
| CPU time | 32.67 seconds |
| Started | Apr 16 12:19:28 PM PDT 24 |
| Finished | Apr 16 12:20:31 PM PDT 24 |
| Peak memory | 144996 kb |
| Host | smart-f646b1b9-374d-4f9b-8ecf-67eece6b14d7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3534329553 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.3534329553 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.3839373907 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 7081640000 ps |
| CPU time | 24.74 seconds |
| Started | Apr 16 12:22:44 PM PDT 24 |
| Finished | Apr 16 12:23:36 PM PDT 24 |
| Peak memory | 143424 kb |
| Host | smart-8d46da21-8fa8-4619-b4cd-6f0c52243fc1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3839373907 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.3839373907 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.1185563208 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 11986460000 ps |
| CPU time | 44.31 seconds |
| Started | Apr 16 12:21:43 PM PDT 24 |
| Finished | Apr 16 12:23:10 PM PDT 24 |
| Peak memory | 144672 kb |
| Host | smart-5d3c2280-d7b2-479c-8525-1b0554633f5b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1185563208 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.1185563208 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.1954295562 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 8354500000 ps |
| CPU time | 31.12 seconds |
| Started | Apr 16 12:21:42 PM PDT 24 |
| Finished | Apr 16 12:22:44 PM PDT 24 |
| Peak memory | 144656 kb |
| Host | smart-af7a85a5-42cd-4ef8-94a5-651459f41854 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1954295562 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.1954295562 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.3896464161 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 4362320000 ps |
| CPU time | 13.44 seconds |
| Started | Apr 16 12:22:58 PM PDT 24 |
| Finished | Apr 16 12:23:26 PM PDT 24 |
| Peak memory | 145060 kb |
| Host | smart-f704ff27-ecee-4d71-b833-71f251df62d1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3896464161 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.3896464161 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.1937706277 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 3446580000 ps |
| CPU time | 12.91 seconds |
| Started | Apr 16 12:21:43 PM PDT 24 |
| Finished | Apr 16 12:22:11 PM PDT 24 |
| Peak memory | 144524 kb |
| Host | smart-0296dfd4-c520-49a7-b504-84b1d58fbf45 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1937706277 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.1937706277 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.1193369876 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 5792040000 ps |
| CPU time | 17.31 seconds |
| Started | Apr 16 12:22:38 PM PDT 24 |
| Finished | Apr 16 12:23:15 PM PDT 24 |
| Peak memory | 143860 kb |
| Host | smart-7b0a1ae9-aa8e-4b0c-a4dd-d919b4ebfc75 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1193369876 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.1193369876 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.2028739286 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 10934940000 ps |
| CPU time | 41.53 seconds |
| Started | Apr 16 12:21:42 PM PDT 24 |
| Finished | Apr 16 12:23:03 PM PDT 24 |
| Peak memory | 143112 kb |
| Host | smart-3b20cf2e-17d8-44a9-9c62-d0a2863bbbc6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2028739286 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.2028739286 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.1084247277 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 9791040000 ps |
| CPU time | 29.35 seconds |
| Started | Apr 16 12:22:38 PM PDT 24 |
| Finished | Apr 16 12:23:36 PM PDT 24 |
| Peak memory | 143744 kb |
| Host | smart-c90593c6-fed5-4463-9d55-02b2eeba7ded |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1084247277 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.1084247277 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.695578268 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 8433240000 ps |
| CPU time | 29.54 seconds |
| Started | Apr 16 12:21:01 PM PDT 24 |
| Finished | Apr 16 12:21:56 PM PDT 24 |
| Peak memory | 143464 kb |
| Host | smart-d90b5d6e-834a-48bf-8239-602214e7c4b0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=695578268 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.695578268 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.2817633265 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 11305700000 ps |
| CPU time | 46.99 seconds |
| Started | Apr 16 12:20:05 PM PDT 24 |
| Finished | Apr 16 12:21:40 PM PDT 24 |
| Peak memory | 145028 kb |
| Host | smart-74203c34-a562-4292-9a72-d3c031dd6c72 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2817633265 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.2817633265 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.3388900054 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 13215300000 ps |
| CPU time | 43.56 seconds |
| Started | Apr 16 12:21:01 PM PDT 24 |
| Finished | Apr 16 12:22:22 PM PDT 24 |
| Peak memory | 143768 kb |
| Host | smart-f6b53b22-b7cc-4b27-8849-df916bb312e2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3388900054 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.3388900054 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.1978614841 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 9846220000 ps |
| CPU time | 36.97 seconds |
| Started | Apr 16 12:18:31 PM PDT 24 |
| Finished | Apr 16 12:19:41 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-048a704f-debc-4870-917a-bd3cbc16771a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1978614841 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.1978614841 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.3750933877 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 11223240000 ps |
| CPU time | 34.57 seconds |
| Started | Apr 16 12:21:20 PM PDT 24 |
| Finished | Apr 16 12:22:24 PM PDT 24 |
| Peak memory | 143460 kb |
| Host | smart-e62781af-90ba-4399-9ec2-c3745858d6a0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3750933877 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.3750933877 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.2011514906 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 10286420000 ps |
| CPU time | 34.62 seconds |
| Started | Apr 16 12:16:57 PM PDT 24 |
| Finished | Apr 16 12:18:04 PM PDT 24 |
| Peak memory | 144948 kb |
| Host | smart-ae9f1607-7bc9-4596-bd4f-26bba8ce4a0b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2011514906 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.2011514906 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.1865390311 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 8747580000 ps |
| CPU time | 37.06 seconds |
| Started | Apr 16 12:16:47 PM PDT 24 |
| Finished | Apr 16 12:18:00 PM PDT 24 |
| Peak memory | 144952 kb |
| Host | smart-40a99281-208a-4267-9d63-115da7545b3f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1865390311 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.1865390311 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.1109335608 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 11370800000 ps |
| CPU time | 50.07 seconds |
| Started | Apr 16 12:17:44 PM PDT 24 |
| Finished | Apr 16 12:19:24 PM PDT 24 |
| Peak memory | 144996 kb |
| Host | smart-dbd3ad73-9cfd-4c81-a7e9-e6cdc3f88625 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1109335608 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.1109335608 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.3177757015 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 9873500000 ps |
| CPU time | 42.89 seconds |
| Started | Apr 16 12:17:05 PM PDT 24 |
| Finished | Apr 16 12:18:28 PM PDT 24 |
| Peak memory | 144932 kb |
| Host | smart-1fd68a7d-d4ef-432c-834a-77852117acfb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3177757015 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.3177757015 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.121006023 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 8702320000 ps |
| CPU time | 36.69 seconds |
| Started | Apr 16 12:16:32 PM PDT 24 |
| Finished | Apr 16 12:17:42 PM PDT 24 |
| Peak memory | 144872 kb |
| Host | smart-c69a145b-da0e-4ca7-9f83-dd76dbf3ad79 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=121006023 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.121006023 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.2320640472 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 6014620000 ps |
| CPU time | 24.69 seconds |
| Started | Apr 16 12:16:58 PM PDT 24 |
| Finished | Apr 16 12:17:45 PM PDT 24 |
| Peak memory | 144516 kb |
| Host | smart-b6079671-18ad-4d4c-81b8-ac9c99210981 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2320640472 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.2320640472 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.2150835529 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 6485200000 ps |
| CPU time | 27.1 seconds |
| Started | Apr 16 12:17:16 PM PDT 24 |
| Finished | Apr 16 12:18:10 PM PDT 24 |
| Peak memory | 145312 kb |
| Host | smart-bd554981-3b0b-435a-be07-3be9a6480935 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2150835529 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.2150835529 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.1954038896 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 6867740000 ps |
| CPU time | 23.17 seconds |
| Started | Apr 16 12:22:52 PM PDT 24 |
| Finished | Apr 16 12:23:39 PM PDT 24 |
| Peak memory | 145036 kb |
| Host | smart-8fa45a7e-7f8f-4cfb-af1c-fbcf0224d221 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1954038896 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.1954038896 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.3788546567 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 10331060000 ps |
| CPU time | 36.1 seconds |
| Started | Apr 16 12:21:45 PM PDT 24 |
| Finished | Apr 16 12:22:57 PM PDT 24 |
| Peak memory | 144728 kb |
| Host | smart-8c533398-731f-46db-8223-fd12886c2409 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3788546567 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.3788546567 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.3108804009 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 8084180000 ps |
| CPU time | 29.03 seconds |
| Started | Apr 16 12:21:44 PM PDT 24 |
| Finished | Apr 16 12:22:42 PM PDT 24 |
| Peak memory | 144728 kb |
| Host | smart-46f48b4a-9bd7-4492-9966-01c7eb7e7891 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3108804009 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.3108804009 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.4106077206 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 12898480000 ps |
| CPU time | 35.77 seconds |
| Started | Apr 16 12:22:24 PM PDT 24 |
| Finished | Apr 16 12:23:31 PM PDT 24 |
| Peak memory | 144932 kb |
| Host | smart-2495ac31-bdcd-4b90-8555-1c9acdba194a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4106077206 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.4106077206 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.17630420 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 11507200000 ps |
| CPU time | 46.33 seconds |
| Started | Apr 16 12:17:08 PM PDT 24 |
| Finished | Apr 16 12:18:39 PM PDT 24 |
| Peak memory | 145312 kb |
| Host | smart-81b21c9a-95ff-4d80-92d0-43a0addc0e6c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=17630420 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.17630420 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.970068384 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 12497960000 ps |
| CPU time | 50.79 seconds |
| Started | Apr 16 12:19:28 PM PDT 24 |
| Finished | Apr 16 12:21:07 PM PDT 24 |
| Peak memory | 145312 kb |
| Host | smart-86a0e7d0-3bae-4ca6-bc35-8ef46f51d97a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=970068384 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.970068384 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.2337033170 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 7953980000 ps |
| CPU time | 30.65 seconds |
| Started | Apr 16 12:21:43 PM PDT 24 |
| Finished | Apr 16 12:22:44 PM PDT 24 |
| Peak memory | 143484 kb |
| Host | smart-355b5bd9-c653-40f6-8096-83d175981c9b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2337033170 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.2337033170 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.897262570 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 9147480000 ps |
| CPU time | 34.04 seconds |
| Started | Apr 16 12:21:16 PM PDT 24 |
| Finished | Apr 16 12:22:21 PM PDT 24 |
| Peak memory | 144320 kb |
| Host | smart-d16046f2-0487-4e18-80b5-9287e2432add |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=897262570 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.897262570 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.965652448 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 14484440000 ps |
| CPU time | 58.43 seconds |
| Started | Apr 16 12:16:24 PM PDT 24 |
| Finished | Apr 16 12:18:16 PM PDT 24 |
| Peak memory | 143680 kb |
| Host | smart-dd3ca3b3-106e-46ef-a639-330551ad33db |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=965652448 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.965652448 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.2034464131 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 4047980000 ps |
| CPU time | 13.84 seconds |
| Started | Apr 16 12:21:45 PM PDT 24 |
| Finished | Apr 16 12:22:14 PM PDT 24 |
| Peak memory | 144576 kb |
| Host | smart-1e9ac290-28fe-486f-9e3b-04556845c3d6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2034464131 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.2034464131 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.2962912558 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 13857620000 ps |
| CPU time | 47.06 seconds |
| Started | Apr 16 12:18:16 PM PDT 24 |
| Finished | Apr 16 12:19:46 PM PDT 24 |
| Peak memory | 144952 kb |
| Host | smart-672967ff-857f-4bd7-af92-8176b3ebd52c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2962912558 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.2962912558 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.3494410688 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 7560280000 ps |
| CPU time | 26.08 seconds |
| Started | Apr 16 12:21:26 PM PDT 24 |
| Finished | Apr 16 12:22:16 PM PDT 24 |
| Peak memory | 145008 kb |
| Host | smart-26cc61fe-57c5-4892-b2b7-9ae2b7b1ef87 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3494410688 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.3494410688 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.864031140 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 4742380000 ps |
| CPU time | 17.07 seconds |
| Started | Apr 16 12:21:19 PM PDT 24 |
| Finished | Apr 16 12:21:52 PM PDT 24 |
| Peak memory | 144644 kb |
| Host | smart-aac18624-b196-4464-aede-12c936f34913 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=864031140 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.864031140 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.2632634594 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 15128620000 ps |
| CPU time | 55.48 seconds |
| Started | Apr 16 12:21:20 PM PDT 24 |
| Finished | Apr 16 12:23:07 PM PDT 24 |
| Peak memory | 144720 kb |
| Host | smart-4805b1be-51ef-4f68-8583-c38238364002 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2632634594 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.2632634594 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.2451823463 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 12669080000 ps |
| CPU time | 45.98 seconds |
| Started | Apr 16 12:21:19 PM PDT 24 |
| Finished | Apr 16 12:22:48 PM PDT 24 |
| Peak memory | 144652 kb |
| Host | smart-77f9f110-c4c7-4da5-9f55-c953c59dbfe1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2451823463 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.2451823463 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.1091303917 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 14367880000 ps |
| CPU time | 49.22 seconds |
| Started | Apr 16 12:21:26 PM PDT 24 |
| Finished | Apr 16 12:23:00 PM PDT 24 |
| Peak memory | 145028 kb |
| Host | smart-dd7d90df-47e2-4efc-b20b-dc65921ab9af |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1091303917 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.1091303917 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |