| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/0.prim_present_test.3446048758 | ||
| Name |
|---|
| /workspace/coverage/default/1.prim_present_test.2222813875 |
| /workspace/coverage/default/10.prim_present_test.3441411781 |
| /workspace/coverage/default/11.prim_present_test.3586783280 |
| /workspace/coverage/default/12.prim_present_test.137674188 |
| /workspace/coverage/default/13.prim_present_test.1282404276 |
| /workspace/coverage/default/14.prim_present_test.1236498634 |
| /workspace/coverage/default/15.prim_present_test.4126154847 |
| /workspace/coverage/default/16.prim_present_test.2683976347 |
| /workspace/coverage/default/17.prim_present_test.4051824872 |
| /workspace/coverage/default/18.prim_present_test.171211512 |
| /workspace/coverage/default/19.prim_present_test.1899740370 |
| /workspace/coverage/default/2.prim_present_test.219148775 |
| /workspace/coverage/default/20.prim_present_test.2883762156 |
| /workspace/coverage/default/21.prim_present_test.3385655662 |
| /workspace/coverage/default/22.prim_present_test.2540073311 |
| /workspace/coverage/default/23.prim_present_test.3833780916 |
| /workspace/coverage/default/24.prim_present_test.3174762033 |
| /workspace/coverage/default/25.prim_present_test.3470581039 |
| /workspace/coverage/default/26.prim_present_test.2058047878 |
| /workspace/coverage/default/27.prim_present_test.2209064466 |
| /workspace/coverage/default/28.prim_present_test.3778787895 |
| /workspace/coverage/default/29.prim_present_test.1525036951 |
| /workspace/coverage/default/3.prim_present_test.4208564109 |
| /workspace/coverage/default/30.prim_present_test.3772814492 |
| /workspace/coverage/default/31.prim_present_test.2947057077 |
| /workspace/coverage/default/32.prim_present_test.2196664431 |
| /workspace/coverage/default/33.prim_present_test.3160399325 |
| /workspace/coverage/default/34.prim_present_test.24169384 |
| /workspace/coverage/default/35.prim_present_test.2726646014 |
| /workspace/coverage/default/36.prim_present_test.4043770704 |
| /workspace/coverage/default/37.prim_present_test.2839143587 |
| /workspace/coverage/default/38.prim_present_test.3769193156 |
| /workspace/coverage/default/39.prim_present_test.416726243 |
| /workspace/coverage/default/4.prim_present_test.654929370 |
| /workspace/coverage/default/40.prim_present_test.2285607033 |
| /workspace/coverage/default/41.prim_present_test.4190198771 |
| /workspace/coverage/default/42.prim_present_test.1434529823 |
| /workspace/coverage/default/43.prim_present_test.1629805876 |
| /workspace/coverage/default/44.prim_present_test.2307894316 |
| /workspace/coverage/default/45.prim_present_test.636437143 |
| /workspace/coverage/default/46.prim_present_test.954383416 |
| /workspace/coverage/default/47.prim_present_test.2190924343 |
| /workspace/coverage/default/48.prim_present_test.2080538187 |
| /workspace/coverage/default/49.prim_present_test.300772343 |
| /workspace/coverage/default/5.prim_present_test.3627373843 |
| /workspace/coverage/default/6.prim_present_test.3693250822 |
| /workspace/coverage/default/7.prim_present_test.1071696196 |
| /workspace/coverage/default/8.prim_present_test.4242240870 |
| /workspace/coverage/default/9.prim_present_test.208215689 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/25.prim_present_test.3470581039 | Apr 18 01:13:13 PM PDT 24 | Apr 18 01:14:26 PM PDT 24 | 10910760000 ps | ||
| T2 | /workspace/coverage/default/2.prim_present_test.219148775 | Apr 18 01:13:01 PM PDT 24 | Apr 18 01:13:39 PM PDT 24 | 5028820000 ps | ||
| T3 | /workspace/coverage/default/12.prim_present_test.137674188 | Apr 18 01:13:08 PM PDT 24 | Apr 18 01:13:47 PM PDT 24 | 5810640000 ps | ||
| T4 | /workspace/coverage/default/44.prim_present_test.2307894316 | Apr 18 01:13:21 PM PDT 24 | Apr 18 01:14:11 PM PDT 24 | 8447500000 ps | ||
| T5 | /workspace/coverage/default/7.prim_present_test.1071696196 | Apr 18 01:13:09 PM PDT 24 | Apr 18 01:14:38 PM PDT 24 | 14052300000 ps | ||
| T6 | /workspace/coverage/default/16.prim_present_test.2683976347 | Apr 18 01:13:14 PM PDT 24 | Apr 18 01:14:38 PM PDT 24 | 13749740000 ps | ||
| T7 | /workspace/coverage/default/39.prim_present_test.416726243 | Apr 18 01:13:14 PM PDT 24 | Apr 18 01:15:00 PM PDT 24 | 14718800000 ps | ||
| T8 | /workspace/coverage/default/15.prim_present_test.4126154847 | Apr 18 01:13:13 PM PDT 24 | Apr 18 01:14:01 PM PDT 24 | 6408940000 ps | ||
| T9 | /workspace/coverage/default/17.prim_present_test.4051824872 | Apr 18 01:13:13 PM PDT 24 | Apr 18 01:14:30 PM PDT 24 | 13851420000 ps | ||
| T10 | /workspace/coverage/default/0.prim_present_test.3446048758 | Apr 18 01:12:59 PM PDT 24 | Apr 18 01:13:51 PM PDT 24 | 10065080000 ps | ||
| T11 | /workspace/coverage/default/35.prim_present_test.2726646014 | Apr 18 01:13:14 PM PDT 24 | Apr 18 01:14:31 PM PDT 24 | 13002020000 ps | ||
| T12 | /workspace/coverage/default/34.prim_present_test.24169384 | Apr 18 01:13:15 PM PDT 24 | Apr 18 01:14:44 PM PDT 24 | 14892400000 ps | ||
| T13 | /workspace/coverage/default/20.prim_present_test.2883762156 | Apr 18 01:13:14 PM PDT 24 | Apr 18 01:14:22 PM PDT 24 | 11411100000 ps | ||
| T14 | /workspace/coverage/default/38.prim_present_test.3769193156 | Apr 18 01:13:14 PM PDT 24 | Apr 18 01:14:15 PM PDT 24 | 9474220000 ps | ||
| T15 | /workspace/coverage/default/48.prim_present_test.2080538187 | Apr 18 01:13:22 PM PDT 24 | Apr 18 01:13:49 PM PDT 24 | 4395800000 ps | ||
| T16 | /workspace/coverage/default/14.prim_present_test.1236498634 | Apr 18 01:13:06 PM PDT 24 | Apr 18 01:14:36 PM PDT 24 | 14536520000 ps | ||
| T17 | /workspace/coverage/default/33.prim_present_test.3160399325 | Apr 18 01:13:13 PM PDT 24 | Apr 18 01:13:59 PM PDT 24 | 5934020000 ps | ||
| T18 | /workspace/coverage/default/4.prim_present_test.654929370 | Apr 18 01:13:07 PM PDT 24 | Apr 18 01:14:03 PM PDT 24 | 9402920000 ps | ||
| T19 | /workspace/coverage/default/40.prim_present_test.2285607033 | Apr 18 01:13:14 PM PDT 24 | Apr 18 01:14:22 PM PDT 24 | 9691220000 ps | ||
| T20 | /workspace/coverage/default/23.prim_present_test.3833780916 | Apr 18 01:13:14 PM PDT 24 | Apr 18 01:14:36 PM PDT 24 | 11695680000 ps | ||
| T21 | /workspace/coverage/default/42.prim_present_test.1434529823 | Apr 18 01:13:23 PM PDT 24 | Apr 18 01:13:48 PM PDT 24 | 4028760000 ps | ||
| T22 | /workspace/coverage/default/30.prim_present_test.3772814492 | Apr 18 01:13:15 PM PDT 24 | Apr 18 01:14:02 PM PDT 24 | 7098380000 ps | ||
| T23 | /workspace/coverage/default/11.prim_present_test.3586783280 | Apr 18 01:13:10 PM PDT 24 | Apr 18 01:14:36 PM PDT 24 | 11579740000 ps | ||
| T24 | /workspace/coverage/default/24.prim_present_test.3174762033 | Apr 18 01:13:14 PM PDT 24 | Apr 18 01:13:51 PM PDT 24 | 5099500000 ps | ||
| T25 | /workspace/coverage/default/43.prim_present_test.1629805876 | Apr 18 01:13:25 PM PDT 24 | Apr 18 01:14:47 PM PDT 24 | 13340540000 ps | ||
| T26 | /workspace/coverage/default/21.prim_present_test.3385655662 | Apr 18 01:13:14 PM PDT 24 | Apr 18 01:14:15 PM PDT 24 | 7598720000 ps | ||
| T27 | /workspace/coverage/default/6.prim_present_test.3693250822 | Apr 18 01:13:07 PM PDT 24 | Apr 18 01:14:22 PM PDT 24 | 10629900000 ps | ||
| T28 | /workspace/coverage/default/26.prim_present_test.2058047878 | Apr 18 01:13:14 PM PDT 24 | Apr 18 01:14:48 PM PDT 24 | 13226460000 ps | ||
| T29 | /workspace/coverage/default/46.prim_present_test.954383416 | Apr 18 01:13:21 PM PDT 24 | Apr 18 01:14:08 PM PDT 24 | 7820060000 ps | ||
| T30 | /workspace/coverage/default/32.prim_present_test.2196664431 | Apr 18 01:13:14 PM PDT 24 | Apr 18 01:14:05 PM PDT 24 | 8048220000 ps | ||
| T31 | /workspace/coverage/default/19.prim_present_test.1899740370 | Apr 18 01:13:16 PM PDT 24 | Apr 18 01:14:00 PM PDT 24 | 5921000000 ps | ||
| T32 | /workspace/coverage/default/3.prim_present_test.4208564109 | Apr 18 01:13:01 PM PDT 24 | Apr 18 01:14:46 PM PDT 24 | 14342460000 ps | ||
| T33 | /workspace/coverage/default/29.prim_present_test.1525036951 | Apr 18 01:13:18 PM PDT 24 | Apr 18 01:14:47 PM PDT 24 | 13739820000 ps | ||
| T34 | /workspace/coverage/default/45.prim_present_test.636437143 | Apr 18 01:13:21 PM PDT 24 | Apr 18 01:14:14 PM PDT 24 | 8814540000 ps | ||
| T35 | /workspace/coverage/default/27.prim_present_test.2209064466 | Apr 18 01:13:13 PM PDT 24 | Apr 18 01:13:34 PM PDT 24 | 3525320000 ps | ||
| T36 | /workspace/coverage/default/9.prim_present_test.208215689 | Apr 18 01:13:07 PM PDT 24 | Apr 18 01:13:37 PM PDT 24 | 4995340000 ps | ||
| T37 | /workspace/coverage/default/36.prim_present_test.4043770704 | Apr 18 01:13:13 PM PDT 24 | Apr 18 01:14:07 PM PDT 24 | 9654020000 ps | ||
| T38 | /workspace/coverage/default/37.prim_present_test.2839143587 | Apr 18 01:13:16 PM PDT 24 | Apr 18 01:14:49 PM PDT 24 | 12785020000 ps | ||
| T39 | /workspace/coverage/default/1.prim_present_test.2222813875 | Apr 18 01:13:02 PM PDT 24 | Apr 18 01:14:03 PM PDT 24 | 10495980000 ps | ||
| T40 | /workspace/coverage/default/28.prim_present_test.3778787895 | Apr 18 01:13:13 PM PDT 24 | Apr 18 01:14:33 PM PDT 24 | 10775600000 ps | ||
| T41 | /workspace/coverage/default/31.prim_present_test.2947057077 | Apr 18 01:13:15 PM PDT 24 | Apr 18 01:14:30 PM PDT 24 | 12400620000 ps | ||
| T42 | /workspace/coverage/default/8.prim_present_test.4242240870 | Apr 18 01:13:05 PM PDT 24 | Apr 18 01:13:50 PM PDT 24 | 6100180000 ps | ||
| T43 | /workspace/coverage/default/5.prim_present_test.3627373843 | Apr 18 01:13:10 PM PDT 24 | Apr 18 01:14:02 PM PDT 24 | 7800840000 ps | ||
| T44 | /workspace/coverage/default/49.prim_present_test.300772343 | Apr 18 01:13:23 PM PDT 24 | Apr 18 01:14:11 PM PDT 24 | 7305460000 ps | ||
| T45 | /workspace/coverage/default/18.prim_present_test.171211512 | Apr 18 01:13:13 PM PDT 24 | Apr 18 01:14:12 PM PDT 24 | 9955960000 ps | ||
| T46 | /workspace/coverage/default/22.prim_present_test.2540073311 | Apr 18 01:13:11 PM PDT 24 | Apr 18 01:14:54 PM PDT 24 | 14887440000 ps | ||
| T47 | /workspace/coverage/default/41.prim_present_test.4190198771 | Apr 18 01:13:15 PM PDT 24 | Apr 18 01:14:57 PM PDT 24 | 13862580000 ps | ||
| T48 | /workspace/coverage/default/10.prim_present_test.3441411781 | Apr 18 01:13:09 PM PDT 24 | Apr 18 01:13:34 PM PDT 24 | 3431700000 ps | ||
| T49 | /workspace/coverage/default/13.prim_present_test.1282404276 | Apr 18 01:13:07 PM PDT 24 | Apr 18 01:14:05 PM PDT 24 | 9809640000 ps | ||
| T50 | /workspace/coverage/default/47.prim_present_test.2190924343 | Apr 18 01:13:20 PM PDT 24 | Apr 18 01:13:51 PM PDT 24 | 5845360000 ps |
| Test location | /workspace/coverage/default/0.prim_present_test.3446048758 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 10065080000 ps |
| CPU time | 27.82 seconds |
| Started | Apr 18 01:12:59 PM PDT 24 |
| Finished | Apr 18 01:13:51 PM PDT 24 |
| Peak memory | 145212 kb |
| Host | smart-fd1adcc8-e9d5-4ca9-bb07-65ac1fad2563 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3446048758 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.3446048758 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/1.prim_present_test.2222813875 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 10495980000 ps |
| CPU time | 32.78 seconds |
| Started | Apr 18 01:13:02 PM PDT 24 |
| Finished | Apr 18 01:14:03 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-f8ddd889-c422-498b-98dc-11bdd9d1f3be |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2222813875 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.2222813875 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/10.prim_present_test.3441411781 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 3431700000 ps |
| CPU time | 12.48 seconds |
| Started | Apr 18 01:13:09 PM PDT 24 |
| Finished | Apr 18 01:13:34 PM PDT 24 |
| Peak memory | 145044 kb |
| Host | smart-97452022-92ef-4db9-8951-914c44ffe68e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3441411781 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.3441411781 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/11.prim_present_test.3586783280 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 11579740000 ps |
| CPU time | 44.44 seconds |
| Started | Apr 18 01:13:10 PM PDT 24 |
| Finished | Apr 18 01:14:36 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-cf68c317-db4e-4750-9ccf-9f9cc35deb07 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3586783280 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.3586783280 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.137674188 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 5810640000 ps |
| CPU time | 20.2 seconds |
| Started | Apr 18 01:13:08 PM PDT 24 |
| Finished | Apr 18 01:13:47 PM PDT 24 |
| Peak memory | 145136 kb |
| Host | smart-096ca540-61ff-4c68-b912-82dff94aa969 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=137674188 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.137674188 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.1282404276 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 9809640000 ps |
| CPU time | 30.34 seconds |
| Started | Apr 18 01:13:07 PM PDT 24 |
| Finished | Apr 18 01:14:05 PM PDT 24 |
| Peak memory | 145120 kb |
| Host | smart-c839a98c-4761-4211-ad30-d05668e2e10e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1282404276 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.1282404276 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.1236498634 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 14536520000 ps |
| CPU time | 47.95 seconds |
| Started | Apr 18 01:13:06 PM PDT 24 |
| Finished | Apr 18 01:14:36 PM PDT 24 |
| Peak memory | 145196 kb |
| Host | smart-1a2631ec-01b4-4cf8-b62f-bda1e57b46bf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1236498634 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.1236498634 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.4126154847 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 6408940000 ps |
| CPU time | 25.27 seconds |
| Started | Apr 18 01:13:13 PM PDT 24 |
| Finished | Apr 18 01:14:01 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-ae62f706-bbc2-445f-b48a-0125af76bc50 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4126154847 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.4126154847 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.2683976347 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 13749740000 ps |
| CPU time | 44.64 seconds |
| Started | Apr 18 01:13:14 PM PDT 24 |
| Finished | Apr 18 01:14:38 PM PDT 24 |
| Peak memory | 145200 kb |
| Host | smart-8fa6ee31-0e8a-49ff-94e3-f59ceeaa97f4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2683976347 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.2683976347 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.4051824872 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 13851420000 ps |
| CPU time | 40.86 seconds |
| Started | Apr 18 01:13:13 PM PDT 24 |
| Finished | Apr 18 01:14:30 PM PDT 24 |
| Peak memory | 145092 kb |
| Host | smart-1a60f9df-617d-46e1-aed2-ac68972e0d21 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4051824872 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.4051824872 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.171211512 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 9955960000 ps |
| CPU time | 31.53 seconds |
| Started | Apr 18 01:13:13 PM PDT 24 |
| Finished | Apr 18 01:14:12 PM PDT 24 |
| Peak memory | 145196 kb |
| Host | smart-3bb82a71-cf12-4745-95c7-6ad25f64a5f7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=171211512 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.171211512 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.1899740370 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 5921000000 ps |
| CPU time | 22.94 seconds |
| Started | Apr 18 01:13:16 PM PDT 24 |
| Finished | Apr 18 01:14:00 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-3ebac78e-d0bd-45cf-8ef4-707295c991ee |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1899740370 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.1899740370 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.219148775 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 5028820000 ps |
| CPU time | 18.76 seconds |
| Started | Apr 18 01:13:01 PM PDT 24 |
| Finished | Apr 18 01:13:39 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-65317a30-a2ed-4c6c-850a-4387bf6e05c6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=219148775 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.219148775 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.2883762156 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 11411100000 ps |
| CPU time | 35.96 seconds |
| Started | Apr 18 01:13:14 PM PDT 24 |
| Finished | Apr 18 01:14:22 PM PDT 24 |
| Peak memory | 145144 kb |
| Host | smart-2a538252-8885-474c-8684-d156b8c3a098 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2883762156 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.2883762156 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.3385655662 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 7598720000 ps |
| CPU time | 30.94 seconds |
| Started | Apr 18 01:13:14 PM PDT 24 |
| Finished | Apr 18 01:14:15 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-aeb23ac4-16a1-43af-9971-4650d680eab3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3385655662 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.3385655662 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.2540073311 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 14887440000 ps |
| CPU time | 53.3 seconds |
| Started | Apr 18 01:13:11 PM PDT 24 |
| Finished | Apr 18 01:14:54 PM PDT 24 |
| Peak memory | 145128 kb |
| Host | smart-c783c414-e98b-400d-8664-2287b5652451 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2540073311 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.2540073311 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.3833780916 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 11695680000 ps |
| CPU time | 42.05 seconds |
| Started | Apr 18 01:13:14 PM PDT 24 |
| Finished | Apr 18 01:14:36 PM PDT 24 |
| Peak memory | 145080 kb |
| Host | smart-a404d002-9574-4ccc-93f2-c3399ec0a343 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3833780916 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.3833780916 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.3174762033 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 5099500000 ps |
| CPU time | 18.61 seconds |
| Started | Apr 18 01:13:14 PM PDT 24 |
| Finished | Apr 18 01:13:51 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-17d95bd6-2eea-474b-872e-2a34eb1b1fac |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3174762033 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.3174762033 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.3470581039 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 10910760000 ps |
| CPU time | 37.57 seconds |
| Started | Apr 18 01:13:13 PM PDT 24 |
| Finished | Apr 18 01:14:26 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-11076adf-3765-49ad-86f5-29e89b0d857b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3470581039 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.3470581039 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.2058047878 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 13226460000 ps |
| CPU time | 48.2 seconds |
| Started | Apr 18 01:13:14 PM PDT 24 |
| Finished | Apr 18 01:14:48 PM PDT 24 |
| Peak memory | 145052 kb |
| Host | smart-8624d820-eabc-473f-aed9-53d3f1e71e72 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2058047878 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.2058047878 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.2209064466 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 3525320000 ps |
| CPU time | 11.35 seconds |
| Started | Apr 18 01:13:13 PM PDT 24 |
| Finished | Apr 18 01:13:34 PM PDT 24 |
| Peak memory | 144980 kb |
| Host | smart-81faab22-4644-463c-a025-479680aae93a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2209064466 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.2209064466 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.3778787895 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 10775600000 ps |
| CPU time | 39.68 seconds |
| Started | Apr 18 01:13:13 PM PDT 24 |
| Finished | Apr 18 01:14:33 PM PDT 24 |
| Peak memory | 145152 kb |
| Host | smart-45f6a9dc-b70b-4cff-a253-b7cbc3b45e1c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3778787895 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.3778787895 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.1525036951 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 13739820000 ps |
| CPU time | 47.09 seconds |
| Started | Apr 18 01:13:18 PM PDT 24 |
| Finished | Apr 18 01:14:47 PM PDT 24 |
| Peak memory | 145120 kb |
| Host | smart-ac1552d3-7d48-4192-97c4-a4ced1350e5f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1525036951 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.1525036951 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.4208564109 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 14342460000 ps |
| CPU time | 54.83 seconds |
| Started | Apr 18 01:13:01 PM PDT 24 |
| Finished | Apr 18 01:14:46 PM PDT 24 |
| Peak memory | 145156 kb |
| Host | smart-dc6188f0-c3a3-4168-8abf-5b65058f688d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4208564109 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.4208564109 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.3772814492 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 7098380000 ps |
| CPU time | 24.42 seconds |
| Started | Apr 18 01:13:15 PM PDT 24 |
| Finished | Apr 18 01:14:02 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-36b1fdca-c1b0-477c-be87-fd9cc699944d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3772814492 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.3772814492 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.2947057077 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 12400620000 ps |
| CPU time | 39.89 seconds |
| Started | Apr 18 01:13:15 PM PDT 24 |
| Finished | Apr 18 01:14:30 PM PDT 24 |
| Peak memory | 145116 kb |
| Host | smart-1c9dd4bf-bd6c-4bb6-b356-1ea9f9f0f04a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2947057077 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.2947057077 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.2196664431 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 8048220000 ps |
| CPU time | 26.91 seconds |
| Started | Apr 18 01:13:14 PM PDT 24 |
| Finished | Apr 18 01:14:05 PM PDT 24 |
| Peak memory | 145200 kb |
| Host | smart-8c1fa8e4-6720-4043-8eff-11a4f3fb61ab |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2196664431 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.2196664431 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.3160399325 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 5934020000 ps |
| CPU time | 22.95 seconds |
| Started | Apr 18 01:13:13 PM PDT 24 |
| Finished | Apr 18 01:13:59 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-7785e598-e663-48b5-81f6-c387b2c38c3d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3160399325 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.3160399325 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.24169384 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 14892400000 ps |
| CPU time | 47.16 seconds |
| Started | Apr 18 01:13:15 PM PDT 24 |
| Finished | Apr 18 01:14:44 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-fd61709b-0b46-41ba-ab91-bf588e2a752b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=24169384 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.24169384 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.2726646014 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 13002020000 ps |
| CPU time | 40.56 seconds |
| Started | Apr 18 01:13:14 PM PDT 24 |
| Finished | Apr 18 01:14:31 PM PDT 24 |
| Peak memory | 145120 kb |
| Host | smart-1816b86d-4f65-4d13-a356-cb3325f3fbf6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2726646014 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.2726646014 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.4043770704 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 9654020000 ps |
| CPU time | 28.48 seconds |
| Started | Apr 18 01:13:13 PM PDT 24 |
| Finished | Apr 18 01:14:07 PM PDT 24 |
| Peak memory | 145296 kb |
| Host | smart-07620a38-d907-4ca7-ad84-ad5b6da8fdfe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4043770704 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.4043770704 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.2839143587 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 12785020000 ps |
| CPU time | 48.84 seconds |
| Started | Apr 18 01:13:16 PM PDT 24 |
| Finished | Apr 18 01:14:49 PM PDT 24 |
| Peak memory | 145196 kb |
| Host | smart-23fab076-dbff-4c4d-a89d-3114e30a46d1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2839143587 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.2839143587 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.3769193156 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 9474220000 ps |
| CPU time | 31.95 seconds |
| Started | Apr 18 01:13:14 PM PDT 24 |
| Finished | Apr 18 01:14:15 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-414fb38b-0e54-4888-94ad-ed8a90775e68 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3769193156 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.3769193156 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.416726243 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 14718800000 ps |
| CPU time | 55.71 seconds |
| Started | Apr 18 01:13:14 PM PDT 24 |
| Finished | Apr 18 01:15:00 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-29e04186-14f3-44ac-a580-4017044d9910 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=416726243 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.416726243 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.654929370 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 9402920000 ps |
| CPU time | 29.46 seconds |
| Started | Apr 18 01:13:07 PM PDT 24 |
| Finished | Apr 18 01:14:03 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-f7e2720f-df03-4135-9743-020e5a10752c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=654929370 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.654929370 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.2285607033 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 9691220000 ps |
| CPU time | 35.3 seconds |
| Started | Apr 18 01:13:14 PM PDT 24 |
| Finished | Apr 18 01:14:22 PM PDT 24 |
| Peak memory | 145136 kb |
| Host | smart-e891f0ad-1298-495e-84fb-ee2c0e9785e2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2285607033 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.2285607033 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.4190198771 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 13862580000 ps |
| CPU time | 53.26 seconds |
| Started | Apr 18 01:13:15 PM PDT 24 |
| Finished | Apr 18 01:14:57 PM PDT 24 |
| Peak memory | 145196 kb |
| Host | smart-67fc7f25-059f-4699-a2b3-9cecbd6397f6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4190198771 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.4190198771 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.1434529823 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 4028760000 ps |
| CPU time | 13.19 seconds |
| Started | Apr 18 01:13:23 PM PDT 24 |
| Finished | Apr 18 01:13:48 PM PDT 24 |
| Peak memory | 145044 kb |
| Host | smart-fc64f2e1-94b0-4c07-bf70-c603404a5728 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1434529823 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.1434529823 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.1629805876 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 13340540000 ps |
| CPU time | 43.3 seconds |
| Started | Apr 18 01:13:25 PM PDT 24 |
| Finished | Apr 18 01:14:47 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-57f17a53-1515-429c-ab20-5695bb3be050 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1629805876 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.1629805876 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.2307894316 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 8447500000 ps |
| CPU time | 26.28 seconds |
| Started | Apr 18 01:13:21 PM PDT 24 |
| Finished | Apr 18 01:14:11 PM PDT 24 |
| Peak memory | 145196 kb |
| Host | smart-57475c33-6109-48eb-86dc-bfe9bdf079d5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2307894316 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.2307894316 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.636437143 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 8814540000 ps |
| CPU time | 28.2 seconds |
| Started | Apr 18 01:13:21 PM PDT 24 |
| Finished | Apr 18 01:14:14 PM PDT 24 |
| Peak memory | 145216 kb |
| Host | smart-28571826-ef95-4af5-8053-b0429fa33ad9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=636437143 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.636437143 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.954383416 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 7820060000 ps |
| CPU time | 25.47 seconds |
| Started | Apr 18 01:13:21 PM PDT 24 |
| Finished | Apr 18 01:14:08 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-ada5c5be-ecb8-409a-ba43-639cbe37331a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=954383416 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.954383416 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.2190924343 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 5845360000 ps |
| CPU time | 16.79 seconds |
| Started | Apr 18 01:13:20 PM PDT 24 |
| Finished | Apr 18 01:13:51 PM PDT 24 |
| Peak memory | 145152 kb |
| Host | smart-cc1e487a-9eb4-455e-a89b-b1628ba4718f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2190924343 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.2190924343 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.2080538187 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 4395800000 ps |
| CPU time | 13.8 seconds |
| Started | Apr 18 01:13:22 PM PDT 24 |
| Finished | Apr 18 01:13:49 PM PDT 24 |
| Peak memory | 145196 kb |
| Host | smart-57f997e2-c1e7-4c51-ac64-b720de4ae9e9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2080538187 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.2080538187 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.300772343 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 7305460000 ps |
| CPU time | 25.02 seconds |
| Started | Apr 18 01:13:23 PM PDT 24 |
| Finished | Apr 18 01:14:11 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-a9b687bd-d3ba-4a47-a2cb-7970944b984f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=300772343 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.300772343 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.3627373843 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 7800840000 ps |
| CPU time | 26.58 seconds |
| Started | Apr 18 01:13:10 PM PDT 24 |
| Finished | Apr 18 01:14:02 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-782d8703-31c5-4acb-9c26-92ae1ca785e6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3627373843 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.3627373843 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.3693250822 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 10629900000 ps |
| CPU time | 40.07 seconds |
| Started | Apr 18 01:13:07 PM PDT 24 |
| Finished | Apr 18 01:14:22 PM PDT 24 |
| Peak memory | 145232 kb |
| Host | smart-188e9a80-cd21-4e90-9b29-9e437c58ba84 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3693250822 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.3693250822 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.1071696196 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 14052300000 ps |
| CPU time | 46.67 seconds |
| Started | Apr 18 01:13:09 PM PDT 24 |
| Finished | Apr 18 01:14:38 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-9a265369-7d38-44ae-93d9-f58b125fa9c1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1071696196 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.1071696196 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.4242240870 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 6100180000 ps |
| CPU time | 23.09 seconds |
| Started | Apr 18 01:13:05 PM PDT 24 |
| Finished | Apr 18 01:13:50 PM PDT 24 |
| Peak memory | 145080 kb |
| Host | smart-3b063ec5-eb4f-41f3-b5bc-533db2566157 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4242240870 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.4242240870 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.208215689 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 4995340000 ps |
| CPU time | 15.68 seconds |
| Started | Apr 18 01:13:07 PM PDT 24 |
| Finished | Apr 18 01:13:37 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-eef4dc67-8c8c-425a-8c72-0d8c69c7dd86 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=208215689 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.208215689 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |