| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/0.prim_present_test.2704078006 | ||
| Name |
|---|
| /workspace/coverage/default/1.prim_present_test.2026243595 |
| /workspace/coverage/default/10.prim_present_test.3497817169 |
| /workspace/coverage/default/11.prim_present_test.3397188100 |
| /workspace/coverage/default/12.prim_present_test.1143968285 |
| /workspace/coverage/default/13.prim_present_test.3896952652 |
| /workspace/coverage/default/14.prim_present_test.417196883 |
| /workspace/coverage/default/15.prim_present_test.3255656692 |
| /workspace/coverage/default/16.prim_present_test.54190386 |
| /workspace/coverage/default/17.prim_present_test.3820269333 |
| /workspace/coverage/default/18.prim_present_test.579551098 |
| /workspace/coverage/default/19.prim_present_test.359863401 |
| /workspace/coverage/default/2.prim_present_test.1209736012 |
| /workspace/coverage/default/20.prim_present_test.3937288225 |
| /workspace/coverage/default/21.prim_present_test.462075927 |
| /workspace/coverage/default/22.prim_present_test.3607767825 |
| /workspace/coverage/default/23.prim_present_test.3489030182 |
| /workspace/coverage/default/24.prim_present_test.2003447443 |
| /workspace/coverage/default/25.prim_present_test.2279611225 |
| /workspace/coverage/default/26.prim_present_test.796544056 |
| /workspace/coverage/default/27.prim_present_test.2555160245 |
| /workspace/coverage/default/28.prim_present_test.536379727 |
| /workspace/coverage/default/29.prim_present_test.1892529037 |
| /workspace/coverage/default/3.prim_present_test.3532813754 |
| /workspace/coverage/default/30.prim_present_test.597275819 |
| /workspace/coverage/default/31.prim_present_test.2131523430 |
| /workspace/coverage/default/32.prim_present_test.3484861667 |
| /workspace/coverage/default/33.prim_present_test.2629752282 |
| /workspace/coverage/default/34.prim_present_test.3493339699 |
| /workspace/coverage/default/35.prim_present_test.1529832401 |
| /workspace/coverage/default/36.prim_present_test.964567353 |
| /workspace/coverage/default/37.prim_present_test.912839394 |
| /workspace/coverage/default/38.prim_present_test.2331569400 |
| /workspace/coverage/default/39.prim_present_test.2645966522 |
| /workspace/coverage/default/4.prim_present_test.515301941 |
| /workspace/coverage/default/40.prim_present_test.3270580911 |
| /workspace/coverage/default/41.prim_present_test.3837817129 |
| /workspace/coverage/default/42.prim_present_test.145055298 |
| /workspace/coverage/default/43.prim_present_test.232476509 |
| /workspace/coverage/default/44.prim_present_test.3877434072 |
| /workspace/coverage/default/45.prim_present_test.2666787798 |
| /workspace/coverage/default/46.prim_present_test.4172092831 |
| /workspace/coverage/default/47.prim_present_test.547493283 |
| /workspace/coverage/default/48.prim_present_test.1285809021 |
| /workspace/coverage/default/49.prim_present_test.3653891977 |
| /workspace/coverage/default/5.prim_present_test.3996002301 |
| /workspace/coverage/default/6.prim_present_test.3917914623 |
| /workspace/coverage/default/7.prim_present_test.4201733715 |
| /workspace/coverage/default/8.prim_present_test.3999573373 |
| /workspace/coverage/default/9.prim_present_test.1900704521 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/32.prim_present_test.3484861667 | Apr 21 12:40:13 PM PDT 24 | Apr 21 12:41:41 PM PDT 24 | 14016960000 ps | ||
| T2 | /workspace/coverage/default/30.prim_present_test.597275819 | Apr 21 12:40:15 PM PDT 24 | Apr 21 12:41:23 PM PDT 24 | 9347740000 ps | ||
| T3 | /workspace/coverage/default/41.prim_present_test.3837817129 | Apr 21 12:40:01 PM PDT 24 | Apr 21 12:40:48 PM PDT 24 | 5893720000 ps | ||
| T4 | /workspace/coverage/default/13.prim_present_test.3896952652 | Apr 21 12:40:04 PM PDT 24 | Apr 21 12:40:56 PM PDT 24 | 7593140000 ps | ||
| T5 | /workspace/coverage/default/25.prim_present_test.2279611225 | Apr 21 12:39:57 PM PDT 24 | Apr 21 12:41:03 PM PDT 24 | 10788000000 ps | ||
| T6 | /workspace/coverage/default/0.prim_present_test.2704078006 | Apr 21 12:39:43 PM PDT 24 | Apr 21 12:40:36 PM PDT 24 | 7295540000 ps | ||
| T7 | /workspace/coverage/default/2.prim_present_test.1209736012 | Apr 21 12:39:59 PM PDT 24 | Apr 21 12:41:24 PM PDT 24 | 13941940000 ps | ||
| T8 | /workspace/coverage/default/6.prim_present_test.3917914623 | Apr 21 12:39:48 PM PDT 24 | Apr 21 12:40:31 PM PDT 24 | 5695940000 ps | ||
| T9 | /workspace/coverage/default/28.prim_present_test.536379727 | Apr 21 12:39:39 PM PDT 24 | Apr 21 12:40:43 PM PDT 24 | 9295660000 ps | ||
| T10 | /workspace/coverage/default/9.prim_present_test.1900704521 | Apr 21 12:39:53 PM PDT 24 | Apr 21 12:40:29 PM PDT 24 | 5488860000 ps | ||
| T11 | /workspace/coverage/default/24.prim_present_test.2003447443 | Apr 21 12:39:52 PM PDT 24 | Apr 21 12:40:46 PM PDT 24 | 8900720000 ps | ||
| T12 | /workspace/coverage/default/27.prim_present_test.2555160245 | Apr 21 12:39:48 PM PDT 24 | Apr 21 12:41:07 PM PDT 24 | 10724760000 ps | ||
| T13 | /workspace/coverage/default/34.prim_present_test.3493339699 | Apr 21 12:40:11 PM PDT 24 | Apr 21 12:40:43 PM PDT 24 | 4453460000 ps | ||
| T14 | /workspace/coverage/default/7.prim_present_test.4201733715 | Apr 21 12:39:58 PM PDT 24 | Apr 21 12:40:18 PM PDT 24 | 3527180000 ps | ||
| T15 | /workspace/coverage/default/12.prim_present_test.1143968285 | Apr 21 12:39:58 PM PDT 24 | Apr 21 12:40:34 PM PDT 24 | 5637040000 ps | ||
| T16 | /workspace/coverage/default/39.prim_present_test.2645966522 | Apr 21 12:39:35 PM PDT 24 | Apr 21 12:39:54 PM PDT 24 | 3147740000 ps | ||
| T17 | /workspace/coverage/default/37.prim_present_test.912839394 | Apr 21 12:40:02 PM PDT 24 | Apr 21 12:41:10 PM PDT 24 | 11492320000 ps | ||
| T18 | /workspace/coverage/default/45.prim_present_test.2666787798 | Apr 21 12:40:10 PM PDT 24 | Apr 21 12:40:35 PM PDT 24 | 3771460000 ps | ||
| T19 | /workspace/coverage/default/10.prim_present_test.3497817169 | Apr 21 12:39:53 PM PDT 24 | Apr 21 12:40:45 PM PDT 24 | 7536720000 ps | ||
| T20 | /workspace/coverage/default/4.prim_present_test.515301941 | Apr 21 12:39:46 PM PDT 24 | Apr 21 12:40:18 PM PDT 24 | 4401380000 ps | ||
| T21 | /workspace/coverage/default/31.prim_present_test.2131523430 | Apr 21 12:39:43 PM PDT 24 | Apr 21 12:40:49 PM PDT 24 | 12033580000 ps | ||
| T22 | /workspace/coverage/default/11.prim_present_test.3397188100 | Apr 21 12:39:48 PM PDT 24 | Apr 21 12:40:20 PM PDT 24 | 3630720000 ps | ||
| T23 | /workspace/coverage/default/8.prim_present_test.3999573373 | Apr 21 12:39:53 PM PDT 24 | Apr 21 12:40:46 PM PDT 24 | 7501380000 ps | ||
| T24 | /workspace/coverage/default/46.prim_present_test.4172092831 | Apr 21 12:39:51 PM PDT 24 | Apr 21 12:40:27 PM PDT 24 | 4411920000 ps | ||
| T25 | /workspace/coverage/default/26.prim_present_test.796544056 | Apr 21 12:40:00 PM PDT 24 | Apr 21 12:41:20 PM PDT 24 | 13297760000 ps | ||
| T26 | /workspace/coverage/default/1.prim_present_test.2026243595 | Apr 21 12:39:47 PM PDT 24 | Apr 21 12:40:32 PM PDT 24 | 7319100000 ps | ||
| T27 | /workspace/coverage/default/21.prim_present_test.462075927 | Apr 21 12:39:58 PM PDT 24 | Apr 21 12:40:44 PM PDT 24 | 7572680000 ps | ||
| T28 | /workspace/coverage/default/20.prim_present_test.3937288225 | Apr 21 12:39:49 PM PDT 24 | Apr 21 12:41:23 PM PDT 24 | 14165140000 ps | ||
| T29 | /workspace/coverage/default/42.prim_present_test.145055298 | Apr 21 12:39:56 PM PDT 24 | Apr 21 12:41:21 PM PDT 24 | 14287900000 ps | ||
| T30 | /workspace/coverage/default/3.prim_present_test.3532813754 | Apr 21 12:39:59 PM PDT 24 | Apr 21 12:41:32 PM PDT 24 | 14317040000 ps | ||
| T31 | /workspace/coverage/default/19.prim_present_test.359863401 | Apr 21 12:39:36 PM PDT 24 | Apr 21 12:40:01 PM PDT 24 | 3733640000 ps | ||
| T32 | /workspace/coverage/default/29.prim_present_test.1892529037 | Apr 21 12:39:50 PM PDT 24 | Apr 21 12:40:35 PM PDT 24 | 6720800000 ps | ||
| T33 | /workspace/coverage/default/48.prim_present_test.1285809021 | Apr 21 12:39:54 PM PDT 24 | Apr 21 12:40:56 PM PDT 24 | 9954720000 ps | ||
| T34 | /workspace/coverage/default/49.prim_present_test.3653891977 | Apr 21 12:39:58 PM PDT 24 | Apr 21 12:40:41 PM PDT 24 | 6792100000 ps | ||
| T35 | /workspace/coverage/default/44.prim_present_test.3877434072 | Apr 21 12:40:03 PM PDT 24 | Apr 21 12:41:27 PM PDT 24 | 10925020000 ps | ||
| T36 | /workspace/coverage/default/22.prim_present_test.3607767825 | Apr 21 12:40:07 PM PDT 24 | Apr 21 12:40:53 PM PDT 24 | 7098380000 ps | ||
| T37 | /workspace/coverage/default/36.prim_present_test.964567353 | Apr 21 12:39:45 PM PDT 24 | Apr 21 12:41:16 PM PDT 24 | 11173020000 ps | ||
| T38 | /workspace/coverage/default/16.prim_present_test.54190386 | Apr 21 12:39:39 PM PDT 24 | Apr 21 12:40:24 PM PDT 24 | 6172720000 ps | ||
| T39 | /workspace/coverage/default/17.prim_present_test.3820269333 | Apr 21 12:39:45 PM PDT 24 | Apr 21 12:40:30 PM PDT 24 | 5826760000 ps | ||
| T40 | /workspace/coverage/default/18.prim_present_test.579551098 | Apr 21 12:39:42 PM PDT 24 | Apr 21 12:40:49 PM PDT 24 | 9942940000 ps | ||
| T41 | /workspace/coverage/default/47.prim_present_test.547493283 | Apr 21 12:39:49 PM PDT 24 | Apr 21 12:40:56 PM PDT 24 | 11063900000 ps | ||
| T42 | /workspace/coverage/default/40.prim_present_test.3270580911 | Apr 21 12:39:48 PM PDT 24 | Apr 21 12:40:45 PM PDT 24 | 9051380000 ps | ||
| T43 | /workspace/coverage/default/5.prim_present_test.3996002301 | Apr 21 12:39:43 PM PDT 24 | Apr 21 12:40:46 PM PDT 24 | 8755020000 ps | ||
| T44 | /workspace/coverage/default/35.prim_present_test.1529832401 | Apr 21 12:40:03 PM PDT 24 | Apr 21 12:40:37 PM PDT 24 | 4441060000 ps | ||
| T45 | /workspace/coverage/default/14.prim_present_test.417196883 | Apr 21 12:39:46 PM PDT 24 | Apr 21 12:41:15 PM PDT 24 | 14062220000 ps | ||
| T46 | /workspace/coverage/default/43.prim_present_test.232476509 | Apr 21 12:40:05 PM PDT 24 | Apr 21 12:41:00 PM PDT 24 | 8997440000 ps | ||
| T47 | /workspace/coverage/default/23.prim_present_test.3489030182 | Apr 21 12:39:51 PM PDT 24 | Apr 21 12:40:22 PM PDT 24 | 3875620000 ps | ||
| T48 | /workspace/coverage/default/15.prim_present_test.3255656692 | Apr 21 12:39:48 PM PDT 24 | Apr 21 12:40:44 PM PDT 24 | 8603120000 ps | ||
| T49 | /workspace/coverage/default/38.prim_present_test.2331569400 | Apr 21 12:39:53 PM PDT 24 | Apr 21 12:41:23 PM PDT 24 | 14414380000 ps | ||
| T50 | /workspace/coverage/default/33.prim_present_test.2629752282 | Apr 21 12:39:42 PM PDT 24 | Apr 21 12:41:06 PM PDT 24 | 13437880000 ps |
| Test location | /workspace/coverage/default/0.prim_present_test.2704078006 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 7295540000 ps |
| CPU time | 27.36 seconds |
| Started | Apr 21 12:39:43 PM PDT 24 |
| Finished | Apr 21 12:40:36 PM PDT 24 |
| Peak memory | 145164 kb |
| Host | smart-3247d75a-0653-4d0e-8245-9a33862f0c31 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2704078006 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.2704078006 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/1.prim_present_test.2026243595 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 7319100000 ps |
| CPU time | 23.36 seconds |
| Started | Apr 21 12:39:47 PM PDT 24 |
| Finished | Apr 21 12:40:32 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-6929b5ed-23c9-4eff-a01b-b0f8dce5139c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2026243595 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.2026243595 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/10.prim_present_test.3497817169 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 7536720000 ps |
| CPU time | 26.91 seconds |
| Started | Apr 21 12:39:53 PM PDT 24 |
| Finished | Apr 21 12:40:45 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-67fcf06b-34fa-484d-8b3e-0c7c998389dd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3497817169 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.3497817169 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/11.prim_present_test.3397188100 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 3630720000 ps |
| CPU time | 13.31 seconds |
| Started | Apr 21 12:39:48 PM PDT 24 |
| Finished | Apr 21 12:40:20 PM PDT 24 |
| Peak memory | 144988 kb |
| Host | smart-a48fb204-7309-4c9e-b235-e773dfeadd1e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3397188100 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.3397188100 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.1143968285 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 5637040000 ps |
| CPU time | 19.16 seconds |
| Started | Apr 21 12:39:58 PM PDT 24 |
| Finished | Apr 21 12:40:34 PM PDT 24 |
| Peak memory | 145116 kb |
| Host | smart-4c64169f-423a-4e1e-91d8-4cb3eb0c7cb3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1143968285 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.1143968285 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.3896952652 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 7593140000 ps |
| CPU time | 26.94 seconds |
| Started | Apr 21 12:40:04 PM PDT 24 |
| Finished | Apr 21 12:40:56 PM PDT 24 |
| Peak memory | 145140 kb |
| Host | smart-204ac59f-627d-45fe-bf78-69a587d7ab6c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3896952652 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.3896952652 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.417196883 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 14062220000 ps |
| CPU time | 46.68 seconds |
| Started | Apr 21 12:39:46 PM PDT 24 |
| Finished | Apr 21 12:41:15 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-966e92ee-db10-4bfa-b394-7b48772c93f2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=417196883 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.417196883 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.3255656692 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 8603120000 ps |
| CPU time | 29.55 seconds |
| Started | Apr 21 12:39:48 PM PDT 24 |
| Finished | Apr 21 12:40:44 PM PDT 24 |
| Peak memory | 145108 kb |
| Host | smart-5d66ef7c-29ea-456c-a8b8-0e41a42eb7d1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3255656692 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.3255656692 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.54190386 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 6172720000 ps |
| CPU time | 22.55 seconds |
| Started | Apr 21 12:39:39 PM PDT 24 |
| Finished | Apr 21 12:40:24 PM PDT 24 |
| Peak memory | 145112 kb |
| Host | smart-0bcc9092-f71b-49ed-b980-57c66e8f7067 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=54190386 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.54190386 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.3820269333 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 5826760000 ps |
| CPU time | 23.6 seconds |
| Started | Apr 21 12:39:45 PM PDT 24 |
| Finished | Apr 21 12:40:30 PM PDT 24 |
| Peak memory | 145104 kb |
| Host | smart-ea47ae4c-8885-4b9f-811a-a341a9371359 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3820269333 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.3820269333 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.579551098 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 9942940000 ps |
| CPU time | 34.7 seconds |
| Started | Apr 21 12:39:42 PM PDT 24 |
| Finished | Apr 21 12:40:49 PM PDT 24 |
| Peak memory | 145160 kb |
| Host | smart-19da454c-d6d9-421a-b09a-ac9f4219e823 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=579551098 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.579551098 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.359863401 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 3733640000 ps |
| CPU time | 13 seconds |
| Started | Apr 21 12:39:36 PM PDT 24 |
| Finished | Apr 21 12:40:01 PM PDT 24 |
| Peak memory | 144976 kb |
| Host | smart-311d9cbc-6d9b-4287-af89-d9858426697d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=359863401 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.359863401 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.1209736012 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 13941940000 ps |
| CPU time | 44.94 seconds |
| Started | Apr 21 12:39:59 PM PDT 24 |
| Finished | Apr 21 12:41:24 PM PDT 24 |
| Peak memory | 145096 kb |
| Host | smart-19f4c933-84e9-4823-b418-5ff3858cc1eb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1209736012 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.1209736012 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.3937288225 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 14165140000 ps |
| CPU time | 49.33 seconds |
| Started | Apr 21 12:39:49 PM PDT 24 |
| Finished | Apr 21 12:41:23 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-509d6d6f-4692-4c6f-b4e8-6e0a99f9f6e7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3937288225 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.3937288225 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.462075927 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 7572680000 ps |
| CPU time | 24.73 seconds |
| Started | Apr 21 12:39:58 PM PDT 24 |
| Finished | Apr 21 12:40:44 PM PDT 24 |
| Peak memory | 145048 kb |
| Host | smart-6ba7a765-44e5-4dc6-9d52-0648723debb1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=462075927 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.462075927 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.3607767825 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 7098380000 ps |
| CPU time | 24.71 seconds |
| Started | Apr 21 12:40:07 PM PDT 24 |
| Finished | Apr 21 12:40:53 PM PDT 24 |
| Peak memory | 145088 kb |
| Host | smart-2b0706a8-37ca-4456-8633-0e22654b7e97 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3607767825 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.3607767825 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.3489030182 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 3875620000 ps |
| CPU time | 14.04 seconds |
| Started | Apr 21 12:39:51 PM PDT 24 |
| Finished | Apr 21 12:40:22 PM PDT 24 |
| Peak memory | 144996 kb |
| Host | smart-5f1cda68-d07f-4586-987e-71a492c15d3a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3489030182 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.3489030182 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.2003447443 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 8900720000 ps |
| CPU time | 28.94 seconds |
| Started | Apr 21 12:39:52 PM PDT 24 |
| Finished | Apr 21 12:40:46 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-4b5cd871-ccf7-48f6-8680-8c0829adc4de |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2003447443 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.2003447443 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.2279611225 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 10788000000 ps |
| CPU time | 35.47 seconds |
| Started | Apr 21 12:39:57 PM PDT 24 |
| Finished | Apr 21 12:41:03 PM PDT 24 |
| Peak memory | 145196 kb |
| Host | smart-de01d0c5-7094-4b87-9c37-eb378a7808a1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2279611225 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.2279611225 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.796544056 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 13297760000 ps |
| CPU time | 42.98 seconds |
| Started | Apr 21 12:40:00 PM PDT 24 |
| Finished | Apr 21 12:41:20 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-f1fdc8f6-360d-467a-b241-46b4d6e8157b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=796544056 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.796544056 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.2555160245 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 10724760000 ps |
| CPU time | 40.82 seconds |
| Started | Apr 21 12:39:48 PM PDT 24 |
| Finished | Apr 21 12:41:07 PM PDT 24 |
| Peak memory | 145088 kb |
| Host | smart-1c3b2cfd-1cf0-42fe-b78f-6cc17b5e5837 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2555160245 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.2555160245 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.536379727 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 9295660000 ps |
| CPU time | 33.15 seconds |
| Started | Apr 21 12:39:39 PM PDT 24 |
| Finished | Apr 21 12:40:43 PM PDT 24 |
| Peak memory | 145116 kb |
| Host | smart-e1c1c318-31f9-432f-a876-f1c4b6183ff0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=536379727 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.536379727 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.1892529037 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 6720800000 ps |
| CPU time | 23.58 seconds |
| Started | Apr 21 12:39:50 PM PDT 24 |
| Finished | Apr 21 12:40:35 PM PDT 24 |
| Peak memory | 145108 kb |
| Host | smart-0afa4817-0f36-4ce8-918b-5db935140e4f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1892529037 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.1892529037 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.3532813754 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 14317040000 ps |
| CPU time | 49.44 seconds |
| Started | Apr 21 12:39:59 PM PDT 24 |
| Finished | Apr 21 12:41:32 PM PDT 24 |
| Peak memory | 145064 kb |
| Host | smart-9fb5603f-40ac-42dc-baae-a65f51c24bf6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3532813754 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.3532813754 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.597275819 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 9347740000 ps |
| CPU time | 34.19 seconds |
| Started | Apr 21 12:40:15 PM PDT 24 |
| Finished | Apr 21 12:41:23 PM PDT 24 |
| Peak memory | 145124 kb |
| Host | smart-04fc2d7c-2012-47ad-ad93-d52f3c4ec10b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=597275819 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.597275819 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.2131523430 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 12033580000 ps |
| CPU time | 35.49 seconds |
| Started | Apr 21 12:39:43 PM PDT 24 |
| Finished | Apr 21 12:40:49 PM PDT 24 |
| Peak memory | 145132 kb |
| Host | smart-5ba840a0-0353-4f21-9298-9714c6f72297 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2131523430 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.2131523430 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.3484861667 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 14016960000 ps |
| CPU time | 45.71 seconds |
| Started | Apr 21 12:40:13 PM PDT 24 |
| Finished | Apr 21 12:41:41 PM PDT 24 |
| Peak memory | 145120 kb |
| Host | smart-66814a97-845f-4843-92b5-dabc75d91ad1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3484861667 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.3484861667 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.2629752282 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 13437880000 ps |
| CPU time | 44.68 seconds |
| Started | Apr 21 12:39:42 PM PDT 24 |
| Finished | Apr 21 12:41:06 PM PDT 24 |
| Peak memory | 145112 kb |
| Host | smart-025dd512-3fc9-4e55-99ba-56b14d554333 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2629752282 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.2629752282 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.3493339699 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 4453460000 ps |
| CPU time | 16.77 seconds |
| Started | Apr 21 12:40:11 PM PDT 24 |
| Finished | Apr 21 12:40:43 PM PDT 24 |
| Peak memory | 145152 kb |
| Host | smart-a70527dd-fb0f-4814-8a96-3267dc23d5ca |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3493339699 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.3493339699 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.1529832401 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 4441060000 ps |
| CPU time | 17.03 seconds |
| Started | Apr 21 12:40:03 PM PDT 24 |
| Finished | Apr 21 12:40:37 PM PDT 24 |
| Peak memory | 145104 kb |
| Host | smart-5f617b3c-862a-43ce-a968-6f280b59df38 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1529832401 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.1529832401 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.964567353 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 11173020000 ps |
| CPU time | 46.18 seconds |
| Started | Apr 21 12:39:45 PM PDT 24 |
| Finished | Apr 21 12:41:16 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-c2404b59-11ec-4512-9b05-9de0fda8e318 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=964567353 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.964567353 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.912839394 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 11492320000 ps |
| CPU time | 36.53 seconds |
| Started | Apr 21 12:40:02 PM PDT 24 |
| Finished | Apr 21 12:41:10 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-72f4ed07-3ce9-44cc-ba94-748be010d689 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=912839394 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.912839394 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.2331569400 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 14414380000 ps |
| CPU time | 46.83 seconds |
| Started | Apr 21 12:39:53 PM PDT 24 |
| Finished | Apr 21 12:41:23 PM PDT 24 |
| Peak memory | 145120 kb |
| Host | smart-fd1ccc26-51c4-4e3a-86f0-923620f27382 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2331569400 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.2331569400 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.2645966522 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 3147740000 ps |
| CPU time | 9.72 seconds |
| Started | Apr 21 12:39:35 PM PDT 24 |
| Finished | Apr 21 12:39:54 PM PDT 24 |
| Peak memory | 144968 kb |
| Host | smart-6685a506-b879-44aa-8088-2d1fd16460ce |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2645966522 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.2645966522 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.515301941 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 4401380000 ps |
| CPU time | 16.25 seconds |
| Started | Apr 21 12:39:46 PM PDT 24 |
| Finished | Apr 21 12:40:18 PM PDT 24 |
| Peak memory | 145156 kb |
| Host | smart-ce5b4ecb-a637-456e-83ae-bc6808cfce2e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=515301941 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.515301941 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.3270580911 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 9051380000 ps |
| CPU time | 29.59 seconds |
| Started | Apr 21 12:39:48 PM PDT 24 |
| Finished | Apr 21 12:40:45 PM PDT 24 |
| Peak memory | 145148 kb |
| Host | smart-3dbf796e-f5ae-4ae0-99ee-63ac6a697504 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3270580911 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.3270580911 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.3837817129 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 5893720000 ps |
| CPU time | 24.12 seconds |
| Started | Apr 21 12:40:01 PM PDT 24 |
| Finished | Apr 21 12:40:48 PM PDT 24 |
| Peak memory | 145128 kb |
| Host | smart-d787b39a-cef8-4cbe-a234-0ab5c03680b3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3837817129 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.3837817129 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.145055298 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 14287900000 ps |
| CPU time | 45.39 seconds |
| Started | Apr 21 12:39:56 PM PDT 24 |
| Finished | Apr 21 12:41:21 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-0508da6e-e266-4c08-b48d-cd3d6de046df |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=145055298 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.145055298 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.232476509 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 8997440000 ps |
| CPU time | 29.21 seconds |
| Started | Apr 21 12:40:05 PM PDT 24 |
| Finished | Apr 21 12:41:00 PM PDT 24 |
| Peak memory | 145120 kb |
| Host | smart-6927dd34-1915-4f83-b4f3-aebd324b7695 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=232476509 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.232476509 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.3877434072 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 10925020000 ps |
| CPU time | 43.53 seconds |
| Started | Apr 21 12:40:03 PM PDT 24 |
| Finished | Apr 21 12:41:27 PM PDT 24 |
| Peak memory | 145124 kb |
| Host | smart-718be873-6a55-459a-996a-3da6224858fa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3877434072 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.3877434072 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.2666787798 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 3771460000 ps |
| CPU time | 13.29 seconds |
| Started | Apr 21 12:40:10 PM PDT 24 |
| Finished | Apr 21 12:40:35 PM PDT 24 |
| Peak memory | 144964 kb |
| Host | smart-b583aa51-07cf-4974-947b-431bf8bdad8c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2666787798 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.2666787798 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.4172092831 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 4411920000 ps |
| CPU time | 16.85 seconds |
| Started | Apr 21 12:39:51 PM PDT 24 |
| Finished | Apr 21 12:40:27 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-d039a4df-18f4-4e15-a2eb-9fb9859a6310 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4172092831 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.4172092831 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.547493283 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 11063900000 ps |
| CPU time | 35.48 seconds |
| Started | Apr 21 12:39:49 PM PDT 24 |
| Finished | Apr 21 12:40:56 PM PDT 24 |
| Peak memory | 145144 kb |
| Host | smart-0b74d9c2-5f8c-4f80-aeac-3cfdd4561690 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=547493283 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.547493283 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.1285809021 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 9954720000 ps |
| CPU time | 32.23 seconds |
| Started | Apr 21 12:39:54 PM PDT 24 |
| Finished | Apr 21 12:40:56 PM PDT 24 |
| Peak memory | 145104 kb |
| Host | smart-aef6e3b5-50e7-442d-80f9-d8c33418317b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1285809021 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.1285809021 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.3653891977 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 6792100000 ps |
| CPU time | 22.43 seconds |
| Started | Apr 21 12:39:58 PM PDT 24 |
| Finished | Apr 21 12:40:41 PM PDT 24 |
| Peak memory | 145120 kb |
| Host | smart-deda2b5a-d059-4e13-89e1-a635b8edc870 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3653891977 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.3653891977 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.3996002301 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 8755020000 ps |
| CPU time | 32.6 seconds |
| Started | Apr 21 12:39:43 PM PDT 24 |
| Finished | Apr 21 12:40:46 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-42c6ce87-8f1a-4157-b771-60d8789561e2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3996002301 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.3996002301 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.3917914623 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 5695940000 ps |
| CPU time | 21.99 seconds |
| Started | Apr 21 12:39:48 PM PDT 24 |
| Finished | Apr 21 12:40:31 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-7832323f-77c1-493b-9860-aa0635b192c2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3917914623 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.3917914623 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.4201733715 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 3527180000 ps |
| CPU time | 10.51 seconds |
| Started | Apr 21 12:39:58 PM PDT 24 |
| Finished | Apr 21 12:40:18 PM PDT 24 |
| Peak memory | 144972 kb |
| Host | smart-e1b6a943-a541-44f1-8e25-005d19c15ea6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4201733715 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.4201733715 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.3999573373 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 7501380000 ps |
| CPU time | 27.03 seconds |
| Started | Apr 21 12:39:53 PM PDT 24 |
| Finished | Apr 21 12:40:46 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-60d7cdae-6a2e-4f0a-a89e-0889f168b043 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3999573373 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.3999573373 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.1900704521 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 5488860000 ps |
| CPU time | 19.61 seconds |
| Started | Apr 21 12:39:53 PM PDT 24 |
| Finished | Apr 21 12:40:29 PM PDT 24 |
| Peak memory | 145096 kb |
| Host | smart-d35d3a0c-29d1-4179-a11d-7fae0fc47369 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1900704521 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.1900704521 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |