| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/1.prim_present_test.1125431260 | ||
| Name |
|---|
| /workspace/coverage/default/0.prim_present_test.4046324939 |
| /workspace/coverage/default/10.prim_present_test.2596269251 |
| /workspace/coverage/default/11.prim_present_test.2421451634 |
| /workspace/coverage/default/12.prim_present_test.3517764121 |
| /workspace/coverage/default/13.prim_present_test.1014731283 |
| /workspace/coverage/default/14.prim_present_test.4121340932 |
| /workspace/coverage/default/15.prim_present_test.1470676660 |
| /workspace/coverage/default/16.prim_present_test.3666973828 |
| /workspace/coverage/default/17.prim_present_test.2378356807 |
| /workspace/coverage/default/18.prim_present_test.1031528833 |
| /workspace/coverage/default/19.prim_present_test.3560260469 |
| /workspace/coverage/default/2.prim_present_test.2285500192 |
| /workspace/coverage/default/20.prim_present_test.3427128742 |
| /workspace/coverage/default/21.prim_present_test.4023852227 |
| /workspace/coverage/default/22.prim_present_test.2246424760 |
| /workspace/coverage/default/23.prim_present_test.514657231 |
| /workspace/coverage/default/24.prim_present_test.3664578973 |
| /workspace/coverage/default/25.prim_present_test.3366462613 |
| /workspace/coverage/default/26.prim_present_test.900158849 |
| /workspace/coverage/default/27.prim_present_test.869089475 |
| /workspace/coverage/default/28.prim_present_test.688307915 |
| /workspace/coverage/default/29.prim_present_test.2134744072 |
| /workspace/coverage/default/3.prim_present_test.3906619352 |
| /workspace/coverage/default/30.prim_present_test.2400205186 |
| /workspace/coverage/default/31.prim_present_test.3682644081 |
| /workspace/coverage/default/32.prim_present_test.1502910436 |
| /workspace/coverage/default/33.prim_present_test.1221476934 |
| /workspace/coverage/default/34.prim_present_test.534125736 |
| /workspace/coverage/default/35.prim_present_test.3083079318 |
| /workspace/coverage/default/36.prim_present_test.4044932163 |
| /workspace/coverage/default/37.prim_present_test.3259704585 |
| /workspace/coverage/default/38.prim_present_test.2128707590 |
| /workspace/coverage/default/39.prim_present_test.3232831495 |
| /workspace/coverage/default/4.prim_present_test.3288755669 |
| /workspace/coverage/default/40.prim_present_test.3059128369 |
| /workspace/coverage/default/41.prim_present_test.943616949 |
| /workspace/coverage/default/42.prim_present_test.3200618210 |
| /workspace/coverage/default/43.prim_present_test.895045259 |
| /workspace/coverage/default/44.prim_present_test.2628369030 |
| /workspace/coverage/default/45.prim_present_test.1491181921 |
| /workspace/coverage/default/46.prim_present_test.3130423426 |
| /workspace/coverage/default/47.prim_present_test.2549156977 |
| /workspace/coverage/default/48.prim_present_test.3936908715 |
| /workspace/coverage/default/49.prim_present_test.3225039697 |
| /workspace/coverage/default/5.prim_present_test.4275830311 |
| /workspace/coverage/default/6.prim_present_test.420495557 |
| /workspace/coverage/default/7.prim_present_test.2812221397 |
| /workspace/coverage/default/8.prim_present_test.4253450888 |
| /workspace/coverage/default/9.prim_present_test.1344342220 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/38.prim_present_test.2128707590 | Apr 23 01:29:49 PM PDT 24 | Apr 23 01:30:30 PM PDT 24 | 7441240000 ps | ||
| T2 | /workspace/coverage/default/33.prim_present_test.1221476934 | Apr 23 01:29:58 PM PDT 24 | Apr 23 01:31:00 PM PDT 24 | 9056340000 ps | ||
| T3 | /workspace/coverage/default/11.prim_present_test.2421451634 | Apr 23 01:29:42 PM PDT 24 | Apr 23 01:30:33 PM PDT 24 | 8440060000 ps | ||
| T4 | /workspace/coverage/default/17.prim_present_test.2378356807 | Apr 23 01:29:46 PM PDT 24 | Apr 23 01:31:49 PM PDT 24 | 14594180000 ps | ||
| T5 | /workspace/coverage/default/7.prim_present_test.2812221397 | Apr 23 01:29:44 PM PDT 24 | Apr 23 01:31:17 PM PDT 24 | 11825260000 ps | ||
| T6 | /workspace/coverage/default/1.prim_present_test.1125431260 | Apr 23 01:29:45 PM PDT 24 | Apr 23 01:30:46 PM PDT 24 | 7788440000 ps | ||
| T7 | /workspace/coverage/default/43.prim_present_test.895045259 | Apr 23 01:29:52 PM PDT 24 | Apr 23 01:31:06 PM PDT 24 | 10582160000 ps | ||
| T8 | /workspace/coverage/default/36.prim_present_test.4044932163 | Apr 23 01:29:49 PM PDT 24 | Apr 23 01:31:23 PM PDT 24 | 12839580000 ps | ||
| T9 | /workspace/coverage/default/13.prim_present_test.1014731283 | Apr 23 01:29:52 PM PDT 24 | Apr 23 01:31:30 PM PDT 24 | 12838960000 ps | ||
| T10 | /workspace/coverage/default/8.prim_present_test.4253450888 | Apr 23 01:29:42 PM PDT 24 | Apr 23 01:30:46 PM PDT 24 | 8612420000 ps | ||
| T11 | /workspace/coverage/default/39.prim_present_test.3232831495 | Apr 23 01:29:58 PM PDT 24 | Apr 23 01:31:16 PM PDT 24 | 11235020000 ps | ||
| T12 | /workspace/coverage/default/30.prim_present_test.2400205186 | Apr 23 01:29:58 PM PDT 24 | Apr 23 01:31:02 PM PDT 24 | 8940400000 ps | ||
| T13 | /workspace/coverage/default/2.prim_present_test.2285500192 | Apr 23 01:29:45 PM PDT 24 | Apr 23 01:31:03 PM PDT 24 | 10345320000 ps | ||
| T14 | /workspace/coverage/default/9.prim_present_test.1344342220 | Apr 23 01:29:47 PM PDT 24 | Apr 23 01:31:17 PM PDT 24 | 12719920000 ps | ||
| T15 | /workspace/coverage/default/23.prim_present_test.514657231 | Apr 23 01:29:45 PM PDT 24 | Apr 23 01:30:56 PM PDT 24 | 9198320000 ps | ||
| T16 | /workspace/coverage/default/0.prim_present_test.4046324939 | Apr 23 01:29:43 PM PDT 24 | Apr 23 01:31:21 PM PDT 24 | 12525240000 ps | ||
| T17 | /workspace/coverage/default/42.prim_present_test.3200618210 | Apr 23 01:29:58 PM PDT 24 | Apr 23 01:31:03 PM PDT 24 | 9098500000 ps | ||
| T18 | /workspace/coverage/default/28.prim_present_test.688307915 | Apr 23 01:29:52 PM PDT 24 | Apr 23 01:31:01 PM PDT 24 | 9058200000 ps | ||
| T19 | /workspace/coverage/default/34.prim_present_test.534125736 | Apr 23 01:29:51 PM PDT 24 | Apr 23 01:30:23 PM PDT 24 | 3837800000 ps | ||
| T20 | /workspace/coverage/default/37.prim_present_test.3259704585 | Apr 23 01:29:49 PM PDT 24 | Apr 23 01:30:31 PM PDT 24 | 5607280000 ps | ||
| T21 | /workspace/coverage/default/32.prim_present_test.1502910436 | Apr 23 01:29:50 PM PDT 24 | Apr 23 01:30:29 PM PDT 24 | 4666120000 ps | ||
| T22 | /workspace/coverage/default/47.prim_present_test.2549156977 | Apr 23 01:29:52 PM PDT 24 | Apr 23 01:30:45 PM PDT 24 | 8149280000 ps | ||
| T23 | /workspace/coverage/default/15.prim_present_test.1470676660 | Apr 23 01:29:46 PM PDT 24 | Apr 23 01:30:41 PM PDT 24 | 7080400000 ps | ||
| T24 | /workspace/coverage/default/35.prim_present_test.3083079318 | Apr 23 01:29:58 PM PDT 24 | Apr 23 01:30:26 PM PDT 24 | 3759060000 ps | ||
| T25 | /workspace/coverage/default/26.prim_present_test.900158849 | Apr 23 01:29:53 PM PDT 24 | Apr 23 01:30:57 PM PDT 24 | 12128440000 ps | ||
| T26 | /workspace/coverage/default/41.prim_present_test.943616949 | Apr 23 01:29:49 PM PDT 24 | Apr 23 01:30:16 PM PDT 24 | 3948160000 ps | ||
| T27 | /workspace/coverage/default/29.prim_present_test.2134744072 | Apr 23 01:29:50 PM PDT 24 | Apr 23 01:30:38 PM PDT 24 | 5969980000 ps | ||
| T28 | /workspace/coverage/default/18.prim_present_test.1031528833 | Apr 23 01:29:46 PM PDT 24 | Apr 23 01:30:53 PM PDT 24 | 8790360000 ps | ||
| T29 | /workspace/coverage/default/27.prim_present_test.869089475 | Apr 23 01:29:53 PM PDT 24 | Apr 23 01:31:31 PM PDT 24 | 13028680000 ps | ||
| T30 | /workspace/coverage/default/5.prim_present_test.4275830311 | Apr 23 01:29:47 PM PDT 24 | Apr 23 01:30:21 PM PDT 24 | 4052940000 ps | ||
| T31 | /workspace/coverage/default/48.prim_present_test.3936908715 | Apr 23 01:29:54 PM PDT 24 | Apr 23 01:31:35 PM PDT 24 | 13346120000 ps | ||
| T32 | /workspace/coverage/default/21.prim_present_test.4023852227 | Apr 23 01:29:46 PM PDT 24 | Apr 23 01:30:13 PM PDT 24 | 3407520000 ps | ||
| T33 | /workspace/coverage/default/16.prim_present_test.3666973828 | Apr 23 01:29:47 PM PDT 24 | Apr 23 01:30:29 PM PDT 24 | 5860240000 ps | ||
| T34 | /workspace/coverage/default/49.prim_present_test.3225039697 | Apr 23 01:29:52 PM PDT 24 | Apr 23 01:31:05 PM PDT 24 | 11497280000 ps | ||
| T35 | /workspace/coverage/default/6.prim_present_test.420495557 | Apr 23 01:29:42 PM PDT 24 | Apr 23 01:30:34 PM PDT 24 | 7493940000 ps | ||
| T36 | /workspace/coverage/default/31.prim_present_test.3682644081 | Apr 23 01:29:51 PM PDT 24 | Apr 23 01:31:02 PM PDT 24 | 9296280000 ps | ||
| T37 | /workspace/coverage/default/4.prim_present_test.3288755669 | Apr 23 01:29:48 PM PDT 24 | Apr 23 01:30:35 PM PDT 24 | 5806300000 ps | ||
| T38 | /workspace/coverage/default/45.prim_present_test.1491181921 | Apr 23 01:29:53 PM PDT 24 | Apr 23 01:30:43 PM PDT 24 | 6599900000 ps | ||
| T39 | /workspace/coverage/default/10.prim_present_test.2596269251 | Apr 23 01:29:45 PM PDT 24 | Apr 23 01:30:44 PM PDT 24 | 7808900000 ps | ||
| T40 | /workspace/coverage/default/12.prim_present_test.3517764121 | Apr 23 01:29:45 PM PDT 24 | Apr 23 01:31:13 PM PDT 24 | 11771320000 ps | ||
| T41 | /workspace/coverage/default/25.prim_present_test.3366462613 | Apr 23 01:29:48 PM PDT 24 | Apr 23 01:30:57 PM PDT 24 | 9955960000 ps | ||
| T42 | /workspace/coverage/default/3.prim_present_test.3906619352 | Apr 23 01:29:43 PM PDT 24 | Apr 23 01:31:12 PM PDT 24 | 11132720000 ps | ||
| T43 | /workspace/coverage/default/44.prim_present_test.2628369030 | Apr 23 01:29:51 PM PDT 24 | Apr 23 01:31:13 PM PDT 24 | 11769460000 ps | ||
| T44 | /workspace/coverage/default/40.prim_present_test.3059128369 | Apr 23 01:29:50 PM PDT 24 | Apr 23 01:30:44 PM PDT 24 | 7364360000 ps | ||
| T45 | /workspace/coverage/default/46.prim_present_test.3130423426 | Apr 23 01:29:57 PM PDT 24 | Apr 23 01:30:48 PM PDT 24 | 9054480000 ps | ||
| T46 | /workspace/coverage/default/19.prim_present_test.3560260469 | Apr 23 01:29:46 PM PDT 24 | Apr 23 01:30:55 PM PDT 24 | 9239240000 ps | ||
| T47 | /workspace/coverage/default/22.prim_present_test.2246424760 | Apr 23 01:29:50 PM PDT 24 | Apr 23 01:31:18 PM PDT 24 | 12776960000 ps | ||
| T48 | /workspace/coverage/default/14.prim_present_test.4121340932 | Apr 23 01:29:47 PM PDT 24 | Apr 23 01:30:12 PM PDT 24 | 3256860000 ps | ||
| T49 | /workspace/coverage/default/20.prim_present_test.3427128742 | Apr 23 01:29:44 PM PDT 24 | Apr 23 01:30:48 PM PDT 24 | 9520100000 ps | ||
| T50 | /workspace/coverage/default/24.prim_present_test.3664578973 | Apr 23 01:29:45 PM PDT 24 | Apr 23 01:31:04 PM PDT 24 | 11636780000 ps |
| Test location | /workspace/coverage/default/1.prim_present_test.1125431260 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 7788440000 ps |
| CPU time | 30.66 seconds |
| Started | Apr 23 01:29:45 PM PDT 24 |
| Finished | Apr 23 01:30:46 PM PDT 24 |
| Peak memory | 145152 kb |
| Host | smart-6fa16971-c694-4802-a221-941aa722ce0f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1125431260 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.1125431260 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/0.prim_present_test.4046324939 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 12525240000 ps |
| CPU time | 50.71 seconds |
| Started | Apr 23 01:29:43 PM PDT 24 |
| Finished | Apr 23 01:31:21 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-b8126e6f-2c3d-4365-8e80-533fe6da219b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4046324939 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.4046324939 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/10.prim_present_test.2596269251 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 7808900000 ps |
| CPU time | 30.45 seconds |
| Started | Apr 23 01:29:45 PM PDT 24 |
| Finished | Apr 23 01:30:44 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-cca23945-58a1-4c38-b1c0-94a06be98e54 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2596269251 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.2596269251 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/11.prim_present_test.2421451634 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 8440060000 ps |
| CPU time | 26.88 seconds |
| Started | Apr 23 01:29:42 PM PDT 24 |
| Finished | Apr 23 01:30:33 PM PDT 24 |
| Peak memory | 145132 kb |
| Host | smart-bfb0e53e-0372-4313-9b9f-01a2345d0ffc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2421451634 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.2421451634 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.3517764121 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 11771320000 ps |
| CPU time | 45.24 seconds |
| Started | Apr 23 01:29:45 PM PDT 24 |
| Finished | Apr 23 01:31:13 PM PDT 24 |
| Peak memory | 145156 kb |
| Host | smart-45548478-ac29-4408-ae83-02c71cfd1d1a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3517764121 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.3517764121 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.1014731283 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 12838960000 ps |
| CPU time | 50.36 seconds |
| Started | Apr 23 01:29:52 PM PDT 24 |
| Finished | Apr 23 01:31:30 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-d866a612-dd31-4e17-8ffd-a9dadf48beb8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1014731283 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.1014731283 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.4121340932 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 3256860000 ps |
| CPU time | 12.46 seconds |
| Started | Apr 23 01:29:47 PM PDT 24 |
| Finished | Apr 23 01:30:12 PM PDT 24 |
| Peak memory | 144956 kb |
| Host | smart-c3a4f3b9-15fe-4667-8b13-ed0dfb612687 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4121340932 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.4121340932 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.1470676660 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 7080400000 ps |
| CPU time | 27.71 seconds |
| Started | Apr 23 01:29:46 PM PDT 24 |
| Finished | Apr 23 01:30:41 PM PDT 24 |
| Peak memory | 145164 kb |
| Host | smart-943ebc8a-e50f-4d9b-94ab-fa07cf09982e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1470676660 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.1470676660 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.3666973828 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 5860240000 ps |
| CPU time | 21.65 seconds |
| Started | Apr 23 01:29:47 PM PDT 24 |
| Finished | Apr 23 01:30:29 PM PDT 24 |
| Peak memory | 145104 kb |
| Host | smart-9c9686d9-312a-4f79-af7c-44a1602e4509 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3666973828 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.3666973828 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.2378356807 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 14594180000 ps |
| CPU time | 62.27 seconds |
| Started | Apr 23 01:29:46 PM PDT 24 |
| Finished | Apr 23 01:31:49 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-3b918c79-3aa1-4b6d-8ae4-901c7ff77bbe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2378356807 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.2378356807 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.1031528833 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 8790360000 ps |
| CPU time | 35.67 seconds |
| Started | Apr 23 01:29:46 PM PDT 24 |
| Finished | Apr 23 01:30:53 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-e050499e-0894-4715-a00b-0b219b9c9075 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1031528833 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.1031528833 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.3560260469 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 9239240000 ps |
| CPU time | 35.59 seconds |
| Started | Apr 23 01:29:46 PM PDT 24 |
| Finished | Apr 23 01:30:55 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-359286bf-f7d1-4121-9675-96c36c396235 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3560260469 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.3560260469 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.2285500192 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 10345320000 ps |
| CPU time | 41.11 seconds |
| Started | Apr 23 01:29:45 PM PDT 24 |
| Finished | Apr 23 01:31:03 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-2bf12135-fff1-4a39-aae6-3ddd6a3a5997 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2285500192 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.2285500192 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.3427128742 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 9520100000 ps |
| CPU time | 33.91 seconds |
| Started | Apr 23 01:29:44 PM PDT 24 |
| Finished | Apr 23 01:30:48 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-7e0c594b-9bba-4be2-a398-fe43d805be9f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3427128742 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.3427128742 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.4023852227 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 3407520000 ps |
| CPU time | 14.22 seconds |
| Started | Apr 23 01:29:46 PM PDT 24 |
| Finished | Apr 23 01:30:13 PM PDT 24 |
| Peak memory | 144952 kb |
| Host | smart-27f7caa9-cd77-475d-93e0-8b981160387f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4023852227 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.4023852227 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.2246424760 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 12776960000 ps |
| CPU time | 44.82 seconds |
| Started | Apr 23 01:29:50 PM PDT 24 |
| Finished | Apr 23 01:31:18 PM PDT 24 |
| Peak memory | 145088 kb |
| Host | smart-61caa5e8-67da-47bf-9c1f-a7c066e00347 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2246424760 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.2246424760 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.514657231 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 9198320000 ps |
| CPU time | 35.93 seconds |
| Started | Apr 23 01:29:45 PM PDT 24 |
| Finished | Apr 23 01:30:56 PM PDT 24 |
| Peak memory | 145108 kb |
| Host | smart-fc9748e7-813e-4578-8121-a68056230e54 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=514657231 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.514657231 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.3664578973 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 11636780000 ps |
| CPU time | 41.53 seconds |
| Started | Apr 23 01:29:45 PM PDT 24 |
| Finished | Apr 23 01:31:04 PM PDT 24 |
| Peak memory | 145200 kb |
| Host | smart-047f79bd-e7ad-41ac-bfc1-917092b11c5c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3664578973 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.3664578973 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.3366462613 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 9955960000 ps |
| CPU time | 36.76 seconds |
| Started | Apr 23 01:29:48 PM PDT 24 |
| Finished | Apr 23 01:30:57 PM PDT 24 |
| Peak memory | 145120 kb |
| Host | smart-a3834c02-b6c7-44ad-bed3-e9a851d19bee |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3366462613 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.3366462613 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.900158849 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 12128440000 ps |
| CPU time | 34.27 seconds |
| Started | Apr 23 01:29:53 PM PDT 24 |
| Finished | Apr 23 01:30:57 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-612c1764-105b-4bbe-8d92-fcb42de09ed8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=900158849 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.900158849 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.869089475 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 13028680000 ps |
| CPU time | 50.19 seconds |
| Started | Apr 23 01:29:53 PM PDT 24 |
| Finished | Apr 23 01:31:31 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-962fbebe-220f-4747-aac0-fe68ec157acc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=869089475 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.869089475 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.688307915 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 9058200000 ps |
| CPU time | 34.88 seconds |
| Started | Apr 23 01:29:52 PM PDT 24 |
| Finished | Apr 23 01:31:01 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-11c07a0f-f7b2-43db-8d45-5b8bd4e16617 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=688307915 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.688307915 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.2134744072 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 5969980000 ps |
| CPU time | 23.92 seconds |
| Started | Apr 23 01:29:50 PM PDT 24 |
| Finished | Apr 23 01:30:38 PM PDT 24 |
| Peak memory | 145084 kb |
| Host | smart-527c9041-dd78-415f-871f-5258db355582 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2134744072 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.2134744072 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.3906619352 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 11132720000 ps |
| CPU time | 45.07 seconds |
| Started | Apr 23 01:29:43 PM PDT 24 |
| Finished | Apr 23 01:31:12 PM PDT 24 |
| Peak memory | 145164 kb |
| Host | smart-bbbf5bd6-8a84-47ff-8416-19d2e582d023 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3906619352 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.3906619352 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.2400205186 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 8940400000 ps |
| CPU time | 33.47 seconds |
| Started | Apr 23 01:29:58 PM PDT 24 |
| Finished | Apr 23 01:31:02 PM PDT 24 |
| Peak memory | 144508 kb |
| Host | smart-7a2e319a-f38d-4a8a-b70d-994e4381140a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2400205186 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.2400205186 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.3682644081 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 9296280000 ps |
| CPU time | 35.94 seconds |
| Started | Apr 23 01:29:51 PM PDT 24 |
| Finished | Apr 23 01:31:02 PM PDT 24 |
| Peak memory | 145152 kb |
| Host | smart-b75b6460-37de-44af-a6e9-33bde39b8f04 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3682644081 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.3682644081 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.1502910436 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 4666120000 ps |
| CPU time | 19.17 seconds |
| Started | Apr 23 01:29:50 PM PDT 24 |
| Finished | Apr 23 01:30:29 PM PDT 24 |
| Peak memory | 145088 kb |
| Host | smart-ce7307b3-21db-457c-b8db-5e0602298d02 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1502910436 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.1502910436 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.1221476934 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 9056340000 ps |
| CPU time | 32.73 seconds |
| Started | Apr 23 01:29:58 PM PDT 24 |
| Finished | Apr 23 01:31:00 PM PDT 24 |
| Peak memory | 145116 kb |
| Host | smart-472eca01-8e51-4a47-befe-ef1fd15ea238 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1221476934 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.1221476934 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.534125736 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 3837800000 ps |
| CPU time | 16.16 seconds |
| Started | Apr 23 01:29:51 PM PDT 24 |
| Finished | Apr 23 01:30:23 PM PDT 24 |
| Peak memory | 144944 kb |
| Host | smart-8ae35fd6-0fbb-4f15-b443-ad1f6a522ab4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=534125736 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.534125736 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.3083079318 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 3759060000 ps |
| CPU time | 14.45 seconds |
| Started | Apr 23 01:29:58 PM PDT 24 |
| Finished | Apr 23 01:30:26 PM PDT 24 |
| Peak memory | 144596 kb |
| Host | smart-4693313c-7835-4640-b129-77ad8c7e31aa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3083079318 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.3083079318 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.4044932163 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 12839580000 ps |
| CPU time | 48.93 seconds |
| Started | Apr 23 01:29:49 PM PDT 24 |
| Finished | Apr 23 01:31:23 PM PDT 24 |
| Peak memory | 145144 kb |
| Host | smart-fa36fa0a-ba15-47b8-acd0-44600467ef23 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4044932163 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.4044932163 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.3259704585 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 5607280000 ps |
| CPU time | 21.19 seconds |
| Started | Apr 23 01:29:49 PM PDT 24 |
| Finished | Apr 23 01:30:31 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-8b4c0223-3625-4f86-bdc8-d7eb7c272256 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3259704585 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.3259704585 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.2128707590 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 7441240000 ps |
| CPU time | 22 seconds |
| Started | Apr 23 01:29:49 PM PDT 24 |
| Finished | Apr 23 01:30:30 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-0c9d5fc5-44a2-4129-8ffb-b82c9574e6a3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2128707590 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.2128707590 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.3232831495 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 11235020000 ps |
| CPU time | 40.87 seconds |
| Started | Apr 23 01:29:58 PM PDT 24 |
| Finished | Apr 23 01:31:16 PM PDT 24 |
| Peak memory | 144756 kb |
| Host | smart-ba699e5f-de57-46c8-9a6f-2a5c82118c27 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3232831495 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.3232831495 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.3288755669 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 5806300000 ps |
| CPU time | 23.83 seconds |
| Started | Apr 23 01:29:48 PM PDT 24 |
| Finished | Apr 23 01:30:35 PM PDT 24 |
| Peak memory | 145092 kb |
| Host | smart-12945739-e392-4e75-b3a9-717da9f2a565 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3288755669 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.3288755669 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.3059128369 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 7364360000 ps |
| CPU time | 28.28 seconds |
| Started | Apr 23 01:29:50 PM PDT 24 |
| Finished | Apr 23 01:30:44 PM PDT 24 |
| Peak memory | 145132 kb |
| Host | smart-bcf7a215-2e08-4b40-b1e1-88373546777e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3059128369 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.3059128369 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.943616949 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 3948160000 ps |
| CPU time | 14.56 seconds |
| Started | Apr 23 01:29:49 PM PDT 24 |
| Finished | Apr 23 01:30:16 PM PDT 24 |
| Peak memory | 144956 kb |
| Host | smart-3d6e4092-277b-4c43-bab2-074fa3e5f1ce |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=943616949 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.943616949 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.3200618210 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 9098500000 ps |
| CPU time | 34.15 seconds |
| Started | Apr 23 01:29:58 PM PDT 24 |
| Finished | Apr 23 01:31:03 PM PDT 24 |
| Peak memory | 144872 kb |
| Host | smart-c5bee527-8876-4eaa-865d-8c43b0ba966e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3200618210 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.3200618210 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.895045259 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 10582160000 ps |
| CPU time | 38.5 seconds |
| Started | Apr 23 01:29:52 PM PDT 24 |
| Finished | Apr 23 01:31:06 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-be795dec-81a9-4b49-bffc-7394f3786257 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=895045259 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.895045259 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.2628369030 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 11769460000 ps |
| CPU time | 40.91 seconds |
| Started | Apr 23 01:29:51 PM PDT 24 |
| Finished | Apr 23 01:31:13 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-878d40c3-e87d-4ca4-b0ca-02cbfaf2bc7a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2628369030 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.2628369030 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.1491181921 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 6599900000 ps |
| CPU time | 25.12 seconds |
| Started | Apr 23 01:29:53 PM PDT 24 |
| Finished | Apr 23 01:30:43 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-fe552e91-36a2-49ec-b084-9cdb8f9e3c1a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1491181921 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.1491181921 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.3130423426 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 9054480000 ps |
| CPU time | 27.62 seconds |
| Started | Apr 23 01:29:57 PM PDT 24 |
| Finished | Apr 23 01:30:48 PM PDT 24 |
| Peak memory | 145124 kb |
| Host | smart-85c43c5a-877e-4e53-b00b-807bf65b1c50 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3130423426 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.3130423426 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.2549156977 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 8149280000 ps |
| CPU time | 28.07 seconds |
| Started | Apr 23 01:29:52 PM PDT 24 |
| Finished | Apr 23 01:30:45 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-e1f6363d-5f50-49bb-8118-76b7ab546989 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2549156977 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.2549156977 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.3936908715 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 13346120000 ps |
| CPU time | 52.29 seconds |
| Started | Apr 23 01:29:54 PM PDT 24 |
| Finished | Apr 23 01:31:35 PM PDT 24 |
| Peak memory | 145120 kb |
| Host | smart-17c86625-4091-41a4-9a60-578e24be591c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3936908715 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.3936908715 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.3225039697 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 11497280000 ps |
| CPU time | 38.49 seconds |
| Started | Apr 23 01:29:52 PM PDT 24 |
| Finished | Apr 23 01:31:05 PM PDT 24 |
| Peak memory | 145204 kb |
| Host | smart-13e4bf1a-ad93-424d-b257-00ac7582e440 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3225039697 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.3225039697 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.4275830311 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 4052940000 ps |
| CPU time | 16.96 seconds |
| Started | Apr 23 01:29:47 PM PDT 24 |
| Finished | Apr 23 01:30:21 PM PDT 24 |
| Peak memory | 144940 kb |
| Host | smart-9d3715e6-bb05-4cc1-87cf-ed2155abb3e2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4275830311 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.4275830311 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.420495557 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 7493940000 ps |
| CPU time | 27.19 seconds |
| Started | Apr 23 01:29:42 PM PDT 24 |
| Finished | Apr 23 01:30:34 PM PDT 24 |
| Peak memory | 145092 kb |
| Host | smart-1c1eaf5d-7045-4f47-ba25-7164480ac545 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=420495557 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.420495557 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.2812221397 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 11825260000 ps |
| CPU time | 47.68 seconds |
| Started | Apr 23 01:29:44 PM PDT 24 |
| Finished | Apr 23 01:31:17 PM PDT 24 |
| Peak memory | 145116 kb |
| Host | smart-3cd3ba29-4b2d-432a-a917-50ad99707616 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2812221397 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.2812221397 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.4253450888 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 8612420000 ps |
| CPU time | 32.28 seconds |
| Started | Apr 23 01:29:42 PM PDT 24 |
| Finished | Apr 23 01:30:46 PM PDT 24 |
| Peak memory | 145108 kb |
| Host | smart-3621fe32-1585-42f0-9049-8e73194fb599 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4253450888 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.4253450888 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.1344342220 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 12719920000 ps |
| CPU time | 45.87 seconds |
| Started | Apr 23 01:29:47 PM PDT 24 |
| Finished | Apr 23 01:31:17 PM PDT 24 |
| Peak memory | 145088 kb |
| Host | smart-90780538-985e-4617-bf21-2b1fa4c4946f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1344342220 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.1344342220 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |