| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/12.prim_present_test.4089710583 | ||
| Name |
|---|
| /workspace/coverage/default/0.prim_present_test.4126747701 |
| /workspace/coverage/default/1.prim_present_test.4160810151 |
| /workspace/coverage/default/10.prim_present_test.1706925666 |
| /workspace/coverage/default/11.prim_present_test.4083284096 |
| /workspace/coverage/default/13.prim_present_test.1304223543 |
| /workspace/coverage/default/14.prim_present_test.563366293 |
| /workspace/coverage/default/15.prim_present_test.823590467 |
| /workspace/coverage/default/16.prim_present_test.1359121089 |
| /workspace/coverage/default/17.prim_present_test.132526463 |
| /workspace/coverage/default/18.prim_present_test.4061498443 |
| /workspace/coverage/default/19.prim_present_test.2268768683 |
| /workspace/coverage/default/2.prim_present_test.3029506162 |
| /workspace/coverage/default/20.prim_present_test.2645009278 |
| /workspace/coverage/default/21.prim_present_test.734082087 |
| /workspace/coverage/default/22.prim_present_test.1365154260 |
| /workspace/coverage/default/23.prim_present_test.1373197498 |
| /workspace/coverage/default/24.prim_present_test.3131540723 |
| /workspace/coverage/default/25.prim_present_test.1886909527 |
| /workspace/coverage/default/26.prim_present_test.1728849539 |
| /workspace/coverage/default/27.prim_present_test.240294840 |
| /workspace/coverage/default/28.prim_present_test.2489819804 |
| /workspace/coverage/default/29.prim_present_test.3180450035 |
| /workspace/coverage/default/3.prim_present_test.1173694280 |
| /workspace/coverage/default/30.prim_present_test.4209295678 |
| /workspace/coverage/default/31.prim_present_test.459335804 |
| /workspace/coverage/default/32.prim_present_test.4107272808 |
| /workspace/coverage/default/33.prim_present_test.1411824053 |
| /workspace/coverage/default/34.prim_present_test.598534599 |
| /workspace/coverage/default/35.prim_present_test.2380826304 |
| /workspace/coverage/default/36.prim_present_test.3799808423 |
| /workspace/coverage/default/37.prim_present_test.1975098623 |
| /workspace/coverage/default/38.prim_present_test.1833054963 |
| /workspace/coverage/default/39.prim_present_test.263627430 |
| /workspace/coverage/default/4.prim_present_test.3002265304 |
| /workspace/coverage/default/40.prim_present_test.1742540380 |
| /workspace/coverage/default/41.prim_present_test.3415429427 |
| /workspace/coverage/default/42.prim_present_test.3531613658 |
| /workspace/coverage/default/43.prim_present_test.4081561590 |
| /workspace/coverage/default/44.prim_present_test.2551939783 |
| /workspace/coverage/default/45.prim_present_test.3884313739 |
| /workspace/coverage/default/46.prim_present_test.854385790 |
| /workspace/coverage/default/47.prim_present_test.4028789829 |
| /workspace/coverage/default/48.prim_present_test.2098585603 |
| /workspace/coverage/default/49.prim_present_test.4142541663 |
| /workspace/coverage/default/5.prim_present_test.2677426962 |
| /workspace/coverage/default/6.prim_present_test.429916526 |
| /workspace/coverage/default/7.prim_present_test.2385563324 |
| /workspace/coverage/default/8.prim_present_test.2892015994 |
| /workspace/coverage/default/9.prim_present_test.808651486 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/36.prim_present_test.3799808423 | Apr 25 12:21:48 PM PDT 24 | Apr 25 12:23:47 PM PDT 24 | 13948760000 ps | ||
| T2 | /workspace/coverage/default/2.prim_present_test.3029506162 | Apr 25 12:21:11 PM PDT 24 | Apr 25 12:21:59 PM PDT 24 | 6518680000 ps | ||
| T3 | /workspace/coverage/default/19.prim_present_test.2268768683 | Apr 25 12:22:23 PM PDT 24 | Apr 25 12:22:53 PM PDT 24 | 4048600000 ps | ||
| T4 | /workspace/coverage/default/14.prim_present_test.563366293 | Apr 25 12:22:09 PM PDT 24 | Apr 25 12:22:51 PM PDT 24 | 5886280000 ps | ||
| T5 | /workspace/coverage/default/42.prim_present_test.3531613658 | Apr 25 12:19:19 PM PDT 24 | Apr 25 12:20:06 PM PDT 24 | 6736920000 ps | ||
| T6 | /workspace/coverage/default/12.prim_present_test.4089710583 | Apr 25 12:22:09 PM PDT 24 | Apr 25 12:23:50 PM PDT 24 | 15297880000 ps | ||
| T7 | /workspace/coverage/default/35.prim_present_test.2380826304 | Apr 25 12:21:28 PM PDT 24 | Apr 25 12:22:28 PM PDT 24 | 8148660000 ps | ||
| T8 | /workspace/coverage/default/48.prim_present_test.2098585603 | Apr 25 12:22:14 PM PDT 24 | Apr 25 12:23:36 PM PDT 24 | 13736720000 ps | ||
| T9 | /workspace/coverage/default/41.prim_present_test.3415429427 | Apr 25 12:19:29 PM PDT 24 | Apr 25 12:20:37 PM PDT 24 | 8952800000 ps | ||
| T10 | /workspace/coverage/default/39.prim_present_test.263627430 | Apr 25 12:22:13 PM PDT 24 | Apr 25 12:23:28 PM PDT 24 | 10813420000 ps | ||
| T11 | /workspace/coverage/default/0.prim_present_test.4126747701 | Apr 25 12:18:32 PM PDT 24 | Apr 25 12:20:41 PM PDT 24 | 14518540000 ps | ||
| T12 | /workspace/coverage/default/44.prim_present_test.2551939783 | Apr 25 12:21:40 PM PDT 24 | Apr 25 12:22:59 PM PDT 24 | 12684580000 ps | ||
| T13 | /workspace/coverage/default/23.prim_present_test.1373197498 | Apr 25 12:18:48 PM PDT 24 | Apr 25 12:20:05 PM PDT 24 | 10834500000 ps | ||
| T14 | /workspace/coverage/default/5.prim_present_test.2677426962 | Apr 25 12:21:54 PM PDT 24 | Apr 25 12:22:24 PM PDT 24 | 5004640000 ps | ||
| T15 | /workspace/coverage/default/33.prim_present_test.1411824053 | Apr 25 12:19:00 PM PDT 24 | Apr 25 12:20:45 PM PDT 24 | 12255540000 ps | ||
| T16 | /workspace/coverage/default/30.prim_present_test.4209295678 | Apr 25 12:20:32 PM PDT 24 | Apr 25 12:21:58 PM PDT 24 | 10354000000 ps | ||
| T17 | /workspace/coverage/default/18.prim_present_test.4061498443 | Apr 25 12:18:44 PM PDT 24 | Apr 25 12:19:34 PM PDT 24 | 7142400000 ps | ||
| T18 | /workspace/coverage/default/29.prim_present_test.3180450035 | Apr 25 12:21:15 PM PDT 24 | Apr 25 12:22:16 PM PDT 24 | 11895320000 ps | ||
| T19 | /workspace/coverage/default/3.prim_present_test.1173694280 | Apr 25 12:21:11 PM PDT 24 | Apr 25 12:21:58 PM PDT 24 | 6283700000 ps | ||
| T20 | /workspace/coverage/default/4.prim_present_test.3002265304 | Apr 25 12:21:50 PM PDT 24 | Apr 25 12:23:23 PM PDT 24 | 14600380000 ps | ||
| T21 | /workspace/coverage/default/28.prim_present_test.2489819804 | Apr 25 12:18:55 PM PDT 24 | Apr 25 12:20:35 PM PDT 24 | 14136000000 ps | ||
| T22 | /workspace/coverage/default/43.prim_present_test.4081561590 | Apr 25 12:21:40 PM PDT 24 | Apr 25 12:23:01 PM PDT 24 | 13145240000 ps | ||
| T23 | /workspace/coverage/default/37.prim_present_test.1975098623 | Apr 25 12:19:11 PM PDT 24 | Apr 25 12:21:00 PM PDT 24 | 13163220000 ps | ||
| T24 | /workspace/coverage/default/49.prim_present_test.4142541663 | Apr 25 12:22:08 PM PDT 24 | Apr 25 12:23:19 PM PDT 24 | 12232600000 ps | ||
| T25 | /workspace/coverage/default/13.prim_present_test.1304223543 | Apr 25 12:18:38 PM PDT 24 | Apr 25 12:20:29 PM PDT 24 | 15135440000 ps | ||
| T26 | /workspace/coverage/default/27.prim_present_test.240294840 | Apr 25 12:18:56 PM PDT 24 | Apr 25 12:20:17 PM PDT 24 | 11876100000 ps | ||
| T27 | /workspace/coverage/default/22.prim_present_test.1365154260 | Apr 25 12:21:25 PM PDT 24 | Apr 25 12:21:49 PM PDT 24 | 3346760000 ps | ||
| T28 | /workspace/coverage/default/11.prim_present_test.4083284096 | Apr 25 12:22:11 PM PDT 24 | Apr 25 12:23:44 PM PDT 24 | 14192420000 ps | ||
| T29 | /workspace/coverage/default/40.prim_present_test.1742540380 | Apr 25 12:21:40 PM PDT 24 | Apr 25 12:23:06 PM PDT 24 | 13884280000 ps | ||
| T30 | /workspace/coverage/default/15.prim_present_test.823590467 | Apr 25 12:22:11 PM PDT 24 | Apr 25 12:23:39 PM PDT 24 | 13211580000 ps | ||
| T31 | /workspace/coverage/default/17.prim_present_test.132526463 | Apr 25 12:22:11 PM PDT 24 | Apr 25 12:23:29 PM PDT 24 | 11644220000 ps | ||
| T32 | /workspace/coverage/default/45.prim_present_test.3884313739 | Apr 25 12:21:24 PM PDT 24 | Apr 25 12:22:38 PM PDT 24 | 13015660000 ps | ||
| T33 | /workspace/coverage/default/24.prim_present_test.3131540723 | Apr 25 12:19:00 PM PDT 24 | Apr 25 12:20:52 PM PDT 24 | 13695800000 ps | ||
| T34 | /workspace/coverage/default/1.prim_present_test.4160810151 | Apr 25 12:21:50 PM PDT 24 | Apr 25 12:23:09 PM PDT 24 | 12507260000 ps | ||
| T35 | /workspace/coverage/default/21.prim_present_test.734082087 | Apr 25 12:21:25 PM PDT 24 | Apr 25 12:22:49 PM PDT 24 | 13334960000 ps | ||
| T36 | /workspace/coverage/default/6.prim_present_test.429916526 | Apr 25 12:22:06 PM PDT 24 | Apr 25 12:22:44 PM PDT 24 | 6190080000 ps | ||
| T37 | /workspace/coverage/default/10.prim_present_test.1706925666 | Apr 25 12:21:11 PM PDT 24 | Apr 25 12:22:22 PM PDT 24 | 9998120000 ps | ||
| T38 | /workspace/coverage/default/26.prim_present_test.1728849539 | Apr 25 12:21:15 PM PDT 24 | Apr 25 12:21:48 PM PDT 24 | 6550300000 ps | ||
| T39 | /workspace/coverage/default/16.prim_present_test.1359121089 | Apr 25 12:22:12 PM PDT 24 | Apr 25 12:22:43 PM PDT 24 | 3964280000 ps | ||
| T40 | /workspace/coverage/default/7.prim_present_test.2385563324 | Apr 25 12:21:12 PM PDT 24 | Apr 25 12:22:48 PM PDT 24 | 14593560000 ps | ||
| T41 | /workspace/coverage/default/34.prim_present_test.598534599 | Apr 25 12:22:09 PM PDT 24 | Apr 25 12:23:37 PM PDT 24 | 13230180000 ps | ||
| T42 | /workspace/coverage/default/32.prim_present_test.4107272808 | Apr 25 12:22:02 PM PDT 24 | Apr 25 12:22:39 PM PDT 24 | 5773440000 ps | ||
| T43 | /workspace/coverage/default/38.prim_present_test.1833054963 | Apr 25 12:22:12 PM PDT 24 | Apr 25 12:22:54 PM PDT 24 | 5287360000 ps | ||
| T44 | /workspace/coverage/default/8.prim_present_test.2892015994 | Apr 25 12:18:32 PM PDT 24 | Apr 25 12:19:02 PM PDT 24 | 3212840000 ps | ||
| T45 | /workspace/coverage/default/9.prim_present_test.808651486 | Apr 25 12:21:51 PM PDT 24 | Apr 25 12:22:30 PM PDT 24 | 5483900000 ps | ||
| T46 | /workspace/coverage/default/46.prim_present_test.854385790 | Apr 25 12:22:15 PM PDT 24 | Apr 25 12:22:48 PM PDT 24 | 5147860000 ps | ||
| T47 | /workspace/coverage/default/25.prim_present_test.1886909527 | Apr 25 12:21:59 PM PDT 24 | Apr 25 12:22:46 PM PDT 24 | 7967000000 ps | ||
| T48 | /workspace/coverage/default/47.prim_present_test.4028789829 | Apr 25 12:22:08 PM PDT 24 | Apr 25 12:22:45 PM PDT 24 | 6005940000 ps | ||
| T49 | /workspace/coverage/default/20.prim_present_test.2645009278 | Apr 25 12:19:10 PM PDT 24 | Apr 25 12:20:57 PM PDT 24 | 13857000000 ps | ||
| T50 | /workspace/coverage/default/31.prim_present_test.459335804 | Apr 25 12:21:21 PM PDT 24 | Apr 25 12:22:45 PM PDT 24 | 9266520000 ps |
| Test location | /workspace/coverage/default/12.prim_present_test.4089710583 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 15297880000 ps |
| CPU time | 52.99 seconds |
| Started | Apr 25 12:22:09 PM PDT 24 |
| Finished | Apr 25 12:23:50 PM PDT 24 |
| Peak memory | 143216 kb |
| Host | smart-1161bc89-95a9-456d-9e39-736eecfbfe46 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4089710583 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.4089710583 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/0.prim_present_test.4126747701 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 14518540000 ps |
| CPU time | 64.31 seconds |
| Started | Apr 25 12:18:32 PM PDT 24 |
| Finished | Apr 25 12:20:41 PM PDT 24 |
| Peak memory | 145152 kb |
| Host | smart-cc768317-3928-4ea9-977f-25c8767679ab |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4126747701 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.4126747701 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/1.prim_present_test.4160810151 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 12507260000 ps |
| CPU time | 41.32 seconds |
| Started | Apr 25 12:21:50 PM PDT 24 |
| Finished | Apr 25 12:23:09 PM PDT 24 |
| Peak memory | 143824 kb |
| Host | smart-b6b43b99-eb71-4dd1-98c7-457b5dd366e7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4160810151 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.4160810151 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/10.prim_present_test.1706925666 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 9998120000 ps |
| CPU time | 36.94 seconds |
| Started | Apr 25 12:21:11 PM PDT 24 |
| Finished | Apr 25 12:22:22 PM PDT 24 |
| Peak memory | 143288 kb |
| Host | smart-4a57a9ac-038e-4591-915b-201efea19892 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1706925666 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.1706925666 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/11.prim_present_test.4083284096 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 14192420000 ps |
| CPU time | 48.34 seconds |
| Started | Apr 25 12:22:11 PM PDT 24 |
| Finished | Apr 25 12:23:44 PM PDT 24 |
| Peak memory | 143372 kb |
| Host | smart-b74069ce-672d-4025-94e1-3c915465fd4a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4083284096 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.4083284096 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.1304223543 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 15135440000 ps |
| CPU time | 58.25 seconds |
| Started | Apr 25 12:18:38 PM PDT 24 |
| Finished | Apr 25 12:20:29 PM PDT 24 |
| Peak memory | 145164 kb |
| Host | smart-b16e862c-382a-4c00-aa84-075f508cee93 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1304223543 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.1304223543 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.563366293 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 5886280000 ps |
| CPU time | 21.32 seconds |
| Started | Apr 25 12:22:09 PM PDT 24 |
| Finished | Apr 25 12:22:51 PM PDT 24 |
| Peak memory | 143560 kb |
| Host | smart-ec2d9257-2aa7-4a7a-abfb-9e55495c5d15 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=563366293 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.563366293 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.823590467 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 13211580000 ps |
| CPU time | 46.09 seconds |
| Started | Apr 25 12:22:11 PM PDT 24 |
| Finished | Apr 25 12:23:39 PM PDT 24 |
| Peak memory | 144556 kb |
| Host | smart-c4ae24dd-6415-42b9-9f47-a67db42495bf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=823590467 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.823590467 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.1359121089 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 3964280000 ps |
| CPU time | 15.53 seconds |
| Started | Apr 25 12:22:12 PM PDT 24 |
| Finished | Apr 25 12:22:43 PM PDT 24 |
| Peak memory | 144476 kb |
| Host | smart-b51d887d-73b7-44cd-9ab7-f48fbd51b9c5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1359121089 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.1359121089 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.132526463 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 11644220000 ps |
| CPU time | 40.52 seconds |
| Started | Apr 25 12:22:11 PM PDT 24 |
| Finished | Apr 25 12:23:29 PM PDT 24 |
| Peak memory | 144556 kb |
| Host | smart-2903f334-bcc8-4651-bd82-257dce15a95e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=132526463 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.132526463 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.4061498443 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 7142400000 ps |
| CPU time | 26.29 seconds |
| Started | Apr 25 12:18:44 PM PDT 24 |
| Finished | Apr 25 12:19:34 PM PDT 24 |
| Peak memory | 145012 kb |
| Host | smart-2e79cb90-4ab6-491b-9511-cf20f0d94263 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4061498443 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.4061498443 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.2268768683 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 4048600000 ps |
| CPU time | 15.64 seconds |
| Started | Apr 25 12:22:23 PM PDT 24 |
| Finished | Apr 25 12:22:53 PM PDT 24 |
| Peak memory | 144524 kb |
| Host | smart-8d16f88b-3838-41fd-8245-d1c8c993384f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2268768683 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.2268768683 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.3029506162 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 6518680000 ps |
| CPU time | 24.42 seconds |
| Started | Apr 25 12:21:11 PM PDT 24 |
| Finished | Apr 25 12:21:59 PM PDT 24 |
| Peak memory | 143180 kb |
| Host | smart-8633377b-b014-4291-a7f0-4a6ebd81a24f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3029506162 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.3029506162 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.2645009278 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 13857000000 ps |
| CPU time | 56.18 seconds |
| Started | Apr 25 12:19:10 PM PDT 24 |
| Finished | Apr 25 12:20:57 PM PDT 24 |
| Peak memory | 145012 kb |
| Host | smart-e6e0fd52-6fbc-424e-915a-892813c43dfa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2645009278 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.2645009278 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.734082087 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 13334960000 ps |
| CPU time | 44.17 seconds |
| Started | Apr 25 12:21:25 PM PDT 24 |
| Finished | Apr 25 12:22:49 PM PDT 24 |
| Peak memory | 144576 kb |
| Host | smart-b8bb2d73-58b5-4a96-8454-d8feab93a51d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=734082087 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.734082087 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.1365154260 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 3346760000 ps |
| CPU time | 12.14 seconds |
| Started | Apr 25 12:21:25 PM PDT 24 |
| Finished | Apr 25 12:21:49 PM PDT 24 |
| Peak memory | 143260 kb |
| Host | smart-2b3352d0-3b4f-4e60-8f36-f158ee77e2a1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1365154260 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.1365154260 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.1373197498 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 10834500000 ps |
| CPU time | 40.45 seconds |
| Started | Apr 25 12:18:48 PM PDT 24 |
| Finished | Apr 25 12:20:05 PM PDT 24 |
| Peak memory | 145008 kb |
| Host | smart-d54da1d1-60f5-47a3-b0df-77f07cae091f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1373197498 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.1373197498 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.3131540723 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 13695800000 ps |
| CPU time | 58.27 seconds |
| Started | Apr 25 12:19:00 PM PDT 24 |
| Finished | Apr 25 12:20:52 PM PDT 24 |
| Peak memory | 145020 kb |
| Host | smart-a866c597-7ad8-44c3-98aa-c39f216dfbe0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3131540723 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.3131540723 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.1886909527 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 7967000000 ps |
| CPU time | 25.03 seconds |
| Started | Apr 25 12:21:59 PM PDT 24 |
| Finished | Apr 25 12:22:46 PM PDT 24 |
| Peak memory | 143764 kb |
| Host | smart-86ed1f00-97ac-4dd3-98b8-11588777a733 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1886909527 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.1886909527 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.1728849539 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 6550300000 ps |
| CPU time | 17.75 seconds |
| Started | Apr 25 12:21:15 PM PDT 24 |
| Finished | Apr 25 12:21:48 PM PDT 24 |
| Peak memory | 145040 kb |
| Host | smart-9839242c-fe26-49d1-8130-3c3a92250fa3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1728849539 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.1728849539 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.240294840 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 11876100000 ps |
| CPU time | 43.1 seconds |
| Started | Apr 25 12:18:56 PM PDT 24 |
| Finished | Apr 25 12:20:17 PM PDT 24 |
| Peak memory | 145028 kb |
| Host | smart-3bcac7ae-0282-4c18-988f-a5dc7dc799af |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=240294840 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.240294840 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.2489819804 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 14136000000 ps |
| CPU time | 53.62 seconds |
| Started | Apr 25 12:18:55 PM PDT 24 |
| Finished | Apr 25 12:20:35 PM PDT 24 |
| Peak memory | 145008 kb |
| Host | smart-29175a21-a05a-4745-9db7-7298f0ca0865 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2489819804 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.2489819804 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.3180450035 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 11895320000 ps |
| CPU time | 33.14 seconds |
| Started | Apr 25 12:21:15 PM PDT 24 |
| Finished | Apr 25 12:22:16 PM PDT 24 |
| Peak memory | 144000 kb |
| Host | smart-8c22a423-a760-4366-88eb-32fa9a775a15 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3180450035 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.3180450035 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.1173694280 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 6283700000 ps |
| CPU time | 23.49 seconds |
| Started | Apr 25 12:21:11 PM PDT 24 |
| Finished | Apr 25 12:21:58 PM PDT 24 |
| Peak memory | 144608 kb |
| Host | smart-f82753c4-7c88-426f-a7d8-b9458e38236d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1173694280 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.1173694280 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.4209295678 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 10354000000 ps |
| CPU time | 43.43 seconds |
| Started | Apr 25 12:20:32 PM PDT 24 |
| Finished | Apr 25 12:21:58 PM PDT 24 |
| Peak memory | 145140 kb |
| Host | smart-f6ec1b2c-a872-4209-a5e1-4435428fba29 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4209295678 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.4209295678 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.459335804 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 9266520000 ps |
| CPU time | 41.1 seconds |
| Started | Apr 25 12:21:21 PM PDT 24 |
| Finished | Apr 25 12:22:45 PM PDT 24 |
| Peak memory | 145156 kb |
| Host | smart-9e03bc72-cb84-45f8-bfac-0a23807d81e6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=459335804 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.459335804 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.4107272808 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 5773440000 ps |
| CPU time | 19.71 seconds |
| Started | Apr 25 12:22:02 PM PDT 24 |
| Finished | Apr 25 12:22:39 PM PDT 24 |
| Peak memory | 143512 kb |
| Host | smart-2c5fc335-6e7b-4daf-8c2d-66fecc788b64 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4107272808 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.4107272808 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.1411824053 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 12255540000 ps |
| CPU time | 53.59 seconds |
| Started | Apr 25 12:19:00 PM PDT 24 |
| Finished | Apr 25 12:20:45 PM PDT 24 |
| Peak memory | 145132 kb |
| Host | smart-69af2654-6c6e-4783-abe0-a410159b6dc7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1411824053 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.1411824053 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.598534599 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 13230180000 ps |
| CPU time | 46.16 seconds |
| Started | Apr 25 12:22:09 PM PDT 24 |
| Finished | Apr 25 12:23:37 PM PDT 24 |
| Peak memory | 143144 kb |
| Host | smart-ea7adee9-9cf8-426e-8e52-8af46b52c872 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=598534599 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.598534599 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.2380826304 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 8148660000 ps |
| CPU time | 30.6 seconds |
| Started | Apr 25 12:21:28 PM PDT 24 |
| Finished | Apr 25 12:22:28 PM PDT 24 |
| Peak memory | 145028 kb |
| Host | smart-001baef6-3e67-4937-b60a-6d0c3e02d8d7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2380826304 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.2380826304 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.3799808423 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 13948760000 ps |
| CPU time | 58.61 seconds |
| Started | Apr 25 12:21:48 PM PDT 24 |
| Finished | Apr 25 12:23:47 PM PDT 24 |
| Peak memory | 145140 kb |
| Host | smart-6b4cee5f-9947-421d-97bf-95ba171a7d8b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3799808423 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.3799808423 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.1975098623 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 13163220000 ps |
| CPU time | 55.23 seconds |
| Started | Apr 25 12:19:11 PM PDT 24 |
| Finished | Apr 25 12:21:00 PM PDT 24 |
| Peak memory | 145128 kb |
| Host | smart-99e317df-40ca-42e0-9635-0c5390895f21 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1975098623 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.1975098623 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.1833054963 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 5287360000 ps |
| CPU time | 21.2 seconds |
| Started | Apr 25 12:22:12 PM PDT 24 |
| Finished | Apr 25 12:22:54 PM PDT 24 |
| Peak memory | 143480 kb |
| Host | smart-b9d5dabc-bd8d-47a5-a3b0-02eda55243ba |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1833054963 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.1833054963 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.263627430 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 10813420000 ps |
| CPU time | 39.19 seconds |
| Started | Apr 25 12:22:13 PM PDT 24 |
| Finished | Apr 25 12:23:28 PM PDT 24 |
| Peak memory | 144628 kb |
| Host | smart-8bb440c6-01ed-43dc-9bb7-15949c7b224f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=263627430 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.263627430 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.3002265304 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 14600380000 ps |
| CPU time | 48.96 seconds |
| Started | Apr 25 12:21:50 PM PDT 24 |
| Finished | Apr 25 12:23:23 PM PDT 24 |
| Peak memory | 143588 kb |
| Host | smart-7b500ad7-0b21-49e4-a7ff-c0dd7c645cb5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3002265304 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.3002265304 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.1742540380 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 13884280000 ps |
| CPU time | 45.77 seconds |
| Started | Apr 25 12:21:40 PM PDT 24 |
| Finished | Apr 25 12:23:06 PM PDT 24 |
| Peak memory | 142480 kb |
| Host | smart-dc3c01ca-6839-46ec-9bc1-b7f583c93182 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1742540380 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.1742540380 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.3415429427 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 8952800000 ps |
| CPU time | 34.95 seconds |
| Started | Apr 25 12:19:29 PM PDT 24 |
| Finished | Apr 25 12:20:37 PM PDT 24 |
| Peak memory | 145028 kb |
| Host | smart-e9f08d36-a9b3-4c0c-bf65-c144f5c82dea |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3415429427 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.3415429427 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.3531613658 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 6736920000 ps |
| CPU time | 24.74 seconds |
| Started | Apr 25 12:19:19 PM PDT 24 |
| Finished | Apr 25 12:20:06 PM PDT 24 |
| Peak memory | 145008 kb |
| Host | smart-a24800e8-27f9-422d-93fa-2d3670de73f2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3531613658 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.3531613658 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.4081561590 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 13145240000 ps |
| CPU time | 43.47 seconds |
| Started | Apr 25 12:21:40 PM PDT 24 |
| Finished | Apr 25 12:23:01 PM PDT 24 |
| Peak memory | 142384 kb |
| Host | smart-48ac194b-fbaf-46c1-8c3c-e21fce5f5bdc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4081561590 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.4081561590 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.2551939783 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 12684580000 ps |
| CPU time | 42.03 seconds |
| Started | Apr 25 12:21:40 PM PDT 24 |
| Finished | Apr 25 12:22:59 PM PDT 24 |
| Peak memory | 143224 kb |
| Host | smart-53d665c8-90df-43fa-a33f-db0bf4fc4ca5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2551939783 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.2551939783 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.3884313739 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 13015660000 ps |
| CPU time | 39.31 seconds |
| Started | Apr 25 12:21:24 PM PDT 24 |
| Finished | Apr 25 12:22:38 PM PDT 24 |
| Peak memory | 144948 kb |
| Host | smart-2b03fe91-6d22-489c-af87-4a3620f12246 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3884313739 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.3884313739 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.854385790 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 5147860000 ps |
| CPU time | 17.58 seconds |
| Started | Apr 25 12:22:15 PM PDT 24 |
| Finished | Apr 25 12:22:48 PM PDT 24 |
| Peak memory | 144640 kb |
| Host | smart-ae325357-7693-455e-8768-f7251ee635bd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=854385790 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.854385790 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.4028789829 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 6005940000 ps |
| CPU time | 19 seconds |
| Started | Apr 25 12:22:08 PM PDT 24 |
| Finished | Apr 25 12:22:45 PM PDT 24 |
| Peak memory | 143720 kb |
| Host | smart-123eb216-01b9-4d86-b888-4b2b55dcf36e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4028789829 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.4028789829 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.2098585603 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 13736720000 ps |
| CPU time | 43.62 seconds |
| Started | Apr 25 12:22:14 PM PDT 24 |
| Finished | Apr 25 12:23:36 PM PDT 24 |
| Peak memory | 144644 kb |
| Host | smart-b82631f0-8d48-45b4-9819-de7205f0b471 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2098585603 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.2098585603 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.4142541663 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 12232600000 ps |
| CPU time | 37.5 seconds |
| Started | Apr 25 12:22:08 PM PDT 24 |
| Finished | Apr 25 12:23:19 PM PDT 24 |
| Peak memory | 143740 kb |
| Host | smart-54f584fb-c379-4dfd-b64c-6bc3fab88ae7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4142541663 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.4142541663 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.2677426962 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 5004640000 ps |
| CPU time | 16.36 seconds |
| Started | Apr 25 12:21:54 PM PDT 24 |
| Finished | Apr 25 12:22:24 PM PDT 24 |
| Peak memory | 144736 kb |
| Host | smart-c8f58a04-42af-4974-9c5c-cb2e7da4ff08 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2677426962 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.2677426962 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.429916526 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 6190080000 ps |
| CPU time | 19.78 seconds |
| Started | Apr 25 12:22:06 PM PDT 24 |
| Finished | Apr 25 12:22:44 PM PDT 24 |
| Peak memory | 145028 kb |
| Host | smart-1ccca4ab-cb8b-4841-bf8b-82cc65596d22 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=429916526 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.429916526 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.2385563324 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 14593560000 ps |
| CPU time | 49.68 seconds |
| Started | Apr 25 12:21:12 PM PDT 24 |
| Finished | Apr 25 12:22:48 PM PDT 24 |
| Peak memory | 144616 kb |
| Host | smart-4e450321-f7e8-4bc4-bbe0-84b0e499b4d7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2385563324 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.2385563324 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.2892015994 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 3212840000 ps |
| CPU time | 14.4 seconds |
| Started | Apr 25 12:18:32 PM PDT 24 |
| Finished | Apr 25 12:19:02 PM PDT 24 |
| Peak memory | 145004 kb |
| Host | smart-dcbd5b01-16bf-46f7-992b-39108418ff86 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2892015994 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.2892015994 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.808651486 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 5483900000 ps |
| CPU time | 20.02 seconds |
| Started | Apr 25 12:21:51 PM PDT 24 |
| Finished | Apr 25 12:22:30 PM PDT 24 |
| Peak memory | 144716 kb |
| Host | smart-0dd7328d-51a0-4477-8761-43dd87066939 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=808651486 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.808651486 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |