| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/10.prim_present_test.3506622568 | ||
| Name |
|---|
| /workspace/coverage/default/0.prim_present_test.4068560085 |
| /workspace/coverage/default/1.prim_present_test.1008726337 |
| /workspace/coverage/default/11.prim_present_test.3302271881 |
| /workspace/coverage/default/12.prim_present_test.3051823407 |
| /workspace/coverage/default/13.prim_present_test.2734346835 |
| /workspace/coverage/default/14.prim_present_test.2164104520 |
| /workspace/coverage/default/15.prim_present_test.3124033307 |
| /workspace/coverage/default/16.prim_present_test.3789885760 |
| /workspace/coverage/default/17.prim_present_test.4073858297 |
| /workspace/coverage/default/18.prim_present_test.2735800734 |
| /workspace/coverage/default/19.prim_present_test.1019068853 |
| /workspace/coverage/default/2.prim_present_test.3110066595 |
| /workspace/coverage/default/20.prim_present_test.288906180 |
| /workspace/coverage/default/21.prim_present_test.3670418744 |
| /workspace/coverage/default/22.prim_present_test.388098765 |
| /workspace/coverage/default/23.prim_present_test.2078567549 |
| /workspace/coverage/default/24.prim_present_test.2507755236 |
| /workspace/coverage/default/25.prim_present_test.1091367313 |
| /workspace/coverage/default/26.prim_present_test.921868428 |
| /workspace/coverage/default/27.prim_present_test.630510057 |
| /workspace/coverage/default/28.prim_present_test.2001754704 |
| /workspace/coverage/default/29.prim_present_test.4004700872 |
| /workspace/coverage/default/3.prim_present_test.1239102232 |
| /workspace/coverage/default/30.prim_present_test.3657061868 |
| /workspace/coverage/default/31.prim_present_test.3147050062 |
| /workspace/coverage/default/32.prim_present_test.3972034277 |
| /workspace/coverage/default/33.prim_present_test.1446345250 |
| /workspace/coverage/default/34.prim_present_test.2869854913 |
| /workspace/coverage/default/35.prim_present_test.2525162010 |
| /workspace/coverage/default/36.prim_present_test.649092421 |
| /workspace/coverage/default/37.prim_present_test.374067088 |
| /workspace/coverage/default/38.prim_present_test.3083392525 |
| /workspace/coverage/default/39.prim_present_test.780002385 |
| /workspace/coverage/default/4.prim_present_test.4119287792 |
| /workspace/coverage/default/40.prim_present_test.3960892980 |
| /workspace/coverage/default/41.prim_present_test.780639640 |
| /workspace/coverage/default/42.prim_present_test.815358613 |
| /workspace/coverage/default/43.prim_present_test.2854536285 |
| /workspace/coverage/default/44.prim_present_test.1016155186 |
| /workspace/coverage/default/45.prim_present_test.1702179400 |
| /workspace/coverage/default/46.prim_present_test.4582100 |
| /workspace/coverage/default/47.prim_present_test.125601963 |
| /workspace/coverage/default/48.prim_present_test.4108910502 |
| /workspace/coverage/default/49.prim_present_test.2790134897 |
| /workspace/coverage/default/5.prim_present_test.1083197837 |
| /workspace/coverage/default/6.prim_present_test.2118597728 |
| /workspace/coverage/default/7.prim_present_test.811140205 |
| /workspace/coverage/default/8.prim_present_test.40446947 |
| /workspace/coverage/default/9.prim_present_test.2670821075 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/47.prim_present_test.125601963 | Apr 28 02:59:59 PM PDT 24 | Apr 28 03:00:48 PM PDT 24 | 7601820000 ps | ||
| T2 | /workspace/coverage/default/9.prim_present_test.2670821075 | Apr 28 02:59:47 PM PDT 24 | Apr 28 03:00:45 PM PDT 24 | 9118340000 ps | ||
| T3 | /workspace/coverage/default/48.prim_present_test.4108910502 | Apr 28 03:00:00 PM PDT 24 | Apr 28 03:01:45 PM PDT 24 | 14911000000 ps | ||
| T4 | /workspace/coverage/default/6.prim_present_test.2118597728 | Apr 28 02:59:44 PM PDT 24 | Apr 28 03:00:44 PM PDT 24 | 10425300000 ps | ||
| T5 | /workspace/coverage/default/4.prim_present_test.4119287792 | Apr 28 02:59:40 PM PDT 24 | Apr 28 03:00:25 PM PDT 24 | 7318480000 ps | ||
| T6 | /workspace/coverage/default/10.prim_present_test.3506622568 | Apr 28 02:59:51 PM PDT 24 | Apr 28 03:00:36 PM PDT 24 | 7047540000 ps | ||
| T7 | /workspace/coverage/default/36.prim_present_test.649092421 | Apr 28 03:00:01 PM PDT 24 | Apr 28 03:00:48 PM PDT 24 | 6669340000 ps | ||
| T8 | /workspace/coverage/default/18.prim_present_test.2735800734 | Apr 28 02:59:59 PM PDT 24 | Apr 28 03:00:27 PM PDT 24 | 5489480000 ps | ||
| T9 | /workspace/coverage/default/42.prim_present_test.815358613 | Apr 28 02:59:57 PM PDT 24 | Apr 28 03:01:11 PM PDT 24 | 11783100000 ps | ||
| T10 | /workspace/coverage/default/37.prim_present_test.374067088 | Apr 28 02:59:56 PM PDT 24 | Apr 28 03:00:43 PM PDT 24 | 5925960000 ps | ||
| T11 | /workspace/coverage/default/7.prim_present_test.811140205 | Apr 28 02:59:55 PM PDT 24 | Apr 28 03:01:39 PM PDT 24 | 14912860000 ps | ||
| T12 | /workspace/coverage/default/40.prim_present_test.3960892980 | Apr 28 03:00:01 PM PDT 24 | Apr 28 03:01:10 PM PDT 24 | 11716140000 ps | ||
| T13 | /workspace/coverage/default/43.prim_present_test.2854536285 | Apr 28 02:59:53 PM PDT 24 | Apr 28 03:00:36 PM PDT 24 | 5547760000 ps | ||
| T14 | /workspace/coverage/default/41.prim_present_test.780639640 | Apr 28 02:59:57 PM PDT 24 | Apr 28 03:00:36 PM PDT 24 | 5264420000 ps | ||
| T15 | /workspace/coverage/default/24.prim_present_test.2507755236 | Apr 28 02:59:41 PM PDT 24 | Apr 28 03:00:44 PM PDT 24 | 8663880000 ps | ||
| T16 | /workspace/coverage/default/16.prim_present_test.3789885760 | Apr 28 02:59:45 PM PDT 24 | Apr 28 03:01:12 PM PDT 24 | 14015100000 ps | ||
| T17 | /workspace/coverage/default/1.prim_present_test.1008726337 | Apr 28 02:59:48 PM PDT 24 | Apr 28 03:01:01 PM PDT 24 | 11062040000 ps | ||
| T18 | /workspace/coverage/default/38.prim_present_test.3083392525 | Apr 28 02:59:50 PM PDT 24 | Apr 28 03:00:59 PM PDT 24 | 9995020000 ps | ||
| T19 | /workspace/coverage/default/26.prim_present_test.921868428 | Apr 28 02:59:48 PM PDT 24 | Apr 28 03:00:39 PM PDT 24 | 8417740000 ps | ||
| T20 | /workspace/coverage/default/28.prim_present_test.2001754704 | Apr 28 02:59:48 PM PDT 24 | Apr 28 03:00:55 PM PDT 24 | 10734680000 ps | ||
| T21 | /workspace/coverage/default/20.prim_present_test.288906180 | Apr 28 02:59:47 PM PDT 24 | Apr 28 03:01:37 PM PDT 24 | 14219700000 ps | ||
| T22 | /workspace/coverage/default/0.prim_present_test.4068560085 | Apr 28 02:59:56 PM PDT 24 | Apr 28 03:00:41 PM PDT 24 | 7450540000 ps | ||
| T23 | /workspace/coverage/default/17.prim_present_test.4073858297 | Apr 28 02:59:53 PM PDT 24 | Apr 28 03:00:36 PM PDT 24 | 5984240000 ps | ||
| T24 | /workspace/coverage/default/5.prim_present_test.1083197837 | Apr 28 02:59:53 PM PDT 24 | Apr 28 03:00:54 PM PDT 24 | 9455620000 ps | ||
| T25 | /workspace/coverage/default/25.prim_present_test.1091367313 | Apr 28 02:59:53 PM PDT 24 | Apr 28 03:00:52 PM PDT 24 | 9005500000 ps | ||
| T26 | /workspace/coverage/default/49.prim_present_test.2790134897 | Apr 28 02:59:56 PM PDT 24 | Apr 28 03:00:57 PM PDT 24 | 8517560000 ps | ||
| T27 | /workspace/coverage/default/3.prim_present_test.1239102232 | Apr 28 02:59:54 PM PDT 24 | Apr 28 03:00:40 PM PDT 24 | 6073520000 ps | ||
| T28 | /workspace/coverage/default/30.prim_present_test.3657061868 | Apr 28 02:59:49 PM PDT 24 | Apr 28 03:00:29 PM PDT 24 | 5734380000 ps | ||
| T29 | /workspace/coverage/default/27.prim_present_test.630510057 | Apr 28 02:59:46 PM PDT 24 | Apr 28 03:00:22 PM PDT 24 | 4974260000 ps | ||
| T30 | /workspace/coverage/default/31.prim_present_test.3147050062 | Apr 28 02:59:47 PM PDT 24 | Apr 28 03:01:05 PM PDT 24 | 13488720000 ps | ||
| T31 | /workspace/coverage/default/8.prim_present_test.40446947 | Apr 28 02:59:46 PM PDT 24 | Apr 28 03:00:39 PM PDT 24 | 8160440000 ps | ||
| T32 | /workspace/coverage/default/34.prim_present_test.2869854913 | Apr 28 02:59:55 PM PDT 24 | Apr 28 03:01:08 PM PDT 24 | 9818320000 ps | ||
| T33 | /workspace/coverage/default/15.prim_present_test.3124033307 | Apr 28 02:59:53 PM PDT 24 | Apr 28 03:01:10 PM PDT 24 | 11564240000 ps | ||
| T34 | /workspace/coverage/default/13.prim_present_test.2734346835 | Apr 28 02:59:55 PM PDT 24 | Apr 28 03:00:24 PM PDT 24 | 3989700000 ps | ||
| T35 | /workspace/coverage/default/35.prim_present_test.2525162010 | Apr 28 02:59:52 PM PDT 24 | Apr 28 03:01:10 PM PDT 24 | 10983920000 ps | ||
| T36 | /workspace/coverage/default/12.prim_present_test.3051823407 | Apr 28 02:59:56 PM PDT 24 | Apr 28 03:00:52 PM PDT 24 | 8222440000 ps | ||
| T37 | /workspace/coverage/default/2.prim_present_test.3110066595 | Apr 28 02:59:42 PM PDT 24 | Apr 28 03:00:41 PM PDT 24 | 8822600000 ps | ||
| T38 | /workspace/coverage/default/33.prim_present_test.1446345250 | Apr 28 02:59:57 PM PDT 24 | Apr 28 03:00:20 PM PDT 24 | 3192380000 ps | ||
| T39 | /workspace/coverage/default/22.prim_present_test.388098765 | Apr 28 02:59:54 PM PDT 24 | Apr 28 03:00:23 PM PDT 24 | 3804940000 ps | ||
| T40 | /workspace/coverage/default/29.prim_present_test.4004700872 | Apr 28 02:59:44 PM PDT 24 | Apr 28 03:00:30 PM PDT 24 | 6697860000 ps | ||
| T41 | /workspace/coverage/default/11.prim_present_test.3302271881 | Apr 28 02:59:53 PM PDT 24 | Apr 28 03:00:28 PM PDT 24 | 5509320000 ps | ||
| T42 | /workspace/coverage/default/44.prim_present_test.1016155186 | Apr 28 03:00:05 PM PDT 24 | Apr 28 03:01:44 PM PDT 24 | 14257520000 ps | ||
| T43 | /workspace/coverage/default/45.prim_present_test.1702179400 | Apr 28 02:59:51 PM PDT 24 | Apr 28 03:00:33 PM PDT 24 | 4841580000 ps | ||
| T44 | /workspace/coverage/default/39.prim_present_test.780002385 | Apr 28 02:59:54 PM PDT 24 | Apr 28 03:01:43 PM PDT 24 | 14958740000 ps | ||
| T45 | /workspace/coverage/default/46.prim_present_test.4582100 | Apr 28 02:59:52 PM PDT 24 | Apr 28 03:01:30 PM PDT 24 | 13737340000 ps | ||
| T46 | /workspace/coverage/default/23.prim_present_test.2078567549 | Apr 28 02:59:48 PM PDT 24 | Apr 28 03:01:49 PM PDT 24 | 15076540000 ps | ||
| T47 | /workspace/coverage/default/19.prim_present_test.1019068853 | Apr 28 02:59:42 PM PDT 24 | Apr 28 03:01:09 PM PDT 24 | 12746580000 ps | ||
| T48 | /workspace/coverage/default/21.prim_present_test.3670418744 | Apr 28 02:59:53 PM PDT 24 | Apr 28 03:00:31 PM PDT 24 | 5184440000 ps | ||
| T49 | /workspace/coverage/default/14.prim_present_test.2164104520 | Apr 28 02:59:54 PM PDT 24 | Apr 28 03:01:34 PM PDT 24 | 13458340000 ps | ||
| T50 | /workspace/coverage/default/32.prim_present_test.3972034277 | Apr 28 02:59:41 PM PDT 24 | Apr 28 03:00:34 PM PDT 24 | 8286920000 ps |
| Test location | /workspace/coverage/default/10.prim_present_test.3506622568 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 7047540000 ps |
| CPU time | 23.29 seconds |
| Started | Apr 28 02:59:51 PM PDT 24 |
| Finished | Apr 28 03:00:36 PM PDT 24 |
| Peak memory | 145116 kb |
| Host | smart-86e1d19e-02a7-4a0b-9f51-2a20b99ff8cf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3506622568 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.3506622568 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/0.prim_present_test.4068560085 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 7450540000 ps |
| CPU time | 24.2 seconds |
| Started | Apr 28 02:59:56 PM PDT 24 |
| Finished | Apr 28 03:00:41 PM PDT 24 |
| Peak memory | 145148 kb |
| Host | smart-f928c4bc-cb4a-428a-8393-f46c31862419 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4068560085 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.4068560085 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/1.prim_present_test.1008726337 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 11062040000 ps |
| CPU time | 38.08 seconds |
| Started | Apr 28 02:59:48 PM PDT 24 |
| Finished | Apr 28 03:01:01 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-384e0d63-3efe-41fb-bc4c-9ef82236783d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1008726337 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.1008726337 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/11.prim_present_test.3302271881 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 5509320000 ps |
| CPU time | 18.33 seconds |
| Started | Apr 28 02:59:53 PM PDT 24 |
| Finished | Apr 28 03:00:28 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-32a297d6-cf25-48de-b3ee-b77751b3d116 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3302271881 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.3302271881 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.3051823407 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 8222440000 ps |
| CPU time | 30.05 seconds |
| Started | Apr 28 02:59:56 PM PDT 24 |
| Finished | Apr 28 03:00:52 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-5ca5b2c3-ae57-4212-9608-dd96ed2739a2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3051823407 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.3051823407 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.2734346835 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 3989700000 ps |
| CPU time | 14.96 seconds |
| Started | Apr 28 02:59:55 PM PDT 24 |
| Finished | Apr 28 03:00:24 PM PDT 24 |
| Peak memory | 144944 kb |
| Host | smart-19b6f48b-a0a9-459c-9105-19f44ac18da4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2734346835 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.2734346835 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.2164104520 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 13458340000 ps |
| CPU time | 51.94 seconds |
| Started | Apr 28 02:59:54 PM PDT 24 |
| Finished | Apr 28 03:01:34 PM PDT 24 |
| Peak memory | 145092 kb |
| Host | smart-9580a41f-f7ac-41cb-bf7e-d8d1dd1440f9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2164104520 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.2164104520 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.3124033307 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 11564240000 ps |
| CPU time | 40.06 seconds |
| Started | Apr 28 02:59:53 PM PDT 24 |
| Finished | Apr 28 03:01:10 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-1c3dc9e9-5efb-482e-9925-9ed0c6905494 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3124033307 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.3124033307 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.3789885760 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 14015100000 ps |
| CPU time | 45.94 seconds |
| Started | Apr 28 02:59:45 PM PDT 24 |
| Finished | Apr 28 03:01:12 PM PDT 24 |
| Peak memory | 145120 kb |
| Host | smart-d202a6ff-df58-4785-87c6-eab02ab4b13e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3789885760 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.3789885760 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.4073858297 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 5984240000 ps |
| CPU time | 22.23 seconds |
| Started | Apr 28 02:59:53 PM PDT 24 |
| Finished | Apr 28 03:00:36 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-a9810a72-d099-4756-b216-c524ba6bf0e9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4073858297 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.4073858297 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.2735800734 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 5489480000 ps |
| CPU time | 14.96 seconds |
| Started | Apr 28 02:59:59 PM PDT 24 |
| Finished | Apr 28 03:00:27 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-45d69313-3501-469e-bf08-e167d54d83d9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2735800734 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.2735800734 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.1019068853 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 12746580000 ps |
| CPU time | 45.34 seconds |
| Started | Apr 28 02:59:42 PM PDT 24 |
| Finished | Apr 28 03:01:09 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-b63c17fc-5ecf-45fb-bf85-9b7585c1f7e9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1019068853 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.1019068853 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.3110066595 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 8822600000 ps |
| CPU time | 31.03 seconds |
| Started | Apr 28 02:59:42 PM PDT 24 |
| Finished | Apr 28 03:00:41 PM PDT 24 |
| Peak memory | 145116 kb |
| Host | smart-2db39556-9124-4a88-9cd2-5071b4c111e8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3110066595 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.3110066595 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.288906180 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 14219700000 ps |
| CPU time | 57.36 seconds |
| Started | Apr 28 02:59:47 PM PDT 24 |
| Finished | Apr 28 03:01:37 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-a363f0bb-0c75-4d0e-94b4-4dc4810e6a93 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=288906180 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.288906180 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.3670418744 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 5184440000 ps |
| CPU time | 19.54 seconds |
| Started | Apr 28 02:59:53 PM PDT 24 |
| Finished | Apr 28 03:00:31 PM PDT 24 |
| Peak memory | 145092 kb |
| Host | smart-07d58819-9982-4910-a066-9e0821097de6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3670418744 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.3670418744 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.388098765 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 3804940000 ps |
| CPU time | 14.73 seconds |
| Started | Apr 28 02:59:54 PM PDT 24 |
| Finished | Apr 28 03:00:23 PM PDT 24 |
| Peak memory | 145052 kb |
| Host | smart-8c1a7d62-0d2c-4b02-b0ca-8c3e869891bb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=388098765 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.388098765 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.2078567549 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 15076540000 ps |
| CPU time | 65.31 seconds |
| Started | Apr 28 02:59:48 PM PDT 24 |
| Finished | Apr 28 03:01:49 PM PDT 24 |
| Peak memory | 145200 kb |
| Host | smart-990ab65e-6310-40c0-87ef-b21ac14ac311 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2078567549 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.2078567549 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.2507755236 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 8663880000 ps |
| CPU time | 30.95 seconds |
| Started | Apr 28 02:59:41 PM PDT 24 |
| Finished | Apr 28 03:00:44 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-8f7711e5-c0dd-4b47-9af6-a5f433150fec |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2507755236 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.2507755236 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.1091367313 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 9005500000 ps |
| CPU time | 31.23 seconds |
| Started | Apr 28 02:59:53 PM PDT 24 |
| Finished | Apr 28 03:00:52 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-279b3844-4ec2-44a1-8452-a5cdec688ee3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1091367313 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.1091367313 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.921868428 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 8417740000 ps |
| CPU time | 26.92 seconds |
| Started | Apr 28 02:59:48 PM PDT 24 |
| Finished | Apr 28 03:00:39 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-306fb3e2-5ed7-4c3a-ade7-ab4a9679acea |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=921868428 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.921868428 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.630510057 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 4974260000 ps |
| CPU time | 18.74 seconds |
| Started | Apr 28 02:59:46 PM PDT 24 |
| Finished | Apr 28 03:00:22 PM PDT 24 |
| Peak memory | 145228 kb |
| Host | smart-f1581d9a-8aa4-434b-b7f3-ec27db16696a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=630510057 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.630510057 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.2001754704 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 10734680000 ps |
| CPU time | 35.13 seconds |
| Started | Apr 28 02:59:48 PM PDT 24 |
| Finished | Apr 28 03:00:55 PM PDT 24 |
| Peak memory | 145128 kb |
| Host | smart-408d5a65-ea81-41bc-8011-b15f6207de8b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2001754704 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.2001754704 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.4004700872 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 6697860000 ps |
| CPU time | 24.44 seconds |
| Started | Apr 28 02:59:44 PM PDT 24 |
| Finished | Apr 28 03:00:30 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-41e4e48a-f165-4e39-a77d-662a66679955 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4004700872 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.4004700872 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.1239102232 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 6073520000 ps |
| CPU time | 23.69 seconds |
| Started | Apr 28 02:59:54 PM PDT 24 |
| Finished | Apr 28 03:00:40 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-8bb9d3b1-36df-4bb1-9ca5-923d73177d18 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1239102232 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.1239102232 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.3657061868 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 5734380000 ps |
| CPU time | 20.73 seconds |
| Started | Apr 28 02:59:49 PM PDT 24 |
| Finished | Apr 28 03:00:29 PM PDT 24 |
| Peak memory | 145196 kb |
| Host | smart-436a83f8-2c29-48c0-9878-bd804a0f26d1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3657061868 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.3657061868 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.3147050062 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 13488720000 ps |
| CPU time | 41.24 seconds |
| Started | Apr 28 02:59:47 PM PDT 24 |
| Finished | Apr 28 03:01:05 PM PDT 24 |
| Peak memory | 145144 kb |
| Host | smart-f6de4328-fc70-4671-a03a-ac6cbea0e568 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3147050062 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.3147050062 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.3972034277 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 8286920000 ps |
| CPU time | 26.97 seconds |
| Started | Apr 28 02:59:41 PM PDT 24 |
| Finished | Apr 28 03:00:34 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-d813e559-dc96-4f39-8a6d-f66d530205d9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3972034277 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.3972034277 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.1446345250 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 3192380000 ps |
| CPU time | 11.54 seconds |
| Started | Apr 28 02:59:57 PM PDT 24 |
| Finished | Apr 28 03:00:20 PM PDT 24 |
| Peak memory | 144968 kb |
| Host | smart-c6027945-f571-41fe-bd3b-ed3275083d46 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1446345250 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.1446345250 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.2869854913 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 9818320000 ps |
| CPU time | 36.7 seconds |
| Started | Apr 28 02:59:55 PM PDT 24 |
| Finished | Apr 28 03:01:08 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-3777d253-9af8-4f22-b77a-ee09d6e12b19 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2869854913 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.2869854913 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.2525162010 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 10983920000 ps |
| CPU time | 41.69 seconds |
| Started | Apr 28 02:59:52 PM PDT 24 |
| Finished | Apr 28 03:01:10 PM PDT 24 |
| Peak memory | 145196 kb |
| Host | smart-adc4d5eb-a4bf-4d3f-8f5e-d63e9cd2e341 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2525162010 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.2525162010 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.649092421 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 6669340000 ps |
| CPU time | 24.44 seconds |
| Started | Apr 28 03:00:01 PM PDT 24 |
| Finished | Apr 28 03:00:48 PM PDT 24 |
| Peak memory | 145092 kb |
| Host | smart-ba8f8a94-8ab1-497a-ba73-ed6660c77862 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=649092421 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.649092421 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.374067088 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 5925960000 ps |
| CPU time | 24.59 seconds |
| Started | Apr 28 02:59:56 PM PDT 24 |
| Finished | Apr 28 03:00:43 PM PDT 24 |
| Peak memory | 145124 kb |
| Host | smart-3677ca7b-1335-49b6-8594-e6b035e3ca66 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=374067088 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.374067088 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.3083392525 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 9995020000 ps |
| CPU time | 37 seconds |
| Started | Apr 28 02:59:50 PM PDT 24 |
| Finished | Apr 28 03:00:59 PM PDT 24 |
| Peak memory | 145196 kb |
| Host | smart-63158080-2248-410d-bd5b-d1032108b1ec |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3083392525 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.3083392525 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.780002385 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 14958740000 ps |
| CPU time | 56.17 seconds |
| Started | Apr 28 02:59:54 PM PDT 24 |
| Finished | Apr 28 03:01:43 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-891efb5e-0f99-4f64-9a04-6e478419c792 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=780002385 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.780002385 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.4119287792 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 7318480000 ps |
| CPU time | 23.03 seconds |
| Started | Apr 28 02:59:40 PM PDT 24 |
| Finished | Apr 28 03:00:25 PM PDT 24 |
| Peak memory | 145208 kb |
| Host | smart-ba567d8b-a3ac-4a93-97ac-ab9f96e29bb2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4119287792 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.4119287792 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.3960892980 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 11716140000 ps |
| CPU time | 36.86 seconds |
| Started | Apr 28 03:00:01 PM PDT 24 |
| Finished | Apr 28 03:01:10 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-a5465875-41df-4e17-9309-840ff22bba63 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3960892980 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.3960892980 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.780639640 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 5264420000 ps |
| CPU time | 20.28 seconds |
| Started | Apr 28 02:59:57 PM PDT 24 |
| Finished | Apr 28 03:00:36 PM PDT 24 |
| Peak memory | 145092 kb |
| Host | smart-cc9dff3d-8414-4338-8c7a-d447e890e12e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=780639640 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.780639640 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.815358613 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 11783100000 ps |
| CPU time | 38.65 seconds |
| Started | Apr 28 02:59:57 PM PDT 24 |
| Finished | Apr 28 03:01:11 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-868d9ce6-6f38-45c8-8470-b13e5054edd1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=815358613 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.815358613 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.2854536285 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 5547760000 ps |
| CPU time | 22.18 seconds |
| Started | Apr 28 02:59:53 PM PDT 24 |
| Finished | Apr 28 03:00:36 PM PDT 24 |
| Peak memory | 145124 kb |
| Host | smart-c3a3f412-c9b5-4904-ad58-c6dcc0c5a4b3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2854536285 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.2854536285 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.1016155186 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 14257520000 ps |
| CPU time | 49.95 seconds |
| Started | Apr 28 03:00:05 PM PDT 24 |
| Finished | Apr 28 03:01:44 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-c109d9f3-1a9d-4edf-8142-24bd5b5f9cab |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1016155186 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.1016155186 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.1702179400 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 4841580000 ps |
| CPU time | 21.93 seconds |
| Started | Apr 28 02:59:51 PM PDT 24 |
| Finished | Apr 28 03:00:33 PM PDT 24 |
| Peak memory | 145156 kb |
| Host | smart-840a60ab-eb79-4d76-b133-6dd842486bd7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1702179400 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.1702179400 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.4582100 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 13737340000 ps |
| CPU time | 50.07 seconds |
| Started | Apr 28 02:59:52 PM PDT 24 |
| Finished | Apr 28 03:01:30 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-37990df3-edfd-4818-9664-8e2b445577e9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4582100 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.4582100 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.125601963 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 7601820000 ps |
| CPU time | 25.66 seconds |
| Started | Apr 28 02:59:59 PM PDT 24 |
| Finished | Apr 28 03:00:48 PM PDT 24 |
| Peak memory | 145036 kb |
| Host | smart-3ef46b5e-5c9c-45f5-af23-333e04a39aeb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=125601963 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.125601963 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.4108910502 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 14911000000 ps |
| CPU time | 54.48 seconds |
| Started | Apr 28 03:00:00 PM PDT 24 |
| Finished | Apr 28 03:01:45 PM PDT 24 |
| Peak memory | 145196 kb |
| Host | smart-1e22fa25-334d-43ba-ae63-09e6f0c2d75c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4108910502 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.4108910502 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.2790134897 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 8517560000 ps |
| CPU time | 31.58 seconds |
| Started | Apr 28 02:59:56 PM PDT 24 |
| Finished | Apr 28 03:00:57 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-3799b3bc-32b0-44de-ba0d-6c987ffdcffd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2790134897 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.2790134897 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.1083197837 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 9455620000 ps |
| CPU time | 32.22 seconds |
| Started | Apr 28 02:59:53 PM PDT 24 |
| Finished | Apr 28 03:00:54 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-62aecc81-08ed-4b0a-b71c-4570e4193bbc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1083197837 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.1083197837 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.2118597728 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 10425300000 ps |
| CPU time | 32.46 seconds |
| Started | Apr 28 02:59:44 PM PDT 24 |
| Finished | Apr 28 03:00:44 PM PDT 24 |
| Peak memory | 145204 kb |
| Host | smart-d0b45634-e85f-4245-a21b-f11bad3566e6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2118597728 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.2118597728 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.811140205 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 14912860000 ps |
| CPU time | 53.48 seconds |
| Started | Apr 28 02:59:55 PM PDT 24 |
| Finished | Apr 28 03:01:39 PM PDT 24 |
| Peak memory | 145196 kb |
| Host | smart-95983551-4e74-43f1-b0a2-1acdd3215a1e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=811140205 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.811140205 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.40446947 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 8160440000 ps |
| CPU time | 28.15 seconds |
| Started | Apr 28 02:59:46 PM PDT 24 |
| Finished | Apr 28 03:00:39 PM PDT 24 |
| Peak memory | 145124 kb |
| Host | smart-c9915d1c-cb65-4f63-9a82-dab2b46e172d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=40446947 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.40446947 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.2670821075 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 9118340000 ps |
| CPU time | 30.77 seconds |
| Started | Apr 28 02:59:47 PM PDT 24 |
| Finished | Apr 28 03:00:45 PM PDT 24 |
| Peak memory | 145228 kb |
| Host | smart-796621a0-98a6-42ea-8c0b-0553452e02a0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2670821075 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.2670821075 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |