| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/1.prim_present_test.1012889150 | ||
| Name |
|---|
| /workspace/coverage/default/0.prim_present_test.1462056673 |
| /workspace/coverage/default/10.prim_present_test.3950851035 |
| /workspace/coverage/default/11.prim_present_test.2145714466 |
| /workspace/coverage/default/12.prim_present_test.1773736884 |
| /workspace/coverage/default/13.prim_present_test.1684824006 |
| /workspace/coverage/default/14.prim_present_test.3503164579 |
| /workspace/coverage/default/15.prim_present_test.3863692573 |
| /workspace/coverage/default/16.prim_present_test.243608358 |
| /workspace/coverage/default/17.prim_present_test.887617890 |
| /workspace/coverage/default/18.prim_present_test.2027985259 |
| /workspace/coverage/default/19.prim_present_test.281324221 |
| /workspace/coverage/default/2.prim_present_test.1363129981 |
| /workspace/coverage/default/20.prim_present_test.2575010262 |
| /workspace/coverage/default/21.prim_present_test.3545713967 |
| /workspace/coverage/default/22.prim_present_test.3537296041 |
| /workspace/coverage/default/23.prim_present_test.934824115 |
| /workspace/coverage/default/24.prim_present_test.2941898324 |
| /workspace/coverage/default/25.prim_present_test.2173564646 |
| /workspace/coverage/default/26.prim_present_test.1772385720 |
| /workspace/coverage/default/27.prim_present_test.2287915262 |
| /workspace/coverage/default/28.prim_present_test.825128953 |
| /workspace/coverage/default/29.prim_present_test.3494633594 |
| /workspace/coverage/default/3.prim_present_test.252675730 |
| /workspace/coverage/default/30.prim_present_test.2540915540 |
| /workspace/coverage/default/31.prim_present_test.188115925 |
| /workspace/coverage/default/32.prim_present_test.4065470823 |
| /workspace/coverage/default/33.prim_present_test.2881020632 |
| /workspace/coverage/default/34.prim_present_test.1534816445 |
| /workspace/coverage/default/35.prim_present_test.4033643280 |
| /workspace/coverage/default/36.prim_present_test.1316974656 |
| /workspace/coverage/default/37.prim_present_test.652488433 |
| /workspace/coverage/default/38.prim_present_test.525850576 |
| /workspace/coverage/default/39.prim_present_test.2524279986 |
| /workspace/coverage/default/4.prim_present_test.3156702059 |
| /workspace/coverage/default/40.prim_present_test.2079883600 |
| /workspace/coverage/default/41.prim_present_test.2071599788 |
| /workspace/coverage/default/42.prim_present_test.4289794964 |
| /workspace/coverage/default/43.prim_present_test.3182986691 |
| /workspace/coverage/default/44.prim_present_test.2505428154 |
| /workspace/coverage/default/45.prim_present_test.2850136919 |
| /workspace/coverage/default/46.prim_present_test.554781438 |
| /workspace/coverage/default/47.prim_present_test.3492292740 |
| /workspace/coverage/default/48.prim_present_test.4216794007 |
| /workspace/coverage/default/49.prim_present_test.2415334634 |
| /workspace/coverage/default/5.prim_present_test.246213308 |
| /workspace/coverage/default/6.prim_present_test.2227020210 |
| /workspace/coverage/default/7.prim_present_test.3292864011 |
| /workspace/coverage/default/8.prim_present_test.2551778510 |
| /workspace/coverage/default/9.prim_present_test.453903253 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/7.prim_present_test.3292864011 | Apr 30 12:17:55 PM PDT 24 | Apr 30 12:19:19 PM PDT 24 | 12081320000 ps | ||
| T2 | /workspace/coverage/default/12.prim_present_test.1773736884 | Apr 30 12:22:15 PM PDT 24 | Apr 30 12:23:15 PM PDT 24 | 8686200000 ps | ||
| T3 | /workspace/coverage/default/13.prim_present_test.1684824006 | Apr 30 12:22:03 PM PDT 24 | Apr 30 12:22:37 PM PDT 24 | 5356800000 ps | ||
| T4 | /workspace/coverage/default/38.prim_present_test.525850576 | Apr 30 12:26:38 PM PDT 24 | Apr 30 12:27:49 PM PDT 24 | 11384440000 ps | ||
| T5 | /workspace/coverage/default/23.prim_present_test.934824115 | Apr 30 12:26:31 PM PDT 24 | Apr 30 12:27:55 PM PDT 24 | 13039220000 ps | ||
| T6 | /workspace/coverage/default/30.prim_present_test.2540915540 | Apr 30 12:27:07 PM PDT 24 | Apr 30 12:27:26 PM PDT 24 | 3159520000 ps | ||
| T7 | /workspace/coverage/default/1.prim_present_test.1012889150 | Apr 30 12:18:02 PM PDT 24 | Apr 30 12:18:29 PM PDT 24 | 4284820000 ps | ||
| T8 | /workspace/coverage/default/49.prim_present_test.2415334634 | Apr 30 12:26:39 PM PDT 24 | Apr 30 12:28:03 PM PDT 24 | 12409920000 ps | ||
| T9 | /workspace/coverage/default/17.prim_present_test.887617890 | Apr 30 12:22:02 PM PDT 24 | Apr 30 12:22:57 PM PDT 24 | 7758680000 ps | ||
| T10 | /workspace/coverage/default/19.prim_present_test.281324221 | Apr 30 12:22:06 PM PDT 24 | Apr 30 12:22:35 PM PDT 24 | 4421220000 ps | ||
| T11 | /workspace/coverage/default/26.prim_present_test.1772385720 | Apr 30 12:26:34 PM PDT 24 | Apr 30 12:27:45 PM PDT 24 | 10350280000 ps | ||
| T12 | /workspace/coverage/default/39.prim_present_test.2524279986 | Apr 30 12:26:42 PM PDT 24 | Apr 30 12:27:33 PM PDT 24 | 7463560000 ps | ||
| T13 | /workspace/coverage/default/37.prim_present_test.652488433 | Apr 30 12:26:39 PM PDT 24 | Apr 30 12:27:45 PM PDT 24 | 10364540000 ps | ||
| T14 | /workspace/coverage/default/43.prim_present_test.3182986691 | Apr 30 12:26:41 PM PDT 24 | Apr 30 12:27:54 PM PDT 24 | 12568020000 ps | ||
| T15 | /workspace/coverage/default/9.prim_present_test.453903253 | Apr 30 12:21:56 PM PDT 24 | Apr 30 12:23:21 PM PDT 24 | 14706400000 ps | ||
| T16 | /workspace/coverage/default/14.prim_present_test.3503164579 | Apr 30 12:22:02 PM PDT 24 | Apr 30 12:22:25 PM PDT 24 | 3463940000 ps | ||
| T17 | /workspace/coverage/default/45.prim_present_test.2850136919 | Apr 30 12:26:44 PM PDT 24 | Apr 30 12:28:05 PM PDT 24 | 11417920000 ps | ||
| T18 | /workspace/coverage/default/47.prim_present_test.3492292740 | Apr 30 12:26:46 PM PDT 24 | Apr 30 12:27:46 PM PDT 24 | 7348240000 ps | ||
| T19 | /workspace/coverage/default/0.prim_present_test.1462056673 | Apr 30 12:22:23 PM PDT 24 | Apr 30 12:23:22 PM PDT 24 | 9125160000 ps | ||
| T20 | /workspace/coverage/default/46.prim_present_test.554781438 | Apr 30 12:26:38 PM PDT 24 | Apr 30 12:27:07 PM PDT 24 | 3933280000 ps | ||
| T21 | /workspace/coverage/default/3.prim_present_test.252675730 | Apr 30 12:22:06 PM PDT 24 | Apr 30 12:22:30 PM PDT 24 | 3451540000 ps | ||
| T22 | /workspace/coverage/default/16.prim_present_test.243608358 | Apr 30 12:22:02 PM PDT 24 | Apr 30 12:23:07 PM PDT 24 | 9682540000 ps | ||
| T23 | /workspace/coverage/default/24.prim_present_test.2941898324 | Apr 30 12:26:34 PM PDT 24 | Apr 30 12:27:35 PM PDT 24 | 9625500000 ps | ||
| T24 | /workspace/coverage/default/2.prim_present_test.1363129981 | Apr 30 12:18:06 PM PDT 24 | Apr 30 12:18:39 PM PDT 24 | 4416260000 ps | ||
| T25 | /workspace/coverage/default/40.prim_present_test.2079883600 | Apr 30 12:26:44 PM PDT 24 | Apr 30 12:28:13 PM PDT 24 | 13452140000 ps | ||
| T26 | /workspace/coverage/default/34.prim_present_test.1534816445 | Apr 30 12:26:41 PM PDT 24 | Apr 30 12:27:47 PM PDT 24 | 10353380000 ps | ||
| T27 | /workspace/coverage/default/35.prim_present_test.4033643280 | Apr 30 12:26:39 PM PDT 24 | Apr 30 12:27:30 PM PDT 24 | 7014680000 ps | ||
| T28 | /workspace/coverage/default/18.prim_present_test.2027985259 | Apr 30 12:22:02 PM PDT 24 | Apr 30 12:23:20 PM PDT 24 | 12307000000 ps | ||
| T29 | /workspace/coverage/default/32.prim_present_test.4065470823 | Apr 30 12:26:39 PM PDT 24 | Apr 30 12:28:04 PM PDT 24 | 11328020000 ps | ||
| T30 | /workspace/coverage/default/10.prim_present_test.3950851035 | Apr 30 12:18:45 PM PDT 24 | Apr 30 12:19:18 PM PDT 24 | 4785160000 ps | ||
| T31 | /workspace/coverage/default/31.prim_present_test.188115925 | Apr 30 12:26:41 PM PDT 24 | Apr 30 12:27:16 PM PDT 24 | 5526680000 ps | ||
| T32 | /workspace/coverage/default/42.prim_present_test.4289794964 | Apr 30 12:26:44 PM PDT 24 | Apr 30 12:27:37 PM PDT 24 | 6860920000 ps | ||
| T33 | /workspace/coverage/default/5.prim_present_test.246213308 | Apr 30 12:22:06 PM PDT 24 | Apr 30 12:23:26 PM PDT 24 | 13733620000 ps | ||
| T34 | /workspace/coverage/default/11.prim_present_test.2145714466 | Apr 30 12:17:55 PM PDT 24 | Apr 30 12:18:58 PM PDT 24 | 8640940000 ps | ||
| T35 | /workspace/coverage/default/29.prim_present_test.3494633594 | Apr 30 12:27:12 PM PDT 24 | Apr 30 12:28:40 PM PDT 24 | 15433660000 ps | ||
| T36 | /workspace/coverage/default/33.prim_present_test.2881020632 | Apr 30 12:26:41 PM PDT 24 | Apr 30 12:27:24 PM PDT 24 | 6487680000 ps | ||
| T37 | /workspace/coverage/default/44.prim_present_test.2505428154 | Apr 30 12:26:41 PM PDT 24 | Apr 30 12:27:13 PM PDT 24 | 4747960000 ps | ||
| T38 | /workspace/coverage/default/27.prim_present_test.2287915262 | Apr 30 12:26:30 PM PDT 24 | Apr 30 12:28:13 PM PDT 24 | 13724940000 ps | ||
| T39 | /workspace/coverage/default/25.prim_present_test.2173564646 | Apr 30 12:26:31 PM PDT 24 | Apr 30 12:27:30 PM PDT 24 | 8420840000 ps | ||
| T40 | /workspace/coverage/default/15.prim_present_test.3863692573 | Apr 30 12:22:05 PM PDT 24 | Apr 30 12:23:08 PM PDT 24 | 10275880000 ps | ||
| T41 | /workspace/coverage/default/48.prim_present_test.4216794007 | Apr 30 12:26:39 PM PDT 24 | Apr 30 12:28:08 PM PDT 24 | 10278980000 ps | ||
| T42 | /workspace/coverage/default/28.prim_present_test.825128953 | Apr 30 12:26:34 PM PDT 24 | Apr 30 12:27:04 PM PDT 24 | 3876240000 ps | ||
| T43 | /workspace/coverage/default/22.prim_present_test.3537296041 | Apr 30 12:26:37 PM PDT 24 | Apr 30 12:27:53 PM PDT 24 | 12520280000 ps | ||
| T44 | /workspace/coverage/default/41.prim_present_test.2071599788 | Apr 30 12:26:38 PM PDT 24 | Apr 30 12:27:07 PM PDT 24 | 3584840000 ps | ||
| T45 | /workspace/coverage/default/4.prim_present_test.3156702059 | Apr 30 12:18:20 PM PDT 24 | Apr 30 12:19:13 PM PDT 24 | 8861660000 ps | ||
| T46 | /workspace/coverage/default/21.prim_present_test.3545713967 | Apr 30 12:26:32 PM PDT 24 | Apr 30 12:27:31 PM PDT 24 | 8303660000 ps | ||
| T47 | /workspace/coverage/default/36.prim_present_test.1316974656 | Apr 30 12:26:43 PM PDT 24 | Apr 30 12:27:16 PM PDT 24 | 4492520000 ps | ||
| T48 | /workspace/coverage/default/8.prim_present_test.2551778510 | Apr 30 12:22:01 PM PDT 24 | Apr 30 12:23:32 PM PDT 24 | 14423060000 ps | ||
| T49 | /workspace/coverage/default/20.prim_present_test.2575010262 | Apr 30 12:26:33 PM PDT 24 | Apr 30 12:27:29 PM PDT 24 | 8698600000 ps | ||
| T50 | /workspace/coverage/default/6.prim_present_test.2227020210 | Apr 30 12:18:46 PM PDT 24 | Apr 30 12:19:39 PM PDT 24 | 8051320000 ps |
| Test location | /workspace/coverage/default/1.prim_present_test.1012889150 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4284820000 ps |
| CPU time | 14.43 seconds |
| Started | Apr 30 12:18:02 PM PDT 24 |
| Finished | Apr 30 12:18:29 PM PDT 24 |
| Peak memory | 145064 kb |
| Host | smart-288322b9-9fac-4da8-90f8-b4289bb29cf4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1012889150 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.1012889150 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/0.prim_present_test.1462056673 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 9125160000 ps |
| CPU time | 31.15 seconds |
| Started | Apr 30 12:22:23 PM PDT 24 |
| Finished | Apr 30 12:23:22 PM PDT 24 |
| Peak memory | 144984 kb |
| Host | smart-df37b951-aca3-4f0f-88ff-d4913a6ae9d8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1462056673 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.1462056673 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/10.prim_present_test.3950851035 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 4785160000 ps |
| CPU time | 17.24 seconds |
| Started | Apr 30 12:18:45 PM PDT 24 |
| Finished | Apr 30 12:19:18 PM PDT 24 |
| Peak memory | 145232 kb |
| Host | smart-b06d2a02-2d44-4597-823a-c18f95a96fa0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3950851035 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.3950851035 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/11.prim_present_test.2145714466 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 8640940000 ps |
| CPU time | 32.47 seconds |
| Started | Apr 30 12:17:55 PM PDT 24 |
| Finished | Apr 30 12:18:58 PM PDT 24 |
| Peak memory | 145028 kb |
| Host | smart-b35ebfcd-f6a5-407a-b04b-c4190232b42b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2145714466 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.2145714466 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.1773736884 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 8686200000 ps |
| CPU time | 30.86 seconds |
| Started | Apr 30 12:22:15 PM PDT 24 |
| Finished | Apr 30 12:23:15 PM PDT 24 |
| Peak memory | 144756 kb |
| Host | smart-fe8261e3-5e1e-4cfe-bbde-7eadebddacf8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1773736884 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.1773736884 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.1684824006 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 5356800000 ps |
| CPU time | 17.59 seconds |
| Started | Apr 30 12:22:03 PM PDT 24 |
| Finished | Apr 30 12:22:37 PM PDT 24 |
| Peak memory | 144936 kb |
| Host | smart-881cef96-d066-426a-9b3b-a50a85fa6636 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1684824006 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.1684824006 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.3503164579 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 3463940000 ps |
| CPU time | 12.36 seconds |
| Started | Apr 30 12:22:02 PM PDT 24 |
| Finished | Apr 30 12:22:25 PM PDT 24 |
| Peak memory | 144328 kb |
| Host | smart-4c20d4c7-14fd-4d91-988c-6996ee4d5744 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3503164579 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.3503164579 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.3863692573 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 10275880000 ps |
| CPU time | 33.1 seconds |
| Started | Apr 30 12:22:05 PM PDT 24 |
| Finished | Apr 30 12:23:08 PM PDT 24 |
| Peak memory | 144724 kb |
| Host | smart-821043b7-733f-41c8-9369-034122e813be |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3863692573 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.3863692573 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.243608358 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 9682540000 ps |
| CPU time | 35.01 seconds |
| Started | Apr 30 12:22:02 PM PDT 24 |
| Finished | Apr 30 12:23:07 PM PDT 24 |
| Peak memory | 143604 kb |
| Host | smart-e3d74630-df18-4b97-b8bb-5f022559e9fe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=243608358 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.243608358 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.887617890 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 7758680000 ps |
| CPU time | 28.38 seconds |
| Started | Apr 30 12:22:02 PM PDT 24 |
| Finished | Apr 30 12:22:57 PM PDT 24 |
| Peak memory | 144764 kb |
| Host | smart-a4e99a9b-03cd-4a7c-88f9-19887ec523b7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=887617890 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.887617890 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.2027985259 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 12307000000 ps |
| CPU time | 41.87 seconds |
| Started | Apr 30 12:22:02 PM PDT 24 |
| Finished | Apr 30 12:23:20 PM PDT 24 |
| Peak memory | 144764 kb |
| Host | smart-e4af42aa-dbf6-49be-b050-e9b2602a8493 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2027985259 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.2027985259 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.281324221 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 4421220000 ps |
| CPU time | 15.37 seconds |
| Started | Apr 30 12:22:06 PM PDT 24 |
| Finished | Apr 30 12:22:35 PM PDT 24 |
| Peak memory | 144836 kb |
| Host | smart-f3e8ab5a-1c4e-4bca-acca-25d0efc1cf2e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=281324221 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.281324221 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.1363129981 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 4416260000 ps |
| CPU time | 17.01 seconds |
| Started | Apr 30 12:18:06 PM PDT 24 |
| Finished | Apr 30 12:18:39 PM PDT 24 |
| Peak memory | 145020 kb |
| Host | smart-0557cae7-a0a9-42cf-b7c0-3fd02d94ef38 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1363129981 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.1363129981 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.2575010262 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 8698600000 ps |
| CPU time | 28.99 seconds |
| Started | Apr 30 12:26:33 PM PDT 24 |
| Finished | Apr 30 12:27:29 PM PDT 24 |
| Peak memory | 145048 kb |
| Host | smart-08920990-0256-462b-8a47-15e98fa954e5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2575010262 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.2575010262 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.3545713967 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 8303660000 ps |
| CPU time | 31.5 seconds |
| Started | Apr 30 12:26:32 PM PDT 24 |
| Finished | Apr 30 12:27:31 PM PDT 24 |
| Peak memory | 144956 kb |
| Host | smart-ce1c3a7e-6dd6-4bf4-b1d2-c82eef8e99d8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3545713967 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.3545713967 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.3537296041 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 12520280000 ps |
| CPU time | 41 seconds |
| Started | Apr 30 12:26:37 PM PDT 24 |
| Finished | Apr 30 12:27:53 PM PDT 24 |
| Peak memory | 145084 kb |
| Host | smart-648fe41c-08f2-42ff-97d1-00bd1bc308c1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3537296041 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.3537296041 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.934824115 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 13039220000 ps |
| CPU time | 43.15 seconds |
| Started | Apr 30 12:26:31 PM PDT 24 |
| Finished | Apr 30 12:27:55 PM PDT 24 |
| Peak memory | 145140 kb |
| Host | smart-0557a498-deb9-4dbb-8a6e-fd54d67c5464 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=934824115 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.934824115 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.2941898324 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 9625500000 ps |
| CPU time | 32.23 seconds |
| Started | Apr 30 12:26:34 PM PDT 24 |
| Finished | Apr 30 12:27:35 PM PDT 24 |
| Peak memory | 145068 kb |
| Host | smart-6d1e5644-2f2d-4b0d-b257-82652aee0472 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2941898324 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.2941898324 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.2173564646 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 8420840000 ps |
| CPU time | 31.33 seconds |
| Started | Apr 30 12:26:31 PM PDT 24 |
| Finished | Apr 30 12:27:30 PM PDT 24 |
| Peak memory | 145068 kb |
| Host | smart-1e961253-7974-46e4-beec-fe09fe4f6ca2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2173564646 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.2173564646 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.1772385720 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 10350280000 ps |
| CPU time | 37.42 seconds |
| Started | Apr 30 12:26:34 PM PDT 24 |
| Finished | Apr 30 12:27:45 PM PDT 24 |
| Peak memory | 145088 kb |
| Host | smart-bf6801dc-1740-45d3-8e4f-dfa0620e8945 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1772385720 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.1772385720 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.2287915262 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 13724940000 ps |
| CPU time | 53.97 seconds |
| Started | Apr 30 12:26:30 PM PDT 24 |
| Finished | Apr 30 12:28:13 PM PDT 24 |
| Peak memory | 145052 kb |
| Host | smart-9267552b-1e6d-45b4-a6a1-fcdef5494340 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2287915262 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.2287915262 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.825128953 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 3876240000 ps |
| CPU time | 15.37 seconds |
| Started | Apr 30 12:26:34 PM PDT 24 |
| Finished | Apr 30 12:27:04 PM PDT 24 |
| Peak memory | 144928 kb |
| Host | smart-c262b785-a1df-476e-9426-815b81b3a56c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=825128953 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.825128953 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.3494633594 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 15433660000 ps |
| CPU time | 48.21 seconds |
| Started | Apr 30 12:27:12 PM PDT 24 |
| Finished | Apr 30 12:28:40 PM PDT 24 |
| Peak memory | 144820 kb |
| Host | smart-b6de9791-4241-4760-8266-218ec94efd9f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3494633594 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.3494633594 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.252675730 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 3451540000 ps |
| CPU time | 12.29 seconds |
| Started | Apr 30 12:22:06 PM PDT 24 |
| Finished | Apr 30 12:22:30 PM PDT 24 |
| Peak memory | 144696 kb |
| Host | smart-6e365721-edba-47e7-8573-99da73ad5783 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=252675730 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.252675730 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.2540915540 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 3159520000 ps |
| CPU time | 9.68 seconds |
| Started | Apr 30 12:27:07 PM PDT 24 |
| Finished | Apr 30 12:27:26 PM PDT 24 |
| Peak memory | 144872 kb |
| Host | smart-b17c487e-501d-4e4a-ae8e-7e2c66035759 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2540915540 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.2540915540 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.188115925 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 5526680000 ps |
| CPU time | 18.73 seconds |
| Started | Apr 30 12:26:41 PM PDT 24 |
| Finished | Apr 30 12:27:16 PM PDT 24 |
| Peak memory | 145016 kb |
| Host | smart-8b5084d5-120f-4a78-a5a1-0123274ce8be |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=188115925 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.188115925 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.4065470823 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 11328020000 ps |
| CPU time | 43.68 seconds |
| Started | Apr 30 12:26:39 PM PDT 24 |
| Finished | Apr 30 12:28:04 PM PDT 24 |
| Peak memory | 145072 kb |
| Host | smart-915031eb-eac8-49f1-9fd9-e63dddb1ffb2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4065470823 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.4065470823 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.2881020632 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 6487680000 ps |
| CPU time | 22.88 seconds |
| Started | Apr 30 12:26:41 PM PDT 24 |
| Finished | Apr 30 12:27:24 PM PDT 24 |
| Peak memory | 145072 kb |
| Host | smart-99e0f1ed-f35c-4742-812e-683365069ae2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2881020632 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.2881020632 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.1534816445 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 10353380000 ps |
| CPU time | 34.94 seconds |
| Started | Apr 30 12:26:41 PM PDT 24 |
| Finished | Apr 30 12:27:47 PM PDT 24 |
| Peak memory | 145068 kb |
| Host | smart-276adcd4-c54e-46c2-bf38-9fc1466f0c8c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1534816445 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.1534816445 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.4033643280 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 7014680000 ps |
| CPU time | 26.16 seconds |
| Started | Apr 30 12:26:39 PM PDT 24 |
| Finished | Apr 30 12:27:30 PM PDT 24 |
| Peak memory | 144964 kb |
| Host | smart-49f73ede-933a-45f4-8526-da67a35e999c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4033643280 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.4033643280 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.1316974656 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 4492520000 ps |
| CPU time | 17.11 seconds |
| Started | Apr 30 12:26:43 PM PDT 24 |
| Finished | Apr 30 12:27:16 PM PDT 24 |
| Peak memory | 145048 kb |
| Host | smart-5e7d9c7a-5ea2-4259-af2a-df9348e686b5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1316974656 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.1316974656 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.652488433 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 10364540000 ps |
| CPU time | 34.94 seconds |
| Started | Apr 30 12:26:39 PM PDT 24 |
| Finished | Apr 30 12:27:45 PM PDT 24 |
| Peak memory | 145268 kb |
| Host | smart-181faa85-6aeb-42c8-bec6-e8a49af78712 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=652488433 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.652488433 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.525850576 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 11384440000 ps |
| CPU time | 37.52 seconds |
| Started | Apr 30 12:26:38 PM PDT 24 |
| Finished | Apr 30 12:27:49 PM PDT 24 |
| Peak memory | 145016 kb |
| Host | smart-b4e866aa-c9ad-40ef-a674-9b5509ffb7e5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=525850576 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.525850576 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.2524279986 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 7463560000 ps |
| CPU time | 27.2 seconds |
| Started | Apr 30 12:26:42 PM PDT 24 |
| Finished | Apr 30 12:27:33 PM PDT 24 |
| Peak memory | 145068 kb |
| Host | smart-2d157c80-8359-42a6-98ca-005a44a1eb81 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2524279986 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.2524279986 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.3156702059 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 8861660000 ps |
| CPU time | 28.34 seconds |
| Started | Apr 30 12:18:20 PM PDT 24 |
| Finished | Apr 30 12:19:13 PM PDT 24 |
| Peak memory | 144796 kb |
| Host | smart-a3b591a4-5678-4cb4-a5a4-de9590c97395 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3156702059 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.3156702059 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.2079883600 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 13452140000 ps |
| CPU time | 46.98 seconds |
| Started | Apr 30 12:26:44 PM PDT 24 |
| Finished | Apr 30 12:28:13 PM PDT 24 |
| Peak memory | 144972 kb |
| Host | smart-5672dad8-ead7-4790-8034-ee9f2291bc86 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2079883600 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.2079883600 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.2071599788 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 3584840000 ps |
| CPU time | 15.32 seconds |
| Started | Apr 30 12:26:38 PM PDT 24 |
| Finished | Apr 30 12:27:07 PM PDT 24 |
| Peak memory | 145056 kb |
| Host | smart-053f3a3a-8d54-4132-8985-7923bed5d288 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2071599788 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.2071599788 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.4289794964 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 6860920000 ps |
| CPU time | 27.75 seconds |
| Started | Apr 30 12:26:44 PM PDT 24 |
| Finished | Apr 30 12:27:37 PM PDT 24 |
| Peak memory | 145044 kb |
| Host | smart-c57c1ec6-195e-45af-87b9-8b9197b89237 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4289794964 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.4289794964 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.3182986691 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 12568020000 ps |
| CPU time | 39.28 seconds |
| Started | Apr 30 12:26:41 PM PDT 24 |
| Finished | Apr 30 12:27:54 PM PDT 24 |
| Peak memory | 145036 kb |
| Host | smart-a05ffc80-990e-4461-86a8-354cc6fc709d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3182986691 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.3182986691 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.2505428154 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 4747960000 ps |
| CPU time | 16.88 seconds |
| Started | Apr 30 12:26:41 PM PDT 24 |
| Finished | Apr 30 12:27:13 PM PDT 24 |
| Peak memory | 145072 kb |
| Host | smart-681e5b4e-6984-4644-b5e7-74cf8439dbb1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2505428154 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.2505428154 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.2850136919 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 11417920000 ps |
| CPU time | 42.62 seconds |
| Started | Apr 30 12:26:44 PM PDT 24 |
| Finished | Apr 30 12:28:05 PM PDT 24 |
| Peak memory | 144980 kb |
| Host | smart-f68ec542-7a36-49bb-b338-810a98e61911 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2850136919 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.2850136919 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.554781438 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 3933280000 ps |
| CPU time | 15.1 seconds |
| Started | Apr 30 12:26:38 PM PDT 24 |
| Finished | Apr 30 12:27:07 PM PDT 24 |
| Peak memory | 144924 kb |
| Host | smart-f5716d65-4b32-4d8f-bcdb-543d0a8abf94 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=554781438 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.554781438 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.3492292740 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 7348240000 ps |
| CPU time | 31.95 seconds |
| Started | Apr 30 12:26:46 PM PDT 24 |
| Finished | Apr 30 12:27:46 PM PDT 24 |
| Peak memory | 145060 kb |
| Host | smart-7b503d5d-8938-4dd2-89c7-6615446fb459 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3492292740 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.3492292740 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.4216794007 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 10278980000 ps |
| CPU time | 44.75 seconds |
| Started | Apr 30 12:26:39 PM PDT 24 |
| Finished | Apr 30 12:28:08 PM PDT 24 |
| Peak memory | 145000 kb |
| Host | smart-353869fa-8625-4478-8537-61e33cc530a2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4216794007 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.4216794007 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.2415334634 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 12409920000 ps |
| CPU time | 44.64 seconds |
| Started | Apr 30 12:26:39 PM PDT 24 |
| Finished | Apr 30 12:28:03 PM PDT 24 |
| Peak memory | 144964 kb |
| Host | smart-13e5a611-3f28-4d27-b6e5-0145dd359399 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2415334634 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.2415334634 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.246213308 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 13733620000 ps |
| CPU time | 43.06 seconds |
| Started | Apr 30 12:22:06 PM PDT 24 |
| Finished | Apr 30 12:23:26 PM PDT 24 |
| Peak memory | 144840 kb |
| Host | smart-f9945a74-1c40-452d-9a4f-2906da7e6490 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=246213308 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.246213308 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.2227020210 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 8051320000 ps |
| CPU time | 27.8 seconds |
| Started | Apr 30 12:18:46 PM PDT 24 |
| Finished | Apr 30 12:19:39 PM PDT 24 |
| Peak memory | 145020 kb |
| Host | smart-dbe9d715-cb7e-454c-9266-ac09b7327522 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2227020210 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.2227020210 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.3292864011 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 12081320000 ps |
| CPU time | 43.62 seconds |
| Started | Apr 30 12:17:55 PM PDT 24 |
| Finished | Apr 30 12:19:19 PM PDT 24 |
| Peak memory | 145020 kb |
| Host | smart-5e832e12-cc2d-4b11-ba1a-3b8f91a4ad57 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3292864011 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.3292864011 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.2551778510 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 14423060000 ps |
| CPU time | 48.97 seconds |
| Started | Apr 30 12:22:01 PM PDT 24 |
| Finished | Apr 30 12:23:32 PM PDT 24 |
| Peak memory | 144012 kb |
| Host | smart-0252f201-efca-49ac-95fc-6c3733ca357d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2551778510 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.2551778510 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.453903253 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 14706400000 ps |
| CPU time | 45.87 seconds |
| Started | Apr 30 12:21:56 PM PDT 24 |
| Finished | Apr 30 12:23:21 PM PDT 24 |
| Peak memory | 144008 kb |
| Host | smart-2653dd92-629a-4a11-9dc4-e6487d57fe67 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=453903253 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.453903253 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |