| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/10.prim_present_test.3372451217 | ||
| Name |
|---|
| /workspace/coverage/default/0.prim_present_test.1376208479 |
| /workspace/coverage/default/1.prim_present_test.1787172441 |
| /workspace/coverage/default/11.prim_present_test.4281858770 |
| /workspace/coverage/default/12.prim_present_test.2738425195 |
| /workspace/coverage/default/13.prim_present_test.250197496 |
| /workspace/coverage/default/14.prim_present_test.2068500035 |
| /workspace/coverage/default/15.prim_present_test.4095300361 |
| /workspace/coverage/default/16.prim_present_test.1769596955 |
| /workspace/coverage/default/17.prim_present_test.695306777 |
| /workspace/coverage/default/18.prim_present_test.3582014393 |
| /workspace/coverage/default/19.prim_present_test.3596219213 |
| /workspace/coverage/default/2.prim_present_test.986930710 |
| /workspace/coverage/default/20.prim_present_test.2257100388 |
| /workspace/coverage/default/21.prim_present_test.1848936331 |
| /workspace/coverage/default/22.prim_present_test.487847356 |
| /workspace/coverage/default/23.prim_present_test.352713376 |
| /workspace/coverage/default/24.prim_present_test.4271373503 |
| /workspace/coverage/default/25.prim_present_test.4110726210 |
| /workspace/coverage/default/26.prim_present_test.635504601 |
| /workspace/coverage/default/27.prim_present_test.3103428271 |
| /workspace/coverage/default/28.prim_present_test.1949631150 |
| /workspace/coverage/default/29.prim_present_test.2915726766 |
| /workspace/coverage/default/3.prim_present_test.1882864440 |
| /workspace/coverage/default/30.prim_present_test.2865323784 |
| /workspace/coverage/default/31.prim_present_test.707483983 |
| /workspace/coverage/default/32.prim_present_test.3368592635 |
| /workspace/coverage/default/33.prim_present_test.229463416 |
| /workspace/coverage/default/34.prim_present_test.3064422697 |
| /workspace/coverage/default/35.prim_present_test.1938571520 |
| /workspace/coverage/default/36.prim_present_test.3555397565 |
| /workspace/coverage/default/37.prim_present_test.2877665674 |
| /workspace/coverage/default/38.prim_present_test.2525094803 |
| /workspace/coverage/default/39.prim_present_test.1551916272 |
| /workspace/coverage/default/4.prim_present_test.1040098775 |
| /workspace/coverage/default/40.prim_present_test.2465038968 |
| /workspace/coverage/default/41.prim_present_test.1009103713 |
| /workspace/coverage/default/42.prim_present_test.817779671 |
| /workspace/coverage/default/43.prim_present_test.3888903171 |
| /workspace/coverage/default/44.prim_present_test.1018350048 |
| /workspace/coverage/default/45.prim_present_test.2351791787 |
| /workspace/coverage/default/46.prim_present_test.3156990269 |
| /workspace/coverage/default/47.prim_present_test.161916732 |
| /workspace/coverage/default/48.prim_present_test.2166959252 |
| /workspace/coverage/default/49.prim_present_test.2513766812 |
| /workspace/coverage/default/5.prim_present_test.3891381426 |
| /workspace/coverage/default/6.prim_present_test.558195499 |
| /workspace/coverage/default/7.prim_present_test.1141432665 |
| /workspace/coverage/default/8.prim_present_test.1549742147 |
| /workspace/coverage/default/9.prim_present_test.2352168167 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/44.prim_present_test.1018350048 | May 02 02:06:17 PM PDT 24 | May 02 02:06:41 PM PDT 24 | 3180600000 ps | ||
| T2 | /workspace/coverage/default/46.prim_present_test.3156990269 | May 02 02:06:16 PM PDT 24 | May 02 02:06:53 PM PDT 24 | 4352400000 ps | ||
| T3 | /workspace/coverage/default/10.prim_present_test.3372451217 | May 02 02:06:16 PM PDT 24 | May 02 02:06:55 PM PDT 24 | 4181900000 ps | ||
| T4 | /workspace/coverage/default/18.prim_present_test.3582014393 | May 02 02:06:06 PM PDT 24 | May 02 02:07:52 PM PDT 24 | 13701380000 ps | ||
| T5 | /workspace/coverage/default/40.prim_present_test.2465038968 | May 02 02:06:16 PM PDT 24 | May 02 02:07:21 PM PDT 24 | 8030240000 ps | ||
| T6 | /workspace/coverage/default/7.prim_present_test.1141432665 | May 02 02:06:01 PM PDT 24 | May 02 02:07:02 PM PDT 24 | 8012260000 ps | ||
| T7 | /workspace/coverage/default/45.prim_present_test.2351791787 | May 02 02:06:16 PM PDT 24 | May 02 02:07:16 PM PDT 24 | 7586940000 ps | ||
| T8 | /workspace/coverage/default/33.prim_present_test.229463416 | May 02 02:06:07 PM PDT 24 | May 02 02:06:56 PM PDT 24 | 7363120000 ps | ||
| T9 | /workspace/coverage/default/16.prim_present_test.1769596955 | May 02 02:06:07 PM PDT 24 | May 02 02:07:41 PM PDT 24 | 12501060000 ps | ||
| T10 | /workspace/coverage/default/35.prim_present_test.1938571520 | May 02 02:06:16 PM PDT 24 | May 02 02:07:17 PM PDT 24 | 8991240000 ps | ||
| T11 | /workspace/coverage/default/15.prim_present_test.4095300361 | May 02 02:06:08 PM PDT 24 | May 02 02:06:42 PM PDT 24 | 4648140000 ps | ||
| T12 | /workspace/coverage/default/11.prim_present_test.4281858770 | May 02 02:06:05 PM PDT 24 | May 02 02:07:11 PM PDT 24 | 9835680000 ps | ||
| T13 | /workspace/coverage/default/29.prim_present_test.2915726766 | May 02 02:06:11 PM PDT 24 | May 02 02:08:05 PM PDT 24 | 13797480000 ps | ||
| T14 | /workspace/coverage/default/25.prim_present_test.4110726210 | May 02 02:06:10 PM PDT 24 | May 02 02:07:00 PM PDT 24 | 6222320000 ps | ||
| T15 | /workspace/coverage/default/32.prim_present_test.3368592635 | May 02 02:06:10 PM PDT 24 | May 02 02:08:03 PM PDT 24 | 15005240000 ps | ||
| T16 | /workspace/coverage/default/21.prim_present_test.1848936331 | May 02 02:06:09 PM PDT 24 | May 02 02:07:10 PM PDT 24 | 8037680000 ps | ||
| T17 | /workspace/coverage/default/0.prim_present_test.1376208479 | May 02 02:06:03 PM PDT 24 | May 02 02:06:55 PM PDT 24 | 5748020000 ps | ||
| T18 | /workspace/coverage/default/20.prim_present_test.2257100388 | May 02 02:06:08 PM PDT 24 | May 02 02:07:01 PM PDT 24 | 7164100000 ps | ||
| T19 | /workspace/coverage/default/49.prim_present_test.2513766812 | May 02 02:06:17 PM PDT 24 | May 02 02:06:49 PM PDT 24 | 4214140000 ps | ||
| T20 | /workspace/coverage/default/5.prim_present_test.3891381426 | May 02 02:06:01 PM PDT 24 | May 02 02:08:02 PM PDT 24 | 14511100000 ps | ||
| T21 | /workspace/coverage/default/36.prim_present_test.3555397565 | May 02 02:06:18 PM PDT 24 | May 02 02:08:09 PM PDT 24 | 13568700000 ps | ||
| T22 | /workspace/coverage/default/48.prim_present_test.2166959252 | May 02 02:06:17 PM PDT 24 | May 02 02:06:45 PM PDT 24 | 3630100000 ps | ||
| T23 | /workspace/coverage/default/38.prim_present_test.2525094803 | May 02 02:06:16 PM PDT 24 | May 02 02:06:48 PM PDT 24 | 3343660000 ps | ||
| T24 | /workspace/coverage/default/28.prim_present_test.1949631150 | May 02 02:06:09 PM PDT 24 | May 02 02:07:18 PM PDT 24 | 8173460000 ps | ||
| T25 | /workspace/coverage/default/2.prim_present_test.986930710 | May 02 02:06:03 PM PDT 24 | May 02 02:06:57 PM PDT 24 | 7071720000 ps | ||
| T26 | /workspace/coverage/default/19.prim_present_test.3596219213 | May 02 02:06:09 PM PDT 24 | May 02 02:06:42 PM PDT 24 | 3778900000 ps | ||
| T27 | /workspace/coverage/default/14.prim_present_test.2068500035 | May 02 02:06:06 PM PDT 24 | May 02 02:06:35 PM PDT 24 | 4561340000 ps | ||
| T28 | /workspace/coverage/default/34.prim_present_test.3064422697 | May 02 02:06:07 PM PDT 24 | May 02 02:06:50 PM PDT 24 | 6091500000 ps | ||
| T29 | /workspace/coverage/default/39.prim_present_test.1551916272 | May 02 02:06:16 PM PDT 24 | May 02 02:06:50 PM PDT 24 | 4470200000 ps | ||
| T30 | /workspace/coverage/default/6.prim_present_test.558195499 | May 02 02:06:00 PM PDT 24 | May 02 02:07:49 PM PDT 24 | 14503660000 ps | ||
| T31 | /workspace/coverage/default/8.prim_present_test.1549742147 | May 02 02:06:16 PM PDT 24 | May 02 02:07:59 PM PDT 24 | 12800520000 ps | ||
| T32 | /workspace/coverage/default/41.prim_present_test.1009103713 | May 02 02:06:15 PM PDT 24 | May 02 02:07:01 PM PDT 24 | 6160940000 ps | ||
| T33 | /workspace/coverage/default/9.prim_present_test.2352168167 | May 02 02:06:11 PM PDT 24 | May 02 02:06:45 PM PDT 24 | 3946920000 ps | ||
| T34 | /workspace/coverage/default/37.prim_present_test.2877665674 | May 02 02:06:17 PM PDT 24 | May 02 02:07:22 PM PDT 24 | 8962720000 ps | ||
| T35 | /workspace/coverage/default/31.prim_present_test.707483983 | May 02 02:06:10 PM PDT 24 | May 02 02:07:54 PM PDT 24 | 12772000000 ps | ||
| T36 | /workspace/coverage/default/24.prim_present_test.4271373503 | May 02 02:06:10 PM PDT 24 | May 02 02:06:46 PM PDT 24 | 4297840000 ps | ||
| T37 | /workspace/coverage/default/43.prim_present_test.3888903171 | May 02 02:06:17 PM PDT 24 | May 02 02:07:32 PM PDT 24 | 10336020000 ps | ||
| T38 | /workspace/coverage/default/17.prim_present_test.695306777 | May 02 02:06:10 PM PDT 24 | May 02 02:06:57 PM PDT 24 | 5963160000 ps | ||
| T39 | /workspace/coverage/default/1.prim_present_test.1787172441 | May 02 02:06:02 PM PDT 24 | May 02 02:07:24 PM PDT 24 | 9499020000 ps | ||
| T40 | /workspace/coverage/default/3.prim_present_test.1882864440 | May 02 02:06:01 PM PDT 24 | May 02 02:07:46 PM PDT 24 | 13884900000 ps | ||
| T41 | /workspace/coverage/default/26.prim_present_test.635504601 | May 02 02:06:08 PM PDT 24 | May 02 02:06:56 PM PDT 24 | 5945180000 ps | ||
| T42 | /workspace/coverage/default/23.prim_present_test.352713376 | May 02 02:06:07 PM PDT 24 | May 02 02:07:53 PM PDT 24 | 14581780000 ps | ||
| T43 | /workspace/coverage/default/13.prim_present_test.250197496 | May 02 02:06:10 PM PDT 24 | May 02 02:08:01 PM PDT 24 | 15443580000 ps | ||
| T44 | /workspace/coverage/default/12.prim_present_test.2738425195 | May 02 02:06:10 PM PDT 24 | May 02 02:08:06 PM PDT 24 | 14126080000 ps | ||
| T45 | /workspace/coverage/default/4.prim_present_test.1040098775 | May 02 02:06:01 PM PDT 24 | May 02 02:07:35 PM PDT 24 | 12532680000 ps | ||
| T46 | /workspace/coverage/default/22.prim_present_test.487847356 | May 02 02:06:06 PM PDT 24 | May 02 02:07:14 PM PDT 24 | 8879020000 ps | ||
| T47 | /workspace/coverage/default/30.prim_present_test.2865323784 | May 02 02:06:05 PM PDT 24 | May 02 02:07:35 PM PDT 24 | 13496160000 ps | ||
| T48 | /workspace/coverage/default/27.prim_present_test.3103428271 | May 02 02:06:06 PM PDT 24 | May 02 02:06:53 PM PDT 24 | 6694760000 ps | ||
| T49 | /workspace/coverage/default/47.prim_present_test.161916732 | May 02 02:06:16 PM PDT 24 | May 02 02:07:28 PM PDT 24 | 11063900000 ps | ||
| T50 | /workspace/coverage/default/42.prim_present_test.817779671 | May 02 02:06:17 PM PDT 24 | May 02 02:07:54 PM PDT 24 | 14942000000 ps |
| Test location | /workspace/coverage/default/10.prim_present_test.3372451217 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 4181900000 ps |
| CPU time | 19.28 seconds |
| Started | May 02 02:06:16 PM PDT 24 |
| Finished | May 02 02:06:55 PM PDT 24 |
| Peak memory | 145040 kb |
| Host | smart-82592adf-a1b6-4d3a-afce-abf6e6ebbb41 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3372451217 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.3372451217 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/0.prim_present_test.1376208479 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 5748020000 ps |
| CPU time | 24.34 seconds |
| Started | May 02 02:06:03 PM PDT 24 |
| Finished | May 02 02:06:55 PM PDT 24 |
| Peak memory | 145200 kb |
| Host | smart-eb79e64f-bdef-4fea-ae88-a0f9a7b1e076 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1376208479 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.1376208479 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/1.prim_present_test.1787172441 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 9499020000 ps |
| CPU time | 40.17 seconds |
| Started | May 02 02:06:02 PM PDT 24 |
| Finished | May 02 02:07:24 PM PDT 24 |
| Peak memory | 145228 kb |
| Host | smart-e6b51d54-1052-49ff-9a6d-df44d78ffc2f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1787172441 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.1787172441 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/11.prim_present_test.4281858770 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 9835680000 ps |
| CPU time | 33.16 seconds |
| Started | May 02 02:06:05 PM PDT 24 |
| Finished | May 02 02:07:11 PM PDT 24 |
| Peak memory | 145196 kb |
| Host | smart-7fb46117-67c4-46ae-be13-fc4593b76dbb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4281858770 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.4281858770 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.2738425195 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 14126080000 ps |
| CPU time | 55.86 seconds |
| Started | May 02 02:06:10 PM PDT 24 |
| Finished | May 02 02:08:06 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-358019ce-1398-41eb-83c0-beff56961b0b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2738425195 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.2738425195 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.250197496 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 15443580000 ps |
| CPU time | 55.98 seconds |
| Started | May 02 02:06:10 PM PDT 24 |
| Finished | May 02 02:08:01 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-4851c750-a94c-418c-8b74-ffa0042ba185 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=250197496 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.250197496 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.2068500035 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 4561340000 ps |
| CPU time | 14.67 seconds |
| Started | May 02 02:06:06 PM PDT 24 |
| Finished | May 02 02:06:35 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-4f71eba1-5ed5-4551-8702-32d8555e280d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2068500035 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.2068500035 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.4095300361 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 4648140000 ps |
| CPU time | 16.52 seconds |
| Started | May 02 02:06:08 PM PDT 24 |
| Finished | May 02 02:06:42 PM PDT 24 |
| Peak memory | 145236 kb |
| Host | smart-37fa3b68-47a7-4dbe-a816-2afe5c311b54 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4095300361 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.4095300361 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.1769596955 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 12501060000 ps |
| CPU time | 47.43 seconds |
| Started | May 02 02:06:07 PM PDT 24 |
| Finished | May 02 02:07:41 PM PDT 24 |
| Peak memory | 145096 kb |
| Host | smart-b305870d-c450-4564-983b-127c1bcbf86d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1769596955 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.1769596955 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.695306777 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 5963160000 ps |
| CPU time | 22.79 seconds |
| Started | May 02 02:06:10 PM PDT 24 |
| Finished | May 02 02:06:57 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-b5c9e1a7-840c-4078-add9-23e3e12068a4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=695306777 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.695306777 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.3582014393 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 13701380000 ps |
| CPU time | 52.86 seconds |
| Started | May 02 02:06:06 PM PDT 24 |
| Finished | May 02 02:07:52 PM PDT 24 |
| Peak memory | 145156 kb |
| Host | smart-eb1df90e-194b-4924-83a7-1551755f483a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3582014393 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.3582014393 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.3596219213 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 3778900000 ps |
| CPU time | 15.85 seconds |
| Started | May 02 02:06:09 PM PDT 24 |
| Finished | May 02 02:06:42 PM PDT 24 |
| Peak memory | 145040 kb |
| Host | smart-cf1e4996-8622-465e-bbd5-2a145eae883e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3596219213 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.3596219213 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.986930710 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 7071720000 ps |
| CPU time | 26.26 seconds |
| Started | May 02 02:06:03 PM PDT 24 |
| Finished | May 02 02:06:57 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-b34b6eee-2e78-43ba-ac01-4bb3b23994c0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=986930710 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.986930710 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.2257100388 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 7164100000 ps |
| CPU time | 27.12 seconds |
| Started | May 02 02:06:08 PM PDT 24 |
| Finished | May 02 02:07:01 PM PDT 24 |
| Peak memory | 145120 kb |
| Host | smart-a97b40dd-b310-47a6-86b8-028a242a75ff |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2257100388 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.2257100388 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.1848936331 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 8037680000 ps |
| CPU time | 29.97 seconds |
| Started | May 02 02:06:09 PM PDT 24 |
| Finished | May 02 02:07:10 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-90a58579-a68f-4432-9987-c5b3166edec7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1848936331 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.1848936331 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.487847356 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 8879020000 ps |
| CPU time | 34.34 seconds |
| Started | May 02 02:06:06 PM PDT 24 |
| Finished | May 02 02:07:14 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-6fb502df-32d7-47c6-885a-fca75f809b2e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=487847356 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.487847356 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.352713376 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 14581780000 ps |
| CPU time | 54.13 seconds |
| Started | May 02 02:06:07 PM PDT 24 |
| Finished | May 02 02:07:53 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-88e59a96-f6d1-4765-8747-fe664db72f12 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=352713376 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.352713376 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.4271373503 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 4297840000 ps |
| CPU time | 17.32 seconds |
| Started | May 02 02:06:10 PM PDT 24 |
| Finished | May 02 02:06:46 PM PDT 24 |
| Peak memory | 145152 kb |
| Host | smart-8fe5ea07-f95e-4019-9193-50f6fd97f533 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4271373503 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.4271373503 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.4110726210 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 6222320000 ps |
| CPU time | 24.54 seconds |
| Started | May 02 02:06:10 PM PDT 24 |
| Finished | May 02 02:07:00 PM PDT 24 |
| Peak memory | 145152 kb |
| Host | smart-3e639455-4656-4a26-8922-79268e2a804d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4110726210 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.4110726210 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.635504601 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 5945180000 ps |
| CPU time | 22.74 seconds |
| Started | May 02 02:06:08 PM PDT 24 |
| Finished | May 02 02:06:56 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-49c0c31f-23d6-469a-8dee-5db79397231b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=635504601 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.635504601 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.3103428271 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 6694760000 ps |
| CPU time | 23.82 seconds |
| Started | May 02 02:06:06 PM PDT 24 |
| Finished | May 02 02:06:53 PM PDT 24 |
| Peak memory | 145132 kb |
| Host | smart-62d14030-dc8e-475c-83d1-9a46c655401e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3103428271 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.3103428271 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.1949631150 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 8173460000 ps |
| CPU time | 34.04 seconds |
| Started | May 02 02:06:09 PM PDT 24 |
| Finished | May 02 02:07:18 PM PDT 24 |
| Peak memory | 145240 kb |
| Host | smart-eb125170-9594-4702-8408-cd53779317f6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1949631150 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.1949631150 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.2915726766 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 13797480000 ps |
| CPU time | 54.32 seconds |
| Started | May 02 02:06:11 PM PDT 24 |
| Finished | May 02 02:08:05 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-54e8e62d-1c43-4b24-9034-ac239a66be2d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2915726766 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.2915726766 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.1882864440 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 13884900000 ps |
| CPU time | 53.14 seconds |
| Started | May 02 02:06:01 PM PDT 24 |
| Finished | May 02 02:07:46 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-691e6252-2677-4c8b-b08d-16a5b8779f72 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1882864440 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.1882864440 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.2865323784 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 13496160000 ps |
| CPU time | 46.01 seconds |
| Started | May 02 02:06:05 PM PDT 24 |
| Finished | May 02 02:07:35 PM PDT 24 |
| Peak memory | 145144 kb |
| Host | smart-7a9d0906-ed8b-44f1-b858-c498df8293ce |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2865323784 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.2865323784 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.707483983 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 12772000000 ps |
| CPU time | 51.83 seconds |
| Started | May 02 02:06:10 PM PDT 24 |
| Finished | May 02 02:07:54 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-c2fd3708-46ca-49e1-94d3-b5710cdb985f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=707483983 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.707483983 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.3368592635 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 15005240000 ps |
| CPU time | 57.53 seconds |
| Started | May 02 02:06:10 PM PDT 24 |
| Finished | May 02 02:08:03 PM PDT 24 |
| Peak memory | 145152 kb |
| Host | smart-cb79fbf9-f71b-41ac-8a92-41dc58663b53 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3368592635 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.3368592635 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.229463416 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 7363120000 ps |
| CPU time | 25.81 seconds |
| Started | May 02 02:06:07 PM PDT 24 |
| Finished | May 02 02:06:56 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-d82d1a7c-38de-4a69-8ea0-4f1e55cb0db2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=229463416 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.229463416 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.3064422697 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 6091500000 ps |
| CPU time | 21.55 seconds |
| Started | May 02 02:06:07 PM PDT 24 |
| Finished | May 02 02:06:50 PM PDT 24 |
| Peak memory | 145080 kb |
| Host | smart-220811dd-15ed-4388-bbc3-a7552e7095c8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3064422697 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.3064422697 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.1938571520 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 8991240000 ps |
| CPU time | 31.78 seconds |
| Started | May 02 02:06:16 PM PDT 24 |
| Finished | May 02 02:07:17 PM PDT 24 |
| Peak memory | 145128 kb |
| Host | smart-67f145d5-45a0-47c9-bd05-70bb3fe25358 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1938571520 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.1938571520 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.3555397565 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 13568700000 ps |
| CPU time | 52.79 seconds |
| Started | May 02 02:06:18 PM PDT 24 |
| Finished | May 02 02:08:09 PM PDT 24 |
| Peak memory | 145164 kb |
| Host | smart-993510ef-c11d-490e-ac22-fced31415fc4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3555397565 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.3555397565 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.2877665674 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 8962720000 ps |
| CPU time | 33.47 seconds |
| Started | May 02 02:06:17 PM PDT 24 |
| Finished | May 02 02:07:22 PM PDT 24 |
| Peak memory | 145148 kb |
| Host | smart-b7407b6a-bc30-4939-a7f4-59dafb906e25 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2877665674 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.2877665674 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.2525094803 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 3343660000 ps |
| CPU time | 16.88 seconds |
| Started | May 02 02:06:16 PM PDT 24 |
| Finished | May 02 02:06:48 PM PDT 24 |
| Peak memory | 145028 kb |
| Host | smart-aa98b237-037b-4cb4-bc5a-59502c74370e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2525094803 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.2525094803 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.1551916272 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 4470200000 ps |
| CPU time | 16.6 seconds |
| Started | May 02 02:06:16 PM PDT 24 |
| Finished | May 02 02:06:50 PM PDT 24 |
| Peak memory | 145156 kb |
| Host | smart-80992e2a-e15b-41d1-83f5-09eb43640019 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1551916272 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.1551916272 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.1040098775 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 12532680000 ps |
| CPU time | 47.59 seconds |
| Started | May 02 02:06:01 PM PDT 24 |
| Finished | May 02 02:07:35 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-f1b309cf-b751-4b87-9f45-2c804d1b14dc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1040098775 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.1040098775 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.2465038968 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 8030240000 ps |
| CPU time | 32.79 seconds |
| Started | May 02 02:06:16 PM PDT 24 |
| Finished | May 02 02:07:21 PM PDT 24 |
| Peak memory | 145152 kb |
| Host | smart-50a53e81-7860-4948-bb09-4b2602c11c00 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2465038968 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.2465038968 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.1009103713 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 6160940000 ps |
| CPU time | 22.87 seconds |
| Started | May 02 02:06:15 PM PDT 24 |
| Finished | May 02 02:07:01 PM PDT 24 |
| Peak memory | 145164 kb |
| Host | smart-3b1bbf02-76f7-432b-946a-c818a74fd1c3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1009103713 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.1009103713 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.817779671 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 14942000000 ps |
| CPU time | 50.08 seconds |
| Started | May 02 02:06:17 PM PDT 24 |
| Finished | May 02 02:07:54 PM PDT 24 |
| Peak memory | 145080 kb |
| Host | smart-00eb11a6-a815-444a-94c4-d6ecdcc2943b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=817779671 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.817779671 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.3888903171 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 10336020000 ps |
| CPU time | 38.24 seconds |
| Started | May 02 02:06:17 PM PDT 24 |
| Finished | May 02 02:07:32 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-8e54e47b-ef44-4bdd-b072-0baffc83d548 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3888903171 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.3888903171 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.1018350048 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 3180600000 ps |
| CPU time | 12.18 seconds |
| Started | May 02 02:06:17 PM PDT 24 |
| Finished | May 02 02:06:41 PM PDT 24 |
| Peak memory | 144952 kb |
| Host | smart-56218ac0-23a9-4fba-bb43-0f50fe5ea28f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1018350048 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.1018350048 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.2351791787 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 7586940000 ps |
| CPU time | 29.31 seconds |
| Started | May 02 02:06:16 PM PDT 24 |
| Finished | May 02 02:07:16 PM PDT 24 |
| Peak memory | 145092 kb |
| Host | smart-7bffcc35-ee8e-4807-a5e8-c5ae3b1b5f47 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2351791787 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.2351791787 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.3156990269 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 4352400000 ps |
| CPU time | 17.82 seconds |
| Started | May 02 02:06:16 PM PDT 24 |
| Finished | May 02 02:06:53 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-edcae4eb-92de-4546-a638-33f048a4f0cc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3156990269 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.3156990269 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.161916732 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 11063900000 ps |
| CPU time | 37.51 seconds |
| Started | May 02 02:06:16 PM PDT 24 |
| Finished | May 02 02:07:28 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-e1c9f807-acab-412d-8c29-fa1c3c2e0494 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=161916732 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.161916732 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.2166959252 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 3630100000 ps |
| CPU time | 13.23 seconds |
| Started | May 02 02:06:17 PM PDT 24 |
| Finished | May 02 02:06:45 PM PDT 24 |
| Peak memory | 145088 kb |
| Host | smart-ae30852c-91e4-45b2-8f9f-873b329babc1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2166959252 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.2166959252 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.2513766812 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 4214140000 ps |
| CPU time | 16.12 seconds |
| Started | May 02 02:06:17 PM PDT 24 |
| Finished | May 02 02:06:49 PM PDT 24 |
| Peak memory | 145000 kb |
| Host | smart-5e430b39-1c7e-4bfa-9565-1f36453a6b40 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2513766812 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.2513766812 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.3891381426 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 14511100000 ps |
| CPU time | 59.11 seconds |
| Started | May 02 02:06:01 PM PDT 24 |
| Finished | May 02 02:08:02 PM PDT 24 |
| Peak memory | 145220 kb |
| Host | smart-f8d775a3-e64e-469d-bb57-2424c86c45fc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3891381426 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.3891381426 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.558195499 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 14503660000 ps |
| CPU time | 55.44 seconds |
| Started | May 02 02:06:00 PM PDT 24 |
| Finished | May 02 02:07:49 PM PDT 24 |
| Peak memory | 145164 kb |
| Host | smart-8718f018-bb88-490b-9989-933f8aefe669 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=558195499 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.558195499 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.1141432665 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 8012260000 ps |
| CPU time | 30.61 seconds |
| Started | May 02 02:06:01 PM PDT 24 |
| Finished | May 02 02:07:02 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-3a153dbf-419d-4678-80ec-ddb809b2c142 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1141432665 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.1141432665 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.1549742147 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 12800520000 ps |
| CPU time | 52 seconds |
| Started | May 02 02:06:16 PM PDT 24 |
| Finished | May 02 02:07:59 PM PDT 24 |
| Peak memory | 145228 kb |
| Host | smart-83473e2b-2b31-4fe2-ad5c-3f25ff89fde2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1549742147 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.1549742147 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.2352168167 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 3946920000 ps |
| CPU time | 15.92 seconds |
| Started | May 02 02:06:11 PM PDT 24 |
| Finished | May 02 02:06:45 PM PDT 24 |
| Peak memory | 145020 kb |
| Host | smart-ec5172ae-4bd5-4ad7-b960-4a34e328e2aa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2352168167 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.2352168167 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |