| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/1.prim_present_test.684907047 | ||
| Name |
|---|
| /workspace/coverage/default/0.prim_present_test.1552380331 |
| /workspace/coverage/default/10.prim_present_test.690141603 |
| /workspace/coverage/default/11.prim_present_test.1148240536 |
| /workspace/coverage/default/12.prim_present_test.1579776822 |
| /workspace/coverage/default/13.prim_present_test.618892371 |
| /workspace/coverage/default/14.prim_present_test.1324283309 |
| /workspace/coverage/default/15.prim_present_test.1752162997 |
| /workspace/coverage/default/16.prim_present_test.1534676824 |
| /workspace/coverage/default/17.prim_present_test.589798438 |
| /workspace/coverage/default/18.prim_present_test.1741691662 |
| /workspace/coverage/default/19.prim_present_test.245972729 |
| /workspace/coverage/default/2.prim_present_test.105866912 |
| /workspace/coverage/default/20.prim_present_test.1973189847 |
| /workspace/coverage/default/21.prim_present_test.970376973 |
| /workspace/coverage/default/22.prim_present_test.3148056719 |
| /workspace/coverage/default/23.prim_present_test.4225062121 |
| /workspace/coverage/default/24.prim_present_test.1837523962 |
| /workspace/coverage/default/25.prim_present_test.739992960 |
| /workspace/coverage/default/26.prim_present_test.36878190 |
| /workspace/coverage/default/27.prim_present_test.3996327688 |
| /workspace/coverage/default/28.prim_present_test.902332081 |
| /workspace/coverage/default/29.prim_present_test.2976237261 |
| /workspace/coverage/default/3.prim_present_test.1120081031 |
| /workspace/coverage/default/30.prim_present_test.1163412308 |
| /workspace/coverage/default/31.prim_present_test.52219698 |
| /workspace/coverage/default/32.prim_present_test.2151563382 |
| /workspace/coverage/default/33.prim_present_test.738354089 |
| /workspace/coverage/default/34.prim_present_test.3374400761 |
| /workspace/coverage/default/35.prim_present_test.2032249923 |
| /workspace/coverage/default/36.prim_present_test.226589607 |
| /workspace/coverage/default/37.prim_present_test.2201931037 |
| /workspace/coverage/default/38.prim_present_test.4126385068 |
| /workspace/coverage/default/39.prim_present_test.1898852588 |
| /workspace/coverage/default/4.prim_present_test.746585380 |
| /workspace/coverage/default/40.prim_present_test.2429672575 |
| /workspace/coverage/default/41.prim_present_test.4174112391 |
| /workspace/coverage/default/42.prim_present_test.747072459 |
| /workspace/coverage/default/43.prim_present_test.1930155655 |
| /workspace/coverage/default/44.prim_present_test.2836735035 |
| /workspace/coverage/default/45.prim_present_test.3280169981 |
| /workspace/coverage/default/46.prim_present_test.1762431403 |
| /workspace/coverage/default/47.prim_present_test.2568820591 |
| /workspace/coverage/default/48.prim_present_test.1309504974 |
| /workspace/coverage/default/49.prim_present_test.3711500044 |
| /workspace/coverage/default/5.prim_present_test.1598190568 |
| /workspace/coverage/default/6.prim_present_test.1756910218 |
| /workspace/coverage/default/7.prim_present_test.2295472648 |
| /workspace/coverage/default/8.prim_present_test.3041509820 |
| /workspace/coverage/default/9.prim_present_test.3856969302 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/36.prim_present_test.226589607 | May 05 12:29:11 PM PDT 24 | May 05 12:29:43 PM PDT 24 | 4241420000 ps | ||
| T2 | /workspace/coverage/default/49.prim_present_test.3711500044 | May 05 12:29:12 PM PDT 24 | May 05 12:30:45 PM PDT 24 | 12548800000 ps | ||
| T3 | /workspace/coverage/default/1.prim_present_test.684907047 | May 05 12:29:01 PM PDT 24 | May 05 12:30:06 PM PDT 24 | 10533800000 ps | ||
| T4 | /workspace/coverage/default/4.prim_present_test.746585380 | May 05 12:29:05 PM PDT 24 | May 05 12:29:59 PM PDT 24 | 9027820000 ps | ||
| T5 | /workspace/coverage/default/21.prim_present_test.970376973 | May 05 12:29:02 PM PDT 24 | May 05 12:30:29 PM PDT 24 | 14458400000 ps | ||
| T6 | /workspace/coverage/default/40.prim_present_test.2429672575 | May 05 12:29:08 PM PDT 24 | May 05 12:30:45 PM PDT 24 | 14730580000 ps | ||
| T7 | /workspace/coverage/default/20.prim_present_test.1973189847 | May 05 12:29:05 PM PDT 24 | May 05 12:30:22 PM PDT 24 | 11545640000 ps | ||
| T8 | /workspace/coverage/default/30.prim_present_test.1163412308 | May 05 12:29:06 PM PDT 24 | May 05 12:30:09 PM PDT 24 | 10515200000 ps | ||
| T9 | /workspace/coverage/default/7.prim_present_test.2295472648 | May 05 12:29:03 PM PDT 24 | May 05 12:29:44 PM PDT 24 | 5274960000 ps | ||
| T10 | /workspace/coverage/default/35.prim_present_test.2032249923 | May 05 12:29:11 PM PDT 24 | May 05 12:29:43 PM PDT 24 | 4558860000 ps | ||
| T11 | /workspace/coverage/default/12.prim_present_test.1579776822 | May 05 12:29:05 PM PDT 24 | May 05 12:30:33 PM PDT 24 | 13033020000 ps | ||
| T12 | /workspace/coverage/default/39.prim_present_test.1898852588 | May 05 12:29:06 PM PDT 24 | May 05 12:30:10 PM PDT 24 | 10005560000 ps | ||
| T13 | /workspace/coverage/default/5.prim_present_test.1598190568 | May 05 12:29:05 PM PDT 24 | May 05 12:30:10 PM PDT 24 | 9528780000 ps | ||
| T14 | /workspace/coverage/default/33.prim_present_test.738354089 | May 05 12:29:09 PM PDT 24 | May 05 12:29:43 PM PDT 24 | 4744240000 ps | ||
| T15 | /workspace/coverage/default/3.prim_present_test.1120081031 | May 05 12:29:07 PM PDT 24 | May 05 12:30:06 PM PDT 24 | 7832460000 ps | ||
| T16 | /workspace/coverage/default/13.prim_present_test.618892371 | May 05 12:29:03 PM PDT 24 | May 05 12:30:23 PM PDT 24 | 12372100000 ps | ||
| T17 | /workspace/coverage/default/45.prim_present_test.3280169981 | May 05 12:29:08 PM PDT 24 | May 05 12:30:32 PM PDT 24 | 11489220000 ps | ||
| T18 | /workspace/coverage/default/27.prim_present_test.3996327688 | May 05 12:29:08 PM PDT 24 | May 05 12:30:31 PM PDT 24 | 12925760000 ps | ||
| T19 | /workspace/coverage/default/11.prim_present_test.1148240536 | May 05 12:29:10 PM PDT 24 | May 05 12:30:51 PM PDT 24 | 14070280000 ps | ||
| T20 | /workspace/coverage/default/43.prim_present_test.1930155655 | May 05 12:29:09 PM PDT 24 | May 05 12:30:37 PM PDT 24 | 12817880000 ps | ||
| T21 | /workspace/coverage/default/28.prim_present_test.902332081 | May 05 12:29:09 PM PDT 24 | May 05 12:30:23 PM PDT 24 | 13424240000 ps | ||
| T22 | /workspace/coverage/default/0.prim_present_test.1552380331 | May 05 12:29:02 PM PDT 24 | May 05 12:30:39 PM PDT 24 | 15113740000 ps | ||
| T23 | /workspace/coverage/default/9.prim_present_test.3856969302 | May 05 12:29:02 PM PDT 24 | May 05 12:30:05 PM PDT 24 | 9249780000 ps | ||
| T24 | /workspace/coverage/default/29.prim_present_test.2976237261 | May 05 12:29:06 PM PDT 24 | May 05 12:30:46 PM PDT 24 | 14317040000 ps | ||
| T25 | /workspace/coverage/default/18.prim_present_test.1741691662 | May 05 12:29:10 PM PDT 24 | May 05 12:30:36 PM PDT 24 | 11443340000 ps | ||
| T26 | /workspace/coverage/default/32.prim_present_test.2151563382 | May 05 12:29:08 PM PDT 24 | May 05 12:30:22 PM PDT 24 | 10830780000 ps | ||
| T27 | /workspace/coverage/default/26.prim_present_test.36878190 | May 05 12:29:07 PM PDT 24 | May 05 12:29:41 PM PDT 24 | 5365480000 ps | ||
| T28 | /workspace/coverage/default/38.prim_present_test.4126385068 | May 05 12:29:09 PM PDT 24 | May 05 12:30:26 PM PDT 24 | 11133340000 ps | ||
| T29 | /workspace/coverage/default/23.prim_present_test.4225062121 | May 05 12:29:01 PM PDT 24 | May 05 12:29:28 PM PDT 24 | 3481920000 ps | ||
| T30 | /workspace/coverage/default/10.prim_present_test.690141603 | May 05 12:29:04 PM PDT 24 | May 05 12:29:47 PM PDT 24 | 5504360000 ps | ||
| T31 | /workspace/coverage/default/31.prim_present_test.52219698 | May 05 12:29:08 PM PDT 24 | May 05 12:30:02 PM PDT 24 | 8094720000 ps | ||
| T32 | /workspace/coverage/default/19.prim_present_test.245972729 | May 05 12:29:03 PM PDT 24 | May 05 12:30:02 PM PDT 24 | 8577080000 ps | ||
| T33 | /workspace/coverage/default/25.prim_present_test.739992960 | May 05 12:29:02 PM PDT 24 | May 05 12:30:10 PM PDT 24 | 9600080000 ps | ||
| T34 | /workspace/coverage/default/2.prim_present_test.105866912 | May 05 12:29:02 PM PDT 24 | May 05 12:30:16 PM PDT 24 | 11002520000 ps | ||
| T35 | /workspace/coverage/default/42.prim_present_test.747072459 | May 05 12:29:07 PM PDT 24 | May 05 12:30:21 PM PDT 24 | 10076860000 ps | ||
| T36 | /workspace/coverage/default/17.prim_present_test.589798438 | May 05 12:29:01 PM PDT 24 | May 05 12:29:37 PM PDT 24 | 5380360000 ps | ||
| T37 | /workspace/coverage/default/44.prim_present_test.2836735035 | May 05 12:29:12 PM PDT 24 | May 05 12:30:15 PM PDT 24 | 8800280000 ps | ||
| T38 | /workspace/coverage/default/37.prim_present_test.2201931037 | May 05 12:29:08 PM PDT 24 | May 05 12:30:13 PM PDT 24 | 10420340000 ps | ||
| T39 | /workspace/coverage/default/24.prim_present_test.1837523962 | May 05 12:29:10 PM PDT 24 | May 05 12:30:35 PM PDT 24 | 11727300000 ps | ||
| T40 | /workspace/coverage/default/16.prim_present_test.1534676824 | May 05 12:29:01 PM PDT 24 | May 05 12:30:13 PM PDT 24 | 11483020000 ps | ||
| T41 | /workspace/coverage/default/48.prim_present_test.1309504974 | May 05 12:29:14 PM PDT 24 | May 05 12:29:55 PM PDT 24 | 6053060000 ps | ||
| T42 | /workspace/coverage/default/15.prim_present_test.1752162997 | May 05 12:29:10 PM PDT 24 | May 05 12:29:56 PM PDT 24 | 5993540000 ps | ||
| T43 | /workspace/coverage/default/46.prim_present_test.1762431403 | May 05 12:29:14 PM PDT 24 | May 05 12:30:38 PM PDT 24 | 11201540000 ps | ||
| T44 | /workspace/coverage/default/6.prim_present_test.1756910218 | May 05 12:29:10 PM PDT 24 | May 05 12:29:40 PM PDT 24 | 3829740000 ps | ||
| T45 | /workspace/coverage/default/8.prim_present_test.3041509820 | May 05 12:29:05 PM PDT 24 | May 05 12:29:55 PM PDT 24 | 7117600000 ps | ||
| T46 | /workspace/coverage/default/34.prim_present_test.3374400761 | May 05 12:29:06 PM PDT 24 | May 05 12:29:37 PM PDT 24 | 4985420000 ps | ||
| T47 | /workspace/coverage/default/14.prim_present_test.1324283309 | May 05 12:29:10 PM PDT 24 | May 05 12:29:41 PM PDT 24 | 3937000000 ps | ||
| T48 | /workspace/coverage/default/47.prim_present_test.2568820591 | May 05 12:29:13 PM PDT 24 | May 05 12:30:09 PM PDT 24 | 7203780000 ps | ||
| T49 | /workspace/coverage/default/22.prim_present_test.3148056719 | May 05 12:29:05 PM PDT 24 | May 05 12:29:59 PM PDT 24 | 6524880000 ps | ||
| T50 | /workspace/coverage/default/41.prim_present_test.4174112391 | May 05 12:29:07 PM PDT 24 | May 05 12:30:40 PM PDT 24 | 13826620000 ps |
| Test location | /workspace/coverage/default/1.prim_present_test.684907047 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 10533800000 ps |
| CPU time | 34.02 seconds |
| Started | May 05 12:29:01 PM PDT 24 |
| Finished | May 05 12:30:06 PM PDT 24 |
| Peak memory | 145112 kb |
| Host | smart-e77c046d-209d-4f8b-a7fb-943999facd5b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=684907047 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.684907047 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/0.prim_present_test.1552380331 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 15113740000 ps |
| CPU time | 51.55 seconds |
| Started | May 05 12:29:02 PM PDT 24 |
| Finished | May 05 12:30:39 PM PDT 24 |
| Peak memory | 145200 kb |
| Host | smart-f5ba24a9-b348-43dc-9d7b-030ad864b7ef |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1552380331 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.1552380331 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/10.prim_present_test.690141603 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 5504360000 ps |
| CPU time | 22.29 seconds |
| Started | May 05 12:29:04 PM PDT 24 |
| Finished | May 05 12:29:47 PM PDT 24 |
| Peak memory | 145152 kb |
| Host | smart-1863c191-7f1a-414c-870f-2dba644c8aab |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=690141603 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.690141603 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/11.prim_present_test.1148240536 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 14070280000 ps |
| CPU time | 52.32 seconds |
| Started | May 05 12:29:10 PM PDT 24 |
| Finished | May 05 12:30:51 PM PDT 24 |
| Peak memory | 145020 kb |
| Host | smart-27779f1d-0333-473f-8cc5-fa08a431df5f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1148240536 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.1148240536 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.1579776822 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 13033020000 ps |
| CPU time | 46.3 seconds |
| Started | May 05 12:29:05 PM PDT 24 |
| Finished | May 05 12:30:33 PM PDT 24 |
| Peak memory | 145008 kb |
| Host | smart-c5631780-d24c-4d90-947c-4b2a1a3ee6dc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1579776822 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.1579776822 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.618892371 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 12372100000 ps |
| CPU time | 42.39 seconds |
| Started | May 05 12:29:03 PM PDT 24 |
| Finished | May 05 12:30:23 PM PDT 24 |
| Peak memory | 145048 kb |
| Host | smart-8afc152b-4294-4890-91db-82781c817027 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=618892371 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.618892371 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.1324283309 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 3937000000 ps |
| CPU time | 15.99 seconds |
| Started | May 05 12:29:10 PM PDT 24 |
| Finished | May 05 12:29:41 PM PDT 24 |
| Peak memory | 144892 kb |
| Host | smart-56506448-780c-431f-a9b3-728db5ff2dc3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1324283309 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.1324283309 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.1752162997 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 5993540000 ps |
| CPU time | 23.43 seconds |
| Started | May 05 12:29:10 PM PDT 24 |
| Finished | May 05 12:29:56 PM PDT 24 |
| Peak memory | 145036 kb |
| Host | smart-d570366f-94b8-4e99-a0d2-5e9c94d0e9d1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1752162997 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.1752162997 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.1534676824 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 11483020000 ps |
| CPU time | 38.52 seconds |
| Started | May 05 12:29:01 PM PDT 24 |
| Finished | May 05 12:30:13 PM PDT 24 |
| Peak memory | 145128 kb |
| Host | smart-6626f0f6-b0e8-401d-82b8-fb2b4a176cb7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1534676824 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.1534676824 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.589798438 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 5380360000 ps |
| CPU time | 18.5 seconds |
| Started | May 05 12:29:01 PM PDT 24 |
| Finished | May 05 12:29:37 PM PDT 24 |
| Peak memory | 145108 kb |
| Host | smart-ad536cdd-4faa-46b7-a971-8730b78b4b05 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=589798438 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.589798438 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.1741691662 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 11443340000 ps |
| CPU time | 44.44 seconds |
| Started | May 05 12:29:10 PM PDT 24 |
| Finished | May 05 12:30:36 PM PDT 24 |
| Peak memory | 145036 kb |
| Host | smart-fcd7ed3e-f4c7-4e4d-9fff-3d1aa8a9b666 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1741691662 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.1741691662 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.245972729 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 8577080000 ps |
| CPU time | 31.23 seconds |
| Started | May 05 12:29:03 PM PDT 24 |
| Finished | May 05 12:30:02 PM PDT 24 |
| Peak memory | 145048 kb |
| Host | smart-b38e56dd-8976-43a6-88ea-efe717d2dbd0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=245972729 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.245972729 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.105866912 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 11002520000 ps |
| CPU time | 38.43 seconds |
| Started | May 05 12:29:02 PM PDT 24 |
| Finished | May 05 12:30:16 PM PDT 24 |
| Peak memory | 145040 kb |
| Host | smart-045d033f-8285-43fc-a650-3c6f60408513 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=105866912 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.105866912 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.1973189847 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 11545640000 ps |
| CPU time | 40.66 seconds |
| Started | May 05 12:29:05 PM PDT 24 |
| Finished | May 05 12:30:22 PM PDT 24 |
| Peak memory | 145120 kb |
| Host | smart-ec0bad82-4c24-4220-a51d-1c1a6edeeae3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1973189847 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.1973189847 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.970376973 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 14458400000 ps |
| CPU time | 46.25 seconds |
| Started | May 05 12:29:02 PM PDT 24 |
| Finished | May 05 12:30:29 PM PDT 24 |
| Peak memory | 145104 kb |
| Host | smart-778a4690-4a78-4049-a516-aa0b1ac5b21c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=970376973 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.970376973 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.3148056719 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 6524880000 ps |
| CPU time | 27.26 seconds |
| Started | May 05 12:29:05 PM PDT 24 |
| Finished | May 05 12:29:59 PM PDT 24 |
| Peak memory | 145068 kb |
| Host | smart-5307a38d-8d83-4b1a-a783-8ef88ee40492 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3148056719 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.3148056719 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.4225062121 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 3481920000 ps |
| CPU time | 13.26 seconds |
| Started | May 05 12:29:01 PM PDT 24 |
| Finished | May 05 12:29:28 PM PDT 24 |
| Peak memory | 144880 kb |
| Host | smart-63990dc1-1e8e-47b1-9618-0dd32fecae04 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4225062121 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.4225062121 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.1837523962 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 11727300000 ps |
| CPU time | 43.53 seconds |
| Started | May 05 12:29:10 PM PDT 24 |
| Finished | May 05 12:30:35 PM PDT 24 |
| Peak memory | 145036 kb |
| Host | smart-25f84933-1e07-4dc2-afd6-37f0d9f8a26f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1837523962 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.1837523962 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.739992960 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 9600080000 ps |
| CPU time | 35.95 seconds |
| Started | May 05 12:29:02 PM PDT 24 |
| Finished | May 05 12:30:10 PM PDT 24 |
| Peak memory | 145128 kb |
| Host | smart-b8c93b11-5700-4a3f-9c85-f00d9875b34c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=739992960 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.739992960 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.36878190 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 5365480000 ps |
| CPU time | 17.79 seconds |
| Started | May 05 12:29:07 PM PDT 24 |
| Finished | May 05 12:29:41 PM PDT 24 |
| Peak memory | 145128 kb |
| Host | smart-edfac5c1-8a9f-4c29-ad89-ac2a754e366a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=36878190 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.36878190 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.3996327688 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 12925760000 ps |
| CPU time | 44.06 seconds |
| Started | May 05 12:29:08 PM PDT 24 |
| Finished | May 05 12:30:31 PM PDT 24 |
| Peak memory | 145016 kb |
| Host | smart-922fd55b-0332-4531-a2b5-99b0843d0445 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3996327688 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.3996327688 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.902332081 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 13424240000 ps |
| CPU time | 40.33 seconds |
| Started | May 05 12:29:09 PM PDT 24 |
| Finished | May 05 12:30:23 PM PDT 24 |
| Peak memory | 145156 kb |
| Host | smart-ba8aaa3d-28eb-4d44-a0be-764b6f012576 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=902332081 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.902332081 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.2976237261 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 14317040000 ps |
| CPU time | 52.59 seconds |
| Started | May 05 12:29:06 PM PDT 24 |
| Finished | May 05 12:30:46 PM PDT 24 |
| Peak memory | 145128 kb |
| Host | smart-9daa8341-a9b3-42e8-ab8c-5e83301de716 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2976237261 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.2976237261 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.1120081031 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 7832460000 ps |
| CPU time | 30.68 seconds |
| Started | May 05 12:29:07 PM PDT 24 |
| Finished | May 05 12:30:06 PM PDT 24 |
| Peak memory | 145152 kb |
| Host | smart-940df17d-3be9-4249-b10c-5c6958129d43 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1120081031 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.1120081031 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.1163412308 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 10515200000 ps |
| CPU time | 33.34 seconds |
| Started | May 05 12:29:06 PM PDT 24 |
| Finished | May 05 12:30:09 PM PDT 24 |
| Peak memory | 145112 kb |
| Host | smart-c8ef7fc1-36d1-4741-b8ee-21fd5527a87f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1163412308 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.1163412308 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.52219698 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 8094720000 ps |
| CPU time | 28.73 seconds |
| Started | May 05 12:29:08 PM PDT 24 |
| Finished | May 05 12:30:02 PM PDT 24 |
| Peak memory | 145084 kb |
| Host | smart-27fcc9e2-5dd1-4f6a-83fd-cade7f22d818 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=52219698 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.52219698 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.2151563382 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 10830780000 ps |
| CPU time | 38.97 seconds |
| Started | May 05 12:29:08 PM PDT 24 |
| Finished | May 05 12:30:22 PM PDT 24 |
| Peak memory | 145120 kb |
| Host | smart-f914ac06-747e-4853-a02f-45df7d47bca9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2151563382 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.2151563382 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.738354089 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 4744240000 ps |
| CPU time | 17.67 seconds |
| Started | May 05 12:29:09 PM PDT 24 |
| Finished | May 05 12:29:43 PM PDT 24 |
| Peak memory | 145068 kb |
| Host | smart-6854743f-5abb-4a9a-aee6-1a6b663c509e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=738354089 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.738354089 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.3374400761 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 4985420000 ps |
| CPU time | 16.36 seconds |
| Started | May 05 12:29:06 PM PDT 24 |
| Finished | May 05 12:29:37 PM PDT 24 |
| Peak memory | 145148 kb |
| Host | smart-c04aeff4-6243-444c-bbf2-342a304c1397 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3374400761 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.3374400761 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.2032249923 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 4558860000 ps |
| CPU time | 15.79 seconds |
| Started | May 05 12:29:11 PM PDT 24 |
| Finished | May 05 12:29:43 PM PDT 24 |
| Peak memory | 145028 kb |
| Host | smart-9c85a994-c410-4cf1-b886-b2626ccde04f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2032249923 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.2032249923 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.226589607 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 4241420000 ps |
| CPU time | 16.07 seconds |
| Started | May 05 12:29:11 PM PDT 24 |
| Finished | May 05 12:29:43 PM PDT 24 |
| Peak memory | 144880 kb |
| Host | smart-a772be65-39b7-41ca-8041-a122559c17d9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=226589607 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.226589607 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.2201931037 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 10420340000 ps |
| CPU time | 34.35 seconds |
| Started | May 05 12:29:08 PM PDT 24 |
| Finished | May 05 12:30:13 PM PDT 24 |
| Peak memory | 145120 kb |
| Host | smart-66a733a5-50f7-4703-a9c3-64f793137a53 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2201931037 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.2201931037 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.4126385068 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 11133340000 ps |
| CPU time | 40.31 seconds |
| Started | May 05 12:29:09 PM PDT 24 |
| Finished | May 05 12:30:26 PM PDT 24 |
| Peak memory | 145068 kb |
| Host | smart-ba614685-e569-4e66-a075-490dd4400145 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4126385068 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.4126385068 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.1898852588 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 10005560000 ps |
| CPU time | 33.33 seconds |
| Started | May 05 12:29:06 PM PDT 24 |
| Finished | May 05 12:30:10 PM PDT 24 |
| Peak memory | 145156 kb |
| Host | smart-e71ca981-1cd0-4b74-b52e-7821d63c88bc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1898852588 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.1898852588 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.746585380 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 9027820000 ps |
| CPU time | 29.32 seconds |
| Started | May 05 12:29:05 PM PDT 24 |
| Finished | May 05 12:29:59 PM PDT 24 |
| Peak memory | 145148 kb |
| Host | smart-fb073f3d-bee1-427e-bec6-d88a91f0e0bd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=746585380 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.746585380 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.2429672575 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 14730580000 ps |
| CPU time | 50.71 seconds |
| Started | May 05 12:29:08 PM PDT 24 |
| Finished | May 05 12:30:45 PM PDT 24 |
| Peak memory | 145080 kb |
| Host | smart-76d2c630-1a59-48ce-899a-6b58d1edc113 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2429672575 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.2429672575 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.4174112391 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 13826620000 ps |
| CPU time | 48.55 seconds |
| Started | May 05 12:29:07 PM PDT 24 |
| Finished | May 05 12:30:40 PM PDT 24 |
| Peak memory | 145008 kb |
| Host | smart-d0f49461-9a99-4c70-a7eb-21cc678fb9ca |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4174112391 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.4174112391 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.747072459 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 10076860000 ps |
| CPU time | 38.92 seconds |
| Started | May 05 12:29:07 PM PDT 24 |
| Finished | May 05 12:30:21 PM PDT 24 |
| Peak memory | 145112 kb |
| Host | smart-e2e3ea39-89fa-4b5f-9f11-33b929d0b4f5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=747072459 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.747072459 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.1930155655 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 12817880000 ps |
| CPU time | 46.28 seconds |
| Started | May 05 12:29:09 PM PDT 24 |
| Finished | May 05 12:30:37 PM PDT 24 |
| Peak memory | 145068 kb |
| Host | smart-21aa6b4b-31b6-4471-97aa-fb8b97d5507e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1930155655 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.1930155655 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.2836735035 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 8800280000 ps |
| CPU time | 32.42 seconds |
| Started | May 05 12:29:12 PM PDT 24 |
| Finished | May 05 12:30:15 PM PDT 24 |
| Peak memory | 145028 kb |
| Host | smart-256856f1-9b3f-42a8-9723-677984abaa2a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2836735035 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.2836735035 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.3280169981 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 11489220000 ps |
| CPU time | 43.97 seconds |
| Started | May 05 12:29:08 PM PDT 24 |
| Finished | May 05 12:30:32 PM PDT 24 |
| Peak memory | 145024 kb |
| Host | smart-77d7b705-f3b1-4e37-af59-d595ce6c0150 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3280169981 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.3280169981 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.1762431403 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 11201540000 ps |
| CPU time | 43.98 seconds |
| Started | May 05 12:29:14 PM PDT 24 |
| Finished | May 05 12:30:38 PM PDT 24 |
| Peak memory | 145024 kb |
| Host | smart-7cbae822-a3e7-4ddf-a75d-f1af3b0e9135 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1762431403 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.1762431403 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.2568820591 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 7203780000 ps |
| CPU time | 28.63 seconds |
| Started | May 05 12:29:13 PM PDT 24 |
| Finished | May 05 12:30:09 PM PDT 24 |
| Peak memory | 145144 kb |
| Host | smart-1103527c-40b9-4f2f-b8bb-6a191f46f459 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2568820591 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.2568820591 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.1309504974 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 6053060000 ps |
| CPU time | 21.81 seconds |
| Started | May 05 12:29:14 PM PDT 24 |
| Finished | May 05 12:29:55 PM PDT 24 |
| Peak memory | 145104 kb |
| Host | smart-49ba9762-37a3-485b-8c88-c28047f65b58 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1309504974 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.1309504974 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.3711500044 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 12548800000 ps |
| CPU time | 48.47 seconds |
| Started | May 05 12:29:12 PM PDT 24 |
| Finished | May 05 12:30:45 PM PDT 24 |
| Peak memory | 145140 kb |
| Host | smart-3398f095-ff5d-4209-bd09-e1f0d1bc4150 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3711500044 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.3711500044 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.1598190568 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 9528780000 ps |
| CPU time | 34.56 seconds |
| Started | May 05 12:29:05 PM PDT 24 |
| Finished | May 05 12:30:10 PM PDT 24 |
| Peak memory | 145124 kb |
| Host | smart-75f0f550-f62a-4433-a3b3-1a92e26f8e75 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1598190568 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.1598190568 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.1756910218 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 3829740000 ps |
| CPU time | 14.81 seconds |
| Started | May 05 12:29:10 PM PDT 24 |
| Finished | May 05 12:29:40 PM PDT 24 |
| Peak memory | 144896 kb |
| Host | smart-2653cf6d-5044-43e3-9058-2bb7d50ac6c1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1756910218 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.1756910218 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.2295472648 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 5274960000 ps |
| CPU time | 20.56 seconds |
| Started | May 05 12:29:03 PM PDT 24 |
| Finished | May 05 12:29:44 PM PDT 24 |
| Peak memory | 145076 kb |
| Host | smart-8c4c0418-3a4c-4a12-8926-f38c692122ed |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2295472648 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.2295472648 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.3041509820 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 7117600000 ps |
| CPU time | 25.48 seconds |
| Started | May 05 12:29:05 PM PDT 24 |
| Finished | May 05 12:29:55 PM PDT 24 |
| Peak memory | 145140 kb |
| Host | smart-1e960af3-30ea-4f50-b0ba-9887ce3697df |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3041509820 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.3041509820 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.3856969302 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 9249780000 ps |
| CPU time | 33.23 seconds |
| Started | May 05 12:29:02 PM PDT 24 |
| Finished | May 05 12:30:05 PM PDT 24 |
| Peak memory | 145128 kb |
| Host | smart-27c180ea-c972-4e21-bcf8-b55ee09a4b3a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3856969302 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.3856969302 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |