| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/1.prim_present_test.427849258 | ||
| Name |
|---|
| /workspace/coverage/default/0.prim_present_test.511773665 |
| /workspace/coverage/default/10.prim_present_test.963884750 |
| /workspace/coverage/default/11.prim_present_test.330099666 |
| /workspace/coverage/default/12.prim_present_test.2000677967 |
| /workspace/coverage/default/13.prim_present_test.289626381 |
| /workspace/coverage/default/14.prim_present_test.2769868498 |
| /workspace/coverage/default/15.prim_present_test.1777219714 |
| /workspace/coverage/default/16.prim_present_test.1451088059 |
| /workspace/coverage/default/17.prim_present_test.1719779252 |
| /workspace/coverage/default/18.prim_present_test.1547795377 |
| /workspace/coverage/default/19.prim_present_test.851739637 |
| /workspace/coverage/default/2.prim_present_test.3542687914 |
| /workspace/coverage/default/20.prim_present_test.1952552603 |
| /workspace/coverage/default/21.prim_present_test.301858334 |
| /workspace/coverage/default/22.prim_present_test.3795845577 |
| /workspace/coverage/default/23.prim_present_test.1885806418 |
| /workspace/coverage/default/24.prim_present_test.3725417510 |
| /workspace/coverage/default/25.prim_present_test.1678009142 |
| /workspace/coverage/default/26.prim_present_test.2783062333 |
| /workspace/coverage/default/27.prim_present_test.540207366 |
| /workspace/coverage/default/28.prim_present_test.456085205 |
| /workspace/coverage/default/29.prim_present_test.4073911249 |
| /workspace/coverage/default/3.prim_present_test.2058825689 |
| /workspace/coverage/default/30.prim_present_test.54950852 |
| /workspace/coverage/default/31.prim_present_test.3329716841 |
| /workspace/coverage/default/32.prim_present_test.1645074912 |
| /workspace/coverage/default/33.prim_present_test.3074211471 |
| /workspace/coverage/default/34.prim_present_test.3062821570 |
| /workspace/coverage/default/35.prim_present_test.3490402617 |
| /workspace/coverage/default/36.prim_present_test.204478544 |
| /workspace/coverage/default/37.prim_present_test.714782558 |
| /workspace/coverage/default/38.prim_present_test.928415985 |
| /workspace/coverage/default/39.prim_present_test.1392504690 |
| /workspace/coverage/default/4.prim_present_test.40219271 |
| /workspace/coverage/default/40.prim_present_test.366403708 |
| /workspace/coverage/default/41.prim_present_test.1701653944 |
| /workspace/coverage/default/42.prim_present_test.1910652996 |
| /workspace/coverage/default/43.prim_present_test.4127301093 |
| /workspace/coverage/default/44.prim_present_test.1087810482 |
| /workspace/coverage/default/45.prim_present_test.4250072637 |
| /workspace/coverage/default/46.prim_present_test.2191982515 |
| /workspace/coverage/default/47.prim_present_test.3749260576 |
| /workspace/coverage/default/48.prim_present_test.4174673825 |
| /workspace/coverage/default/49.prim_present_test.3785855178 |
| /workspace/coverage/default/5.prim_present_test.1284853533 |
| /workspace/coverage/default/6.prim_present_test.1710316193 |
| /workspace/coverage/default/7.prim_present_test.3926637323 |
| /workspace/coverage/default/8.prim_present_test.1850048830 |
| /workspace/coverage/default/9.prim_present_test.3785149624 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/18.prim_present_test.1547795377 | May 07 12:25:46 PM PDT 24 | May 07 12:26:59 PM PDT 24 | 11409240000 ps | ||
| T2 | /workspace/coverage/default/29.prim_present_test.4073911249 | May 07 12:25:42 PM PDT 24 | May 07 12:27:18 PM PDT 24 | 15387780000 ps | ||
| T3 | /workspace/coverage/default/13.prim_present_test.289626381 | May 07 12:25:41 PM PDT 24 | May 07 12:26:39 PM PDT 24 | 8741380000 ps | ||
| T4 | /workspace/coverage/default/8.prim_present_test.1850048830 | May 07 12:25:38 PM PDT 24 | May 07 12:26:17 PM PDT 24 | 6223560000 ps | ||
| T5 | /workspace/coverage/default/6.prim_present_test.1710316193 | May 07 12:25:36 PM PDT 24 | May 07 12:25:59 PM PDT 24 | 3509200000 ps | ||
| T6 | /workspace/coverage/default/5.prim_present_test.1284853533 | May 07 12:25:37 PM PDT 24 | May 07 12:26:10 PM PDT 24 | 5307820000 ps | ||
| T7 | /workspace/coverage/default/1.prim_present_test.427849258 | May 07 12:25:40 PM PDT 24 | May 07 12:26:49 PM PDT 24 | 11525800000 ps | ||
| T8 | /workspace/coverage/default/10.prim_present_test.963884750 | May 07 12:25:41 PM PDT 24 | May 07 12:26:53 PM PDT 24 | 11652280000 ps | ||
| T9 | /workspace/coverage/default/30.prim_present_test.54950852 | May 07 12:25:43 PM PDT 24 | May 07 12:27:01 PM PDT 24 | 10796680000 ps | ||
| T10 | /workspace/coverage/default/24.prim_present_test.3725417510 | May 07 12:25:44 PM PDT 24 | May 07 12:26:39 PM PDT 24 | 8761220000 ps | ||
| T11 | /workspace/coverage/default/35.prim_present_test.3490402617 | May 07 12:25:42 PM PDT 24 | May 07 12:26:56 PM PDT 24 | 12885460000 ps | ||
| T12 | /workspace/coverage/default/16.prim_present_test.1451088059 | May 07 12:25:45 PM PDT 24 | May 07 12:26:33 PM PDT 24 | 7875860000 ps | ||
| T13 | /workspace/coverage/default/9.prim_present_test.3785149624 | May 07 12:25:47 PM PDT 24 | May 07 12:26:17 PM PDT 24 | 3775180000 ps | ||
| T14 | /workspace/coverage/default/41.prim_present_test.1701653944 | May 07 12:25:46 PM PDT 24 | May 07 12:26:47 PM PDT 24 | 8394180000 ps | ||
| T15 | /workspace/coverage/default/2.prim_present_test.3542687914 | May 07 12:25:45 PM PDT 24 | May 07 12:26:46 PM PDT 24 | 10841940000 ps | ||
| T16 | /workspace/coverage/default/27.prim_present_test.540207366 | May 07 12:25:40 PM PDT 24 | May 07 12:26:03 PM PDT 24 | 3246940000 ps | ||
| T17 | /workspace/coverage/default/32.prim_present_test.1645074912 | May 07 12:25:38 PM PDT 24 | May 07 12:27:07 PM PDT 24 | 13579860000 ps | ||
| T18 | /workspace/coverage/default/19.prim_present_test.851739637 | May 07 12:25:43 PM PDT 24 | May 07 12:26:45 PM PDT 24 | 9883420000 ps | ||
| T19 | /workspace/coverage/default/33.prim_present_test.3074211471 | May 07 12:25:50 PM PDT 24 | May 07 12:26:13 PM PDT 24 | 3320100000 ps | ||
| T20 | /workspace/coverage/default/11.prim_present_test.330099666 | May 07 12:25:43 PM PDT 24 | May 07 12:26:41 PM PDT 24 | 9252880000 ps | ||
| T21 | /workspace/coverage/default/40.prim_present_test.366403708 | May 07 12:25:43 PM PDT 24 | May 07 12:26:20 PM PDT 24 | 6214880000 ps | ||
| T22 | /workspace/coverage/default/36.prim_present_test.204478544 | May 07 12:25:42 PM PDT 24 | May 07 12:26:50 PM PDT 24 | 9196460000 ps | ||
| T23 | /workspace/coverage/default/43.prim_present_test.4127301093 | May 07 12:25:42 PM PDT 24 | May 07 12:26:40 PM PDT 24 | 8620480000 ps | ||
| T24 | /workspace/coverage/default/44.prim_present_test.1087810482 | May 07 12:25:43 PM PDT 24 | May 07 12:26:53 PM PDT 24 | 11091180000 ps | ||
| T25 | /workspace/coverage/default/20.prim_present_test.1952552603 | May 07 12:25:42 PM PDT 24 | May 07 12:26:39 PM PDT 24 | 8446260000 ps | ||
| T26 | /workspace/coverage/default/42.prim_present_test.1910652996 | May 07 12:25:44 PM PDT 24 | May 07 12:26:45 PM PDT 24 | 8607460000 ps | ||
| T27 | /workspace/coverage/default/28.prim_present_test.456085205 | May 07 12:25:43 PM PDT 24 | May 07 12:27:21 PM PDT 24 | 15460940000 ps | ||
| T28 | /workspace/coverage/default/45.prim_present_test.4250072637 | May 07 12:25:45 PM PDT 24 | May 07 12:27:43 PM PDT 24 | 14855200000 ps | ||
| T29 | /workspace/coverage/default/0.prim_present_test.511773665 | May 07 12:25:43 PM PDT 24 | May 07 12:26:51 PM PDT 24 | 10574720000 ps | ||
| T30 | /workspace/coverage/default/7.prim_present_test.3926637323 | May 07 12:25:42 PM PDT 24 | May 07 12:27:23 PM PDT 24 | 14529700000 ps | ||
| T31 | /workspace/coverage/default/25.prim_present_test.1678009142 | May 07 12:25:46 PM PDT 24 | May 07 12:27:19 PM PDT 24 | 14849620000 ps | ||
| T32 | /workspace/coverage/default/47.prim_present_test.3749260576 | May 07 12:25:46 PM PDT 24 | May 07 12:26:35 PM PDT 24 | 5797000000 ps | ||
| T33 | /workspace/coverage/default/37.prim_present_test.714782558 | May 07 12:25:47 PM PDT 24 | May 07 12:26:25 PM PDT 24 | 5722600000 ps | ||
| T34 | /workspace/coverage/default/31.prim_present_test.3329716841 | May 07 12:25:44 PM PDT 24 | May 07 12:26:18 PM PDT 24 | 4242660000 ps | ||
| T35 | /workspace/coverage/default/4.prim_present_test.40219271 | May 07 12:25:39 PM PDT 24 | May 07 12:26:58 PM PDT 24 | 14314560000 ps | ||
| T36 | /workspace/coverage/default/22.prim_present_test.3795845577 | May 07 12:25:34 PM PDT 24 | May 07 12:26:14 PM PDT 24 | 5959440000 ps | ||
| T37 | /workspace/coverage/default/48.prim_present_test.4174673825 | May 07 12:25:45 PM PDT 24 | May 07 12:27:18 PM PDT 24 | 11135200000 ps | ||
| T38 | /workspace/coverage/default/15.prim_present_test.1777219714 | May 07 12:25:54 PM PDT 24 | May 07 12:26:54 PM PDT 24 | 8790360000 ps | ||
| T39 | /workspace/coverage/default/3.prim_present_test.2058825689 | May 07 12:25:46 PM PDT 24 | May 07 12:26:32 PM PDT 24 | 6785280000 ps | ||
| T40 | /workspace/coverage/default/23.prim_present_test.1885806418 | May 07 12:25:44 PM PDT 24 | May 07 12:27:31 PM PDT 24 | 12713720000 ps | ||
| T41 | /workspace/coverage/default/38.prim_present_test.928415985 | May 07 12:25:37 PM PDT 24 | May 07 12:26:04 PM PDT 24 | 4234600000 ps | ||
| T42 | /workspace/coverage/default/34.prim_present_test.3062821570 | May 07 12:25:44 PM PDT 24 | May 07 12:26:23 PM PDT 24 | 5057960000 ps | ||
| T43 | /workspace/coverage/default/49.prim_present_test.3785855178 | May 07 12:25:41 PM PDT 24 | May 07 12:27:00 PM PDT 24 | 9148720000 ps | ||
| T44 | /workspace/coverage/default/21.prim_present_test.301858334 | May 07 12:25:42 PM PDT 24 | May 07 12:26:51 PM PDT 24 | 10370120000 ps | ||
| T45 | /workspace/coverage/default/26.prim_present_test.2783062333 | May 07 12:25:37 PM PDT 24 | May 07 12:26:26 PM PDT 24 | 8329080000 ps | ||
| T46 | /workspace/coverage/default/39.prim_present_test.1392504690 | May 07 12:25:57 PM PDT 24 | May 07 12:27:25 PM PDT 24 | 13263040000 ps | ||
| T47 | /workspace/coverage/default/17.prim_present_test.1719779252 | May 07 12:25:41 PM PDT 24 | May 07 12:26:37 PM PDT 24 | 8396660000 ps | ||
| T48 | /workspace/coverage/default/14.prim_present_test.2769868498 | May 07 12:25:52 PM PDT 24 | May 07 12:27:19 PM PDT 24 | 12952420000 ps | ||
| T49 | /workspace/coverage/default/12.prim_present_test.2000677967 | May 07 12:25:39 PM PDT 24 | May 07 12:27:11 PM PDT 24 | 14455920000 ps | ||
| T50 | /workspace/coverage/default/46.prim_present_test.2191982515 | May 07 12:25:41 PM PDT 24 | May 07 12:27:13 PM PDT 24 | 10918200000 ps |
| Test location | /workspace/coverage/default/1.prim_present_test.427849258 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 11525800000 ps |
| CPU time | 36.34 seconds |
| Started | May 07 12:25:40 PM PDT 24 |
| Finished | May 07 12:26:49 PM PDT 24 |
| Peak memory | 144884 kb |
| Host | smart-d2e64c54-a473-44e2-b451-e891cbf2fa3d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=427849258 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.427849258 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/0.prim_present_test.511773665 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 10574720000 ps |
| CPU time | 36 seconds |
| Started | May 07 12:25:43 PM PDT 24 |
| Finished | May 07 12:26:51 PM PDT 24 |
| Peak memory | 144880 kb |
| Host | smart-fc5fc7b8-d951-45df-8d6f-d36d06535bcc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=511773665 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.511773665 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/10.prim_present_test.963884750 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 11652280000 ps |
| CPU time | 38.63 seconds |
| Started | May 07 12:25:41 PM PDT 24 |
| Finished | May 07 12:26:53 PM PDT 24 |
| Peak memory | 144952 kb |
| Host | smart-b6691bc2-dd7a-4adf-8f28-d6fee7123775 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=963884750 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.963884750 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/11.prim_present_test.330099666 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 9252880000 ps |
| CPU time | 30.91 seconds |
| Started | May 07 12:25:43 PM PDT 24 |
| Finished | May 07 12:26:41 PM PDT 24 |
| Peak memory | 144872 kb |
| Host | smart-20ff1cbd-60f1-4755-90c5-a38db9f2da81 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=330099666 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.330099666 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.2000677967 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 14455920000 ps |
| CPU time | 48.19 seconds |
| Started | May 07 12:25:39 PM PDT 24 |
| Finished | May 07 12:27:11 PM PDT 24 |
| Peak memory | 144920 kb |
| Host | smart-94a2e46a-6ba2-4340-821a-336445e6e862 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2000677967 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.2000677967 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.289626381 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 8741380000 ps |
| CPU time | 29.83 seconds |
| Started | May 07 12:25:41 PM PDT 24 |
| Finished | May 07 12:26:39 PM PDT 24 |
| Peak memory | 144960 kb |
| Host | smart-99d048a0-88bd-4ee4-aa2c-71bef24c8fcd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=289626381 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.289626381 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.2769868498 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 12952420000 ps |
| CPU time | 45.98 seconds |
| Started | May 07 12:25:52 PM PDT 24 |
| Finished | May 07 12:27:19 PM PDT 24 |
| Peak memory | 144880 kb |
| Host | smart-2cdf1321-a2b6-40b7-9a98-c14905dc81e8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2769868498 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.2769868498 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.1777219714 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 8790360000 ps |
| CPU time | 31.25 seconds |
| Started | May 07 12:25:54 PM PDT 24 |
| Finished | May 07 12:26:54 PM PDT 24 |
| Peak memory | 144972 kb |
| Host | smart-44515003-b99f-4fdc-b6bb-09806c745621 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1777219714 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.1777219714 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.1451088059 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 7875860000 ps |
| CPU time | 24.73 seconds |
| Started | May 07 12:25:45 PM PDT 24 |
| Finished | May 07 12:26:33 PM PDT 24 |
| Peak memory | 144760 kb |
| Host | smart-a6d9f97e-414f-4514-9a05-5fe006bcf3f5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1451088059 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.1451088059 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.1719779252 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 8396660000 ps |
| CPU time | 29.41 seconds |
| Started | May 07 12:25:41 PM PDT 24 |
| Finished | May 07 12:26:37 PM PDT 24 |
| Peak memory | 144864 kb |
| Host | smart-c508cec1-06cc-4e1f-830f-e588fe8d7db6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1719779252 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.1719779252 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.1547795377 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 11409240000 ps |
| CPU time | 38.07 seconds |
| Started | May 07 12:25:46 PM PDT 24 |
| Finished | May 07 12:26:59 PM PDT 24 |
| Peak memory | 144924 kb |
| Host | smart-30dea5c0-16fe-4b54-9dfc-05cb0c335e3f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1547795377 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.1547795377 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.851739637 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 9883420000 ps |
| CPU time | 32.5 seconds |
| Started | May 07 12:25:43 PM PDT 24 |
| Finished | May 07 12:26:45 PM PDT 24 |
| Peak memory | 144792 kb |
| Host | smart-fcdeca48-06a9-4ffc-a225-cf9bfbe686ad |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=851739637 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.851739637 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.3542687914 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 10841940000 ps |
| CPU time | 32.79 seconds |
| Started | May 07 12:25:45 PM PDT 24 |
| Finished | May 07 12:26:46 PM PDT 24 |
| Peak memory | 144672 kb |
| Host | smart-b1dfe8dd-8871-4158-a9ad-bb3623a3200f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3542687914 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.3542687914 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.1952552603 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 8446260000 ps |
| CPU time | 29.99 seconds |
| Started | May 07 12:25:42 PM PDT 24 |
| Finished | May 07 12:26:39 PM PDT 24 |
| Peak memory | 144944 kb |
| Host | smart-d9d512a2-d4f7-40d1-bb8a-bb35e73eed9e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1952552603 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.1952552603 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.301858334 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 10370120000 ps |
| CPU time | 36.04 seconds |
| Started | May 07 12:25:42 PM PDT 24 |
| Finished | May 07 12:26:51 PM PDT 24 |
| Peak memory | 144884 kb |
| Host | smart-2eb1e3ed-3634-480e-8ba6-0859823762dc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=301858334 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.301858334 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.3795845577 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 5959440000 ps |
| CPU time | 20.56 seconds |
| Started | May 07 12:25:34 PM PDT 24 |
| Finished | May 07 12:26:14 PM PDT 24 |
| Peak memory | 144800 kb |
| Host | smart-dc06ba28-9076-4142-a874-4418f9578ea4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3795845577 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.3795845577 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.1885806418 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 12713720000 ps |
| CPU time | 53.61 seconds |
| Started | May 07 12:25:44 PM PDT 24 |
| Finished | May 07 12:27:31 PM PDT 24 |
| Peak memory | 145152 kb |
| Host | smart-3e210caf-5e40-4c33-bc14-823e0f7fc306 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1885806418 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.1885806418 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.3725417510 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 8761220000 ps |
| CPU time | 28.8 seconds |
| Started | May 07 12:25:44 PM PDT 24 |
| Finished | May 07 12:26:39 PM PDT 24 |
| Peak memory | 144864 kb |
| Host | smart-9e5f4945-97ec-4020-97f5-8ef4f1f4ab95 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3725417510 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.3725417510 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.1678009142 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 14849620000 ps |
| CPU time | 48.94 seconds |
| Started | May 07 12:25:46 PM PDT 24 |
| Finished | May 07 12:27:19 PM PDT 24 |
| Peak memory | 144936 kb |
| Host | smart-f5429c52-7dfa-4a60-97db-55745cd121ca |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1678009142 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.1678009142 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.2783062333 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 8329080000 ps |
| CPU time | 26.02 seconds |
| Started | May 07 12:25:37 PM PDT 24 |
| Finished | May 07 12:26:26 PM PDT 24 |
| Peak memory | 144876 kb |
| Host | smart-0ea66214-dca5-4b91-aec8-b061333b3214 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2783062333 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.2783062333 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.540207366 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 3246940000 ps |
| CPU time | 11.64 seconds |
| Started | May 07 12:25:40 PM PDT 24 |
| Finished | May 07 12:26:03 PM PDT 24 |
| Peak memory | 144752 kb |
| Host | smart-f908e02f-8e15-41cc-bdc1-204d335229bc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=540207366 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.540207366 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.456085205 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 15460940000 ps |
| CPU time | 52.05 seconds |
| Started | May 07 12:25:43 PM PDT 24 |
| Finished | May 07 12:27:21 PM PDT 24 |
| Peak memory | 144952 kb |
| Host | smart-14f7ab6f-22b5-46e6-97e6-780d6362d9f0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=456085205 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.456085205 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.4073911249 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 15387780000 ps |
| CPU time | 50.5 seconds |
| Started | May 07 12:25:42 PM PDT 24 |
| Finished | May 07 12:27:18 PM PDT 24 |
| Peak memory | 144936 kb |
| Host | smart-22af18ff-0660-4ba1-bfc1-6675f2ec8a84 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4073911249 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.4073911249 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.2058825689 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 6785280000 ps |
| CPU time | 24.13 seconds |
| Started | May 07 12:25:46 PM PDT 24 |
| Finished | May 07 12:26:32 PM PDT 24 |
| Peak memory | 144952 kb |
| Host | smart-f8af647d-0fdf-425b-8425-540b582c9aa7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2058825689 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.2058825689 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.54950852 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 10796680000 ps |
| CPU time | 40.08 seconds |
| Started | May 07 12:25:43 PM PDT 24 |
| Finished | May 07 12:27:01 PM PDT 24 |
| Peak memory | 144948 kb |
| Host | smart-8a06eaa9-1a9b-4b00-b936-12c1285b21f5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=54950852 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.54950852 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.3329716841 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 4242660000 ps |
| CPU time | 17.36 seconds |
| Started | May 07 12:25:44 PM PDT 24 |
| Finished | May 07 12:26:18 PM PDT 24 |
| Peak memory | 144032 kb |
| Host | smart-8a7d721a-febe-45d6-8af8-c03c0acf85f1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3329716841 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.3329716841 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.1645074912 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 13579860000 ps |
| CPU time | 47.5 seconds |
| Started | May 07 12:25:38 PM PDT 24 |
| Finished | May 07 12:27:07 PM PDT 24 |
| Peak memory | 144892 kb |
| Host | smart-75f0c350-567b-4e30-be74-39a676ccf1e1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1645074912 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.1645074912 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.3074211471 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 3320100000 ps |
| CPU time | 11.75 seconds |
| Started | May 07 12:25:50 PM PDT 24 |
| Finished | May 07 12:26:13 PM PDT 24 |
| Peak memory | 144788 kb |
| Host | smart-5d0f691e-81ac-4062-8f31-565647f00794 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3074211471 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.3074211471 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.3062821570 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 5057960000 ps |
| CPU time | 19.83 seconds |
| Started | May 07 12:25:44 PM PDT 24 |
| Finished | May 07 12:26:23 PM PDT 24 |
| Peak memory | 143896 kb |
| Host | smart-65cbddec-27d8-4585-9086-93c20dc0c1c4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3062821570 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.3062821570 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.3490402617 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 12885460000 ps |
| CPU time | 39.39 seconds |
| Started | May 07 12:25:42 PM PDT 24 |
| Finished | May 07 12:26:56 PM PDT 24 |
| Peak memory | 144820 kb |
| Host | smart-2bd39bcc-d773-49c3-bfc0-4e2437fd751d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3490402617 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.3490402617 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.204478544 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 9196460000 ps |
| CPU time | 34.27 seconds |
| Started | May 07 12:25:42 PM PDT 24 |
| Finished | May 07 12:26:50 PM PDT 24 |
| Peak memory | 144936 kb |
| Host | smart-1519aaab-2907-403b-90b9-026d84cbe44d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=204478544 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.204478544 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.714782558 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 5722600000 ps |
| CPU time | 19.69 seconds |
| Started | May 07 12:25:47 PM PDT 24 |
| Finished | May 07 12:26:25 PM PDT 24 |
| Peak memory | 144780 kb |
| Host | smart-19c12a90-982f-48ee-8988-161d3ad84ce5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=714782558 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.714782558 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.928415985 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 4234600000 ps |
| CPU time | 13.86 seconds |
| Started | May 07 12:25:37 PM PDT 24 |
| Finished | May 07 12:26:04 PM PDT 24 |
| Peak memory | 144680 kb |
| Host | smart-68dca97e-665e-4d6c-b783-7d093d3386d1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=928415985 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.928415985 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.1392504690 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 13263040000 ps |
| CPU time | 46.66 seconds |
| Started | May 07 12:25:57 PM PDT 24 |
| Finished | May 07 12:27:25 PM PDT 24 |
| Peak memory | 144952 kb |
| Host | smart-5d8695d0-c3d1-44f2-ab5e-433e38477105 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1392504690 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.1392504690 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.40219271 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 14314560000 ps |
| CPU time | 42.47 seconds |
| Started | May 07 12:25:39 PM PDT 24 |
| Finished | May 07 12:26:58 PM PDT 24 |
| Peak memory | 144008 kb |
| Host | smart-cd24c216-9f7e-49c6-b7ab-e3837c69b79d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=40219271 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.40219271 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.366403708 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 6214880000 ps |
| CPU time | 19.72 seconds |
| Started | May 07 12:25:43 PM PDT 24 |
| Finished | May 07 12:26:20 PM PDT 24 |
| Peak memory | 144960 kb |
| Host | smart-1d126924-c0c1-40ae-8cfc-34e1aed34ac3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=366403708 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.366403708 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.1701653944 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 8394180000 ps |
| CPU time | 31.3 seconds |
| Started | May 07 12:25:46 PM PDT 24 |
| Finished | May 07 12:26:47 PM PDT 24 |
| Peak memory | 144880 kb |
| Host | smart-2b1c4aea-4e7f-4c43-b509-dd1c1d59e8ae |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1701653944 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.1701653944 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.1910652996 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 8607460000 ps |
| CPU time | 32.13 seconds |
| Started | May 07 12:25:44 PM PDT 24 |
| Finished | May 07 12:26:45 PM PDT 24 |
| Peak memory | 144384 kb |
| Host | smart-2e78db46-c15d-45ce-88d6-4fcc091048f1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1910652996 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.1910652996 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.4127301093 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 8620480000 ps |
| CPU time | 30.44 seconds |
| Started | May 07 12:25:42 PM PDT 24 |
| Finished | May 07 12:26:40 PM PDT 24 |
| Peak memory | 144948 kb |
| Host | smart-5e3e3bbf-2ab8-41a5-8091-d663fbe12fe8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4127301093 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.4127301093 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.1087810482 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 11091180000 ps |
| CPU time | 36.95 seconds |
| Started | May 07 12:25:43 PM PDT 24 |
| Finished | May 07 12:26:53 PM PDT 24 |
| Peak memory | 144788 kb |
| Host | smart-a3ff9067-b1ef-49ba-a562-88a766a050a0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1087810482 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.1087810482 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.4250072637 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 14855200000 ps |
| CPU time | 59.17 seconds |
| Started | May 07 12:25:45 PM PDT 24 |
| Finished | May 07 12:27:43 PM PDT 24 |
| Peak memory | 144924 kb |
| Host | smart-54420b34-2b73-4133-960a-0befc55a629b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4250072637 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.4250072637 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.2191982515 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 10918200000 ps |
| CPU time | 45.99 seconds |
| Started | May 07 12:25:41 PM PDT 24 |
| Finished | May 07 12:27:13 PM PDT 24 |
| Peak memory | 145112 kb |
| Host | smart-a47cdb00-7cb0-417a-ac2c-da19f077a300 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2191982515 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.2191982515 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.3749260576 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 5797000000 ps |
| CPU time | 23.77 seconds |
| Started | May 07 12:25:46 PM PDT 24 |
| Finished | May 07 12:26:35 PM PDT 24 |
| Peak memory | 145004 kb |
| Host | smart-b4e5215f-fe64-4856-89fd-0c08e87940bc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3749260576 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.3749260576 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.4174673825 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 11135200000 ps |
| CPU time | 46.37 seconds |
| Started | May 07 12:25:45 PM PDT 24 |
| Finished | May 07 12:27:18 PM PDT 24 |
| Peak memory | 145112 kb |
| Host | smart-8944013a-aec8-4388-8322-dbcb92e5179e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4174673825 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.4174673825 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.3785855178 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 9148720000 ps |
| CPU time | 39.38 seconds |
| Started | May 07 12:25:41 PM PDT 24 |
| Finished | May 07 12:27:00 PM PDT 24 |
| Peak memory | 145112 kb |
| Host | smart-76549cb6-bfde-4563-89af-3783f51172bf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3785855178 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.3785855178 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.1284853533 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 5307820000 ps |
| CPU time | 17.49 seconds |
| Started | May 07 12:25:37 PM PDT 24 |
| Finished | May 07 12:26:10 PM PDT 24 |
| Peak memory | 144888 kb |
| Host | smart-ec5fb255-3962-4123-808b-f1636c3613cb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1284853533 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.1284853533 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.1710316193 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 3509200000 ps |
| CPU time | 11.85 seconds |
| Started | May 07 12:25:36 PM PDT 24 |
| Finished | May 07 12:25:59 PM PDT 24 |
| Peak memory | 144804 kb |
| Host | smart-a38125c6-d776-4556-919d-08e895466e18 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1710316193 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.1710316193 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.3926637323 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 14529700000 ps |
| CPU time | 51.96 seconds |
| Started | May 07 12:25:42 PM PDT 24 |
| Finished | May 07 12:27:23 PM PDT 24 |
| Peak memory | 144936 kb |
| Host | smart-633e2588-baf2-4675-bd1a-89410a426622 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3926637323 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.3926637323 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.1850048830 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 6223560000 ps |
| CPU time | 20.52 seconds |
| Started | May 07 12:25:38 PM PDT 24 |
| Finished | May 07 12:26:17 PM PDT 24 |
| Peak memory | 144792 kb |
| Host | smart-fa0d1e5d-39e3-4c59-b39c-c483d396f112 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1850048830 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.1850048830 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.3785149624 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 3775180000 ps |
| CPU time | 14.86 seconds |
| Started | May 07 12:25:47 PM PDT 24 |
| Finished | May 07 12:26:17 PM PDT 24 |
| Peak memory | 144512 kb |
| Host | smart-bb188a94-0104-4bb1-b2ea-afef695421f8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3785149624 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.3785149624 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |