| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/1.prim_present_test.1618910914 | ||
| Name |
|---|
| /workspace/coverage/default/0.prim_present_test.1086531921 |
| /workspace/coverage/default/10.prim_present_test.1040704936 |
| /workspace/coverage/default/11.prim_present_test.2343987767 |
| /workspace/coverage/default/12.prim_present_test.1818734232 |
| /workspace/coverage/default/13.prim_present_test.3321854778 |
| /workspace/coverage/default/14.prim_present_test.1564360622 |
| /workspace/coverage/default/15.prim_present_test.3883412223 |
| /workspace/coverage/default/16.prim_present_test.2863433620 |
| /workspace/coverage/default/17.prim_present_test.3014049226 |
| /workspace/coverage/default/18.prim_present_test.2816138790 |
| /workspace/coverage/default/19.prim_present_test.1348668209 |
| /workspace/coverage/default/2.prim_present_test.1215856496 |
| /workspace/coverage/default/20.prim_present_test.1106651634 |
| /workspace/coverage/default/21.prim_present_test.4229822128 |
| /workspace/coverage/default/22.prim_present_test.621153987 |
| /workspace/coverage/default/23.prim_present_test.2117003274 |
| /workspace/coverage/default/24.prim_present_test.1159137219 |
| /workspace/coverage/default/25.prim_present_test.4029989531 |
| /workspace/coverage/default/26.prim_present_test.1442580819 |
| /workspace/coverage/default/27.prim_present_test.3604595438 |
| /workspace/coverage/default/28.prim_present_test.2117762712 |
| /workspace/coverage/default/29.prim_present_test.2081384884 |
| /workspace/coverage/default/3.prim_present_test.2491855071 |
| /workspace/coverage/default/30.prim_present_test.4206959924 |
| /workspace/coverage/default/31.prim_present_test.2094747367 |
| /workspace/coverage/default/32.prim_present_test.2662174390 |
| /workspace/coverage/default/33.prim_present_test.1870445129 |
| /workspace/coverage/default/34.prim_present_test.3626711093 |
| /workspace/coverage/default/35.prim_present_test.1093665599 |
| /workspace/coverage/default/36.prim_present_test.3198801867 |
| /workspace/coverage/default/37.prim_present_test.1341922525 |
| /workspace/coverage/default/38.prim_present_test.2461269314 |
| /workspace/coverage/default/39.prim_present_test.3904982558 |
| /workspace/coverage/default/4.prim_present_test.2538454633 |
| /workspace/coverage/default/40.prim_present_test.3557937316 |
| /workspace/coverage/default/41.prim_present_test.2388204513 |
| /workspace/coverage/default/42.prim_present_test.1183014990 |
| /workspace/coverage/default/43.prim_present_test.2033153466 |
| /workspace/coverage/default/44.prim_present_test.2622988170 |
| /workspace/coverage/default/45.prim_present_test.162943813 |
| /workspace/coverage/default/46.prim_present_test.329038272 |
| /workspace/coverage/default/47.prim_present_test.342349409 |
| /workspace/coverage/default/48.prim_present_test.3005899898 |
| /workspace/coverage/default/49.prim_present_test.251053132 |
| /workspace/coverage/default/5.prim_present_test.4031522296 |
| /workspace/coverage/default/6.prim_present_test.551687782 |
| /workspace/coverage/default/7.prim_present_test.3989437595 |
| /workspace/coverage/default/8.prim_present_test.156871922 |
| /workspace/coverage/default/9.prim_present_test.1126075484 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/21.prim_present_test.4229822128 | May 09 01:02:42 PM PDT 24 | May 09 01:03:33 PM PDT 24 | 6747460000 ps | ||
| T2 | /workspace/coverage/default/6.prim_present_test.551687782 | May 09 01:02:44 PM PDT 24 | May 09 01:03:14 PM PDT 24 | 4297840000 ps | ||
| T3 | /workspace/coverage/default/30.prim_present_test.4206959924 | May 09 01:02:47 PM PDT 24 | May 09 01:03:29 PM PDT 24 | 5307820000 ps | ||
| T4 | /workspace/coverage/default/27.prim_present_test.3604595438 | May 09 01:02:48 PM PDT 24 | May 09 01:03:50 PM PDT 24 | 9564120000 ps | ||
| T5 | /workspace/coverage/default/36.prim_present_test.3198801867 | May 09 01:02:49 PM PDT 24 | May 09 01:03:21 PM PDT 24 | 3879340000 ps | ||
| T6 | /workspace/coverage/default/19.prim_present_test.1348668209 | May 09 01:02:37 PM PDT 24 | May 09 01:04:16 PM PDT 24 | 13331860000 ps | ||
| T7 | /workspace/coverage/default/17.prim_present_test.3014049226 | May 09 01:02:36 PM PDT 24 | May 09 01:03:45 PM PDT 24 | 9645340000 ps | ||
| T8 | /workspace/coverage/default/1.prim_present_test.1618910914 | May 09 01:02:38 PM PDT 24 | May 09 01:03:14 PM PDT 24 | 4822980000 ps | ||
| T9 | /workspace/coverage/default/31.prim_present_test.2094747367 | May 09 01:02:52 PM PDT 24 | May 09 01:03:40 PM PDT 24 | 7006000000 ps | ||
| T10 | /workspace/coverage/default/43.prim_present_test.2033153466 | May 09 01:02:48 PM PDT 24 | May 09 01:03:23 PM PDT 24 | 4462140000 ps | ||
| T11 | /workspace/coverage/default/24.prim_present_test.1159137219 | May 09 01:02:43 PM PDT 24 | May 09 01:03:19 PM PDT 24 | 4622100000 ps | ||
| T12 | /workspace/coverage/default/5.prim_present_test.4031522296 | May 09 01:02:36 PM PDT 24 | May 09 01:03:54 PM PDT 24 | 11191000000 ps | ||
| T13 | /workspace/coverage/default/14.prim_present_test.1564360622 | May 09 01:02:41 PM PDT 24 | May 09 01:04:18 PM PDT 24 | 13045420000 ps | ||
| T14 | /workspace/coverage/default/8.prim_present_test.156871922 | May 09 01:02:38 PM PDT 24 | May 09 01:03:20 PM PDT 24 | 5500020000 ps | ||
| T15 | /workspace/coverage/default/13.prim_present_test.3321854778 | May 09 01:02:46 PM PDT 24 | May 09 01:04:18 PM PDT 24 | 14658040000 ps | ||
| T16 | /workspace/coverage/default/44.prim_present_test.2622988170 | May 09 01:02:50 PM PDT 24 | May 09 01:04:23 PM PDT 24 | 12223300000 ps | ||
| T17 | /workspace/coverage/default/3.prim_present_test.2491855071 | May 09 01:02:39 PM PDT 24 | May 09 01:03:54 PM PDT 24 | 9790420000 ps | ||
| T18 | /workspace/coverage/default/40.prim_present_test.3557937316 | May 09 01:02:47 PM PDT 24 | May 09 01:03:53 PM PDT 24 | 9026580000 ps | ||
| T19 | /workspace/coverage/default/0.prim_present_test.1086531921 | May 09 01:02:37 PM PDT 24 | May 09 01:03:33 PM PDT 24 | 8438200000 ps | ||
| T20 | /workspace/coverage/default/12.prim_present_test.1818734232 | May 09 01:02:41 PM PDT 24 | May 09 01:04:25 PM PDT 24 | 14021920000 ps | ||
| T21 | /workspace/coverage/default/23.prim_present_test.2117003274 | May 09 01:02:38 PM PDT 24 | May 09 01:04:35 PM PDT 24 | 15442340000 ps | ||
| T22 | /workspace/coverage/default/49.prim_present_test.251053132 | May 09 01:02:52 PM PDT 24 | May 09 01:04:00 PM PDT 24 | 9616820000 ps | ||
| T23 | /workspace/coverage/default/47.prim_present_test.342349409 | May 09 01:02:47 PM PDT 24 | May 09 01:04:25 PM PDT 24 | 13108040000 ps | ||
| T24 | /workspace/coverage/default/2.prim_present_test.1215856496 | May 09 01:02:40 PM PDT 24 | May 09 01:03:59 PM PDT 24 | 10463120000 ps | ||
| T25 | /workspace/coverage/default/4.prim_present_test.2538454633 | May 09 01:02:45 PM PDT 24 | May 09 01:03:32 PM PDT 24 | 6995460000 ps | ||
| T26 | /workspace/coverage/default/28.prim_present_test.2117762712 | May 09 01:02:49 PM PDT 24 | May 09 01:04:20 PM PDT 24 | 13294660000 ps | ||
| T27 | /workspace/coverage/default/10.prim_present_test.1040704936 | May 09 01:02:41 PM PDT 24 | May 09 01:04:09 PM PDT 24 | 11952360000 ps | ||
| T28 | /workspace/coverage/default/22.prim_present_test.621153987 | May 09 01:02:41 PM PDT 24 | May 09 01:04:09 PM PDT 24 | 14566900000 ps | ||
| T29 | /workspace/coverage/default/16.prim_present_test.2863433620 | May 09 01:02:38 PM PDT 24 | May 09 01:03:56 PM PDT 24 | 11502860000 ps | ||
| T30 | /workspace/coverage/default/18.prim_present_test.2816138790 | May 09 01:02:38 PM PDT 24 | May 09 01:03:06 PM PDT 24 | 3344280000 ps | ||
| T31 | /workspace/coverage/default/15.prim_present_test.3883412223 | May 09 01:02:40 PM PDT 24 | May 09 01:04:07 PM PDT 24 | 11750240000 ps | ||
| T32 | /workspace/coverage/default/46.prim_present_test.329038272 | May 09 01:02:48 PM PDT 24 | May 09 01:03:40 PM PDT 24 | 7937240000 ps | ||
| T33 | /workspace/coverage/default/37.prim_present_test.1341922525 | May 09 01:02:48 PM PDT 24 | May 09 01:03:23 PM PDT 24 | 4700840000 ps | ||
| T34 | /workspace/coverage/default/39.prim_present_test.3904982558 | May 09 01:02:45 PM PDT 24 | May 09 01:03:46 PM PDT 24 | 10010520000 ps | ||
| T35 | /workspace/coverage/default/32.prim_present_test.2662174390 | May 09 01:02:51 PM PDT 24 | May 09 01:03:27 PM PDT 24 | 5052380000 ps | ||
| T36 | /workspace/coverage/default/38.prim_present_test.2461269314 | May 09 01:02:50 PM PDT 24 | May 09 01:03:42 PM PDT 24 | 8624820000 ps | ||
| T37 | /workspace/coverage/default/29.prim_present_test.2081384884 | May 09 01:02:49 PM PDT 24 | May 09 01:03:27 PM PDT 24 | 5064160000 ps | ||
| T38 | /workspace/coverage/default/26.prim_present_test.1442580819 | May 09 01:02:50 PM PDT 24 | May 09 01:04:08 PM PDT 24 | 11028560000 ps | ||
| T39 | /workspace/coverage/default/25.prim_present_test.4029989531 | May 09 01:02:47 PM PDT 24 | May 09 01:03:35 PM PDT 24 | 6957020000 ps | ||
| T40 | /workspace/coverage/default/11.prim_present_test.2343987767 | May 09 01:02:40 PM PDT 24 | May 09 01:03:15 PM PDT 24 | 5582480000 ps | ||
| T41 | /workspace/coverage/default/45.prim_present_test.162943813 | May 09 01:02:49 PM PDT 24 | May 09 01:04:28 PM PDT 24 | 13593500000 ps | ||
| T42 | /workspace/coverage/default/41.prim_present_test.2388204513 | May 09 01:02:48 PM PDT 24 | May 09 01:03:21 PM PDT 24 | 4265600000 ps | ||
| T43 | /workspace/coverage/default/20.prim_present_test.1106651634 | May 09 01:02:39 PM PDT 24 | May 09 01:04:02 PM PDT 24 | 13351700000 ps | ||
| T44 | /workspace/coverage/default/33.prim_present_test.1870445129 | May 09 01:02:48 PM PDT 24 | May 09 01:03:17 PM PDT 24 | 3687140000 ps | ||
| T45 | /workspace/coverage/default/9.prim_present_test.1126075484 | May 09 01:02:37 PM PDT 24 | May 09 01:04:25 PM PDT 24 | 14842180000 ps | ||
| T46 | /workspace/coverage/default/35.prim_present_test.1093665599 | May 09 01:02:51 PM PDT 24 | May 09 01:03:33 PM PDT 24 | 5880700000 ps | ||
| T47 | /workspace/coverage/default/42.prim_present_test.1183014990 | May 09 01:02:49 PM PDT 24 | May 09 01:03:27 PM PDT 24 | 4715100000 ps | ||
| T48 | /workspace/coverage/default/34.prim_present_test.3626711093 | May 09 01:02:47 PM PDT 24 | May 09 01:04:25 PM PDT 24 | 13212820000 ps | ||
| T49 | /workspace/coverage/default/7.prim_present_test.3989437595 | May 09 01:02:41 PM PDT 24 | May 09 01:03:52 PM PDT 24 | 9495300000 ps | ||
| T50 | /workspace/coverage/default/48.prim_present_test.3005899898 | May 09 01:02:48 PM PDT 24 | May 09 01:04:25 PM PDT 24 | 14374700000 ps |
| Test location | /workspace/coverage/default/1.prim_present_test.1618910914 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 4822980000 ps |
| CPU time | 17.32 seconds |
| Started | May 09 01:02:38 PM PDT 24 |
| Finished | May 09 01:03:14 PM PDT 24 |
| Peak memory | 145212 kb |
| Host | smart-f05edcc5-ba6a-4586-9ef7-d166927cb674 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1618910914 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.1618910914 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/0.prim_present_test.1086531921 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 8438200000 ps |
| CPU time | 28.73 seconds |
| Started | May 09 01:02:37 PM PDT 24 |
| Finished | May 09 01:03:33 PM PDT 24 |
| Peak memory | 145212 kb |
| Host | smart-9392baa1-4c35-4b5d-b65b-8ddb6730cef5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1086531921 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.1086531921 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/10.prim_present_test.1040704936 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 11952360000 ps |
| CPU time | 44.29 seconds |
| Started | May 09 01:02:41 PM PDT 24 |
| Finished | May 09 01:04:09 PM PDT 24 |
| Peak memory | 145160 kb |
| Host | smart-011f54e1-9c4c-4f25-9719-0c2361dd1ffd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1040704936 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.1040704936 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/11.prim_present_test.2343987767 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 5582480000 ps |
| CPU time | 17.3 seconds |
| Started | May 09 01:02:40 PM PDT 24 |
| Finished | May 09 01:03:15 PM PDT 24 |
| Peak memory | 145216 kb |
| Host | smart-c0a17949-6abc-4e47-ab31-aca3e1f6b879 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2343987767 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.2343987767 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.1818734232 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 14021920000 ps |
| CPU time | 52.21 seconds |
| Started | May 09 01:02:41 PM PDT 24 |
| Finished | May 09 01:04:25 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-ec88e3fa-3f4e-4b7e-8573-a9d2758529fd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1818734232 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.1818734232 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.3321854778 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 14658040000 ps |
| CPU time | 48.07 seconds |
| Started | May 09 01:02:46 PM PDT 24 |
| Finished | May 09 01:04:18 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-e99d8a12-cc27-4b18-8830-4a920cb04ec1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3321854778 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.3321854778 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.1564360622 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 13045420000 ps |
| CPU time | 48.93 seconds |
| Started | May 09 01:02:41 PM PDT 24 |
| Finished | May 09 01:04:18 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-15bb63b6-aaf9-4d9c-9ebe-45d3d903c480 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1564360622 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.1564360622 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.3883412223 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 11750240000 ps |
| CPU time | 43.13 seconds |
| Started | May 09 01:02:40 PM PDT 24 |
| Finished | May 09 01:04:07 PM PDT 24 |
| Peak memory | 145160 kb |
| Host | smart-0d09d628-0be0-473b-96e9-5861da163ee7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3883412223 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.3883412223 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.2863433620 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 11502860000 ps |
| CPU time | 39.55 seconds |
| Started | May 09 01:02:38 PM PDT 24 |
| Finished | May 09 01:03:56 PM PDT 24 |
| Peak memory | 144988 kb |
| Host | smart-4021d184-7199-444f-a6a9-7c2a4d930291 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2863433620 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.2863433620 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.3014049226 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 9645340000 ps |
| CPU time | 34.06 seconds |
| Started | May 09 01:02:36 PM PDT 24 |
| Finished | May 09 01:03:45 PM PDT 24 |
| Peak memory | 145164 kb |
| Host | smart-8d4cf75e-bb14-4388-86e0-5429c97f86d2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3014049226 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.3014049226 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.2816138790 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 3344280000 ps |
| CPU time | 12.94 seconds |
| Started | May 09 01:02:38 PM PDT 24 |
| Finished | May 09 01:03:06 PM PDT 24 |
| Peak memory | 144864 kb |
| Host | smart-22b9f348-5946-4d2d-9bab-1754dbbf0d23 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2816138790 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.2816138790 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.1348668209 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 13331860000 ps |
| CPU time | 50.14 seconds |
| Started | May 09 01:02:37 PM PDT 24 |
| Finished | May 09 01:04:16 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-70201635-e419-4ecf-bd1c-70fa73e6af11 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1348668209 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.1348668209 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.1215856496 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 10463120000 ps |
| CPU time | 39 seconds |
| Started | May 09 01:02:40 PM PDT 24 |
| Finished | May 09 01:03:59 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-5189d149-17c3-4e3e-a5fe-e03dc1bea37b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1215856496 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.1215856496 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.1106651634 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 13351700000 ps |
| CPU time | 42.9 seconds |
| Started | May 09 01:02:39 PM PDT 24 |
| Finished | May 09 01:04:02 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-6bd7b826-537c-4c94-a81b-3b0747336154 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1106651634 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.1106651634 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.4229822128 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 6747460000 ps |
| CPU time | 24.88 seconds |
| Started | May 09 01:02:42 PM PDT 24 |
| Finished | May 09 01:03:33 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-13ead9f1-284d-4fa6-82f0-c92948c6b4d9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4229822128 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.4229822128 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.621153987 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 14566900000 ps |
| CPU time | 46.27 seconds |
| Started | May 09 01:02:41 PM PDT 24 |
| Finished | May 09 01:04:09 PM PDT 24 |
| Peak memory | 145216 kb |
| Host | smart-0a0793be-c17a-4125-9596-06033bc1908a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=621153987 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.621153987 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.2117003274 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 15442340000 ps |
| CPU time | 59.55 seconds |
| Started | May 09 01:02:38 PM PDT 24 |
| Finished | May 09 01:04:35 PM PDT 24 |
| Peak memory | 145108 kb |
| Host | smart-a3734bbb-3386-4beb-a7b0-8daed923bdf0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2117003274 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.2117003274 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.1159137219 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 4622100000 ps |
| CPU time | 17.36 seconds |
| Started | May 09 01:02:43 PM PDT 24 |
| Finished | May 09 01:03:19 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-35dd068f-eda8-4f14-990c-fb883c742dbd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1159137219 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.1159137219 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.4029989531 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 6957020000 ps |
| CPU time | 24.66 seconds |
| Started | May 09 01:02:47 PM PDT 24 |
| Finished | May 09 01:03:35 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-e586ddd8-6d64-4dad-8132-beec59bf51d6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4029989531 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.4029989531 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.1442580819 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 11028560000 ps |
| CPU time | 40.24 seconds |
| Started | May 09 01:02:50 PM PDT 24 |
| Finished | May 09 01:04:08 PM PDT 24 |
| Peak memory | 145160 kb |
| Host | smart-b076c369-40c8-408e-8b03-552311c34605 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1442580819 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.1442580819 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.3604595438 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 9564120000 ps |
| CPU time | 32.47 seconds |
| Started | May 09 01:02:48 PM PDT 24 |
| Finished | May 09 01:03:50 PM PDT 24 |
| Peak memory | 145088 kb |
| Host | smart-0d8e51b4-e47b-4dee-880c-8116b3c1510a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3604595438 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.3604595438 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.2117762712 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 13294660000 ps |
| CPU time | 47.43 seconds |
| Started | May 09 01:02:49 PM PDT 24 |
| Finished | May 09 01:04:20 PM PDT 24 |
| Peak memory | 145132 kb |
| Host | smart-d069024c-7d8a-44f4-a813-ca6cf98b6126 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2117762712 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.2117762712 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.2081384884 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 5064160000 ps |
| CPU time | 18.92 seconds |
| Started | May 09 01:02:49 PM PDT 24 |
| Finished | May 09 01:03:27 PM PDT 24 |
| Peak memory | 145156 kb |
| Host | smart-10e0f215-0d1b-41a7-a938-5bc54bf723d5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2081384884 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.2081384884 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.2491855071 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 9790420000 ps |
| CPU time | 38.23 seconds |
| Started | May 09 01:02:39 PM PDT 24 |
| Finished | May 09 01:03:54 PM PDT 24 |
| Peak memory | 145148 kb |
| Host | smart-bba14491-c9f1-43be-9b3f-e8ff5966f56b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2491855071 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.2491855071 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.4206959924 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 5307820000 ps |
| CPU time | 20.27 seconds |
| Started | May 09 01:02:47 PM PDT 24 |
| Finished | May 09 01:03:29 PM PDT 24 |
| Peak memory | 145120 kb |
| Host | smart-9b5cd47b-4f29-42b4-b61d-f6a7ce5848d1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4206959924 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.4206959924 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.2094747367 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 7006000000 ps |
| CPU time | 24.62 seconds |
| Started | May 09 01:02:52 PM PDT 24 |
| Finished | May 09 01:03:40 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-dd9de80f-734a-46bd-99c6-6d07de2d4ae4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2094747367 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.2094747367 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.2662174390 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 5052380000 ps |
| CPU time | 18.24 seconds |
| Started | May 09 01:02:51 PM PDT 24 |
| Finished | May 09 01:03:27 PM PDT 24 |
| Peak memory | 145144 kb |
| Host | smart-356f6b8b-cc88-47fc-b394-d2bbc9e508e3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2662174390 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.2662174390 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.1870445129 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 3687140000 ps |
| CPU time | 14.13 seconds |
| Started | May 09 01:02:48 PM PDT 24 |
| Finished | May 09 01:03:17 PM PDT 24 |
| Peak memory | 145016 kb |
| Host | smart-7ba4ee64-b96b-4766-baf1-6a475444d181 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1870445129 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.1870445129 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.3626711093 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 13212820000 ps |
| CPU time | 50.72 seconds |
| Started | May 09 01:02:47 PM PDT 24 |
| Finished | May 09 01:04:25 PM PDT 24 |
| Peak memory | 145160 kb |
| Host | smart-66d1cad9-d164-48d1-8820-3c57935dab60 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3626711093 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.3626711093 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.1093665599 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 5880700000 ps |
| CPU time | 21.38 seconds |
| Started | May 09 01:02:51 PM PDT 24 |
| Finished | May 09 01:03:33 PM PDT 24 |
| Peak memory | 145144 kb |
| Host | smart-5e46072f-6cf2-4869-8f18-0979c95c9bea |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1093665599 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.1093665599 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.3198801867 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 3879340000 ps |
| CPU time | 15.62 seconds |
| Started | May 09 01:02:49 PM PDT 24 |
| Finished | May 09 01:03:21 PM PDT 24 |
| Peak memory | 144988 kb |
| Host | smart-cd00dbe7-0f6d-405b-8155-37f5b5411b58 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3198801867 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.3198801867 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.1341922525 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 4700840000 ps |
| CPU time | 17.49 seconds |
| Started | May 09 01:02:48 PM PDT 24 |
| Finished | May 09 01:03:23 PM PDT 24 |
| Peak memory | 145100 kb |
| Host | smart-03016712-d5a2-46e6-b7fa-43c0e28d3900 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1341922525 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.1341922525 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.2461269314 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 8624820000 ps |
| CPU time | 27.18 seconds |
| Started | May 09 01:02:50 PM PDT 24 |
| Finished | May 09 01:03:42 PM PDT 24 |
| Peak memory | 145064 kb |
| Host | smart-99a78712-8b0c-484f-880a-6b1fcf07fe8c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2461269314 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.2461269314 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.3904982558 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 10010520000 ps |
| CPU time | 32.25 seconds |
| Started | May 09 01:02:45 PM PDT 24 |
| Finished | May 09 01:03:46 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-d9901bc8-59c9-42e5-b1b3-82386421f640 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3904982558 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.3904982558 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.2538454633 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 6995460000 ps |
| CPU time | 23.95 seconds |
| Started | May 09 01:02:45 PM PDT 24 |
| Finished | May 09 01:03:32 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-21ebf253-7066-49f3-b322-64b77262c98a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2538454633 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.2538454633 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.3557937316 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 9026580000 ps |
| CPU time | 34.39 seconds |
| Started | May 09 01:02:47 PM PDT 24 |
| Finished | May 09 01:03:53 PM PDT 24 |
| Peak memory | 145156 kb |
| Host | smart-6135aacb-ac34-4a10-bc7b-b240fb56071f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3557937316 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.3557937316 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.2388204513 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 4265600000 ps |
| CPU time | 16.3 seconds |
| Started | May 09 01:02:48 PM PDT 24 |
| Finished | May 09 01:03:21 PM PDT 24 |
| Peak memory | 145012 kb |
| Host | smart-65f8ec24-7dd2-4dcf-9cfb-c8551db70868 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2388204513 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.2388204513 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.1183014990 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 4715100000 ps |
| CPU time | 18.96 seconds |
| Started | May 09 01:02:49 PM PDT 24 |
| Finished | May 09 01:03:27 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-471113f4-7bcf-41f7-ab6f-cd90103e0232 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1183014990 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.1183014990 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.2033153466 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 4462140000 ps |
| CPU time | 16.86 seconds |
| Started | May 09 01:02:48 PM PDT 24 |
| Finished | May 09 01:03:23 PM PDT 24 |
| Peak memory | 145160 kb |
| Host | smart-319dbc2f-8138-48c9-9734-dbbf9c46def2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2033153466 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.2033153466 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.2622988170 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 12223300000 ps |
| CPU time | 48.56 seconds |
| Started | May 09 01:02:50 PM PDT 24 |
| Finished | May 09 01:04:23 PM PDT 24 |
| Peak memory | 145148 kb |
| Host | smart-541e0e0c-a1d3-4692-8c2d-9907e0d4a996 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2622988170 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.2622988170 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.162943813 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 13593500000 ps |
| CPU time | 50.55 seconds |
| Started | May 09 01:02:49 PM PDT 24 |
| Finished | May 09 01:04:28 PM PDT 24 |
| Peak memory | 145144 kb |
| Host | smart-1e417c06-3255-46d0-9940-bc215e30488a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=162943813 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.162943813 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.329038272 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 7937240000 ps |
| CPU time | 27.34 seconds |
| Started | May 09 01:02:48 PM PDT 24 |
| Finished | May 09 01:03:40 PM PDT 24 |
| Peak memory | 145088 kb |
| Host | smart-6073216a-3e53-4427-ba6e-5e79a2dd90fd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=329038272 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.329038272 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.342349409 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 13108040000 ps |
| CPU time | 50.19 seconds |
| Started | May 09 01:02:47 PM PDT 24 |
| Finished | May 09 01:04:25 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-3c0395f0-52f0-406b-bb57-8655b3a2362e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=342349409 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.342349409 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.3005899898 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 14374700000 ps |
| CPU time | 50.89 seconds |
| Started | May 09 01:02:48 PM PDT 24 |
| Finished | May 09 01:04:25 PM PDT 24 |
| Peak memory | 145140 kb |
| Host | smart-7472e428-bf38-49af-9759-23b1e84a3268 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3005899898 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.3005899898 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.251053132 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 9616820000 ps |
| CPU time | 34.7 seconds |
| Started | May 09 01:02:52 PM PDT 24 |
| Finished | May 09 01:04:00 PM PDT 24 |
| Peak memory | 145196 kb |
| Host | smart-e3221a4f-77ff-4635-b717-820d54f230f5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=251053132 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.251053132 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.4031522296 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 11191000000 ps |
| CPU time | 38.94 seconds |
| Started | May 09 01:02:36 PM PDT 24 |
| Finished | May 09 01:03:54 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-84125e86-bdc9-4ef1-a3b9-03b48f7709c0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4031522296 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.4031522296 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.551687782 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 4297840000 ps |
| CPU time | 14.72 seconds |
| Started | May 09 01:02:44 PM PDT 24 |
| Finished | May 09 01:03:14 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-070b5799-abf4-429d-8404-88fc26514206 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=551687782 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.551687782 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.3989437595 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 9495300000 ps |
| CPU time | 35.56 seconds |
| Started | May 09 01:02:41 PM PDT 24 |
| Finished | May 09 01:03:52 PM PDT 24 |
| Peak memory | 145224 kb |
| Host | smart-60a8711d-890e-4813-b3fa-fb7828d799cd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3989437595 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.3989437595 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.156871922 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 5500020000 ps |
| CPU time | 20.43 seconds |
| Started | May 09 01:02:38 PM PDT 24 |
| Finished | May 09 01:03:20 PM PDT 24 |
| Peak memory | 144996 kb |
| Host | smart-76073abe-1894-4446-a816-7d2b07ae57d4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=156871922 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.156871922 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.1126075484 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 14842180000 ps |
| CPU time | 55.54 seconds |
| Started | May 09 01:02:37 PM PDT 24 |
| Finished | May 09 01:04:25 PM PDT 24 |
| Peak memory | 145212 kb |
| Host | smart-a97849c8-5f45-4532-adfd-85a39cff7d1d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1126075484 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.1126075484 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |