| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/0.prim_present_test.3935019075 | ||
| Name |
|---|
| /workspace/coverage/default/1.prim_present_test.3192538930 |
| /workspace/coverage/default/10.prim_present_test.1990877157 |
| /workspace/coverage/default/11.prim_present_test.4029511595 |
| /workspace/coverage/default/12.prim_present_test.1734968256 |
| /workspace/coverage/default/13.prim_present_test.1281162222 |
| /workspace/coverage/default/14.prim_present_test.3747327893 |
| /workspace/coverage/default/15.prim_present_test.3044444487 |
| /workspace/coverage/default/16.prim_present_test.215536862 |
| /workspace/coverage/default/17.prim_present_test.2083956137 |
| /workspace/coverage/default/18.prim_present_test.2888439832 |
| /workspace/coverage/default/19.prim_present_test.3485397936 |
| /workspace/coverage/default/2.prim_present_test.4241999797 |
| /workspace/coverage/default/20.prim_present_test.1714398027 |
| /workspace/coverage/default/21.prim_present_test.2901839125 |
| /workspace/coverage/default/22.prim_present_test.1066119238 |
| /workspace/coverage/default/23.prim_present_test.999556284 |
| /workspace/coverage/default/24.prim_present_test.3983852889 |
| /workspace/coverage/default/25.prim_present_test.944589373 |
| /workspace/coverage/default/26.prim_present_test.75896687 |
| /workspace/coverage/default/27.prim_present_test.2396737779 |
| /workspace/coverage/default/28.prim_present_test.1044658902 |
| /workspace/coverage/default/29.prim_present_test.1108982151 |
| /workspace/coverage/default/3.prim_present_test.868977597 |
| /workspace/coverage/default/30.prim_present_test.222872707 |
| /workspace/coverage/default/31.prim_present_test.508332656 |
| /workspace/coverage/default/32.prim_present_test.1519788651 |
| /workspace/coverage/default/33.prim_present_test.2038467538 |
| /workspace/coverage/default/34.prim_present_test.2677206967 |
| /workspace/coverage/default/35.prim_present_test.44814500 |
| /workspace/coverage/default/36.prim_present_test.2514831497 |
| /workspace/coverage/default/37.prim_present_test.2046782837 |
| /workspace/coverage/default/38.prim_present_test.691754466 |
| /workspace/coverage/default/39.prim_present_test.420125091 |
| /workspace/coverage/default/4.prim_present_test.2015883492 |
| /workspace/coverage/default/40.prim_present_test.1591869527 |
| /workspace/coverage/default/41.prim_present_test.2731052927 |
| /workspace/coverage/default/42.prim_present_test.1312021582 |
| /workspace/coverage/default/43.prim_present_test.765025559 |
| /workspace/coverage/default/44.prim_present_test.2396075342 |
| /workspace/coverage/default/45.prim_present_test.3143123294 |
| /workspace/coverage/default/46.prim_present_test.2976427422 |
| /workspace/coverage/default/47.prim_present_test.4037187585 |
| /workspace/coverage/default/48.prim_present_test.170007330 |
| /workspace/coverage/default/49.prim_present_test.1253868395 |
| /workspace/coverage/default/5.prim_present_test.3129449803 |
| /workspace/coverage/default/6.prim_present_test.4073309360 |
| /workspace/coverage/default/7.prim_present_test.777532651 |
| /workspace/coverage/default/8.prim_present_test.2490057780 |
| /workspace/coverage/default/9.prim_present_test.473903882 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/45.prim_present_test.3143123294 | May 12 01:56:16 PM PDT 24 | May 12 01:57:36 PM PDT 24 | 8796560000 ps | ||
| T2 | /workspace/coverage/default/40.prim_present_test.1591869527 | May 12 01:56:22 PM PDT 24 | May 12 01:58:00 PM PDT 24 | 12514080000 ps | ||
| T3 | /workspace/coverage/default/25.prim_present_test.944589373 | May 12 01:56:12 PM PDT 24 | May 12 01:57:56 PM PDT 24 | 15214180000 ps | ||
| T4 | /workspace/coverage/default/13.prim_present_test.1281162222 | May 12 01:56:01 PM PDT 24 | May 12 01:57:22 PM PDT 24 | 11535720000 ps | ||
| T5 | /workspace/coverage/default/23.prim_present_test.999556284 | May 12 01:56:10 PM PDT 24 | May 12 01:57:14 PM PDT 24 | 8009780000 ps | ||
| T6 | /workspace/coverage/default/0.prim_present_test.3935019075 | May 12 01:55:53 PM PDT 24 | May 12 01:56:44 PM PDT 24 | 8458660000 ps | ||
| T7 | /workspace/coverage/default/46.prim_present_test.2976427422 | May 12 01:56:23 PM PDT 24 | May 12 01:56:58 PM PDT 24 | 4049220000 ps | ||
| T8 | /workspace/coverage/default/5.prim_present_test.3129449803 | May 12 01:55:57 PM PDT 24 | May 12 01:56:50 PM PDT 24 | 6469080000 ps | ||
| T9 | /workspace/coverage/default/3.prim_present_test.868977597 | May 12 01:55:58 PM PDT 24 | May 12 01:56:26 PM PDT 24 | 4155240000 ps | ||
| T10 | /workspace/coverage/default/29.prim_present_test.1108982151 | May 12 01:56:17 PM PDT 24 | May 12 01:58:09 PM PDT 24 | 14514820000 ps | ||
| T11 | /workspace/coverage/default/6.prim_present_test.4073309360 | May 12 01:55:58 PM PDT 24 | May 12 01:57:28 PM PDT 24 | 10959120000 ps | ||
| T12 | /workspace/coverage/default/22.prim_present_test.1066119238 | May 12 01:56:08 PM PDT 24 | May 12 01:56:36 PM PDT 24 | 3808040000 ps | ||
| T13 | /workspace/coverage/default/37.prim_present_test.2046782837 | May 12 01:56:14 PM PDT 24 | May 12 01:57:54 PM PDT 24 | 14592940000 ps | ||
| T14 | /workspace/coverage/default/12.prim_present_test.1734968256 | May 12 01:56:00 PM PDT 24 | May 12 01:57:34 PM PDT 24 | 11579740000 ps | ||
| T15 | /workspace/coverage/default/27.prim_present_test.2396737779 | May 12 01:56:09 PM PDT 24 | May 12 01:57:48 PM PDT 24 | 15216040000 ps | ||
| T16 | /workspace/coverage/default/30.prim_present_test.222872707 | May 12 01:56:17 PM PDT 24 | May 12 01:56:55 PM PDT 24 | 4505540000 ps | ||
| T17 | /workspace/coverage/default/18.prim_present_test.2888439832 | May 12 01:56:05 PM PDT 24 | May 12 01:56:55 PM PDT 24 | 6087160000 ps | ||
| T18 | /workspace/coverage/default/20.prim_present_test.1714398027 | May 12 01:56:03 PM PDT 24 | May 12 01:57:20 PM PDT 24 | 10446380000 ps | ||
| T19 | /workspace/coverage/default/32.prim_present_test.1519788651 | May 12 01:56:11 PM PDT 24 | May 12 01:56:52 PM PDT 24 | 4476400000 ps | ||
| T20 | /workspace/coverage/default/11.prim_present_test.4029511595 | May 12 01:56:01 PM PDT 24 | May 12 01:57:37 PM PDT 24 | 11633680000 ps | ||
| T21 | /workspace/coverage/default/34.prim_present_test.2677206967 | May 12 01:56:13 PM PDT 24 | May 12 01:57:48 PM PDT 24 | 11589660000 ps | ||
| T22 | /workspace/coverage/default/2.prim_present_test.4241999797 | May 12 01:55:55 PM PDT 24 | May 12 01:56:58 PM PDT 24 | 9259080000 ps | ||
| T23 | /workspace/coverage/default/7.prim_present_test.777532651 | May 12 01:55:59 PM PDT 24 | May 12 01:57:14 PM PDT 24 | 8290640000 ps | ||
| T24 | /workspace/coverage/default/38.prim_present_test.691754466 | May 12 01:56:17 PM PDT 24 | May 12 01:58:03 PM PDT 24 | 13543280000 ps | ||
| T25 | /workspace/coverage/default/41.prim_present_test.2731052927 | May 12 01:56:17 PM PDT 24 | May 12 01:57:07 PM PDT 24 | 7373040000 ps | ||
| T26 | /workspace/coverage/default/47.prim_present_test.4037187585 | May 12 01:56:21 PM PDT 24 | May 12 01:58:04 PM PDT 24 | 15037480000 ps | ||
| T27 | /workspace/coverage/default/16.prim_present_test.215536862 | May 12 01:56:02 PM PDT 24 | May 12 01:56:26 PM PDT 24 | 3338700000 ps | ||
| T28 | /workspace/coverage/default/9.prim_present_test.473903882 | May 12 01:56:04 PM PDT 24 | May 12 01:57:43 PM PDT 24 | 12130920000 ps | ||
| T29 | /workspace/coverage/default/43.prim_present_test.765025559 | May 12 01:56:22 PM PDT 24 | May 12 01:57:54 PM PDT 24 | 11532000000 ps | ||
| T30 | /workspace/coverage/default/26.prim_present_test.75896687 | May 12 01:56:11 PM PDT 24 | May 12 01:56:47 PM PDT 24 | 4790120000 ps | ||
| T31 | /workspace/coverage/default/14.prim_present_test.3747327893 | May 12 01:56:01 PM PDT 24 | May 12 01:56:27 PM PDT 24 | 3511060000 ps | ||
| T32 | /workspace/coverage/default/42.prim_present_test.1312021582 | May 12 01:56:18 PM PDT 24 | May 12 01:57:37 PM PDT 24 | 9522580000 ps | ||
| T33 | /workspace/coverage/default/39.prim_present_test.420125091 | May 12 01:56:15 PM PDT 24 | May 12 01:57:30 PM PDT 24 | 11753340000 ps | ||
| T34 | /workspace/coverage/default/49.prim_present_test.1253868395 | May 12 01:56:22 PM PDT 24 | May 12 01:57:28 PM PDT 24 | 8900720000 ps | ||
| T35 | /workspace/coverage/default/15.prim_present_test.3044444487 | May 12 01:56:01 PM PDT 24 | May 12 01:57:36 PM PDT 24 | 11743420000 ps | ||
| T36 | /workspace/coverage/default/4.prim_present_test.2015883492 | May 12 01:55:57 PM PDT 24 | May 12 01:56:53 PM PDT 24 | 9519480000 ps | ||
| T37 | /workspace/coverage/default/1.prim_present_test.3192538930 | May 12 01:55:55 PM PDT 24 | May 12 01:57:15 PM PDT 24 | 13532120000 ps | ||
| T38 | /workspace/coverage/default/17.prim_present_test.2083956137 | May 12 01:56:01 PM PDT 24 | May 12 01:56:35 PM PDT 24 | 4960000000 ps | ||
| T39 | /workspace/coverage/default/8.prim_present_test.2490057780 | May 12 01:55:59 PM PDT 24 | May 12 01:56:33 PM PDT 24 | 6148540000 ps | ||
| T40 | /workspace/coverage/default/19.prim_present_test.3485397936 | May 12 01:56:03 PM PDT 24 | May 12 01:56:58 PM PDT 24 | 9439500000 ps | ||
| T41 | /workspace/coverage/default/35.prim_present_test.44814500 | May 12 01:56:13 PM PDT 24 | May 12 01:57:52 PM PDT 24 | 14876900000 ps | ||
| T42 | /workspace/coverage/default/44.prim_present_test.2396075342 | May 12 01:56:17 PM PDT 24 | May 12 01:57:42 PM PDT 24 | 13828480000 ps | ||
| T43 | /workspace/coverage/default/31.prim_present_test.508332656 | May 12 01:56:10 PM PDT 24 | May 12 01:56:44 PM PDT 24 | 5333240000 ps | ||
| T44 | /workspace/coverage/default/36.prim_present_test.2514831497 | May 12 01:56:12 PM PDT 24 | May 12 01:56:52 PM PDT 24 | 5525440000 ps | ||
| T45 | /workspace/coverage/default/48.prim_present_test.170007330 | May 12 01:56:21 PM PDT 24 | May 12 01:58:07 PM PDT 24 | 12024900000 ps | ||
| T46 | /workspace/coverage/default/33.prim_present_test.2038467538 | May 12 01:56:14 PM PDT 24 | May 12 01:56:37 PM PDT 24 | 3407520000 ps | ||
| T47 | /workspace/coverage/default/24.prim_present_test.3983852889 | May 12 01:56:10 PM PDT 24 | May 12 01:56:51 PM PDT 24 | 5531020000 ps | ||
| T48 | /workspace/coverage/default/28.prim_present_test.1044658902 | May 12 01:56:12 PM PDT 24 | May 12 01:57:18 PM PDT 24 | 9053240000 ps | ||
| T49 | /workspace/coverage/default/21.prim_present_test.2901839125 | May 12 01:56:07 PM PDT 24 | May 12 01:57:49 PM PDT 24 | 13954340000 ps | ||
| T50 | /workspace/coverage/default/10.prim_present_test.1990877157 | May 12 01:56:01 PM PDT 24 | May 12 01:57:12 PM PDT 24 | 10650360000 ps |
| Test location | /workspace/coverage/default/0.prim_present_test.3935019075 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 8458660000 ps |
| CPU time | 27.22 seconds |
| Started | May 12 01:55:53 PM PDT 24 |
| Finished | May 12 01:56:44 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-34513bb8-72e7-4d01-9285-cf89558e8d89 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3935019075 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.3935019075 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/1.prim_present_test.3192538930 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 13532120000 ps |
| CPU time | 42.63 seconds |
| Started | May 12 01:55:55 PM PDT 24 |
| Finished | May 12 01:57:15 PM PDT 24 |
| Peak memory | 145096 kb |
| Host | smart-e097eefd-4aa7-403c-a909-29e7e331d04a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3192538930 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.3192538930 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/10.prim_present_test.1990877157 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 10650360000 ps |
| CPU time | 36.97 seconds |
| Started | May 12 01:56:01 PM PDT 24 |
| Finished | May 12 01:57:12 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-570d1b27-42ac-43af-bf4e-2c33d882601f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1990877157 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.1990877157 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/11.prim_present_test.4029511595 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 11633680000 ps |
| CPU time | 47.74 seconds |
| Started | May 12 01:56:01 PM PDT 24 |
| Finished | May 12 01:57:37 PM PDT 24 |
| Peak memory | 145148 kb |
| Host | smart-093e49c5-3e69-4fd1-8ba3-a00cfcf106de |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4029511595 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.4029511595 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.1734968256 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 11579740000 ps |
| CPU time | 46.2 seconds |
| Started | May 12 01:56:00 PM PDT 24 |
| Finished | May 12 01:57:34 PM PDT 24 |
| Peak memory | 145124 kb |
| Host | smart-c94315b3-69e9-4d3d-9200-1f5bd118c681 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1734968256 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.1734968256 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.1281162222 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 11535720000 ps |
| CPU time | 40.21 seconds |
| Started | May 12 01:56:01 PM PDT 24 |
| Finished | May 12 01:57:22 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-3c0a6875-88e2-4b66-8865-0ec1815ba8b3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1281162222 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.1281162222 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.3747327893 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 3511060000 ps |
| CPU time | 12.71 seconds |
| Started | May 12 01:56:01 PM PDT 24 |
| Finished | May 12 01:56:27 PM PDT 24 |
| Peak memory | 145032 kb |
| Host | smart-72fb02ed-6dcf-4b37-b944-f3df5fc57d5e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3747327893 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.3747327893 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.3044444487 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 11743420000 ps |
| CPU time | 47.56 seconds |
| Started | May 12 01:56:01 PM PDT 24 |
| Finished | May 12 01:57:36 PM PDT 24 |
| Peak memory | 145156 kb |
| Host | smart-5c9977ac-78d2-428d-b2f7-8b2357117c3f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3044444487 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.3044444487 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.215536862 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 3338700000 ps |
| CPU time | 12.31 seconds |
| Started | May 12 01:56:02 PM PDT 24 |
| Finished | May 12 01:56:26 PM PDT 24 |
| Peak memory | 145016 kb |
| Host | smart-74737fe3-411f-4bb0-8366-9556a00d11dc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=215536862 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.215536862 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.2083956137 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 4960000000 ps |
| CPU time | 17.41 seconds |
| Started | May 12 01:56:01 PM PDT 24 |
| Finished | May 12 01:56:35 PM PDT 24 |
| Peak memory | 145148 kb |
| Host | smart-ec80b34e-40cd-44c8-aa25-5a8a5551b2c3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2083956137 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.2083956137 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.2888439832 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 6087160000 ps |
| CPU time | 24.88 seconds |
| Started | May 12 01:56:05 PM PDT 24 |
| Finished | May 12 01:56:55 PM PDT 24 |
| Peak memory | 145148 kb |
| Host | smart-c2dbeb8c-ce57-4fac-8c78-da6d509736e1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2888439832 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.2888439832 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.3485397936 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 9439500000 ps |
| CPU time | 29.68 seconds |
| Started | May 12 01:56:03 PM PDT 24 |
| Finished | May 12 01:56:58 PM PDT 24 |
| Peak memory | 145156 kb |
| Host | smart-2929143f-9a03-45b0-8a0d-9d5b4c731e80 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3485397936 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.3485397936 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.4241999797 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 9259080000 ps |
| CPU time | 33.6 seconds |
| Started | May 12 01:55:55 PM PDT 24 |
| Finished | May 12 01:56:58 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-8a93fcb1-51fd-42c0-b56e-a040dbc50419 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4241999797 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.4241999797 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.1714398027 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 10446380000 ps |
| CPU time | 39.8 seconds |
| Started | May 12 01:56:03 PM PDT 24 |
| Finished | May 12 01:57:20 PM PDT 24 |
| Peak memory | 145156 kb |
| Host | smart-ebf72f9b-b58b-489d-a401-55c7241fc121 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1714398027 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.1714398027 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.2901839125 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 13954340000 ps |
| CPU time | 51.61 seconds |
| Started | May 12 01:56:07 PM PDT 24 |
| Finished | May 12 01:57:49 PM PDT 24 |
| Peak memory | 145152 kb |
| Host | smart-1f2937ec-dbb6-415a-8a91-d40b6a23b74f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2901839125 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.2901839125 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.1066119238 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 3808040000 ps |
| CPU time | 14.66 seconds |
| Started | May 12 01:56:08 PM PDT 24 |
| Finished | May 12 01:56:36 PM PDT 24 |
| Peak memory | 145036 kb |
| Host | smart-bee985bd-cdb4-4196-9281-6cc913eeab10 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1066119238 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.1066119238 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.999556284 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 8009780000 ps |
| CPU time | 30.88 seconds |
| Started | May 12 01:56:10 PM PDT 24 |
| Finished | May 12 01:57:14 PM PDT 24 |
| Peak memory | 145160 kb |
| Host | smart-51f0cbc9-2fd8-46fc-ab35-03e6ae0d5293 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=999556284 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.999556284 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.3983852889 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 5531020000 ps |
| CPU time | 20.87 seconds |
| Started | May 12 01:56:10 PM PDT 24 |
| Finished | May 12 01:56:51 PM PDT 24 |
| Peak memory | 145080 kb |
| Host | smart-199c670c-7017-4e5a-b9f1-755aa1dfe845 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3983852889 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.3983852889 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.944589373 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 15214180000 ps |
| CPU time | 53.22 seconds |
| Started | May 12 01:56:12 PM PDT 24 |
| Finished | May 12 01:57:56 PM PDT 24 |
| Peak memory | 145164 kb |
| Host | smart-1df539d5-398d-4baf-81c7-456342341464 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=944589373 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.944589373 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.75896687 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 4790120000 ps |
| CPU time | 18.99 seconds |
| Started | May 12 01:56:11 PM PDT 24 |
| Finished | May 12 01:56:47 PM PDT 24 |
| Peak memory | 145132 kb |
| Host | smart-70582ea9-ccbd-40ce-8a2f-d42fa64bdaae |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=75896687 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.75896687 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.2396737779 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 15216040000 ps |
| CPU time | 53.08 seconds |
| Started | May 12 01:56:09 PM PDT 24 |
| Finished | May 12 01:57:48 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-23096c12-f1cd-4dc7-adc9-f540e8a6f400 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2396737779 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.2396737779 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.1044658902 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 9053240000 ps |
| CPU time | 32.92 seconds |
| Started | May 12 01:56:12 PM PDT 24 |
| Finished | May 12 01:57:18 PM PDT 24 |
| Peak memory | 145160 kb |
| Host | smart-ea9ea14c-4558-4bfe-b6c0-723e30841140 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1044658902 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.1044658902 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.1108982151 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 14514820000 ps |
| CPU time | 55.65 seconds |
| Started | May 12 01:56:17 PM PDT 24 |
| Finished | May 12 01:58:09 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-4d7465b5-3af8-4b2b-969f-a2cc63070f7f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1108982151 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.1108982151 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.868977597 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 4155240000 ps |
| CPU time | 14.68 seconds |
| Started | May 12 01:55:58 PM PDT 24 |
| Finished | May 12 01:56:26 PM PDT 24 |
| Peak memory | 145024 kb |
| Host | smart-194c5cdf-8735-4f2a-801f-500060238629 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=868977597 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.868977597 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.222872707 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 4505540000 ps |
| CPU time | 18.83 seconds |
| Started | May 12 01:56:17 PM PDT 24 |
| Finished | May 12 01:56:55 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-51000be3-5f23-413e-b85a-96af79b01070 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=222872707 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.222872707 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.508332656 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 5333240000 ps |
| CPU time | 18.44 seconds |
| Started | May 12 01:56:10 PM PDT 24 |
| Finished | May 12 01:56:44 PM PDT 24 |
| Peak memory | 145028 kb |
| Host | smart-011e2ad6-d2b7-4d8e-85b4-d990306ce6ca |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=508332656 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.508332656 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.1519788651 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 4476400000 ps |
| CPU time | 21.63 seconds |
| Started | May 12 01:56:11 PM PDT 24 |
| Finished | May 12 01:56:52 PM PDT 24 |
| Peak memory | 145280 kb |
| Host | smart-8643125a-ac58-4c29-8d5b-80f90f4768a7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1519788651 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.1519788651 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.2038467538 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 3407520000 ps |
| CPU time | 12.07 seconds |
| Started | May 12 01:56:14 PM PDT 24 |
| Finished | May 12 01:56:37 PM PDT 24 |
| Peak memory | 145136 kb |
| Host | smart-7d8f36d7-5bf5-4280-ac14-33a6ac233062 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2038467538 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.2038467538 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.2677206967 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 11589660000 ps |
| CPU time | 46.48 seconds |
| Started | May 12 01:56:13 PM PDT 24 |
| Finished | May 12 01:57:48 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-2ad2a6ed-6649-4811-8f0c-6ab61d75ad63 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2677206967 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.2677206967 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.44814500 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 14876900000 ps |
| CPU time | 51.93 seconds |
| Started | May 12 01:56:13 PM PDT 24 |
| Finished | May 12 01:57:52 PM PDT 24 |
| Peak memory | 145284 kb |
| Host | smart-c5980a07-9c94-48de-8c09-c09d12ff2633 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=44814500 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.44814500 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.2514831497 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 5525440000 ps |
| CPU time | 21.93 seconds |
| Started | May 12 01:56:12 PM PDT 24 |
| Finished | May 12 01:56:52 PM PDT 24 |
| Peak memory | 145164 kb |
| Host | smart-d2a0f4d6-dcc7-4560-a136-ce1b359b8d1c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2514831497 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.2514831497 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.2046782837 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 14592940000 ps |
| CPU time | 51 seconds |
| Started | May 12 01:56:14 PM PDT 24 |
| Finished | May 12 01:57:54 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-5f377a15-9528-4bc2-b4e4-ae6637f26421 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2046782837 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.2046782837 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.691754466 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 13543280000 ps |
| CPU time | 52.39 seconds |
| Started | May 12 01:56:17 PM PDT 24 |
| Finished | May 12 01:58:03 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-f4676066-6dfd-406d-8927-104f2d2ce459 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=691754466 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.691754466 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.420125091 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 11753340000 ps |
| CPU time | 40.12 seconds |
| Started | May 12 01:56:15 PM PDT 24 |
| Finished | May 12 01:57:30 PM PDT 24 |
| Peak memory | 145120 kb |
| Host | smart-8d9b1ed3-757b-4278-b192-ed7dadc2abd8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=420125091 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.420125091 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.2015883492 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 9519480000 ps |
| CPU time | 29.76 seconds |
| Started | May 12 01:55:57 PM PDT 24 |
| Finished | May 12 01:56:53 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-f1ab1e8e-2f19-4b31-8443-0b813b99e234 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2015883492 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.2015883492 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.1591869527 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 12514080000 ps |
| CPU time | 48.47 seconds |
| Started | May 12 01:56:22 PM PDT 24 |
| Finished | May 12 01:58:00 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-96c6c591-02a7-4ba2-8686-f349f96038a4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1591869527 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.1591869527 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.2731052927 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 7373040000 ps |
| CPU time | 26.53 seconds |
| Started | May 12 01:56:17 PM PDT 24 |
| Finished | May 12 01:57:07 PM PDT 24 |
| Peak memory | 145124 kb |
| Host | smart-6795fcd9-dd87-4e14-b9bd-0ccd6e4b0dbf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2731052927 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.2731052927 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.1312021582 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 9522580000 ps |
| CPU time | 38.79 seconds |
| Started | May 12 01:56:18 PM PDT 24 |
| Finished | May 12 01:57:37 PM PDT 24 |
| Peak memory | 145148 kb |
| Host | smart-e5c5cdd0-26f3-4cee-9003-c4d935a1d6c7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1312021582 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.1312021582 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.765025559 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 11532000000 ps |
| CPU time | 45.89 seconds |
| Started | May 12 01:56:22 PM PDT 24 |
| Finished | May 12 01:57:54 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-0c68abb3-7faf-46b0-8585-dd5c8acc8dca |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=765025559 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.765025559 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.2396075342 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 13828480000 ps |
| CPU time | 45.28 seconds |
| Started | May 12 01:56:17 PM PDT 24 |
| Finished | May 12 01:57:42 PM PDT 24 |
| Peak memory | 145124 kb |
| Host | smart-0cc2ab73-6ffa-421f-993d-6c1f94abf762 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2396075342 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.2396075342 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.3143123294 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 8796560000 ps |
| CPU time | 38.33 seconds |
| Started | May 12 01:56:16 PM PDT 24 |
| Finished | May 12 01:57:36 PM PDT 24 |
| Peak memory | 145156 kb |
| Host | smart-8b7a8722-eadf-43bd-8eed-ed18c8e33af1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3143123294 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.3143123294 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.2976427422 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4049220000 ps |
| CPU time | 16.89 seconds |
| Started | May 12 01:56:23 PM PDT 24 |
| Finished | May 12 01:56:58 PM PDT 24 |
| Peak memory | 145024 kb |
| Host | smart-f09fd27b-8b41-4a3e-b352-d33144055c1e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2976427422 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.2976427422 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.4037187585 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 15037480000 ps |
| CPU time | 53.44 seconds |
| Started | May 12 01:56:21 PM PDT 24 |
| Finished | May 12 01:58:04 PM PDT 24 |
| Peak memory | 145084 kb |
| Host | smart-8c8be293-5e11-4a49-8258-48d979380c3d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4037187585 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.4037187585 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.170007330 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 12024900000 ps |
| CPU time | 53.34 seconds |
| Started | May 12 01:56:21 PM PDT 24 |
| Finished | May 12 01:58:07 PM PDT 24 |
| Peak memory | 145132 kb |
| Host | smart-3fba4d70-469c-4220-86b2-978951d9ebbb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=170007330 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.170007330 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.1253868395 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 8900720000 ps |
| CPU time | 34.28 seconds |
| Started | May 12 01:56:22 PM PDT 24 |
| Finished | May 12 01:57:28 PM PDT 24 |
| Peak memory | 145072 kb |
| Host | smart-626dc8f4-965b-44a4-9daa-19502e39a8ca |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1253868395 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.1253868395 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.3129449803 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 6469080000 ps |
| CPU time | 26.74 seconds |
| Started | May 12 01:55:57 PM PDT 24 |
| Finished | May 12 01:56:50 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-c1d3fefb-61fa-42ad-9d4e-9cc44aac3d57 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3129449803 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.3129449803 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.4073309360 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 10959120000 ps |
| CPU time | 43.79 seconds |
| Started | May 12 01:55:58 PM PDT 24 |
| Finished | May 12 01:57:28 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-1e79cec1-ce93-4241-8a30-f91b4b1791d4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4073309360 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.4073309360 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.777532651 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 8290640000 ps |
| CPU time | 36.16 seconds |
| Started | May 12 01:55:59 PM PDT 24 |
| Finished | May 12 01:57:14 PM PDT 24 |
| Peak memory | 145176 kb |
| Host | smart-2f416dbb-0cda-4b8e-ba78-e6dfdfaee342 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=777532651 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.777532651 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.2490057780 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 6148540000 ps |
| CPU time | 17.99 seconds |
| Started | May 12 01:55:59 PM PDT 24 |
| Finished | May 12 01:56:33 PM PDT 24 |
| Peak memory | 145156 kb |
| Host | smart-5826ec82-4043-45bc-b868-f16c0a71614a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2490057780 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.2490057780 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.473903882 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 12130920000 ps |
| CPU time | 48.8 seconds |
| Started | May 12 01:56:04 PM PDT 24 |
| Finished | May 12 01:57:43 PM PDT 24 |
| Peak memory | 145164 kb |
| Host | smart-9a078a0a-dfae-48a1-b618-407d4e196487 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=473903882 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.473903882 |
| Directory | /workspace/9.prim_present_test/latest |
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