| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 97.83 | 90.41 | 100.00 | 98.73 | 100.00 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 97.83 | 97.83 | 90.41 | 90.41 | 100.00 | 100.00 | 98.73 | 98.73 | 100.00 | 100.00 | 100.00 | 100.00 | /workspace/coverage/default/10.prim_present_test.3394720205 | ||
| Name |
|---|
| /workspace/coverage/default/0.prim_present_test.1123258304 |
| /workspace/coverage/default/1.prim_present_test.1797696378 |
| /workspace/coverage/default/11.prim_present_test.3972888588 |
| /workspace/coverage/default/12.prim_present_test.2352651877 |
| /workspace/coverage/default/13.prim_present_test.4128448188 |
| /workspace/coverage/default/14.prim_present_test.2961859160 |
| /workspace/coverage/default/15.prim_present_test.1727531297 |
| /workspace/coverage/default/16.prim_present_test.681177277 |
| /workspace/coverage/default/17.prim_present_test.3082517204 |
| /workspace/coverage/default/18.prim_present_test.3849989847 |
| /workspace/coverage/default/19.prim_present_test.3410780511 |
| /workspace/coverage/default/2.prim_present_test.866388527 |
| /workspace/coverage/default/20.prim_present_test.3848582144 |
| /workspace/coverage/default/21.prim_present_test.2195586004 |
| /workspace/coverage/default/22.prim_present_test.3496808610 |
| /workspace/coverage/default/23.prim_present_test.1258234830 |
| /workspace/coverage/default/24.prim_present_test.2384446857 |
| /workspace/coverage/default/25.prim_present_test.2963644720 |
| /workspace/coverage/default/26.prim_present_test.3970289598 |
| /workspace/coverage/default/27.prim_present_test.3613176584 |
| /workspace/coverage/default/28.prim_present_test.4217646092 |
| /workspace/coverage/default/29.prim_present_test.2601669526 |
| /workspace/coverage/default/3.prim_present_test.3120062070 |
| /workspace/coverage/default/30.prim_present_test.3189541531 |
| /workspace/coverage/default/31.prim_present_test.3330214274 |
| /workspace/coverage/default/32.prim_present_test.4235636641 |
| /workspace/coverage/default/33.prim_present_test.1455794401 |
| /workspace/coverage/default/34.prim_present_test.3131545144 |
| /workspace/coverage/default/35.prim_present_test.2549470905 |
| /workspace/coverage/default/36.prim_present_test.3792260658 |
| /workspace/coverage/default/37.prim_present_test.1620062414 |
| /workspace/coverage/default/38.prim_present_test.3223934676 |
| /workspace/coverage/default/39.prim_present_test.1544710884 |
| /workspace/coverage/default/4.prim_present_test.2758073181 |
| /workspace/coverage/default/40.prim_present_test.4014844246 |
| /workspace/coverage/default/41.prim_present_test.2223918082 |
| /workspace/coverage/default/42.prim_present_test.775891975 |
| /workspace/coverage/default/43.prim_present_test.2356738393 |
| /workspace/coverage/default/44.prim_present_test.1373163966 |
| /workspace/coverage/default/45.prim_present_test.1732619398 |
| /workspace/coverage/default/46.prim_present_test.914966290 |
| /workspace/coverage/default/47.prim_present_test.2070523862 |
| /workspace/coverage/default/48.prim_present_test.1805357404 |
| /workspace/coverage/default/49.prim_present_test.2839243477 |
| /workspace/coverage/default/5.prim_present_test.1112032288 |
| /workspace/coverage/default/6.prim_present_test.2206836081 |
| /workspace/coverage/default/7.prim_present_test.3921845173 |
| /workspace/coverage/default/8.prim_present_test.1821037540 |
| /workspace/coverage/default/9.prim_present_test.1661587797 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/10.prim_present_test.3394720205 | May 14 01:17:41 PM PDT 24 | May 14 01:18:51 PM PDT 24 | 8706660000 ps | ||
| T2 | /workspace/coverage/default/32.prim_present_test.4235636641 | May 14 01:17:38 PM PDT 24 | May 14 01:18:53 PM PDT 24 | 9665180000 ps | ||
| T3 | /workspace/coverage/default/47.prim_present_test.2070523862 | May 14 01:17:40 PM PDT 24 | May 14 01:18:37 PM PDT 24 | 7850440000 ps | ||
| T4 | /workspace/coverage/default/31.prim_present_test.3330214274 | May 14 01:17:41 PM PDT 24 | May 14 01:19:29 PM PDT 24 | 14304640000 ps | ||
| T5 | /workspace/coverage/default/44.prim_present_test.1373163966 | May 14 01:17:40 PM PDT 24 | May 14 01:18:48 PM PDT 24 | 11136440000 ps | ||
| T6 | /workspace/coverage/default/36.prim_present_test.3792260658 | May 14 01:17:40 PM PDT 24 | May 14 01:18:05 PM PDT 24 | 3370940000 ps | ||
| T7 | /workspace/coverage/default/15.prim_present_test.1727531297 | May 14 01:17:36 PM PDT 24 | May 14 01:18:59 PM PDT 24 | 10987640000 ps | ||
| T8 | /workspace/coverage/default/25.prim_present_test.2963644720 | May 14 01:17:37 PM PDT 24 | May 14 01:18:55 PM PDT 24 | 10987640000 ps | ||
| T9 | /workspace/coverage/default/2.prim_present_test.866388527 | May 14 01:17:41 PM PDT 24 | May 14 01:18:54 PM PDT 24 | 9373160000 ps | ||
| T10 | /workspace/coverage/default/41.prim_present_test.2223918082 | May 14 01:17:39 PM PDT 24 | May 14 01:18:14 PM PDT 24 | 4787020000 ps | ||
| T11 | /workspace/coverage/default/49.prim_present_test.2839243477 | May 14 01:17:38 PM PDT 24 | May 14 01:18:18 PM PDT 24 | 5351840000 ps | ||
| T12 | /workspace/coverage/default/37.prim_present_test.1620062414 | May 14 01:17:40 PM PDT 24 | May 14 01:18:26 PM PDT 24 | 6382900000 ps | ||
| T13 | /workspace/coverage/default/12.prim_present_test.2352651877 | May 14 01:17:41 PM PDT 24 | May 14 01:18:46 PM PDT 24 | 8332800000 ps | ||
| T14 | /workspace/coverage/default/34.prim_present_test.3131545144 | May 14 01:17:41 PM PDT 24 | May 14 01:18:11 PM PDT 24 | 3792540000 ps | ||
| T15 | /workspace/coverage/default/27.prim_present_test.3613176584 | May 14 01:17:33 PM PDT 24 | May 14 01:19:07 PM PDT 24 | 12516560000 ps | ||
| T16 | /workspace/coverage/default/39.prim_present_test.1544710884 | May 14 01:17:41 PM PDT 24 | May 14 01:18:19 PM PDT 24 | 4601640000 ps | ||
| T17 | /workspace/coverage/default/14.prim_present_test.2961859160 | May 14 01:17:40 PM PDT 24 | May 14 01:18:26 PM PDT 24 | 6000980000 ps | ||
| T18 | /workspace/coverage/default/48.prim_present_test.1805357404 | May 14 01:17:41 PM PDT 24 | May 14 01:18:29 PM PDT 24 | 5927820000 ps | ||
| T19 | /workspace/coverage/default/18.prim_present_test.3849989847 | May 14 01:17:38 PM PDT 24 | May 14 01:18:06 PM PDT 24 | 3305840000 ps | ||
| T20 | /workspace/coverage/default/9.prim_present_test.1661587797 | May 14 01:17:38 PM PDT 24 | May 14 01:18:17 PM PDT 24 | 5956340000 ps | ||
| T21 | /workspace/coverage/default/16.prim_present_test.681177277 | May 14 01:17:42 PM PDT 24 | May 14 01:18:30 PM PDT 24 | 8171600000 ps | ||
| T22 | /workspace/coverage/default/42.prim_present_test.775891975 | May 14 01:17:44 PM PDT 24 | May 14 01:19:46 PM PDT 24 | 14791960000 ps | ||
| T23 | /workspace/coverage/default/20.prim_present_test.3848582144 | May 14 01:17:41 PM PDT 24 | May 14 01:19:00 PM PDT 24 | 10252320000 ps | ||
| T24 | /workspace/coverage/default/38.prim_present_test.3223934676 | May 14 01:17:43 PM PDT 24 | May 14 01:19:10 PM PDT 24 | 12798660000 ps | ||
| T25 | /workspace/coverage/default/35.prim_present_test.2549470905 | May 14 01:17:42 PM PDT 24 | May 14 01:19:24 PM PDT 24 | 12920800000 ps | ||
| T26 | /workspace/coverage/default/8.prim_present_test.1821037540 | May 14 01:17:40 PM PDT 24 | May 14 01:18:40 PM PDT 24 | 7719000000 ps | ||
| T27 | /workspace/coverage/default/3.prim_present_test.3120062070 | May 14 01:17:38 PM PDT 24 | May 14 01:18:15 PM PDT 24 | 5908600000 ps | ||
| T28 | /workspace/coverage/default/0.prim_present_test.1123258304 | May 14 01:17:41 PM PDT 24 | May 14 01:19:41 PM PDT 24 | 15193720000 ps | ||
| T29 | /workspace/coverage/default/13.prim_present_test.4128448188 | May 14 01:17:38 PM PDT 24 | May 14 01:18:50 PM PDT 24 | 9760040000 ps | ||
| T30 | /workspace/coverage/default/6.prim_present_test.2206836081 | May 14 01:17:38 PM PDT 24 | May 14 01:18:52 PM PDT 24 | 11762640000 ps | ||
| T31 | /workspace/coverage/default/23.prim_present_test.1258234830 | May 14 01:17:40 PM PDT 24 | May 14 01:18:32 PM PDT 24 | 8193300000 ps | ||
| T32 | /workspace/coverage/default/40.prim_present_test.4014844246 | May 14 01:17:44 PM PDT 24 | May 14 01:19:37 PM PDT 24 | 13349840000 ps | ||
| T33 | /workspace/coverage/default/46.prim_present_test.914966290 | May 14 01:17:41 PM PDT 24 | May 14 01:19:23 PM PDT 24 | 13923960000 ps | ||
| T34 | /workspace/coverage/default/22.prim_present_test.3496808610 | May 14 01:17:40 PM PDT 24 | May 14 01:18:25 PM PDT 24 | 5540320000 ps | ||
| T35 | /workspace/coverage/default/11.prim_present_test.3972888588 | May 14 01:17:40 PM PDT 24 | May 14 01:18:49 PM PDT 24 | 9455620000 ps | ||
| T36 | /workspace/coverage/default/19.prim_present_test.3410780511 | May 14 01:17:38 PM PDT 24 | May 14 01:19:18 PM PDT 24 | 10959740000 ps | ||
| T37 | /workspace/coverage/default/1.prim_present_test.1797696378 | May 14 01:17:37 PM PDT 24 | May 14 01:18:41 PM PDT 24 | 8082940000 ps | ||
| T38 | /workspace/coverage/default/33.prim_present_test.1455794401 | May 14 01:17:40 PM PDT 24 | May 14 01:18:51 PM PDT 24 | 9964640000 ps | ||
| T39 | /workspace/coverage/default/26.prim_present_test.3970289598 | May 14 01:17:41 PM PDT 24 | May 14 01:19:19 PM PDT 24 | 12582900000 ps | ||
| T40 | /workspace/coverage/default/45.prim_present_test.1732619398 | May 14 01:17:38 PM PDT 24 | May 14 01:19:20 PM PDT 24 | 14473900000 ps | ||
| T41 | /workspace/coverage/default/29.prim_present_test.2601669526 | May 14 01:17:40 PM PDT 24 | May 14 01:19:19 PM PDT 24 | 14109960000 ps | ||
| T42 | /workspace/coverage/default/28.prim_present_test.4217646092 | May 14 01:17:41 PM PDT 24 | May 14 01:19:37 PM PDT 24 | 15418780000 ps | ||
| T43 | /workspace/coverage/default/30.prim_present_test.3189541531 | May 14 01:17:38 PM PDT 24 | May 14 01:18:31 PM PDT 24 | 9059440000 ps | ||
| T44 | /workspace/coverage/default/17.prim_present_test.3082517204 | May 14 01:17:38 PM PDT 24 | May 14 01:19:43 PM PDT 24 | 13883660000 ps | ||
| T45 | /workspace/coverage/default/21.prim_present_test.2195586004 | May 14 01:17:38 PM PDT 24 | May 14 01:18:37 PM PDT 24 | 7894460000 ps | ||
| T46 | /workspace/coverage/default/24.prim_present_test.2384446857 | May 14 01:17:39 PM PDT 24 | May 14 01:18:42 PM PDT 24 | 8081080000 ps | ||
| T47 | /workspace/coverage/default/4.prim_present_test.2758073181 | May 14 01:17:47 PM PDT 24 | May 14 01:19:44 PM PDT 24 | 14886200000 ps | ||
| T48 | /workspace/coverage/default/7.prim_present_test.3921845173 | May 14 01:17:40 PM PDT 24 | May 14 01:18:18 PM PDT 24 | 4348060000 ps | ||
| T49 | /workspace/coverage/default/5.prim_present_test.1112032288 | May 14 01:17:41 PM PDT 24 | May 14 01:18:46 PM PDT 24 | 8221200000 ps | ||
| T50 | /workspace/coverage/default/43.prim_present_test.2356738393 | May 14 01:17:41 PM PDT 24 | May 14 01:19:00 PM PDT 24 | 10419720000 ps |
| Test location | /workspace/coverage/default/10.prim_present_test.3394720205 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 8706660000 ps |
| CPU time | 34.01 seconds |
| Started | May 14 01:17:41 PM PDT 24 |
| Finished | May 14 01:18:51 PM PDT 24 |
| Peak memory | 145128 kb |
| Host | smart-501985af-6773-4fb5-aad1-7d141175e4b2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3394720205 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_present_test.3394720205 |
| Directory | /workspace/10.prim_present_test/latest |
| Test location | /workspace/coverage/default/0.prim_present_test.1123258304 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 15193720000 ps |
| CPU time | 61.3 seconds |
| Started | May 14 01:17:41 PM PDT 24 |
| Finished | May 14 01:19:41 PM PDT 24 |
| Peak memory | 145132 kb |
| Host | smart-457989e7-b6ba-4bc4-8e71-5dd2b4267b94 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1123258304 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_present_test.1123258304 |
| Directory | /workspace/0.prim_present_test/latest |
| Test location | /workspace/coverage/default/1.prim_present_test.1797696378 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 8082940000 ps |
| CPU time | 32.32 seconds |
| Started | May 14 01:17:37 PM PDT 24 |
| Finished | May 14 01:18:41 PM PDT 24 |
| Peak memory | 145144 kb |
| Host | smart-d1816efd-b501-48ec-92d6-58ffef48e53e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1797696378 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_present_test.1797696378 |
| Directory | /workspace/1.prim_present_test/latest |
| Test location | /workspace/coverage/default/11.prim_present_test.3972888588 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 9455620000 ps |
| CPU time | 35.02 seconds |
| Started | May 14 01:17:40 PM PDT 24 |
| Finished | May 14 01:18:49 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-a8e51e7b-cca6-4ac5-8911-e89743409268 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3972888588 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_present_test.3972888588 |
| Directory | /workspace/11.prim_present_test/latest |
| Test location | /workspace/coverage/default/12.prim_present_test.2352651877 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 8332800000 ps |
| CPU time | 33.01 seconds |
| Started | May 14 01:17:41 PM PDT 24 |
| Finished | May 14 01:18:46 PM PDT 24 |
| Peak memory | 145192 kb |
| Host | smart-a3478215-4d13-4e4a-a0af-46124e4fd991 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2352651877 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_present_test.2352651877 |
| Directory | /workspace/12.prim_present_test/latest |
| Test location | /workspace/coverage/default/13.prim_present_test.4128448188 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 9760040000 ps |
| CPU time | 35.79 seconds |
| Started | May 14 01:17:38 PM PDT 24 |
| Finished | May 14 01:18:50 PM PDT 24 |
| Peak memory | 145152 kb |
| Host | smart-4c22a350-5cde-43ae-8a5f-f4d7de70c4e8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4128448188 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_present_test.4128448188 |
| Directory | /workspace/13.prim_present_test/latest |
| Test location | /workspace/coverage/default/14.prim_present_test.2961859160 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 6000980000 ps |
| CPU time | 23.19 seconds |
| Started | May 14 01:17:40 PM PDT 24 |
| Finished | May 14 01:18:26 PM PDT 24 |
| Peak memory | 145164 kb |
| Host | smart-e22527b0-4101-46c5-91c9-868f1d775055 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2961859160 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_present_test.2961859160 |
| Directory | /workspace/14.prim_present_test/latest |
| Test location | /workspace/coverage/default/15.prim_present_test.1727531297 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 10987640000 ps |
| CPU time | 43.18 seconds |
| Started | May 14 01:17:36 PM PDT 24 |
| Finished | May 14 01:18:59 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-d746ed83-6d53-49db-a0ea-63ff0f35c338 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1727531297 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_present_test.1727531297 |
| Directory | /workspace/15.prim_present_test/latest |
| Test location | /workspace/coverage/default/16.prim_present_test.681177277 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 8171600000 ps |
| CPU time | 25.62 seconds |
| Started | May 14 01:17:42 PM PDT 24 |
| Finished | May 14 01:18:30 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-ed1f0d18-9426-4551-aa40-8a98646b8200 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=681177277 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_present_test.681177277 |
| Directory | /workspace/16.prim_present_test/latest |
| Test location | /workspace/coverage/default/17.prim_present_test.3082517204 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 13883660000 ps |
| CPU time | 61.38 seconds |
| Started | May 14 01:17:38 PM PDT 24 |
| Finished | May 14 01:19:43 PM PDT 24 |
| Peak memory | 145184 kb |
| Host | smart-3b82765c-45d4-4110-8c71-bbb585ad0a1a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3082517204 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_present_test.3082517204 |
| Directory | /workspace/17.prim_present_test/latest |
| Test location | /workspace/coverage/default/18.prim_present_test.3849989847 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 3305840000 ps |
| CPU time | 13.95 seconds |
| Started | May 14 01:17:38 PM PDT 24 |
| Finished | May 14 01:18:06 PM PDT 24 |
| Peak memory | 144924 kb |
| Host | smart-f43a222e-b145-4b21-a64b-b27910c55c1c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3849989847 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_present_test.3849989847 |
| Directory | /workspace/18.prim_present_test/latest |
| Test location | /workspace/coverage/default/19.prim_present_test.3410780511 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 10959740000 ps |
| CPU time | 48.74 seconds |
| Started | May 14 01:17:38 PM PDT 24 |
| Finished | May 14 01:19:18 PM PDT 24 |
| Peak memory | 145188 kb |
| Host | smart-a572ea5e-3fa3-4890-b477-944ab2b9f168 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3410780511 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_present_test.3410780511 |
| Directory | /workspace/19.prim_present_test/latest |
| Test location | /workspace/coverage/default/2.prim_present_test.866388527 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 9373160000 ps |
| CPU time | 36.75 seconds |
| Started | May 14 01:17:41 PM PDT 24 |
| Finished | May 14 01:18:54 PM PDT 24 |
| Peak memory | 145164 kb |
| Host | smart-91236067-040f-428e-95ad-4d8425987829 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=866388527 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_present_test.866388527 |
| Directory | /workspace/2.prim_present_test/latest |
| Test location | /workspace/coverage/default/20.prim_present_test.3848582144 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 10252320000 ps |
| CPU time | 39.34 seconds |
| Started | May 14 01:17:41 PM PDT 24 |
| Finished | May 14 01:19:00 PM PDT 24 |
| Peak memory | 145144 kb |
| Host | smart-1934372f-bbf9-40cc-98a2-77a8d74c9e92 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3848582144 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 20.prim_present_test.3848582144 |
| Directory | /workspace/20.prim_present_test/latest |
| Test location | /workspace/coverage/default/21.prim_present_test.2195586004 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 7894460000 ps |
| CPU time | 30.19 seconds |
| Started | May 14 01:17:38 PM PDT 24 |
| Finished | May 14 01:18:37 PM PDT 24 |
| Peak memory | 145076 kb |
| Host | smart-bf58d1f4-de88-4bd5-b7c8-d581073dc613 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2195586004 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 21.prim_present_test.2195586004 |
| Directory | /workspace/21.prim_present_test/latest |
| Test location | /workspace/coverage/default/22.prim_present_test.3496808610 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 5540320000 ps |
| CPU time | 21.85 seconds |
| Started | May 14 01:17:40 PM PDT 24 |
| Finished | May 14 01:18:25 PM PDT 24 |
| Peak memory | 145144 kb |
| Host | smart-f89f39fa-8161-479f-b250-6667b5c4f1db |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3496808610 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 22.prim_present_test.3496808610 |
| Directory | /workspace/22.prim_present_test/latest |
| Test location | /workspace/coverage/default/23.prim_present_test.1258234830 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 8193300000 ps |
| CPU time | 26.78 seconds |
| Started | May 14 01:17:40 PM PDT 24 |
| Finished | May 14 01:18:32 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-9f779681-3956-488e-ad67-b034a2a6c846 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1258234830 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 23.prim_present_test.1258234830 |
| Directory | /workspace/23.prim_present_test/latest |
| Test location | /workspace/coverage/default/24.prim_present_test.2384446857 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 8081080000 ps |
| CPU time | 32.46 seconds |
| Started | May 14 01:17:39 PM PDT 24 |
| Finished | May 14 01:18:42 PM PDT 24 |
| Peak memory | 145084 kb |
| Host | smart-5a0e6202-cc78-4218-ad41-d52bed2c678d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2384446857 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 24.prim_present_test.2384446857 |
| Directory | /workspace/24.prim_present_test/latest |
| Test location | /workspace/coverage/default/25.prim_present_test.2963644720 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 10987640000 ps |
| CPU time | 39.43 seconds |
| Started | May 14 01:17:37 PM PDT 24 |
| Finished | May 14 01:18:55 PM PDT 24 |
| Peak memory | 145116 kb |
| Host | smart-0ea0d0bc-ee29-41cf-aa9e-347c6ffb276d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2963644720 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 25.prim_present_test.2963644720 |
| Directory | /workspace/25.prim_present_test/latest |
| Test location | /workspace/coverage/default/26.prim_present_test.3970289598 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 12582900000 ps |
| CPU time | 48.76 seconds |
| Started | May 14 01:17:41 PM PDT 24 |
| Finished | May 14 01:19:19 PM PDT 24 |
| Peak memory | 145124 kb |
| Host | smart-386db3a2-d28c-499d-95d7-bbdf4c69cc14 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3970289598 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 26.prim_present_test.3970289598 |
| Directory | /workspace/26.prim_present_test/latest |
| Test location | /workspace/coverage/default/27.prim_present_test.3613176584 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 12516560000 ps |
| CPU time | 48.03 seconds |
| Started | May 14 01:17:33 PM PDT 24 |
| Finished | May 14 01:19:07 PM PDT 24 |
| Peak memory | 145128 kb |
| Host | smart-778fe1f6-2727-4da8-9d97-58411806a335 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3613176584 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 27.prim_present_test.3613176584 |
| Directory | /workspace/27.prim_present_test/latest |
| Test location | /workspace/coverage/default/28.prim_present_test.4217646092 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 15418780000 ps |
| CPU time | 60.13 seconds |
| Started | May 14 01:17:41 PM PDT 24 |
| Finished | May 14 01:19:37 PM PDT 24 |
| Peak memory | 145076 kb |
| Host | smart-5d5c9bf3-e2b0-45f4-8b4c-7c47df29e178 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4217646092 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 28.prim_present_test.4217646092 |
| Directory | /workspace/28.prim_present_test/latest |
| Test location | /workspace/coverage/default/29.prim_present_test.2601669526 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 14109960000 ps |
| CPU time | 50.78 seconds |
| Started | May 14 01:17:40 PM PDT 24 |
| Finished | May 14 01:19:19 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-295b0962-adf4-4fc4-ba61-860ecf2c7ee7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2601669526 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.prim_present_test.2601669526 |
| Directory | /workspace/29.prim_present_test/latest |
| Test location | /workspace/coverage/default/3.prim_present_test.3120062070 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 5908600000 ps |
| CPU time | 18.8 seconds |
| Started | May 14 01:17:38 PM PDT 24 |
| Finished | May 14 01:18:15 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-bcf71a54-68b8-4251-b6f0-f6155dd6bfad |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3120062070 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_present_test.3120062070 |
| Directory | /workspace/3.prim_present_test/latest |
| Test location | /workspace/coverage/default/30.prim_present_test.3189541531 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 9059440000 ps |
| CPU time | 28.05 seconds |
| Started | May 14 01:17:38 PM PDT 24 |
| Finished | May 14 01:18:31 PM PDT 24 |
| Peak memory | 145156 kb |
| Host | smart-31fb2f70-80a8-431b-b5b0-b07c732db358 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3189541531 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 30.prim_present_test.3189541531 |
| Directory | /workspace/30.prim_present_test/latest |
| Test location | /workspace/coverage/default/31.prim_present_test.3330214274 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 14304640000 ps |
| CPU time | 54.86 seconds |
| Started | May 14 01:17:41 PM PDT 24 |
| Finished | May 14 01:19:29 PM PDT 24 |
| Peak memory | 145148 kb |
| Host | smart-f505de80-545b-4dd0-9930-b52e88715c70 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3330214274 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 31.prim_present_test.3330214274 |
| Directory | /workspace/31.prim_present_test/latest |
| Test location | /workspace/coverage/default/32.prim_present_test.4235636641 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 9665180000 ps |
| CPU time | 38.41 seconds |
| Started | May 14 01:17:38 PM PDT 24 |
| Finished | May 14 01:18:53 PM PDT 24 |
| Peak memory | 145132 kb |
| Host | smart-104fc1c1-cc93-4fbc-b71f-70dc0392c914 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4235636641 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 32.prim_present_test.4235636641 |
| Directory | /workspace/32.prim_present_test/latest |
| Test location | /workspace/coverage/default/33.prim_present_test.1455794401 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 9964640000 ps |
| CPU time | 36.62 seconds |
| Started | May 14 01:17:40 PM PDT 24 |
| Finished | May 14 01:18:51 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-8da069aa-9023-48cf-8604-b98b1c40c37c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1455794401 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 33.prim_present_test.1455794401 |
| Directory | /workspace/33.prim_present_test/latest |
| Test location | /workspace/coverage/default/34.prim_present_test.3131545144 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 3792540000 ps |
| CPU time | 15.06 seconds |
| Started | May 14 01:17:41 PM PDT 24 |
| Finished | May 14 01:18:11 PM PDT 24 |
| Peak memory | 145052 kb |
| Host | smart-3cf888f2-a606-491e-a898-c0d9bdddbe3f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3131545144 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 34.prim_present_test.3131545144 |
| Directory | /workspace/34.prim_present_test/latest |
| Test location | /workspace/coverage/default/35.prim_present_test.2549470905 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 12920800000 ps |
| CPU time | 52.72 seconds |
| Started | May 14 01:17:42 PM PDT 24 |
| Finished | May 14 01:19:24 PM PDT 24 |
| Peak memory | 145124 kb |
| Host | smart-8e54b5ba-c6f7-4181-ae85-e40be6592957 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2549470905 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 35.prim_present_test.2549470905 |
| Directory | /workspace/35.prim_present_test/latest |
| Test location | /workspace/coverage/default/36.prim_present_test.3792260658 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 3370940000 ps |
| CPU time | 12.26 seconds |
| Started | May 14 01:17:40 PM PDT 24 |
| Finished | May 14 01:18:05 PM PDT 24 |
| Peak memory | 145016 kb |
| Host | smart-05d84025-8e3c-4841-a1f5-8df986df63ae |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3792260658 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 36.prim_present_test.3792260658 |
| Directory | /workspace/36.prim_present_test/latest |
| Test location | /workspace/coverage/default/37.prim_present_test.1620062414 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 6382900000 ps |
| CPU time | 23.7 seconds |
| Started | May 14 01:17:40 PM PDT 24 |
| Finished | May 14 01:18:26 PM PDT 24 |
| Peak memory | 145164 kb |
| Host | smart-2792b905-bacc-4c6c-9f66-5ed3c362c3b3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1620062414 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 37.prim_present_test.1620062414 |
| Directory | /workspace/37.prim_present_test/latest |
| Test location | /workspace/coverage/default/38.prim_present_test.3223934676 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 12798660000 ps |
| CPU time | 45.87 seconds |
| Started | May 14 01:17:43 PM PDT 24 |
| Finished | May 14 01:19:10 PM PDT 24 |
| Peak memory | 145076 kb |
| Host | smart-592d15f2-299d-412d-ac48-e6a4f524387c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3223934676 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 38.prim_present_test.3223934676 |
| Directory | /workspace/38.prim_present_test/latest |
| Test location | /workspace/coverage/default/39.prim_present_test.1544710884 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 4601640000 ps |
| CPU time | 18.33 seconds |
| Started | May 14 01:17:41 PM PDT 24 |
| Finished | May 14 01:18:19 PM PDT 24 |
| Peak memory | 145256 kb |
| Host | smart-8778ea93-b89b-497b-ba35-e1208a28dcc7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1544710884 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 39.prim_present_test.1544710884 |
| Directory | /workspace/39.prim_present_test/latest |
| Test location | /workspace/coverage/default/4.prim_present_test.2758073181 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 14886200000 ps |
| CPU time | 59.22 seconds |
| Started | May 14 01:17:47 PM PDT 24 |
| Finished | May 14 01:19:44 PM PDT 24 |
| Peak memory | 145156 kb |
| Host | smart-c6126ef0-8956-440f-b581-328b64ae1e19 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2758073181 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_present_test.2758073181 |
| Directory | /workspace/4.prim_present_test/latest |
| Test location | /workspace/coverage/default/40.prim_present_test.4014844246 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 13349840000 ps |
| CPU time | 56.46 seconds |
| Started | May 14 01:17:44 PM PDT 24 |
| Finished | May 14 01:19:37 PM PDT 24 |
| Peak memory | 145172 kb |
| Host | smart-16a3a55f-61c6-4b27-9ed9-edc645a61c98 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4014844246 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 40.prim_present_test.4014844246 |
| Directory | /workspace/40.prim_present_test/latest |
| Test location | /workspace/coverage/default/41.prim_present_test.2223918082 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 4787020000 ps |
| CPU time | 17.59 seconds |
| Started | May 14 01:17:39 PM PDT 24 |
| Finished | May 14 01:18:14 PM PDT 24 |
| Peak memory | 145152 kb |
| Host | smart-90afeb8e-b1a8-4308-bea3-f28b5910c806 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2223918082 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 41.prim_present_test.2223918082 |
| Directory | /workspace/41.prim_present_test/latest |
| Test location | /workspace/coverage/default/42.prim_present_test.775891975 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 14791960000 ps |
| CPU time | 61.74 seconds |
| Started | May 14 01:17:44 PM PDT 24 |
| Finished | May 14 01:19:46 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-2bd1c28a-195f-4115-8268-54eb97c257ce |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=775891975 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 42.prim_present_test.775891975 |
| Directory | /workspace/42.prim_present_test/latest |
| Test location | /workspace/coverage/default/43.prim_present_test.2356738393 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 10419720000 ps |
| CPU time | 40.41 seconds |
| Started | May 14 01:17:41 PM PDT 24 |
| Finished | May 14 01:19:00 PM PDT 24 |
| Peak memory | 145152 kb |
| Host | smart-690a55f5-d84a-4708-a1d8-bf96ffd03473 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2356738393 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 43.prim_present_test.2356738393 |
| Directory | /workspace/43.prim_present_test/latest |
| Test location | /workspace/coverage/default/44.prim_present_test.1373163966 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 11136440000 ps |
| CPU time | 35.33 seconds |
| Started | May 14 01:17:40 PM PDT 24 |
| Finished | May 14 01:18:48 PM PDT 24 |
| Peak memory | 145168 kb |
| Host | smart-73ac76bc-b889-4546-85fe-58bd2f97f4f8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1373163966 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.prim_present_test.1373163966 |
| Directory | /workspace/44.prim_present_test/latest |
| Test location | /workspace/coverage/default/45.prim_present_test.1732619398 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 14473900000 ps |
| CPU time | 52.41 seconds |
| Started | May 14 01:17:38 PM PDT 24 |
| Finished | May 14 01:19:20 PM PDT 24 |
| Peak memory | 145148 kb |
| Host | smart-bf18c485-cd38-42fb-9a5a-2a5d3875c102 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1732619398 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 45.prim_present_test.1732619398 |
| Directory | /workspace/45.prim_present_test/latest |
| Test location | /workspace/coverage/default/46.prim_present_test.914966290 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 13923960000 ps |
| CPU time | 52.69 seconds |
| Started | May 14 01:17:41 PM PDT 24 |
| Finished | May 14 01:19:23 PM PDT 24 |
| Peak memory | 145160 kb |
| Host | smart-12c0c542-e84b-4daa-b0c2-22483a6099ee |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=914966290 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 46.prim_present_test.914966290 |
| Directory | /workspace/46.prim_present_test/latest |
| Test location | /workspace/coverage/default/47.prim_present_test.2070523862 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 7850440000 ps |
| CPU time | 29.25 seconds |
| Started | May 14 01:17:40 PM PDT 24 |
| Finished | May 14 01:18:37 PM PDT 24 |
| Peak memory | 145136 kb |
| Host | smart-3dc80898-6f4c-44da-a16b-6fa00ba7634a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2070523862 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 47.prim_present_test.2070523862 |
| Directory | /workspace/47.prim_present_test/latest |
| Test location | /workspace/coverage/default/48.prim_present_test.1805357404 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 5927820000 ps |
| CPU time | 24.08 seconds |
| Started | May 14 01:17:41 PM PDT 24 |
| Finished | May 14 01:18:29 PM PDT 24 |
| Peak memory | 145124 kb |
| Host | smart-618c11c4-c9a7-402d-8c47-74bdf79082e3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1805357404 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 48.prim_present_test.1805357404 |
| Directory | /workspace/48.prim_present_test/latest |
| Test location | /workspace/coverage/default/49.prim_present_test.2839243477 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 5351840000 ps |
| CPU time | 20.18 seconds |
| Started | May 14 01:17:38 PM PDT 24 |
| Finished | May 14 01:18:18 PM PDT 24 |
| Peak memory | 145152 kb |
| Host | smart-7c9e7ccf-dc2a-4c38-a88c-48da346fc1c3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2839243477 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 49.prim_present_test.2839243477 |
| Directory | /workspace/49.prim_present_test/latest |
| Test location | /workspace/coverage/default/5.prim_present_test.1112032288 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 8221200000 ps |
| CPU time | 33.25 seconds |
| Started | May 14 01:17:41 PM PDT 24 |
| Finished | May 14 01:18:46 PM PDT 24 |
| Peak memory | 145160 kb |
| Host | smart-7ed806eb-dd88-4eff-9dde-10fd5b184ab5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1112032288 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_present_test.1112032288 |
| Directory | /workspace/5.prim_present_test/latest |
| Test location | /workspace/coverage/default/6.prim_present_test.2206836081 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 11762640000 ps |
| CPU time | 39.08 seconds |
| Started | May 14 01:17:38 PM PDT 24 |
| Finished | May 14 01:18:52 PM PDT 24 |
| Peak memory | 145160 kb |
| Host | smart-5aeee29f-80f2-449a-9a4f-ed740083c29a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2206836081 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_present_test.2206836081 |
| Directory | /workspace/6.prim_present_test/latest |
| Test location | /workspace/coverage/default/7.prim_present_test.3921845173 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 4348060000 ps |
| CPU time | 18.39 seconds |
| Started | May 14 01:17:40 PM PDT 24 |
| Finished | May 14 01:18:18 PM PDT 24 |
| Peak memory | 145160 kb |
| Host | smart-db0895b6-0d12-46c4-b514-8137f8456bce |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3921845173 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_present_test.3921845173 |
| Directory | /workspace/7.prim_present_test/latest |
| Test location | /workspace/coverage/default/8.prim_present_test.1821037540 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 7719000000 ps |
| CPU time | 30.37 seconds |
| Started | May 14 01:17:40 PM PDT 24 |
| Finished | May 14 01:18:40 PM PDT 24 |
| Peak memory | 145160 kb |
| Host | smart-6eca2aac-23b5-4cf0-9653-3f854cada5a4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1821037540 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_present_test.1821037540 |
| Directory | /workspace/8.prim_present_test/latest |
| Test location | /workspace/coverage/default/9.prim_present_test.1661587797 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 5956340000 ps |
| CPU time | 19.74 seconds |
| Started | May 14 01:17:38 PM PDT 24 |
| Finished | May 14 01:18:17 PM PDT 24 |
| Peak memory | 145164 kb |
| Host | smart-43d3bdb7-3205-44cd-ba4c-5202461ec52e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1661587797 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_present_test.1661587797 |
| Directory | /workspace/9.prim_present_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |